Signal processing device and signal processing method

Abstract

The present application relates to a signal processing device and a signal receiving method. The signal processing device includes a clock recovery circuit and an equalization circuit; the equalization circuit includes a level feedback circuit. The clock recovery circuit is used to generate a clock signal for a received signal; the equalization circuit is used to perform clock data recovery on the received signal based on the clock signal and a feedback signal output by the level feedback circuit, thereby obtaining a clock data recovery signal corresponding to the received signal. The signal processed by this signal processing device is of high quality.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a signal processing device and a signal processing method. Background Art

[0002] With the development of communication technology, the requirements for signal transmission are becoming increasingly higher. Based on this, during the process of signal transmission from a transmitter to a receiver, a signal processing device is usually required to process the received signal to meet the transmission requirements.

[0003] Taking a four-level pulse amplitude modulation (PAM4) signal as an example, in related technologies, when a signal processing device receives a PAM4 signal, it is necessary to further perform clock recovery and data recovery on the PAM4 signal to obtain a processed PAM4 signal.

[0004] However, the quality of the signal processed by the signal processing device in the related art is poor. Summary of the Invention

[0005] Based on this, it is necessary to provide a signal processing device and a signal processing method to address the above technical problems and improve the quality of the signal processed by the signal processing device.

[0006] In a first aspect, the present application provides a signal processing device, the signal processing device comprising: a clock recovery circuit and an equalization circuit; the equalization circuit comprising a level feedback circuit;

[0007] A clock recovery circuit for generating a clock signal for a received signal;

[0008] The equalization circuit is used to perform clock data recovery on the received signal according to the clock signal and the data signal output by the level feedback circuit to obtain a clock data recovery signal.

[0009] The signal processing device of the embodiment of the present application includes: a clock recovery circuit and an equalizing circuit, and the equalizing circuit includes a level feedback circuit. Among them, the clock recovery circuit is used to generate a clock signal of the received signal; the equalizing circuit is used to perform clock data recovery on the received signal based on the clock signal and the data signal output by the level feedback circuit to obtain a clock data recovery signal. In this signal processing device, the clock signal corresponding to the received signal is obtained through the clock recovery circuit, and the level feedback circuit is used to perform level feedback on the received signal to compensate for the loss of the received signal on the transmission path and to restore the data signal of the received signal to the greatest extent. On this basis, the clock data recovery signal generated by the equalizing circuit based on the clock signal and the data signal is more comprehensive and accurate, and the quality of the clock data recovery signal is also higher.

[0010] In one embodiment, the equalization circuit further includes a correction unit and a plurality of shift units;

[0011] a correction unit, configured to correct a received signal according to the data signal;

[0012] Each shift unit is used to perform shift sampling on the corrected received signal to generate multiple data signals.

[0013] In the signal processing device of the embodiment of the present application, multi-level feedback is performed on the received signal through multiple shift units, jitter in the received signal is eliminated from multiple dimensions, the clock recovery signal and data recovery signal of the received signal are improved, and the content of the received signal is restored to a large extent.

[0014] In one embodiment, each shift unit includes a level shift subunit, a signal decision subunit, and a signal sampling subunit;

[0015] A level shift subunit, configured to perform level shifting on the corrected received signal to obtain a reference level;

[0016] A signal decision subunit, configured to perform zero-crossing detection on the corrected received signal according to a reference level and generate a thermometer code;

[0017] The signal sampling subunit is used to perform center sampling and edge sampling on the thermometer code to obtain a data signal.

[0018] In the signal processing device of the embodiment of the present application, the level shifting function, the level decision function and the sampling function are respectively performed by the level shifting subunit, the signal decision subunit and the signal sampling subunit in the shifting unit. The division of labor of each device is clear and the topology structure is simple. While reducing hardware overhead, multi-level feedback is realized. The equalization circuit constructed based on such a shifting unit has stronger frequency locking capability and jitter tolerance.

[0019] In one embodiment, the clock recovery circuit includes an oscillating unit and a buffering unit;

[0020] The oscillation unit is used to provide a clock signal to the equalization circuit through the buffer unit.

[0021] In the signal processing device of the embodiment of the present application, the clock recovery circuit includes an oscillation unit and a buffer unit. Based on the clock signal generated by the oscillation unit and the distribution and processing capabilities of the buffer unit for the clock signal, a clock signal generation and transmission path is constructed. The structure is simple and the hardware overhead is small. While enhancing the jitter tolerance limit of the signal processing device, the frequency locking speed of the clock signal is accelerated.

[0022] In one embodiment, the oscillation unit includes a phase interpolation subunit and a phase selection subunit;

[0023] The phase selection subunit is used to send a quadrature clock signal pair to the phase interpolation subunit;

[0024] The phase interpolation subunit is used to perform interpolation processing on the orthogonal clock signal pair, generate a clock signal, and send the clock signal to the buffer unit.

[0025] In the signal processing device of the embodiment of the present application, taking into account the limitations of the phase selection subunit and the phase interpolation subunit, the phase selection subunit and the phase interpolation subunit are combined to generate a clock recovery circuit that supports both the processing of discrete signals and the processing of continuous signals. This improves the scenario applicability of the clock recovery circuit while having the advantages of phase tracking accuracy, good jitter performance, and fast locking.

[0026] In one embodiment, the oscillation unit further includes a clock generating subunit;

[0027] The clock generating subunit is used to generate a multi-phase clock signal according to a reference clock signal and send the multi-phase clock signal to the phase selecting subunit.

[0028] In the signal processing device of the present embodiment, a multi-phase clock is introduced into the clock recovery circuit, providing the phase selection subunit with a multi-phase clock with different phase differences. This enables the phase selection subunit to quickly obtain a phase clock that meets control requirements, thereby improving the speed at which the clock recovery circuit generates clock signals. Furthermore, the clock generation subunit in the present embodiment does not require a reference to an external clock, resulting in lower costs.

[0029] In one embodiment, the signal processing device further includes an analog filtering circuit;

[0030] The analog filtering circuit is used to filter the received signal and send the filtered received signal to the equalization circuit and the clock recovery circuit respectively.

[0031] In the signal processing device of the embodiment of the present application, taking into account the signal attenuation that occurs when high-speed digital signals are transmitted through a lossy channel, the received signal is compensated by an analog filtering circuit to enhance the high-frequency component of the received signal, thereby compensating for the loss signal of the received signal in the high-frequency channel and improving the quality of the signal processed by the signal processing device.

[0032] In one embodiment, the signal processing device further includes a decoding circuit;

[0033] The decoding circuit is used to decode the output signal of the equalization circuit to generate a clock data recovery signal.

[0034] In the signal processing device of the embodiment of the present application, the multi-path feedback signals output by the equalization circuit are decoded by the decoding circuit to obtain two non-return-to-zero code signals to clearly and unambiguously represent the clock data recovery signal of the received signal.

[0035] In a second aspect, a signal processing method is provided, the method comprising:

[0036] Obtaining a clock signal and a feedback signal of the received signal; the feedback signal is obtained by modifying and shifting the received signal;

[0037] Perform clock data recovery on the received signal according to the clock signal and the feedback signal to generate a clock data recovery signal.

[0038] In the technical solution of the embodiment of the present application, the clock signal and data signal of the received signal are first obtained, and then the clock data of the received signal is recovered based on the clock signal and the data signal to generate a clock data recovery signal. Among them, the data signal is obtained based on the correction and shift sampling of the received signal. In this method, it is equivalent to taking into account the problems such as the loss of the clock signal of the received signal and the inaccuracy of the data signal during the processing of the received signal, and recovering the clock dimension of the received signal based on the clock signal, and recovering the data dimension of the received signal based on the data signal, fully restoring the clock signal and data signal of the received signal, and the quality of the clock data recovery signal is also higher.

[0039] In one embodiment, obtaining a clock signal of a received signal includes:

[0040] Filtering the received signal to obtain a control signal corresponding to the received signal;

[0041] determining an orthogonal clock signal pair from a preset multi-phase clock signal according to a control signal;

[0042] Interpolation processing is performed on the orthogonal clock signal pair to obtain a clock signal.

[0043] In the technical solution of the embodiment of the present application, the received signal is filtered to obtain a control signal corresponding to the received signal. Then, based on the control signal, an orthogonal clock signal pair is determined from a preset multi-phase clock signal, and the orthogonal clock signal pair is interpolated to perform clock phase tracking and data phase calibration to generate a clock signal that is compatible with the received signal.

[0044] In a third aspect, the present application further provides a signal processing device, comprising:

[0045] An acquisition module is used to acquire a clock signal and a data signal of a received signal; the data signal is obtained by correcting and shifting the received signal;

[0046] The recovery module is used to perform clock data recovery on the received signal according to the clock signal and the data signal to generate a clock data recovery signal.

[0047] In a fourth aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any one of the embodiments of the second aspect.

[0048] In a fifth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any one of the embodiments of the second aspect.

[0049] In a sixth aspect, the present application further provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the method in any one of the embodiments of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 is a schematic structural diagram of a signal processing device in one embodiment;

[0052] Figure 2 is a structural diagram of a signal processing device in another embodiment;

[0053] Figure 3 is a structural diagram of a signal processing device in another embodiment;

[0054] Figure 4 is a structural diagram of a signal processing device in another embodiment;

[0055] Figure 5 is a structural diagram of a signal processing device in another embodiment;

[0056] Figure 6 is a structural diagram of a signal processing device in another embodiment;

[0057] Figure 7 is a structural diagram of a signal processing device in another embodiment;

[0058] Figure 8is a structural diagram of a signal processing device in another embodiment;

[0059] Figure 9 1 is a flow chart of a signal processing method according to an embodiment;

[0060] Figure 10 Schematic diagram of a flow chart of a clock signal acquisition step in one embodiment;

[0061] Figure 11 is a structural block diagram of a signal processing device in one embodiment;

[0062] Figure 12 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment.

[0063] Description of reference numerals:

[0064] 01: Signal processing equipment; 10: Equalization circuit;

[0065] 101: level feedback circuit; 102: correction unit;

[0066] 103: shift unit; 103a: level shift subunit;

[0067] 103b: signal decision subunit; 103c: signal sampling subunit;

[0068] 20: clock recovery circuit; 201: phase detection unit;

[0069] 202: conversion unit; 203: filtering unit;

[0070] 204: oscillation unit; 204a: phase interpolation subunit;

[0071] 204b: phase selection subunit; 204c: clock generation subunit;

[0072] 205: buffer unit; 30: analog filter circuit;

[0073] 40: Decoding circuit. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are for the purpose of describing specific embodiments only and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned description of the drawings are intended to cover non-exclusive inclusions. In the description of the embodiments of this application, "multiple" and "multi-layer" mean more than two, unless otherwise clearly and specifically defined. Reference to "embodiments" in this article means that the specific features, structures or characteristics described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0076] In the description of the embodiments of the present application, the orientation or positional relationship indicated by the technical terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the embodiments of the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise clearly specified and limited, the technical terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0077] With the development of communication technology, the requirements for signal transmission are becoming increasingly higher. Based on this, during the process of signal transmission from a transmitter to a receiver, a signal processing device at the receiver end is usually required to process the received signal to meet the transmission requirements.

[0078] In a serial high-speed communication system, high-speed signals are transmitted in a differential form, transmitting only data but not clock. Therefore, it is necessary to design a clock recovery circuit for receiving clock data.

[0079] Furthermore, high-speed data transmission is subject to interference from non-ideal factors, such as PVT (Provider VLAN Transport) mismatch, which can easily lead to different path delays. Lengthy edge selection logic can easily generate glitches, which directly affect subsequent circuits and cause signal jitter. Recovering a low-jitter synchronous clock signal from jittery data is a pressing challenge for clock recovery technology.

[0080] Therefore, designing a circuit topology that can receive clock data while ensuring signal processing quality is a pressing technical issue. Based on this, an embodiment of the present application provides a topology for a signal processing device that improves the signal processing capability of the signal processing device for receiving signals, thereby improving the quality of the processed signals. The signal processing device provided in an embodiment of the present application is described below using an example.

[0081] In an exemplary embodiment, Figure 1 As shown, the signal processing device 01 includes: a clock recovery circuit 20 and an equalizing circuit 10 ; the equalizing circuit 10 includes a level feedback circuit 101 .

[0082] The clock recovery circuit 20 is used to generate a clock signal for the received signal; the equalization circuit 10 is used to perform clock data recovery on the received signal according to the clock signal and the data signal output by the level feedback circuit 101 to obtain a clock data recovery signal.

[0083] exist Figure 1 In the signal processing device 01 shown, the equalization circuit 1 may be a decision feedback equalizer (DFE), and the clock recovery circuit 20 may be a clock data recovery (CDR) circuit.

[0084] The clock recovery circuit 20 locks the phase and frequency of the received signal based on the received signal to achieve clock recovery of the received signal. In the embodiment of the present application, the clock signal output by the clock recovery circuit 20 is connected to the equalization circuit 10, that is, the clock recovery circuit 20 provides the equalization circuit 10 with a clock signal corresponding to the received signal.

[0085] The equalizer circuit 10 uses the clock signal provided by the clock recovery circuit 20 as the clock recovery signal for the received signal. Simultaneously, the level feedback circuit 101 performs nonlinear equalization on the data to be transmitted in the received signal to obtain a data signal, and then filters out interference signals in the received signal to reduce intersymbol interference (ISI) in the received signal, thereby obtaining a data recovery signal corresponding to the received signal. After obtaining the clock recovery signal and the data recovery signal, the equalizer circuit 10 superimposes them to obtain a clock data recovery signal corresponding to the received signal.

[0086] In an embodiment of the present application, a signal processing device includes: a clock recovery circuit and an equalization circuit, wherein the equalization circuit includes a level feedback circuit. The clock recovery circuit is used to generate a clock signal for a received signal; the equalization circuit is used to perform clock data recovery on the received signal based on the clock signal and the data signal output by the level feedback circuit to obtain a clock data recovery signal. In this signal processing device, the clock signal corresponding to the received signal is obtained through the clock recovery circuit, and the level feedback circuit is used to perform level feedback on the received signal to compensate for the loss of the received signal on the transmission path and to recover the data signal of the received signal to the greatest extent possible. On this basis, the clock data recovery signal generated by the equalization circuit based on the clock signal and the data signal is more comprehensive and accurate, and the quality of the clock data recovery signal is also higher.

[0087] The functions of the equalizing circuit are described in the above embodiments. The following describes the principle of the data signal output by the level feedback circuit 101 through an embodiment in combination with the topology of the equalizing circuit 10.

[0088] In an exemplary embodiment, Figure 2 As shown, the equalization circuit 10 further includes a correction unit 102 and a plurality of shift units 103 .

[0089] The correction unit 102 is used to correct the received signal according to the data signal output by the level feedback circuit 101; and each shift unit 103 is used to perform shift sampling on the corrected received signal to generate multiple data signals.

[0090] Furthermore, each data signal enters the level feedback circuit 101 , and the level feedback circuit 101 feeds back and outputs a new data signal based on the data signal.

[0091] Based on the above, it can be seen that in the equalizing circuit 10, the connection relationship between the level feedback circuit 101, the correction unit 102, and the shift unit 103 is as follows: the input end of the correction unit 102 is connected to the output end of the level feedback circuit 101, the output end of the correction unit 102 is connected to the input end of each shift unit 103; and the output end of each shift unit 103 is connected to the level feedback circuit 101.

[0092] Take the equalization circuit 10 including three shift units 103 as an example, see Figure 2 The equalization circuit 10 includes a level feedback circuit 101, a correction unit 102, and three parallel shifting units 103. The three parallel shifting units 103 are located between the correction unit 102 and the level feedback circuit, and each shifting unit 103 is connected to the clock recovery circuit 20 to receive the clock signal output by the clock recovery circuit 20. It should be noted that Figure 2 The equalizer circuit 10 shown includes a three-level feedback loop, the purpose of which is to enhance the jitter tolerance of the output signal of the equalizer circuit 10 .

[0093] Figure 2 In the example, the level feedback circuit 101, the correction unit 102, and the three shifting units 103 respectively form three level feedback loops. In each level feedback loop, the correction unit 102 sums the received signal and the data signal output by the level feedback circuit to filter out interference signals in the received signal and obtain a corrected received signal. Next, the shifting unit 103 performs signal level shifting, signal level determination, and signal level sampling based on the corrected received signal output by the correction unit 102 and the clock signal provided by the clock recovery circuit 20 to obtain multiple data signals. Then, the equalization circuit calculates the weighted average of each data signal output by each level feedback loop and the corresponding compensation coefficient based on the compensation coefficient of each data signal to obtain a new data signal, which is then input into the correction unit.

[0094] It should be noted that Figure 2 Although the components involved in the three shift units 103 shown are identical, the specific values used in the level shifting process are different. Consequently, the decision and sampling processes performed by each shift unit 103 are also different. For example, shift unit A shifts the level signal output by correction unit 102 upward, shift unit B does not shift the level signal output by correction unit 102, and shift unit C shifts the level signal output by correction unit 102 downward.

[0095] In an embodiment of the present application, multi-level feedback is performed on the received signal through multiple shift units to eliminate jitter in the received signal from multiple dimensions, improve the clock recovery signal and data recovery signal of the received signal, and restore the content of the received signal to a large extent.

[0096] As can be seen from the above embodiments, the shift unit 103 needs to implement multiple processing functions such as shifting, judging, sampling, etc. Based on this, the following describes the principle and topology of how the shift unit 103 implements shifting, judging, and sampling through an embodiment.

[0097] In an exemplary embodiment, Figure 3 As shown, each shift unit 103 includes a level shift subunit 103a, a signal decision subunit 103b and a signal sampling subunit 103c.

[0098] Among them, the level shifting subunit 103a is used to level shift the corrected received signal to obtain a reference level; the signal decision subunit 103b is used to perform zero-crossing detection on the corrected received signal according to the reference level to generate a thermometer code; and the signal sampling subunit 103c is used to perform center sampling and edge sampling on the thermometer code to obtain a data signal.

[0099] See Figure 3 ,exist Figure 3 In the structural diagram of the signal processing device 01 shown, the level shifting subunit 103a, the signal decision subunit 103b and the signal sampling subunit 103c are connected in series in sequence. In each shifting unit 103, the input end of the level shifting subunit 103a is connected to the correction unit 102, and the output end of the signal sampling subunit 103c is connected to the level feedback circuit 101.

[0100] Still taking the input signal as a four-level modulation signal (PAM4) and the signal processing device 01 including three shifting units 103 as an example, the implementation principle of the three shifting units 103 is explained: each level shifting sub-unit 103a shifts the level of the received signal output by the correction unit 102 into three paths, namely upper, middle and lower, and outputs three corresponding reference levels; each signal decision sub-unit 103b generates corresponding three-path counting according to the reference levels output by each level shifting sub-unit 103a; each signal sampling sub-unit 103c performs center sampling and edge sampling according to the three-path counting output by each signal decision sub-unit 103b and the clock signal provided by the clock recovery circuit 20, to obtain corresponding three-path signals, namely data signals.

[0101] In an embodiment of the present application, the level shifting subunit, the signal decision subunit and the signal sampling subunit in the shifting unit respectively perform the level shifting function, the level decision function and the sampling function. Each device has a clear division of labor and a simple topology structure. While reducing hardware overhead, multi-level feedback is achieved. The equalization circuit constructed based on such a shifting unit has a stronger frequency locking capability and jitter tolerance.

[0102] As can be seen from the above embodiments, the signal processing device 01 includes an equalization circuit 10 and a clock recovery circuit 20. Figures 1 to 3 The corresponding embodiment describes the topology and implementation principle of the equalization circuit 10 in the signal processing device 01 . The following describes the topology and working principle of the clock recovery circuit 20 .

[0103] In an exemplary embodiment, Figure 4 As shown, the clock recovery circuit 20 includes an oscillating unit 204 and a buffering unit 205 . The oscillating unit 204 is configured to provide a clock signal to the equalizing circuit via the buffering unit 205 .

[0104] It should be noted that, in order to implement basic processing such as filtering and data conversion of the received signal, the clock recovery circuit 20 may further include: a phase detector unit 201 , a conversion unit 202 , and a filtering unit 203 .

[0105] like Figure 4 As shown, the clock recovery circuit 20 of the signal processing device 01 includes: a phase detection unit 201, a conversion unit 202, a filtering unit 203, an oscillation unit 204 and a buffer unit 205 connected in series in sequence.

[0106] The phase detector 201 is a device capable of identifying the phase difference of input signals. Specifically, it refers to a circuit whose output voltage has a definite relationship with the phase difference between two input signals, such as a Bang-Bang phase detector. The conversion unit 202 is a voltage-to-current converter, used to convert the voltage output by the phase detector 201 into a current. The filter unit 203 is a low-pass filter, used to filter the current output by the conversion unit 202. The oscillator 204 generates a reference frequency signal by adjusting the capacitor, inductor, or resistor in the circuit based on the filtered signal output by the filter unit 203. The buffer unit (CLK buffer) 205 generates multiple clock signals by frequency replicating a clock source signal based on the filtered signal output by the oscillator 204. The buffer unit 205 also performs a clock distribution function, used to send the generated multiple clock signals to different shift units 103 in the equalization circuit 103.

[0107] In an embodiment of the present application, the clock recovery circuit includes an oscillation unit and a buffer unit. Based on the clock signal generated by the oscillation unit and the distribution and processing capabilities of the buffer unit for the clock signal, a clock signal generation and transmission path is constructed. The structure is simple and the hardware overhead is small. While enhancing the jitter tolerance limit of the signal processing device, the frequency locking speed of the clock signal is accelerated.

[0108] In a clock recovery circuit, an oscillator unit refers to an electronic device that can generate an adjustable frequency signal. The topology of the oscillator unit is described below through an embodiment.

[0109] In an exemplary embodiment, the oscillation unit 204 includes a phase interpolation subunit 204 a and a phase selection subunit 204 b .

[0110] The phase selection subunit 204b is used to send the orthogonal clock signal pair to the phase interpolation subunit 204a; the phase interpolation subunit 204a is used to interpolate the orthogonal clock signal pair to generate a clock signal and send the clock signal to the buffer unit 205.

[0111] In actual application scenarios, the phase interpolator (PI) 204a is suitable for processing continuous phase clock signals. Specifically, the continuous multi-phase clock is discretized through a digital-to-analog converter to obtain a multi-phase clock signal, and then weighted interpolation is performed to generate a recovered clock signal.

[0112] The phase selector (PS) subunit 204b is adapted to process discrete phase clock signals, specifically to track and calibrate data phases using appropriate clock phases based on multiple discrete phase clocks, thereby generating a recovered clock signal.

[0113] like Figure 5 As shown, Figure 5 In the illustrated signal processing device 01, the oscillation unit 204 includes a digital-to-analog converter (DAC), a phase interpolation subunit 204a, and a phase selection subunit 204b. The DAC input and the first input of the phase selection subunit 204b are both connected to the filtering unit 203. The DAC output and the output of the phase selection subunit 204b are both connected to the phase interpolation subunit 204a. The phase interpolation subunit 204a is then connected to the buffer unit 205.

[0114] Figure 5 In the embodiment, the phase selection subunit 204b selects a pair of orthogonal clock signals from the multiple clock signals based on the filtered signal output from the filtering unit 203, and inputs the selected pair of orthogonal clock signals to the phase interpolation subunit 204a.

[0115] When faced with a continuous input signal, the phase interpolation subunit 204a can perform weighted interpolation based on the multiple clock signals output by the digital-to-analog converter to generate a clock signal, and send it to the buffer unit 205. When faced with a discrete input signal, the phase interpolation subunit 204a performs weighted interpolation based on the two clock signals in the orthogonal clock signal pair sent by the phase selection subunit 204b to generate a clock signal, and send it to the buffer unit 205.

[0116] In an embodiment of the present application, taking into account the limitations of the phase selection subunit and the phase interpolation subunit, the phase selection subunit and the phase interpolation subunit are combined to generate a clock recovery circuit that supports both the processing of discrete signals and the processing of continuous signals, thereby improving the scenario applicability of the clock recovery circuit while having the advantages of phase tracking accuracy, good jitter performance and fast locking.

[0117] As can be seen from the aforementioned embodiment, the phase selection subunit 204b is suitable for processing discrete input phase clock signals, while the phase interpolation subunit 204a is suitable for processing continuously input phase clock signals. Therefore, when the phase selection subunit 204b and the phase interpolation subunit 204a are combined, the phase selection subunit 204b is naturally required to provide the phase interpolation subunit 204a with a multi-phase clock signal to support the phase interpolation subunit 204a in generating clock signals. Based on this, the following describes, through an embodiment, the source of the orthogonal clock signal pair provided by the phase selection subunit 204b to the phase interpolation subunit 204a in combination with the topology of the oscillation unit 204.

[0118] In an exemplary embodiment, Figure 6 As shown, the oscillation unit 204 further includes a clock generation subunit 204c, wherein the clock generation subunit 204c is configured to generate a multi-phase clock signal according to a reference clock signal and send the multi-phase clock signal to the phase selection subunit 204c.

[0119] See Figure 6 , Figure 6 In the signal processing device 01 shown, the clock generation subunit 204c is connected to the phase selection subunit 204b, so that the phase selection subunit 204b can select a quadrature clock signal pair from the multi-phase clock signal generated by the clock generation subunit 204c.

[0120] Clock generation subunit 204c generates a multiphase clock signal based on the received reference clock. This clock generation subunit 204c may be a phase-locked loop (PLL) system. The PLL-based clock recovery circuit has a simple structure and draws on mature PLL theory, making it suitable for high-speed transmission systems. Furthermore, this simple PLL-based clock recovery circuit structure offers strong frequency locking capability and jitter tolerance, making it suitable for high-speed serial transmission.

[0121] In this embodiment, a multi-phase clock is introduced into the clock recovery circuit, providing the phase selection subunit with a multi-phase clock with different phase differences. This allows the phase selection subunit to quickly obtain a phase clock that meets control requirements, thereby increasing the speed at which the clock recovery circuit generates clock signals. Furthermore, the clock generation subunit in this embodiment does not require a reference external clock, resulting in lower costs.

[0122] In the signal processing device, the received signal may be balanced and compensated before being input to the equalization circuit 10 and the clock recovery circuit 20 to improve the quality of the signal processed by the signal processing device. In an exemplary embodiment, Figure 7 As shown, the signal processing device 01 further includes an analog filtering circuit 30 , wherein the analog filtering circuit 30 is configured to filter the received signal and send the filtered received signal to the equalization circuit 10 and the clock recovery circuit 20 respectively.

[0123] Figure 7 In the signal processing device shown, the analog filtering circuit 30 filters the received signal and sends the filtered received signal to the clock recovery circuit 20, so that the clock recovery circuit 20 generates a clock signal based on the filtered received signal.

[0124] At the same time, the analog filtering circuit 30 also sends the filtered received signal to the equalizing circuit 10, so that the equalizing circuit 10 performs nonlinear equalization processing on the filtered received signal, and combines the clock signal output by the clock recovery circuit 20 to generate a clock data recovery signal corresponding to the received signal.

[0125] In an embodiment of the present application, taking into account the signal attenuation that occurs when high-speed digital signals are transmitted through a lossy channel, the received signal is compensated by an analog filtering circuit to enhance the high-frequency component of the received signal, thereby compensating for the loss signal of the received signal in the high-frequency channel and improving the quality of the signal processed by the signal processing device.

[0126] In an embodiment of the present application, multiple sampled data signals of the received signal are fed back based on a level feedback circuit to generate a data signal, which is equivalent to an encoding process of the received signal. Therefore, when the signal processing device generates the final clock data recovery signal, it is necessary to decode the data signal to obtain a clock data recovery signal corresponding to the received signal, so as to restore the received signal to the greatest extent.

[0127] In an exemplary embodiment, Figure 8 As shown, the signal processing device 01 further includes a decoding circuit 40 , which is configured to decode the output signal of the equalization circuit 10 to generate a clock data recovery signal.

[0128] Figure 8 In the signal processing device 01 shown, the decoding circuit 40 decodes the multi-path feedback signals outputted by the equalization circuit 10 to generate two non-return-to-zero code signals: MSB and LSB, and obtains a clock data recovery signal of the received signal.

[0129] The signal processing device provided in the embodiment of the present application decodes the multi-path feedback signals output by the equalization circuit through a decoding circuit to obtain two non-return-to-zero code signals to clearly and unambiguously represent the clock data recovery signal of the received signal.

[0130] Please continue to see Figure 8 Taking the input signal as PAM4 and the analog filter circuit 30 as a continuous time linear equalizer (CTLE) as an example, Figure 8 The processing steps of the signal processing device are shown as follows:

[0131] The attenuated PAM4 signal is first balanced and compensated by the CTLE. The equalized signal is then level-shifted and split into upper, middle, and lower channels, which are then fed into the decision circuit to generate three thermometer codes. The signal sampling subunit generates three level signals based on the three thermometer codes and the clock signal. These signals are weighted with three sets of compensation coefficients, which are then fed back to the level shifter before being added to the CTLE output, performing compensation equalization at the first tap. The PAM4 decoder decodes the three-channel thermometer codes DA, DB, and DC into the original two NRZ signals (MSB and LSB).

[0132] In the CDR architecture, taking the Bang-Bang phase detector as an example, a Bang-Bang phase detector and phase-locked loop (PLL) structure is employed, eliminating the edge selection module. The intermediate decision signal is directly fed into the Bang-Bang phase detector, where it undergoes successive edge sampling and two data sampling cycles to generate the DB, EB, and DBZ-1 signals. The V / I converter, oscillator, and buffer units retain the same NRZ CDR design. Directly feeding the intermediate decision signal into the CDR utilizes the information from the middle transition edge for edge sampling, avoiding the complex digital combinational logic chain in the edge selection module at the expense of PAM4 transition density.

[0133] Compared to traditional clock recovery circuits based on phase-locked loops (PLLs), the clock recovery circuit of this embodiment, based on a phase selection subunit / phase interpolation subunit, utilizes a PLL to generate a multi-phase high-speed reference clock signal. This multi-phase clock is then input into the clock recovery circuit, improving the data and clock recovery capabilities of PAM4 signals. Furthermore, this embodiment combines the advantages of the phase selection subunit and phase interpolation subunit clock recovery circuits, offering high phase tracking accuracy, excellent jitter performance, and fast locking.

[0134] In addition, in an exemplary embodiment, Figure 9As shown, the present application provides a signal processing method, comprising the following steps:

[0135] S901, obtaining a clock signal and a data signal of a received signal; the data signal is obtained based on correction and shift sampling of the received signal.

[0136] The clock signal of the received signal is obtained according to the frequency and phase of the received signal, and the data signal corresponding to the received signal is obtained by performing different level shifts and feedback on the received signal.

[0137] Optionally, the received signal is input into a clock recovery module, which outputs a clock signal of the received signal. The topology of the clock recovery module can be found in the description of the clock recovery circuit in the signal processing device in the above embodiment, and will not be repeated here.

[0138] Optionally, the received signal is input into a level feedback module, which performs different level shifting on the received signal and performs weighted feedback based on the multiple level shifted signals to obtain multiple level shifted signals corresponding to the received signal, thereby obtaining a data signal. The topology of the level feedback module can be found in the description of the level feedback circuit in the signal processing device in the above embodiment, and will not be repeated here.

[0139] S902 , performing clock data recovery on the received signal according to the clock signal and the data signal to generate a clock data recovery signal.

[0140] The clock signal and the data signal are superimposed to obtain a clock data recovery signal having two dimensions of clock information and data information.

[0141] In another scenario, the data signal may also include an initial clock signal. In this case, the initial clock signal of the data signal can be compensated based on the clock signal to obtain a clock data signal. The clock data signal is then analyzed and decoded to generate two non-return-to-zero code signals corresponding to the received signal, namely the clock data recovery signal.

[0142] In an embodiment of the present application, the clock signal and data signal of the received signal are first obtained, and then the clock data of the received signal is recovered based on the clock signal and the data signal to generate a clock data recovery signal. The data signal is obtained by correcting and shifting the received signal. In this method, during the processing of the received signal, the clock dimension of the received signal is recovered based on the clock signal, and the data dimension of the received signal is recovered based on the data signal. The clock signal and data signal of the received signal are fully restored, and the quality of the clock data recovery signal is higher.

[0143] The following describes an implementation method of "obtaining the clock signal of the received signal" in the above embodiment S901 through an embodiment. Figure 10 , the steps of obtaining the clock signal include:

[0144] S1001: Filter a received signal to obtain a control signal corresponding to the received signal.

[0145] The received signal is filtered to generate a control signal corresponding to the received signal, where the control signal is used to indicate a phase requirement of a multi-phase clock required by a clock recovery circuit.

[0146] In one scenario, before filtering the received signal, the received signal may be extracted by a phase detector and the clock phase difference may be recovered.

[0147] S1002: Determine an orthogonal clock signal pair from preset multi-phase clock signals according to a control signal.

[0148] S1003 , performing interpolation processing on the analog signal using the orthogonal clock signal pair to obtain a clock signal.

[0149] In an embodiment of the present application, the received signal is filtered to obtain a control signal corresponding to the received signal. Then, based on the control signal, an orthogonal clock signal pair is determined from a preset multi-phase clock signal, and the orthogonal clock signal pair is interpolated to perform clock phase tracking and data phase calibration to generate a clock signal that is compatible with the received signal.

[0150] In an exemplary embodiment, a signal processing method includes:

[0151] (1) Filter the received signal to obtain the control signal corresponding to the received signal.

[0152] (2) According to the control signal, an orthogonal clock signal pair is determined from the preset multi-phase clock signal.

[0153] (3) The analog signal is interpolated by the orthogonal clock signal pair to obtain the clock signal.

[0154] (4) Obtain the data signal of the received signal.

[0155] The data signal is obtained by correcting and shifting the sampling of the received signal.

[0156] (5) Based on the clock signal and data signal, the clock data of the received signal is recovered to generate a clock data recovery signal.

[0157] In an embodiment of the present application, the clock signal and data signal of the received signal are first obtained, and then the clock data of the received signal is recovered based on the clock signal and the data signal to generate a clock data recovery signal. The data signal is obtained by correcting and shifting the received signal. In this method, during the processing of the received signal, the clock dimension of the received signal is recovered based on the clock signal, and the data dimension of the received signal is recovered based on the data signal. The clock signal and data signal of the received signal are fully restored, and the quality of the clock data recovery signal is higher.

[0158] It will be appreciated that the above process is implemented by computer program instructions, which are provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device, so that the instructions executed by the processor of the computer or other programmable data processing device can implement the output of the test voltage of the target device under test according to the voltage transformation strategy of this embodiment. Of course, these computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device. Alternatively, these computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the computer program instructions are executed on the computer or other programmable device to implement the above functions.

[0159] Based on the same inventive concept, embodiments of the present application further provide a signal receiving device for implementing the aforementioned signal receiving method. The implementation solution provided by this device is similar to the implementation solution described in the aforementioned method. Therefore, the specific limitations of one or more signal receiving device embodiments provided below can be found in the above-mentioned limitations of the signal receiving method and are not further elaborated here.

[0160] In an exemplary embodiment, Figure 11 As shown, a signal receiving device is provided, including: an acquisition module 1101 and a recovery module 1102, wherein:

[0161] The acquisition module 1101 is used to acquire a clock signal and a data signal of a received signal; the data signal is obtained by modifying and shifting the received signal;

[0162] The recovery module 1102 is configured to perform clock data recovery on the received signal according to the clock signal and the data signal, and generate a clock data recovery signal.

[0163] In an exemplary embodiment, the acquisition module 1101 includes a filtering unit, a determination unit, and an interpolation unit, wherein:

[0164] A filtering unit, configured to filter the received signal to obtain a control signal corresponding to the received signal;

[0165] a determining unit, configured to determine an orthogonal clock signal pair from a preset multi-phase clock signal according to a control signal;

[0166] The interpolation unit is used to perform interpolation processing on the orthogonal clock signal pair to obtain a clock signal.

[0167] Each module in the above-mentioned signal transmission device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0168] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 12 As shown. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals via wired or wireless means, and the wireless means can be achieved via Wi-Fi, mobile cellular networks, NFC (near-field communication), or other technologies. When executed by the processor, the computer program implements a signal transmission method. The display unit of the computer device is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse.

[0169] Those skilled in the art will understand that Figure 12The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0170] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0171] Obtaining a clock signal and a feedback signal of the received signal; the feedback signal is obtained by modifying and shifting the received signal;

[0172] Perform clock data recovery on the received signal according to the clock signal and the feedback signal to generate a clock data recovery signal.

[0173] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0174] Filtering the received signal to obtain a control signal corresponding to the received signal;

[0175] determining an orthogonal clock signal pair from a preset multi-phase clock signal according to a control signal;

[0176] Interpolation processing is performed on the orthogonal clock signal pair to obtain a clock signal.

[0177] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0178] Obtaining a clock signal and a feedback signal of the received signal; the feedback signal is obtained by modifying and shifting the received signal;

[0179] Perform clock data recovery on the received signal according to the clock signal and the feedback signal to generate a clock data recovery signal.

[0180] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0181] Filtering the received signal to obtain a control signal corresponding to the received signal;

[0182] determining an orthogonal clock signal pair from a preset multi-phase clock signal according to a control signal;

[0183] Interpolation processing is performed on the orthogonal clock signal pair to obtain a clock signal.

[0184] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0185] Obtaining a clock signal and a feedback signal of the received signal; the feedback signal is obtained by modifying and shifting the received signal;

[0186] Perform clock data recovery on the received signal according to the clock signal and the feedback signal to generate a clock data recovery signal.

[0187] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0188] Filtering the received signal to obtain a control signal corresponding to the received signal;

[0189] determining an orthogonal clock signal pair from a preset multi-phase clock signal according to a control signal;

[0190] Interpolation processing is performed on the orthogonal clock signal pair to obtain a clock signal.

[0191] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like.

[0192] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0193] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A signal processing device, characterized in that The signal processing device includes: a clock recovery circuit and an equalization circuit; the equalization circuit includes a level feedback circuit, a correction unit and a plurality of parallel shifting units; each of the shifting units performs a level shifting process with a different value; The clock recovery circuit is used to generate a clock signal for the received signal; Each of the shifting units is configured to perform signal level shifting, signal level determination, and signal level sampling processing according to the clock signal and the corrected received signal output by the correcting unit to obtain a plurality of data signals; The level feedback circuit is used to perform nonlinear equalization processing on the data signals output by each of the shift units, and to feed back and output a new data signal; The correction unit is configured to sum the received signal and the data signal output by the level feedback circuit to obtain a corrected received signal; The equalization circuit is used to perform clock data recovery on the received signal according to the clock signal and the data signal output by the level feedback circuit to obtain a clock data recovery signal.

2. The signal processing device according to claim 1, wherein Each of the shifting units includes a level shifting subunit, a signal decision subunit and a signal sampling subunit; The level shift subunit is configured to perform level shifting on the corrected received signal to obtain a reference level; The signal decision subunit is configured to perform zero-crossing detection on the corrected received signal according to the reference level to generate a thermometer code; The signal sampling subunit is used to perform center sampling and edge sampling on the thermometer code to obtain the data signal.

3. The signal processing device according to claim 1, wherein The input signal of the signal processing device is a four-level modulated signal.

4. The signal processing device according to any one of claims 1 to 3, characterized in that: The clock recovery circuit includes an oscillation unit and a buffer unit; The oscillation unit is configured to provide the clock signal to the equalization circuit through the buffer unit.

5. The signal processing device according to claim 4, characterized in that The oscillation unit includes a phase interpolation subunit and a phase selection subunit; The phase selection subunit is configured to send a quadrature clock signal pair to the phase interpolation subunit; The phase interpolation subunit is used to perform interpolation processing on the orthogonal clock signal pair to generate the clock signal and send the clock signal to the buffer unit. The signal processing device according to claim 5 , wherein: The oscillation unit also includes a clock generating subunit; The clock generating subunit is configured to generate a multi-phase clock signal according to a reference clock signal, and send the multi-phase clock signal to the phase selecting subunit.

7. The signal processing device according to any one of claims 1 to 3, characterized in that: The signal processing device further includes an analog filtering circuit; The analog filtering circuit is used to filter the received signal and send the filtered received signal to the equalization circuit and the clock recovery circuit respectively.

8. The signal processing device according to any one of claims 1 to 3, characterized in that: The signal processing device further includes a decoding circuit; The decoding circuit is used to decode the output signal of the equalization circuit to generate the clock data recovery signal.

9. A signal processing method, characterized in that: The method comprises: Acquire a clock signal and a data signal of a received signal; the data signal is output by a level feedback circuit in the signal processing device according to any one of claims 1 to 8; Perform clock and data recovery on the received signal according to the clock signal and the data signal to generate a clock and data recovery signal.

10. The method according to claim 9, characterized in that The obtaining of the clock signal of the received signal comprises: filtering the received signal to obtain a control signal corresponding to the received signal; determining, according to the control signal, a quadrature clock signal pair from a preset multi-phase clock signal; Interpolation processing is performed on the orthogonal clock signal pair to obtain the clock signal.

Images