Goa circuit and liquid crystal display panel

Abstract

The application relates to the technical field of liquid crystal display, and discloses a GOA circuit and a liquid crystal display panel, the GOA circuit comprising a charging module, a driving module and a pull-down module; the driving module is connected with the charging module, a top gate output end, a bottom gate output end, a first clock signal end, a second clock signal end and a shift signal end respectively; the charging module is connected with a higher-level shift signal end and a lower-level shift signal end respectively; a connection end of the charging module and the driving module is connected with the pull-down module; the top gate output end is connected with a top gate of a double-gate pixel transistor; and the bottom gate output end is connected with a bottom gate of the double-gate pixel transistor. Therefore, the application can solve the technical problem of optical defects such as residual image and crosstalk in a high-temperature environment.

Description

Technical Field

[0001] This application relates to the field of liquid crystal display technology, and in particular to a GOA circuit and a liquid crystal display panel. Background Technology

[0002] With the development of display technology, the reliability specifications of various electronic display products are constantly improving, requiring that the TFT devices in the display panel can work normally in high-temperature environments for a long time.

[0003] However, under high temperature conditions, the off-state current of TFTs (Thin Film Transistors) increases, and the leakage current of pixel TFTs intensifies. As a result, optical defects such as image retention and crosstalk (communication system crosstalk) are prone to occur at high temperatures.

[0004] Application content

[0005] The main purpose of this application is to propose a GOA circuit and a liquid crystal display panel, which aims to solve the technical problems of optical defects such as image retention and crosstalk in high-temperature environments.

[0006] To achieve the above objectives, this application provides a GOA circuit, which includes: a charging module, a driving module, and a pull-down module;

[0007] The driving module is connected to the charging module, the top gate output terminal, the bottom gate output terminal, the first clock signal terminal, the second clock signal terminal, and the shift signal terminal, respectively. The charging module is connected to the upper-level shift signal terminal and the lower-level shift signal terminal, respectively. The connection terminal between the charging module and the driving module is connected to the pull-down module. The top gate output terminal is externally connected to the top gate of the dual-gate pixel transistor, and the bottom gate output terminal is externally connected to the bottom gate of the dual-gate pixel transistor.

[0008] Optionally, the charging module includes a dual-grid charging unit, and the driving module includes a dual-grid driving unit;

[0009] The dual-gate driving unit is connected to the first clock signal terminal, the second clock signal terminal, the top gate output terminal, the bottom gate output terminal, the shift signal terminal, and the dual-gate charging unit, respectively. The dual-gate charging unit is connected to the upper-level shift signal terminal and the lower-level shift signal terminal, respectively.

[0010] Optionally, the dual-gate driving unit includes: a first transistor, a second transistor, a third transistor, and a first capacitor;

[0011] The first clock signal is connected to the first terminal of the first transistor and the first terminal of the third transistor, the second clock signal is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the top gate output terminal, the bottom gate output terminal is connected to the second terminal of the first transistor and the first terminal of the first capacitor, the control terminal of the first transistor is connected to the control terminal of the second transistor, the control terminal of the third transistor, the dual-gate charging unit and the second terminal of the first capacitor, and the second terminal of the third transistor is connected to the shift signal terminal.

[0012] Optionally, the dual-gate charging unit includes a fourth transistor and a fifth transistor;

[0013] The lower-level shift signal terminal is connected to the control terminal of the fourth transistor, the upper-level shift signal terminal is connected to the control terminal of the fifth transistor and the first terminal of the fifth transistor, the first terminal of the fourth transistor is connected to the second terminal of the fifth transistor and connected to the control terminal of the third transistor, and the second terminal of the fourth transistor is connected to the constant low voltage signal terminal.

[0014] Optionally, the drop-down module includes: a first drop-down unit and a second drop-down unit;

[0015] The first pull-down unit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor;

[0016] The second pull-down unit includes: the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, and the twenty-third transistor;

[0017] The first input signal, the control terminal of the eighth transistor, the second terminal of the eighth transistor and the second terminal of the tenth transistor are connected together; the first terminal of the eighth transistor, the second terminal of the ninth transistor and the control terminal of the tenth transistor are connected together; the control terminal of the ninth transistor, the control terminal of the eleventh transistor, the first terminal of the twelfth transistor and the control terminal of the first transistor are connected together; the first terminal of the tenth transistor, the first terminal of the eleventh transistor, the control terminal of the twelfth transistor, the control terminal of the thirteenth transistor, the control terminal of the fourteenth transistor and the control terminal of the fifteenth transistor are connected together; the constant low voltage signal terminal, the first terminal of the ninth transistor, the second terminal of the eleventh transistor, the second terminal of the twelfth transistor, the second terminal of the thirteenth transistor, the second terminal of the fourteenth transistor and the second terminal of the fifteenth transistor are connected together; the first terminal of the thirteenth transistor is connected to the shift signal terminal; the first terminal of the fourteenth transistor is connected to the top gate output terminal; and the first terminal of the fifteenth transistor is connected to the bottom gate output terminal.

[0018] The second input signal, the second terminal of the sixteenth transistor, the control terminal of the sixteenth transistor, and the second terminal of the eighteenth transistor are all connected together. The first terminal of the sixteenth transistor, the second terminal of the seventeenth transistor, and the control terminal of the eighteenth transistor are all connected together. The control terminals of the seventeenth transistor, the nineteenth transistor, and the twentieth transistor are all connected together. The first terminals of the seventeenth transistor, the nineteenth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, and the twentieth transistor are all connected together. The second terminal of the twentieth transistor is connected to the shift signal terminal. The second terminal of the twentieth transistor is connected to the top gate output terminal. The second terminal of the twentieth transistor is connected to the bottom gate output terminal.

[0019] Optionally, the charging module includes a bottom grid charging unit and a top grid charging unit, and the driving module includes a bottom grid driving unit and a top grid driving unit;

[0020] The bottom gate driving unit is connected to the first clock signal terminal, the bottom gate output terminal, the shift signal terminal and the bottom gate charging unit respectively, and the bottom gate charging unit is connected to the upper-level shift signal terminal and the lower-level shift signal terminal respectively;

[0021] The top gate driving unit is connected to the second clock signal terminal, the top gate output terminal and the top gate charging unit respectively, and the top gate charging unit is connected to the upper-level top gate output terminal, the lower-level top gate output terminal and the bottom gate charging unit respectively;

[0022] The pull-down unit is connected to the bottom gate charging unit, the top gate charging unit, the bottom gate driving unit, and the top gate charging unit, respectively.

[0023] Optionally, the bottom gate driving unit includes a first transistor, a third transistor, and a first capacitor, and the top gate driving unit includes a second transistor and a second capacitor;

[0024] The first clock signal terminal is connected to the first terminal of the first transistor and the first terminal of the third transistor, respectively. The second terminal of the third transistor is connected to the shift signal terminal. The control terminal of the first transistor is connected to the control terminal of the third transistor. The bottom gate output terminal is connected to the second terminal of the first transistor and the first terminal of the first capacitor, respectively. The connection terminal of the first transistor and the third transistor is connected to the second terminal of the first capacitor. The control terminal of the first transistor, the control terminal of the third transistor, and the bottom gate charging unit are all connected together.

[0025] The second clock signal terminal is connected to the second terminal of the second transistor, the top gate output terminal is connected to the first terminal of the second transistor and the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the control terminal of the second transistor and the top gate charging unit.

[0026] Optionally, the bottom gate charging unit includes a fourth transistor and a fifth transistor, and the top gate charging unit includes a sixth transistor and a seventh transistor;

[0027] The lower-level shift signal terminal is connected to the control terminal of the fourth transistor, the upper-level shift signal terminal is connected to the control terminal of the fifth transistor and the first terminal of the fifth transistor respectively, and the first terminal of the fourth transistor is connected to the second terminal of the fifth transistor and connected to the control terminal of the third transistor.

[0028] The lower-level top gate output terminal is connected to the control terminal of the sixth transistor. The upper-level top gate output terminal is connected to the first terminal of the seventh transistor and the control terminal of the seventh transistor. The first terminal of the sixth transistor is connected to the second terminal of the seventh transistor and connected to the control terminal of the second transistor. The second terminal of the sixth transistor, the second terminal of the fourth transistor, and the constant low voltage signal terminal are connected together.

[0029] Optionally, the drop-down module includes: a first drop-down unit and a second drop-down unit;

[0030] The first pull-down unit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a twenty-fourth transistor, and a twenty-fifth transistor;

[0031] The second pull-down unit includes: the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-sixth transistor, and the twenty-seventh transistor;

[0032] The first input signal terminal, the control terminal of the eighth transistor, the second terminal of the eighth transistor, and the second terminal of the tenth transistor are all connected together. The first terminal of the eighth transistor, the second terminal of the ninth transistor, and the control terminal of the tenth transistor are all connected together. The control terminals of the ninth transistor, the eleventh transistor, the twelfth transistor, the twenty-fifth transistor, and the first transistor are all connected together. The first terminal of the tenth transistor, the eleventh transistor, the twenty-fourth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are all connected together. The constant low voltage signal terminal, the first terminal of the ninth transistor, the eleventh transistor, the twenty-fourth transistor, the twelfth transistor, the twenty-fifth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are all connected together. The first terminal of the thirteenth transistor is connected to the shift signal terminal. The first terminal of the fourteenth transistor is connected to the top gate output terminal. The first terminal of the fifteenth transistor is connected to the bottom gate output terminal.

[0033] The second input signal terminal, the second terminal of the sixteenth transistor, the control terminal of the sixteenth transistor, and the second terminal of the eighteenth transistor are all connected together. The first terminal of the sixteenth transistor, the second terminal of the seventeenth transistor, and the control terminal of the eighteenth transistor are all connected together. The control terminals of the seventeenth transistor, the nineteenth transistor, and the first transistor are all connected together. The first terminal of the seventeenth transistor, the first terminal of the nineteenth transistor, the second terminal of the twenty-sixth transistor, the first terminal of the twenty-tenth transistor, the second terminal of the twenty-seventh transistor, the first terminal of the twenty-first transistor, the first terminal of the twenty-second transistor, the first terminal of the twenty-third transistor, and the constant low voltage signal terminal are all connected together. The first terminal of the eighteenth transistor, the second terminal of the nineteenth transistor, the first terminal of the twenty-sixth transistor, the control terminal of the twenty-fifth transistor, the control terminal of the twenty-seventh transistor, the control terminal of the twenty-second transistor, and the control terminal of the twenty-third transistor are all connected together. The second terminal of the twenty-first transistor is connected to the shift signal terminal. The second terminal of the twenty-second transistor is connected to the top gate output terminal. The second terminal of the twenty-third transistor is connected to the bottom gate output terminal. The control terminals of the twenty-fourth transistor, the twenty-sixth transistor, the twenty-tenth transistor, the twenty-seventh transistor, and the second transistor are all connected together.

[0034] Optionally, the GOA circuit further includes: a reset unit;

[0035] The reset unit is connected to the reset signal terminal, the constant low voltage signal terminal, and the charging module, respectively.

[0036] In addition, to achieve the above objectives, this application provides a liquid crystal display panel, which includes the GOA circuit and dual-control-terminal pixel transistors as described above.

[0037] This application provides a GOA circuit, comprising: a charging module, a driving module, and a pull-down module. The charging module is connected to the driving module, a top gate output terminal, a bottom gate output terminal, a first clock signal terminal, a second clock signal terminal, and a shift signal terminal. The charging module is also connected to the upper-level shift signal terminal and the lower-level shift signal terminal. The connection terminal between the charging module and the driving module is connected to the pull-down module. The top gate output terminal is externally connected to the top gate of a dual-control pixel transistor, and the bottom gate output terminal is externally connected to the bottom gate of the dual-control pixel transistor. This application achieves the control of the top and bottom gates of the dual-control pixel transistor by the driving module based on the first and second clock signals, thereby obtaining a smaller off-current for non-scanning line pixels and a larger on-current for scanning lines. This prevents optical defects such as image retention and crosstalk in high-temperature environments. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the framework structure of an embodiment of the GOA circuit of this application;

[0039] Figure 2 This is a schematic diagram illustrating the application of the control pixel transistor in the GOA circuit of this application;

[0040] Figure 3 This is a schematic diagram of the film layer architecture of the dual-gate pixel transistor in the GOA circuit of this application;

[0041] Figure 4 This is a schematic diagram showing the connection between the charging module and the driving module of the GOA circuit in this application;

[0042] Figure 5 This is a schematic diagram of the pull-down module frame of an embodiment of the GOA circuit of the present invention;

[0043] Figure 6 This is a circuit connection diagram of one embodiment of the GOA circuit of the present invention;

[0044] Figure 7 This is a schematic diagram showing the connection between the charging module and the driving module of the GOA circuit in this application;

[0045] Figure 8 This is a circuit connection diagram of another embodiment of the GOA circuit of the present invention.

[0046] Explanation of icon numbers:

[0047]

[0048]

[0049] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0050] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0052] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0053] In this application, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0054] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0055] This application provides a GOA circuit.

[0056] In one embodiment of this application, reference is made to Figure 1 , Figure 2 and Figure 3 , Figure 1 This is a schematic diagram of the framework structure of an embodiment of the GOA circuit of this application. Figure 2 This is a schematic diagram illustrating the application of the control pixel transistor in the GOA circuit of this application. Figure 3 This is a schematic diagram of the film layer architecture of the dual-gate pixel transistor in the GOA circuit of this application. The GOA circuit includes: a charging module 20, a driving module 10, and a pull-down module 30.

[0057] The driving module 10 is connected to the charging module 20, the top gate output terminal Gn_u, the bottom gate output terminal Gn_d, the first clock signal terminal CLK, the second clock signal terminal CK, and the shift signal terminal Zn. The charging module 20 is connected to the upper-level shift signal terminal Zn-N and the lower-level shift signal terminal Zn+N. The connection terminal of the charging module 20 and the driving module 10 is connected to the pull-down module 30. The top gate output terminal Gn_u is externally connected to the top gate of the dual-gate pixel transistor, and the bottom gate output terminal Gn_d is externally connected to the bottom gate of the dual-gate pixel transistor.

[0058] In this embodiment, as Figure 2 As shown, each row of GOA circuits is connected to each dual-gate pixel transistor. The GOA circuit is connected to the top gate of the dual-gate pixel transistor through the top gate output terminal Gn_u, and to the bottom gate of the dual-gate pixel transistor through the bottom gate output terminal Gn_d. The dual-gate pixel transistor is a dual-gate pixel TFT (Thin Film Transistor). Figure 3 As shown, the dual-gate pixel transistor includes a bottom gate M1, a top gate M3, a source / drain M2, and a glass substrate GLASS. Compared to traditional single-gate transistors, the dual-gate pixel transistor includes a top gate and a bottom gate, where M1, M2, and M3 are all metals.

[0059] In this embodiment, the top gate output terminal Gn_u and the bottom gate output terminal Gn_d are the output signals of this stage, and the shift signal terminal Zn is the shift signal of this stage. The charging module 20 operates after receiving the high level of the upper-level shift signal terminal Zn-N or the initial signal input, and further increases the potential of the Q point through the capacitive coupling effect by raising the first clock signal CLK from low level to high level, so that the driving module 10 operates, so as to control the top gate of the dual-gate pixel transistor through the top gate output terminal Gn_u and the bottom gate of the dual-gate pixel transistor through the bottom gate output terminal Gn_d. The bottom gate and the top gate together control the dual-gate pixel transistor, thereby reducing the off-state current of the non-scanning line and increasing the on-state current of the scanning line in the high-temperature environment, thereby reducing the leakage current of the pixel transistor and solving the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) at high temperatures.

[0060] In this embodiment, the shift signal terminal Zn is the shift signal of this stage. The upper shift signal terminal is Zn-N, and the lower shift signal terminal is Zn+N. That is, the signal output by the shift signal terminal Zn is the signal of this stage, the upper shift signal terminal Zn-N outputs the shift signal of the Nth stage above, and the lower shift signal terminal Zn-N outputs the shift signal of the Nth stage below.

[0061] For example, the upper-level shift signal terminal Zn-N can specifically be Zn-4, meaning the charging module 20 receives the shift signal from the upper 4th stage. The lower-level shift signal terminal Zn+N can specifically be Zn-5, meaning the charging module 20 sends the shift signal to the lower 5th stage shift signal terminal. Since the shift signal terminal Zn is independent of the output terminal Gn (i.e., the top gate output terminal Gn_u and the bottom gate output terminal Gn_d), the output signal and the shift signal are separated. Therefore, when a short circuit occurs in the signal of this stage, it does not affect the shift of the entire circuit.

[0062] For example, when the first clock signal terminal CLK and the second clock signal terminal CK are synchronized clock signals, a smaller off-state current for non-scanning rows and a larger on-state current for scanning rows are obtained. When the first clock signal terminal CLK and the second clock signal terminal CK are different clock signals, the pixel bottom gate and top gate of the non-scanning rows have a smaller off-state current, the pixel bottom gate of the scanning rows can be normally turned on with a higher input voltage, and the top gate voltage can be switched according to the usage scenario, or even be in a floating state to reduce power consumption and load.

[0063] It should be noted that the control terminal of a transistor is the gate, the first terminal is the drain, and the second terminal is the source.

[0064] Optionally, in some feasible embodiments, reference is made to Figure 4 , Figure 4 This is a connection diagram of a charging module and a driving module of the GOA circuit of this application. The charging module 20 includes a dual-gate charging unit 21, and the driving module 10 includes a dual-gate driving unit 11.

[0065] The dual-gate driving unit 11 is connected to the first clock signal terminal CLK, the second clock signal terminal CK, the top gate output terminal Gn_u, the bottom gate output terminal Gn_d, the shift signal terminal Zn, and the dual-gate charging unit 21, respectively. The dual-gate charging unit 21 is connected to the upper-level shift signal terminal Zn-N and the lower-level shift signal terminal Zn+N, respectively.

[0066] In this embodiment, the top gate output terminal Gn_u and the bottom gate output terminal Gn_d are the output signals of this stage, and the shift signal terminal Zn is the shift signal of this stage. The dual-gate charging unit 21 operates after receiving the high level of the upper-level shift signal terminal Zn-N or the initial signal input, and further increases the potential of the Q point through the first clock signal CLK to enable the dual-gate driving unit 11 to operate, so as to control the top gate of the dual-gate pixel transistor through the top gate output terminal Gn_u and control the bottom gate of the dual-gate pixel transistor through the bottom gate output terminal Gn_d. The bottom gate and the top gate together control the dual-gate pixel transistor, thereby reducing the off-state current of the non-scanning line and increasing the on-state current of the scanning line in a high-temperature environment, thereby reducing the leakage current of the pixel transistor and solving the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) at high temperatures.

[0067] It should be noted that the dual-gate charging unit 21 charges the top gate drive and the bottom gate drive simultaneously, thereby enabling the dual-gate driving unit 11 to control the top gate and bottom gate of the dual-gate pixel transistor respectively. This reduces the off-state current of the non-scanning line and increases the on-state current of the scanning line in high-temperature environments, thereby reducing the leakage current of the pixel transistor and solving the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) at high temperatures.

[0068] Optionally, in some feasible embodiments, reference is made to Figure 6 , Figure 6 This is a circuit connection diagram of an embodiment of the GOA circuit of the present invention. The dual-gate driving unit 11 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1.

[0069] The first clock signal CLK is connected to the first terminal of the first transistor T1 and the first terminal of the third transistor T3, respectively. The second clock signal CK is connected to the first terminal of the second transistor T2. The second terminal of the second transistor T2 is connected to the top gate output terminal Gn_u. The bottom gate output terminal Gn_d is connected to the second terminal of the first transistor T2 and the first terminal of the first capacitor C1, respectively. The control terminal of the first transistor T1 is connected to the control terminal of the second transistor T2, the control terminal of the third transistor T3, the dual-gate charging unit 21, and the second terminal of the first capacitor C1, respectively. The second terminal of the third transistor T3 is connected to the shift signal terminal Zn.

[0070] In this embodiment, when the upper-level unit or initial signal input of the charging module 20 is high, the charging module 20 charges point Q and the first capacitor C1. The potential of point Q is further increased by the first clock signal CLK, so that the first transistor T1 and the second transistor T2 are fully turned on. The first transistor T1 and the second transistor T2 are driving transistors. The top gate output terminal Gn_u and the bottom gate output terminal Gn_d output high levels to turn on the pixel operation of the dual-gate pixel transistor. Thus, the first-level GOA circuit controls the top gate and bottom gate of the dual-gate pixel transistor respectively. By controlling the top gate and bottom gate of the dual-gate pixel transistor respectively through two driving transistors (the first transistor T1 and the second transistor T2 respectively), the off-state current of the non-scanning line and the on-state current of the scanning line are reduced in high-temperature environment. In turn, the leakage current of the pixel transistor is reduced, and the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) occur at high temperatures are solved.

[0071] It should be noted that when the first clock signal terminal CLK and the second clock signal terminal CK are synchronized clock signals, a smaller off-state current for non-scanning rows and a larger on-state current for scanning rows are obtained. When the first clock signal terminal CLK and the second clock signal terminal CK are different clock signals, the pixel bottom gate and top gate of the non-scanning rows have a smaller off-state current, the pixel bottom gate of the scanning rows can be normally turned on with a higher input voltage, and the top gate voltage can be switched according to the usage scenario, or even left floating to reduce power consumption and load.

[0072] Optionally, in some feasible embodiments, reference is made to Figure 5 , Figure 5 This is a schematic diagram of the pull-down module of an embodiment of the GOA circuit of the present invention. The dual-gate charging unit 21 includes: a fourth transistor T4 and a fifth transistor T5.

[0073] The lower-level shift signal terminal Zn+N is connected to the control terminal of the fourth transistor T4. The upper-level shift signal terminal Zn-N is connected to the control terminal of the fifth transistor T5 and the first terminal of the fifth transistor T5, respectively. The first terminal of the fourth transistor T4 is connected to the second terminal of the fifth transistor T5 and connected to the control terminal of the third transistor T3. The second terminal of the fourth transistor is connected to the constant low voltage signal terminal.

[0074] In this embodiment, the third transistor T3 is connected to the shift signal terminal Zn to control the dual-gate charging unit 21, the fourth transistor T4 is connected to the lower-level shift signal terminal Zn+N, and the fifth transistor T5 is connected to the upper-level shift signal terminal Zn-N. This reduces the load on the shift signal and also prevents the shift function of GOA from being affected when the output signal is abnormal.

[0075] In this embodiment, the dual-gate driving unit 11 includes a first capacitor C1. The first capacitor is charged by the dual-gate charging unit 21. Thus, the top gate and bottom gate of the dual-gate pixel transistor are controlled to be turned on by two driving transistors (the first transistor T1 and the second transistor T2, respectively). This reduces the off-state current of the non-scanning line and increases the on-state current of the scanning line in a high-temperature environment. In turn, it reduces the leakage current of the pixel transistor and solves the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) at high temperatures.

[0076] Optionally, in some feasible embodiments, reference is made to Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the pull-down module of an embodiment of the GOA circuit of the present invention. The pull-down module 30 includes: a first pull-down unit 31 and a second pull-down unit 32.

[0077] The first pull-down unit 31 includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15;

[0078] The second pull-down unit 32 includes: the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23;

[0079] The first input signal terminal V1, the control terminal of the eighth transistor T8, the second terminal of the eighth transistor T8, and the second terminal of the tenth transistor T10 are all connected together. The first terminal of the eighth transistor T8, the second terminal of the ninth transistor T9, and the control terminal of the tenth transistor T10 are all connected together. The control terminal of the ninth transistor T9, the control terminal of the eleventh transistor T11, the first terminal of the twelfth transistor T12, and the control terminal of the first transistor T1 are all connected together. The first terminal of the tenth transistor T10, the first terminal of the eleventh transistor T11, the control terminal of the twelfth transistor T12, and the control terminal of the thirteenth transistor T13 are all connected together. The control terminals of the fourteenth transistor T14 and the fifteenth transistor T15 are connected together. The constant low voltage signal terminal VGL, the first terminal of the ninth transistor T9, the second terminal of the eleventh transistor T11, the second terminal of the twelfth transistor T12, the second terminal of the thirteenth transistor T13, the second terminal of the fourteenth transistor T14, and the second terminal of the fifteenth transistor T15 are all connected together. The first terminal of the thirteenth transistor T13 is connected to the shift signal terminal Zn. The first terminal of the fourteenth transistor T14 is connected to the top gate output terminal Gn_u. The first terminal of the fifteenth transistor T15 is connected to the bottom gate output terminal Gn_d.

[0080] The second input signal terminal V2, the second terminal of the sixteenth transistor T16, the control terminal of the sixteenth transistor T16, and the second terminal of the eighteenth transistor T18 are all connected together. The first terminal of the sixteenth transistor T16, the second terminal of the seventeenth transistor T17, and the control terminal of the eighteenth transistor T18 are all connected together. The control terminals of the seventeenth transistor T17, the nineteenth transistor T19, and the second terminal of the twentieth transistor T20 are all connected together. The first terminals of the seventeenth transistor T17, the nineteenth transistor T19, the twentieth transistor T20, the twentyth transistor T21, and the twenty-second transistor T20 are all connected together. The first terminal of transistor T22, the first terminal of transistor T23, and the constant low voltage signal terminal VGL are all connected together. The first terminal of transistor T18, the second terminal of transistor T19, the control terminal of transistor T20, the control terminal of transistor T21, the control terminal of transistor T22, and the control terminal of transistor T23 are all connected together. The second terminal of transistor T21 is connected to the shift signal terminal Zn. The second terminal of transistor T22 is connected to the top gate output terminal Gn_u. The second terminal of transistor T23 is connected to the bottom gate output terminal Gn_d.

[0081] It should be noted that the constant low voltage signal terminal VGL is Vgate low, which is the low potential (low voltage) of the gate stage.

[0082] In this embodiment, if the charging module 20 is turned off, when the first clock signal CLK switches to a low level, the Q-point potential gradually decreases, the signal of the first signal input terminal V1 of the first pull-down unit 31 is turned on, the gate QB1 node of the pull-down transistor, i.e., the eleventh transistor T11, is written with a high level, the eleventh transistor T11 is turned on, further pulling down the Q-point potential while maintaining a low level during the non-scanning phase, the second signal input terminal V2 of the second pull-down unit 32 remains at a low level and is in a closed state. The two sets of pull-down units, the first pull-down unit 31 and the second pull-down unit 32, work alternately. Due to the voltage shift caused by long-term operation, the individual transistors of the pull-down module 30, as well as the first input signal terminal V1 and the second input signal terminal V2, are protected. Furthermore, by alternating the operation of the first pull-down unit 31 and the second pull-down unit 32, when the charging module 20 is turned off and the first clock signal CLK is switched to a low level, the Q point potential is further pulled down. The top gate and bottom gate of the dual-gate pixel transistor are controlled to be turned on by the two driving transistors (the first transistor T1 and the second transistor T2, respectively). In this way, the off-state current of the non-scanning line and the on-state current of the scanning line are reduced in high-temperature environments. In turn, the leakage current of the pixel transistor is reduced, and the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) that occur at high temperatures are solved.

[0083] For example, when the signal at the first signal input terminal V1 is high, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned on, while the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23 are turned off, further lowering the Q-point potential while maintaining a low level during the non-scanning phase. When the signal at the second signal input terminal V2 is high, transistors T8, T9, T10, T11, T12, T13, T14, and T15 are turned off, while transistors T16, T17, T18, T19, T20, T21, T22, and T23 are turned on, further lowering the Q-point potential while maintaining a low level during the non-scanning phase.

[0084] Optionally, in some feasible embodiments, reference is made to Figure 7 , Figure 7 This is a connection diagram of another embodiment of the charging module and driving module of the GOA circuit of this application. The charging module 20 includes: a bottom gate charging unit 22 and a top gate charging unit 23. The driving module 10 includes: a bottom gate driving unit 12 and a top gate driving unit 13.

[0085] The bottom gate driving unit 12 is connected to the first clock signal terminal CLK, the bottom gate output terminal Gn_d, the shift signal terminal Zn, and the bottom gate charging unit 22, respectively. The bottom gate charging unit 22 is connected to the upper-level shift signal terminal Zn-N and the lower-level shift signal terminal Zn+N, respectively.

[0086] The top gate driving unit 13 is connected to the second clock signal terminal CK, the top gate output terminal Gn_u and the top gate charging unit 13 respectively, and the top gate charging unit 23 is connected to the upper-level top gate output terminal Gn_u-N, the lower-level top gate output terminal Gn_u+N and the bottom gate charging unit 22 respectively.

[0087] The pull-down module 30 is connected to the bottom grid charging unit 22, the top grid charging unit 23, the bottom grid driving unit 12, and the top grid charging unit 13, respectively.

[0088] It should be noted that, compared to Figure 6 In this embodiment, there are two Q points, namely Q1 and Q2. The pull-down module 30 pulls down the Q1 point between the bottom gate charging unit 22 and the bottom gate driving unit 12, and pulls down the Q2 point between the top gate charging unit 23 and the top gate driving unit 13. That is, the Q1 point and the Q2 point share the pull-down module 30, thereby saving layout space.

[0089] In this embodiment, the bottom gate charging unit 22 operates after receiving a high level from the upper shift signal terminal Zn-N or the initial signal input, and further increases the potential of point Q1 through the capacitive coupling effect by raising the first clock signal CLK from low level to high level, so that the bottom gate de-driving unit 12 operates, and controls the bottom gate of the dual-gate pixel transistor through the bottom gate output terminal Gn_d. The top gate charging unit 23 operates after receiving the top gate output signal Gn_u-N from the upper level, and further increases the potential of point Q2 through the second clock signal CK to enable the top gate driving unit 13 to operate. It controls the top gate of the dual-gate pixel transistor through the top gate output Gn_u, thereby controlling the top gate of the dual-gate pixel transistor through the top gate output Gn_u and the bottom gate of the dual-gate pixel transistor through the bottom gate output Gn_d. The bottom gate and the top gate together control the dual-gate pixel transistor, thereby reducing the off-state current of the non-scanning line and increasing the on-state current of the scanning line in high-temperature environments. In turn, it reduces the leakage current of the pixel transistor and solves the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) at high temperatures.

[0090] In this embodiment, when the bottom gate charging module 22 and the top gate charging module 23 charge points Q1 and Q2 respectively, different start-up voltages STV can be input. The first clock signal terminal CLK and the second clock signal terminal CK can also input different voltage values. Ultimately, the bottom gate voltage output through the bottom gate output terminal Gn_d and the top gate voltage output through the top gate output terminal Gn_u are also different. That is, the GOA unit circuit can contain two driving transistors and two sets of Q points, fully realizing independent control of the pixel bottom and top gates. The first-level GOA unit circuit can simultaneously output different high and low level states and control voltage values ​​for the bottom and top gates. Furthermore, by controlling the output of the bottom gate output terminal Gn_d and the top gate output terminal Gn_u through the start-up voltage STV, the switching between the panel single-gate mode and the dual-gate module can be achieved.

[0091] Optionally, in some feasible embodiments, reference is made to Figure 8 , Figure 8 This is a circuit connection diagram of another embodiment of the GOA circuit of the present invention. The bottom gate driving unit 12 includes: a first transistor T1, a third transistor T3 and a first capacitor C1, and the top gate driving unit 13 includes: a second transistor T2 and a second capacitor C2.

[0092] The first clock signal terminal CLK is connected to the first terminal of the first transistor T1 and the first terminal of the third transistor T3 respectively. The second terminal of the third transistor T3 is connected to the shift signal terminal at Zn. The control terminal of the first transistor T1 is connected to the control terminal of the third transistor T3. The bottom gate output terminal Gn_d is connected to the second terminal of the first transistor T1 and the first terminal of the first capacitor C1 respectively. The connection terminal of the first transistor T1 and the third transistor T3 is connected to the second terminal of the first capacitor C1. The control terminals of the first transistor, the third transistor, and the bottom gate charging unit are all connected together.

[0093] The second clock signal terminal CK is connected to the first terminal of the second transistor T2, the top gate output terminal Gn_u is connected to the first terminal of the second transistor T2 and the first terminal of the second capacitor C2 respectively, and the second terminal of the second capacitor C2 is connected to the control terminal of the second transistor T2.

[0094] In this embodiment, the bottom gate driving unit 12 drives the bottom gate of the dual-gate pixel transistor through the first transistor T1, and the top gate driving unit 13 drives the top gate of the dual-gate pixel transistor through the second transistor T2. Specifically, when the upper-level unit or the initial signal input of the bottom gate charging module 22 is high, the bottom gate charging module 22 charges point Q1 and the first capacitor C1. The potential of point Q1 is further increased by the first clock signal CLK to make the first transistor T1 fully turn on. The first transistor T1 is a driving transistor. The bottom gate output terminal Gn_d outputs a high level to enable the pixel operation of the bottom gate of the dual-gate pixel transistor. Thus, the bottom gate of the dual-gate pixel transistor is controlled by the first-level GOA circuit. When the input level is high, the top gate charging module 23 charges point Q2 and the second capacitor C2. The second clock signal CK is used to further increase the potential of point Q2, so that the second transistor T2 is fully turned on. The second transistor T2 is a driving transistor. The top gate output terminal Gn_u outputs a high level to turn on the pixel operation of the top gate of the dual-gate pixel transistor. Thus, the first-level GOA circuit controls the top gate of the dual-gate pixel transistor. The two driving transistors (the first transistor T1 and the second transistor T2) control the top gate and bottom gate of the dual-gate pixel transistor respectively. In high-temperature environments, the off-state current of the non-scanning line and the on-state current of the scanning line are reduced, thereby reducing the leakage current of the pixel transistor and solving the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) at high temperatures.

[0095] It should be noted that when the first clock signal terminal CLK and the second clock signal terminal CK are synchronized clock signals, a smaller off-state current for non-scanning rows and a larger on-state current for scanning rows are obtained. When the first clock signal terminal CLK and the second clock signal terminal CK are different clock signals, the off-state current of the pixel bottom gate and top gate of the non-scanning rows is smaller, the pixel bottom gate of the scanning rows can be normally turned on by inputting a higher voltage, and the top gate voltage can be switched according to the usage scenario, or even left floating to reduce power consumption and load. Furthermore, when the bottom gate charging module 22 and the top gate charging module 23 charge points Q1 and Q2 respectively, different start-up voltages STV can be input, and the first clock signal terminal CLK and the second clock signal terminal CK can also input different voltage values. Finally, the bottom gate voltage output by the bottom gate output terminal Gn_d and the top gate voltage output by the top gate output terminal Gn_u are also different. Moreover, by controlling the output of the bottom gate output terminal Gn_d and the top gate output terminal Gn_u by the start-up voltage STV, the switching between the single-gate mode and the dual-gate module of the panel can be realized.

[0096] Optionally, in some feasible embodiments, reference is made to Figure 8 The bottom gate charging unit 22 includes a fourth transistor T4 and a fifth transistor T5, and the top gate charging unit 23 includes a sixth transistor T6 and a seventh transistor T7.

[0097] The lower-level shift signal terminal Zn+N is connected to the control terminal of the fourth transistor T4, the upper-level shift signal terminal Zn-N is connected to the control terminal of the fifth transistor T5 and the first terminal of the fifth transistor T5 respectively, and the first terminal of the fourth transistor T4 is connected to the second terminal of the fifth transistor T5 and connected to the control terminal of the third transistor T3.

[0098] The lower-level top gate output terminal Gn_u+N is connected to the control terminal of the sixth transistor T6. The upper-level top gate output terminal Gn_u-N is connected to the first terminal of the seventh transistor T7 and the control terminal of the seventh transistor T7. The first terminal of the sixth transistor T6 is connected to the second terminal of the seventh transistor T7 and connected to the control terminal of the second transistor T2. The second terminal of the sixth transistor T6, the second terminal of the fourth transistor, and the constant low voltage signal terminal VGL are all connected together.

[0099] In this embodiment, the shift signal terminal Zn connected to the third transistor T3 serves as the shift signal output from the bottom gate to control the bottom gate charging unit 22. The upper-level shift signal terminal Zn-N is the shift signal from the upper N-pole. The upper-level shift signal terminal Zn-N controls the fourth transistor T4 to charge point Q1 and the first transistor T1 respectively. The top gate output terminal Gn_u connected to the second transistor T2 serves as the shift signal output from the top gate to control the top gate charging unit 23. The upper-level top gate output signal terminal Gn_u-N is the shift signal from the upper N-pole. The upper-level top gate output signal terminal Gn_u-N controls the seventh transistor T7 to charge point Q2 and the second transistor T2 respectively. It should be noted that, compared to the charging module 20 and the driving module 1... Unlike the previous embodiment, in this embodiment, the fourth transistor T4 and the fifth transistor T5 charge the first capacitor C1, controlling only the first transistor T1 to drive the bottom gate of the dual-gate pixel transistor. In this embodiment, the sixth transistor T6 and the seventh transistor T7 charge the second capacitor C2, controlling only the second transistor T2 to drive the top gate of the dual-gate pixel transistor. Thus, by controlling the top and bottom gates of the dual-gate pixel transistor to be turned on by the two driving transistors (the first transistor T1 and the second transistor T2, respectively), the off-state current of the non-scanning line and the on-state current of the scanning line are reduced in high-temperature environments. In turn, the leakage current of the pixel transistor is reduced, and the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) at high temperatures are solved.

[0100] In this embodiment, the shift signal terminal Zn is the shift signal of this stage. The upper shift signal terminal is Zn-N, and the lower shift signal terminal is Zn+N. That is, the signal output by the shift signal terminal Zn is the signal of this stage, the upper shift signal terminal Zn-N outputs the shift signal of the Nth stage above, and the lower shift signal terminal Zn-N outputs the shift signal of the Nth stage below. The bottom gate charging unit 22 receives control from the shift signal terminal Zn, and the top gate charging unit 23 receives control from the top gate output terminal Gn_u.

[0101] Optionally, in some feasible embodiments, reference is made to Figure 5 and Figure 8 The pull-down module 30 includes: a first pull-down unit 31 and a second pull-down unit 32;

[0102] The first pull-down unit includes: the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the twenty-fourth transistor T24, and the twenty-fifth transistor T25;

[0103] The second pull-down unit includes: the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-sixth transistor T26, and the twenty-seventh transistor T27;

[0104] The first input signal terminal V1, the control terminal of the eighth transistor T8, the second terminal of the eighth transistor T8, and the second terminal of the tenth transistor T10 are all connected together. The first terminal of the eighth transistor T8, the second terminal of the ninth transistor T9, and the control terminal of the tenth transistor T10 are all connected together. The control terminal of the ninth transistor T9, the control terminal of the eleventh transistor T11, the first terminal of the twelfth transistor T12, the second terminal of the twenty-fifth transistor T25, and the control terminal of the first transistor T1 are all connected together. The first terminal of the tenth transistor T10, the first terminal of the eleventh transistor T11, the second terminal of the twenty-fourth transistor T24, the control terminal of the twelfth transistor T12, and the control terminal of the thirteenth transistor T13 are all connected together. The control terminals of the fourteenth transistor T14 and the fifteenth transistor T15 are connected together. The constant low voltage signal terminal VGL, the first terminal of the ninth transistor T9, the second terminal of the eleventh transistor T11, the first terminal of the twenty-fourth transistor T24, the second terminal of the twelfth transistor T12, the first terminal of the twenty-fifth transistor T25, the second terminal of the thirteenth transistor T13, the second terminal of the fourteenth transistor T14, and the second terminal of the fifteenth transistor T15 are all connected together. The first terminal of the thirteenth transistor T13 is connected to the shift signal terminal. The first terminal of the fourteenth transistor T14 is connected to the top gate output terminal Gn_d. The first terminal of the fifteenth transistor T15 is connected to the bottom gate output terminal Gn_u.

[0105] The second input signal terminal V2, the second terminal of the sixteenth transistor T16, the control terminal of the sixteenth transistor T16, and the second terminal of the eighteenth transistor T18 are all connected together. The first terminal of the sixteenth transistor T16, the second terminal of the seventeenth transistor T17, and the control terminal of the eighteenth transistor T18 are all connected together. The control terminals of the seventeenth transistor T17, the nineteenth transistor T19, and the first terminal of the first transistor T1 are all connected together. The first terminals of the seventeenth transistor T17, the nineteenth transistor T19, the twenty-sixth transistor T26, the twentieth transistor T20, the twenty-seventh transistor T27, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, and the constant low voltage signal terminal are all connected together. VGL is connected in common. The first terminal of the eighteenth transistor T18, the second terminal of the nineteenth transistor T19, the first terminal of the twenty-sixth transistor T26, the control terminal of the twenty-fifth transistor T25, the control terminal of the twenty-seventh transistor T27, the control terminal of the twenty-second transistor T22, and the control terminal of the twenty-third transistor T23 are all connected in common. The second terminal of the twenty-first transistor T21 is connected to the shift signal terminal Zn. The second terminal of the twenty-second transistor T22 is connected to the top gate output terminal Gn_d. The second terminal of the twenty-third transistor T23 is connected to the bottom gate output terminal Gn_u. The control terminals of the twenty-fourth transistor T24, the twenty-sixth transistor T26, the second terminal of the twentyth transistor T20, the first terminal of the twenty-seventh transistor T27, and the control terminal of the second transistor T2 are connected in common.

[0106] In this embodiment, a twenty-fourth transistor T24 and a twenty-fifth transistor T25 are added to the first pull-down unit 31, and a twenty-sixth transistor T26 and a twenty-seventh transistor T27 are added to the second pull-down unit 32. When the bottom gate charging unit 22 and the top gate charging unit 23 are turned off, and the first clock signal CLK and the second clock signal CK are switched to low level, the potentials of points Q1 and Q2 gradually decrease. The first pull-down unit 31 and the second pull-down unit 32 keep points Q1 and Q2 at a low level. Furthermore, the first pull-down unit 31 and the second pull-down unit 32 can work alternately. When the potentials of points Q1 and Q2 gradually decrease, points Q1 and Q2 are kept at a low level. The top gate and bottom gate of the dual-gate pixel transistor are controlled to be turned on by two driving transistors (the first transistor T1 and the second transistor T2, respectively). Thus, the off-state current of the non-scanning line and the on-state current of the scanning line are reduced in high-temperature environments. In turn, the leakage current of the pixel transistor is reduced, and the technical problems of optical defects such as image retention and crosstalk (communication system crosstalk) that occur at high temperatures are solved.

[0107] Additionally, it should be noted that when the top gate at point Q2 is in a floating state, the first pull-down unit 31 and the second pull-down unit 32 only keep the potential at point Q1 at a low level.

[0108] refer to Figure 6 and Figure 8 The GOA circuit further includes a reset unit 40; the reset unit 40 is connected to the reset signal terminal RESET, the constant low voltage signal terminal VGL, and the charging module 20.

[0109] In this embodiment, the reset unit 40 includes a twenty-eighth transistor T28. The gate of the twenty-eighth transistor T28 is connected to the reset signal terminal RESET, the drain of the twenty-eighth transistor T28 is connected to the charging module 20 and the driving module 10 respectively, and the source of the twenty-eighth transistor T28 is connected to the constant low voltage signal terminal VGL. The reset unit 40 operates during the non-display stage to prevent residual charge in the GOA circuit and reset the voltage of the working node in the circuit without affecting the operation of the GOA circuit. This application realizes that based on the first clock signal and the second clock signal, the top gate and bottom gate of the dual-gate pixel transistor are controlled by the driving module respectively, thereby obtaining a smaller off-current of non-scanning line pixels and a larger on-current of scanning lines. Thus, in high-temperature environments, it prevents optical defects such as image retention and crosstalk (communication system crosstalk).

[0110] For example, such as Figure 6 As shown, the gate of the twenty-eighth transistor T28 is connected to the reset signal terminal RESET. The drain of the twenty-eighth transistor T28 is connected to the source of the fifth transistor T5, the gate of the third transistor T3, the gate of the second transistor T2, and the gate of the first transistor T1, respectively. The source of the twenty-eighth transistor T28 is connected to the constant low voltage signal terminal VGL. Figure 8 As shown, the gate of the twenty-eighth transistor T28 is connected to the reset signal terminal RESET, the drain of the twenty-eighth transistor T28 is connected to the source of the fifth transistor T5, the gate of the third transistor T3, and the gate of the first transistor T1, respectively, and the source of the twenty-eighth transistor T28 is connected to the constant low voltage signal terminal VGL.

[0111] This application utilizes a GOA circuit comprising a charging module, a driving module, and a pull-down module. The charging module is connected to the driving module, a top-gate output terminal, a bottom-gate output terminal, a first clock signal terminal, a second clock signal terminal, and a shift signal terminal. The charging module is also connected to the upper-level shift signal terminal and the lower-level shift signal terminal. The connection between the charging module and the driving module is connected to the pull-down module. The top-gate output terminal is externally connected to the top gate of the dual-gate pixel transistor, and the bottom-gate output terminal is externally connected to the bottom gate of the dual-gate pixel transistor. This application achieves the control of the top and bottom gates of the dual-gate pixel transistor by the driving module based on the first and second clock signals, thereby obtaining a smaller off-current for non-scanning line pixels and a larger on-current for scanning lines. This prevents optical defects such as image retention and crosstalk (in communication systems) in high-temperature environments.

[0112] This application also proposes a liquid crystal display panel, which includes a GOA circuit and a dual-gate pixel transistor. The specific structure of the GOA circuit is as described in the above embodiments. The top gate output terminal of the GOA circuit is connected to the top gate of the dual-gate pixel transistor, and the bottom gate output terminal is connected to the bottom gate of the dual-gate pixel transistor. Since this liquid crystal display panel adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0113] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural transformations made based on the content of the specification and drawings of this application under the concept of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A GOA circuit, characterized by, The GOA circuit includes: a charging module, a driving module, and a pull-down module; The driving module is connected to the charging module, the top gate output terminal, the bottom gate output terminal, the first clock signal terminal, the second clock signal terminal, and the shift signal terminal, respectively. The charging module is connected to the upper-level shift signal terminal and the lower-level shift signal terminal, respectively. The connection terminal between the charging module and the driving module is connected to the pull-down module. The top gate output terminal is externally connected to the top gate of the dual-gate pixel transistor, and the bottom gate output terminal is externally connected to the bottom gate of the dual-gate pixel transistor. The drop-down module includes: a first drop-down unit and a second drop-down unit; The first pull-down unit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; The second pull-down unit includes: the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, and the twenty-third transistor; The first input signal, the control terminal of the eighth transistor, the second terminal of the eighth transistor and the second terminal of the tenth transistor are connected together; the first terminal of the eighth transistor, the second terminal of the ninth transistor and the control terminal of the tenth transistor are connected together; the control terminal of the ninth transistor, the control terminal of the eleventh transistor and the first terminal of the twelfth transistor are connected together; the first terminal of the tenth transistor, the first terminal of the eleventh transistor, the control terminal of the twelfth transistor, the control terminal of the thirteenth transistor, the control terminal of the fourteenth transistor and the control terminal of the fifteenth transistor are connected together; the constant low voltage signal terminal, the first terminal of the ninth transistor, the second terminal of the eleventh transistor, the second terminal of the twelfth transistor, the second terminal of the thirteenth transistor, the second terminal of the fourteenth transistor and the second terminal of the fifteenth transistor are connected together; the first terminal of the thirteenth transistor is connected to the shift signal terminal; the first terminal of the fourteenth transistor is connected to the top gate output terminal; and the first terminal of the fifteenth transistor is connected to the bottom gate output terminal. The second input signal, the second terminal of the sixteenth transistor, the control terminal of the sixteenth transistor, and the second terminal of the eighteenth transistor are all connected together. The first terminal of the sixteenth transistor, the second terminal of the seventeenth transistor, and the control terminal of the eighteenth transistor are all connected together. The control terminals of the seventeenth transistor, the nineteenth transistor, and the twentieth transistor are all connected together. The first terminals of the seventeenth transistor, the nineteenth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, the twentieth transistor, and the twentieth transistor are all connected together. The second terminal of the twentieth transistor is connected to the shift signal terminal. The second terminal of the twentieth transistor is connected to the top gate output terminal. The second terminal of the twentieth transistor is connected to the bottom gate output terminal.

2. The GOA circuit according to claim 1, wherein The charging module includes a dual-grid charging unit, and the driving module includes a dual-grid driving unit. The dual-gate driving unit is connected to the first clock signal terminal, the second clock signal terminal, the top gate output terminal, the bottom gate output terminal, the shift signal terminal, and the dual-gate charging unit, respectively. The dual-gate charging unit is connected to the upper-level shift signal terminal and the lower-level shift signal terminal, respectively.

3. The GOA circuit according to claim 2, wherein The dual-gate driving unit includes: a first transistor, a second transistor, a third transistor, and a first capacitor; The first clock signal is connected to the first terminal of the first transistor and the first terminal of the third transistor, the second clock signal is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the top gate output terminal, the bottom gate output terminal is connected to the second terminal of the first transistor and the first terminal of the first capacitor, the control terminal of the first transistor is connected to the control terminal of the second transistor, the control terminal of the third transistor, the dual-gate charging unit and the second terminal of the first capacitor, and the second terminal of the third transistor is connected to the shift signal terminal.

4. The GOA circuit according to claim 3, wherein The dual-gate charging unit includes: a fourth transistor and a fifth transistor; The lower-level shift signal terminal is connected to the control terminal of the fourth transistor, the upper-level shift signal terminal is connected to the control terminal of the fifth transistor and the first terminal of the fifth transistor, the first terminal of the fourth transistor is connected to the second terminal of the fifth transistor and connected to the control terminal of the third transistor, and the second terminal of the fourth transistor is connected to the constant low voltage signal terminal.

5. A GOA circuit, characterized in that, The GOA circuit includes: a charging module, a driving module, and a pull-down module; The driving module is connected to the charging module, the top gate output terminal, the bottom gate output terminal, the first clock signal terminal, the second clock signal terminal, and the shift signal terminal, respectively. The charging module is connected to the upper-level shift signal terminal and the lower-level shift signal terminal, respectively. The connection terminal between the charging module and the driving module is connected to the pull-down module. The top gate output terminal is externally connected to the top gate of the dual-gate pixel transistor, and the bottom gate output terminal is externally connected to the bottom gate of the dual-gate pixel transistor. The drop-down module includes: a first drop-down unit and a second drop-down unit; The first pull-down unit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a twenty-fourth transistor, and a twenty-fifth transistor; The second pull-down unit includes: the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-sixth transistor, and the twenty-seventh transistor; The first input signal terminal, the control terminal of the eighth transistor, the second terminal of the eighth transistor, and the second terminal of the tenth transistor are all connected together. The first terminal of the eighth transistor, the second terminal of the ninth transistor, and the control terminal of the tenth transistor are all connected together. The control terminals of the ninth transistor, the eleventh transistor, the twelfth transistor, the twenty-fifth transistor, and the first transistor are all connected together. The first terminal of the tenth transistor, the eleventh transistor, the twenty-fourth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are all connected together. The constant low voltage signal terminal, the first terminal of the ninth transistor, the eleventh transistor, the twenty-fourth transistor, the twelfth transistor, the twenty-fifth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are all connected together. The first terminal of the thirteenth transistor is connected to the shift signal terminal. The first terminal of the fourteenth transistor is connected to the top gate output terminal. The first terminal of the fifteenth transistor is connected to the bottom gate output terminal. The second input signal terminal, the second terminal of the sixteenth transistor, the control terminal of the sixteenth transistor, and the second terminal of the eighteenth transistor are all connected together. The first terminal of the sixteenth transistor, the second terminal of the seventeenth transistor, and the control terminal of the eighteenth transistor are all connected together. The control terminals of the seventeenth transistor, the nineteenth transistor, and the first transistor are all connected together. The first terminal of the seventeenth transistor, the first terminal of the nineteenth transistor, the second terminal of the twenty-sixth transistor, the first terminal of the twenty-tenth transistor, the second terminal of the twenty-seventh transistor, the first terminal of the twenty-first transistor, the first terminal of the twenty-second transistor, the first terminal of the twenty-third transistor, and the constant low voltage signal terminal are all connected together. The first terminal of the eighteenth transistor, the second terminal of the nineteenth transistor, the first terminal of the twenty-sixth transistor, the control terminal of the twenty-fifth transistor, the control terminal of the twenty-seventh transistor, the control terminal of the twenty-second transistor, and the control terminal of the twenty-third transistor are all connected together. The second terminal of the twenty-first transistor is connected to the shift signal terminal. The second terminal of the twenty-second transistor is connected to the top gate output terminal. The second terminal of the twenty-third transistor is connected to the bottom gate output terminal. The control terminals of the twenty-fourth transistor, the twenty-sixth transistor, the twenty-tenth transistor, the first terminal of the twenty-seventh transistor, and the second transistor are connected together.

6. The GOA circuit as described in claim 5, characterized in that, The charging module includes a bottom grid charging unit and a top grid charging unit, and the driving module includes a bottom grid driving unit and a top grid driving unit. The bottom gate driving unit is connected to the first clock signal terminal, the bottom gate output terminal, the shift signal terminal and the bottom gate charging unit respectively, and the bottom gate charging unit is connected to the upper-level shift signal terminal and the lower-level shift signal terminal respectively. The top gate driving unit is connected to the second clock signal terminal, the top gate output terminal and the top gate charging unit respectively, and the top gate charging unit is connected to the upper-level top gate output terminal, the lower-level top gate output terminal and the bottom gate charging unit respectively; The pull-down module is connected to the bottom grid charging unit, the top grid charging unit, the bottom grid driving unit, and the top grid charging unit, respectively.

7. The GOA circuit according to claim 6, wherein The bottom gate driving unit includes a first transistor, a third transistor, and a first capacitor; the top gate driving unit includes a second transistor and a second capacitor. The first clock signal terminal is connected to the first terminal of the first transistor and the first terminal of the third transistor, respectively. The second terminal of the third transistor is connected to the shift signal terminal. The control terminal of the first transistor is connected to the control terminal of the third transistor. The bottom gate output terminal is connected to the second terminal of the first transistor and the first terminal of the first capacitor, respectively. The connection terminal of the first transistor and the third transistor is connected to the second terminal of the first capacitor. The control terminal of the first transistor, the control terminal of the third transistor, and the bottom gate charging unit are all connected together. The second clock signal terminal is connected to the second terminal of the second transistor, the top gate output terminal is connected to the first terminal of the second transistor and the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the control terminal of the second transistor and the top gate charging unit.

8. The GOA circuit according to claim 7, wherein The bottom gate charging unit includes a fourth transistor and a fifth transistor, and the top gate charging unit includes a sixth transistor and a seventh transistor; The lower-level shift signal terminal is connected to the control terminal of the fourth transistor, the upper-level shift signal terminal is connected to the control terminal of the fifth transistor and the first terminal of the fifth transistor respectively, and the first terminal of the fourth transistor is connected to the second terminal of the fifth transistor and connected to the control terminal of the third transistor. The lower-level top gate output terminal is connected to the control terminal of the sixth transistor. The upper-level top gate output terminal is connected to the first terminal of the seventh transistor and the control terminal of the seventh transistor. The first terminal of the sixth transistor is connected to the second terminal of the seventh transistor and connected to the control terminal of the second transistor. The second terminal of the sixth transistor, the second terminal of the fourth transistor, and the constant low voltage signal terminal are connected together.

9. A liquid crystal display panel, characterized by comprising: The liquid crystal display panel includes the GOA circuit and dual-gate pixel transistor as described in any one of claims 1 to 4, 5 to 8.

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