Duplexer packaging substrate and duplexer

Abstract

This application provides a duplexer packaging substrate and a duplexer. The packaging substrate includes multiple wiring layers and multiple conductive vias disposed between adjacent wiring layers. The multiple wiring layers include a first wiring layer, a second wiring layer, and a third wiring layer located in the middle wiring layer. At least a portion of a first inductor and a first ground portion are disposed on the first wiring layer. The first inductor is connected to a transmitting filter through the conductive vias, and the transmitting filter is grounded through the conductive vias and the first ground portion. At least a portion of a second inductor and a second ground portion are disposed on the second wiring layer. The second inductor is connected to a receiving filter through the conductive vias, and the receiving filter is grounded through the conductive vias and the second ground portion. A third inductor and a fourth inductor are disposed on the third wiring layer. The area of ​​the first ground portion and / or the area of ​​the second ground portion is at least twice the area of ​​the conductive via connected to the inductor in the corresponding wiring layer.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to a duplexer packaging substrate and a duplexer. Background Technology

[0002] Currently, due to the comprehensive upgrade of mobile terminal radio frequency systems driven by 5G technology, and the exponential increase in the number of base station antenna channels, the demand for radio frequency filters or duplexers has also increased significantly to add communication functions to new frequency bands. With the continuous advancement of communication technology and mobile terminal manufacturing technology, the market's requirements for the size, power consumption, and performance of radio frequency filters are constantly increasing, leading to a growing demand for high-performance radio frequency filters. How to improve filter performance is currently a key research topic in the communications industry. Summary of the Invention

[0003] In view of this, embodiments of this application provide a packaging substrate for a duplexer and a duplexer.

[0004] In a first aspect, embodiments of this application provide a packaging substrate for a duplexer. The packaging substrate includes multiple wiring layers and multiple conductive vias disposed between adjacent wiring layers. The multiple wiring layers include a first wiring layer, a second wiring layer, and a third wiring layer located in the middle wiring layer. At least a portion of a first inductor and a first ground portion are disposed on the first wiring layer. The first inductor is connected to a transmitting filter through the conductive vias, and the transmitting filter is grounded through the conductive vias and the first ground portion. At least a portion of a second inductor and a second ground portion are disposed on the second wiring layer. The second inductor is connected to a receiving filter through the conductive vias, and the receiving filter is grounded through the conductive vias and the second ground portion. A third inductor and a fourth inductor are disposed on the third wiring layer. The third inductor is connected to the transmitting filter and the antenna terminal of the duplexer through conductive vias, respectively, and the fourth inductor is connected to the receiving filter and the antenna terminal of the duplexer through conductive vias, respectively. The area of ​​the first ground portion and / or the area of ​​the second ground portion are at least twice the area of ​​the conductive vias connected to the inductors in the corresponding wiring layers.

[0005] In some embodiments, the plurality of wiring layers further include: a fifth inductor disposed on the first wiring layer and connected to the I / O terminals of the transmitting filter and the duplexer respectively through conductive vias; and a sixth inductor disposed on the second wiring layer and connected to the I / O terminals of the receiving filter and the duplexer respectively through conductive vias.

[0006] In some embodiments, a first inductor, a third inductor, and a fifth inductor are disposed on a first side of a plurality of wiring layers, and a second inductor, a fourth inductor, and a sixth inductor are disposed on a second side of a plurality of wiring layers; wherein the first side and the second side are opposite sides of the plurality of wiring layers.

[0007] In some embodiments, the patterns of the first wiring layer and the second wiring layer both include an inductor pattern, a conductive via pattern, and a grounding pattern; the grounding pattern is arranged in the plane of the first wiring layer and / or in the plane of the second wiring layer, except for the inductor pattern and the conductive via pattern; wherein, in the plane of the first wiring layer, the inductor pattern includes at least a portion of the pattern of the first inductor, the conductive via pattern includes the pattern of the conductive via connected to the first wiring layer, and the grounding pattern includes the pattern of the first grounding portion; wherein, in the plane of the second wiring layer, the inductor pattern includes at least a portion of the pattern of the second inductor, the conductive via pattern includes the pattern of the conductive via connected to the second wiring layer, and the grounding pattern includes the pattern of the second grounding portion.

[0008] In some embodiments, a first inductor is disposed on a first wiring layer, and a second inductor is disposed on a second wiring layer; or, a first portion of a first inductor is disposed on a first wiring layer, a second portion is disposed on a second wiring layer, and a first portion of a second inductor is disposed on a second wiring layer, and a second portion is disposed on a first wiring layer.

[0009] In some embodiments, the first wiring layer, the second wiring layer, and the third wiring layer are adjacent wiring layers among a plurality of wiring layers.

[0010] In some embodiments, a third wiring layer is disposed between the first wiring layer and the second wiring layer.

[0011] In some embodiments, in the first wiring layer, the first inductor is connected to or not connected to the first ground portion, and / or, in the second wiring layer, the second inductor is connected to or not connected to the second ground portion.

[0012] In some embodiments, the projection of the first ground portion onto the surface of the third wiring layer may or may not overlap with the projection of the second ground portion onto the surface of the third wiring layer.

[0013] In some embodiments, the projection of the first ground portion on the surface of the third wiring layer does not overlap with the projection of the second ground portion on the surface of the third wiring layer; and the outer contour of the projection of the first ground portion on the surface of the third wiring layer covers the projection of the second inductor on the surface of the third wiring layer, and the outer contour of the projection of the second ground portion on the surface of the third wiring layer covers the projection of the first inductor on the surface of the third wiring layer.

[0014] In some embodiments, the outer contour of the pattern of the first ground portion includes a closed pattern, and all of the first wiring layer except for the pattern of the first ground portion is within the closed pattern; and / or, the outer contour of the pattern of the second ground portion includes a closed pattern, and all of the second wiring layer except for the pattern of the second ground portion is within the closed pattern.

[0015] In some embodiments, in the first wiring layer, the minimum spacing between the first inductor and the first ground portion is 0.5 times the minimum linewidth, and the minimum spacing between the conductive via connected to the first wiring layer and the first ground portion is 0.5 times the minimum linewidth; and / or, in the second wiring layer, the minimum spacing between the second inductor and the second ground portion is 0.5 times the minimum linewidth, and the minimum spacing between the conductive via connected to the second wiring layer and the second ground portion is 0.5 times the minimum linewidth.

[0016] In some embodiments, the number of conductive vias connected to the inductor in each wiring layer is at least 2; the number of conductive vias in the wiring layer is at least 5.

[0017] In some embodiments, the shape of the conductive via includes a circle, a rounded rectangle, or a dumbbell shape.

[0018] In some embodiments, the number of first inductors and / or the number of second inductors may include one or more.

[0019] In some embodiments, the third wiring layer is located outside the first wiring layer and the second wiring layer as a whole; the plurality of wiring layers further include: a fourth wiring layer located between the third wiring layer and the whole, for use as a separate ground layer.

[0020] In some embodiments, the plurality of wiring layers further include a first pad layer and a second pad layer located on opposite outer sides of the plurality of wiring layers; the first pad layer is used to include connecting a transmit filter and a receive filter to a package substrate; the second pad layer is used to include connecting a duplexer to other radio frequency devices.

[0021] In a second aspect, embodiments of this application provide a duplexer, which includes: a package substrate according to any one of the first aspects and a transmit filter and a receive filter located on the package substrate; wherein, the transmit filter is used to transmit a transmit signal to an antenna end; the receive filter is used to receive a signal from the antenna end; the transmit filter and the receive filter are connected to an inductor of the package substrate.

[0022] In various embodiments of this application, the first wiring layer, the second wiring layer, and the third wiring layer are located in the middle wiring layer of multiple wiring layers. The first inductor and the second inductor are disposed on different layers. The first inductor is disposed on the first wiring layer, and the second inductor is disposed on the second wiring layer. Furthermore, the area of ​​the first ground portion and / or the area of ​​the second ground portion are at least twice the area of ​​the conductive via connected to the inductor in the corresponding wiring layer. In this way, the first ground portion and / or the second ground portion, excluding the inductor and the conductive via, are large-area grounding in the first wiring layer and the second wiring layer, which can reduce the coupling between the first inductor and the second inductor and improve the isolation of the duplexer. Attached Figure Description

[0023] Figure 1A An equivalent circuit diagram of an example of a duplexer using the first type of packaged substrate provided in the embodiments of this application;

[0024] Figure 1B An equivalent circuit diagram of an example of a duplexer using the second type of packaging substrate provided in the embodiments of this application;

[0025] Figure 2 This is a cross-sectional schematic diagram of a packaging substrate provided in an embodiment of this application;

[0026] Figure 3A and Figure 3B These are schematic diagrams showing the planar layout of the first wiring layer and the second wiring layer of the packaging substrate, which serve as a first comparative example, provided in the embodiments of this application.

[0027] Figure 3C A perspective view of a packaging substrate provided as a first comparative example in an embodiment of this application;

[0028] Figure 4A , Figure 4B and Figure 4C These are schematic diagrams showing the planar layout of the first wiring layer, the second wiring layer, and the third wiring layer of the first type of packaging substrate provided in the embodiments of this application;

[0029] Figure 4D A top view schematic diagram of the first type of packaging substrate provided in the embodiments of this application;

[0030] Figure 4E A perspective view of a first type of packaging substrate provided in an embodiment of this application;

[0031] Figure 5 A graph showing the isolation between the TX and RX bands of the first type of packaging substrate of this application and the packaging substrate used as a first comparative example is shown.

[0032] Figure 6 A graph showing the isolation between the TX and RX bands of the first, third, and fifth packaging substrates of this application and the packaging substrate as a second comparative example is shown.

[0033] Figure 7 A graph showing the isolation between the TX and RX bands of the first type of packaging substrate, the sixth type of packaging substrate, and the packaging substrate as a second comparative example of this application is shown.

[0034] Figure 8 A graph showing the isolation between the TX and RX bands of the first type of packaging substrate, the sixth type of packaging substrate, and the packaging substrate as a second comparative example of this application is shown.

[0035] Figure 9 A graph showing the isolation between the TX and RX bands of the first type of packaging substrate, the third type of packaging substrate, and the packaging substrate as a second comparative example of this application is shown.

[0036] Figure 10A , Figure 10B and Figure 10C These are schematic diagrams showing the planar layout of the first wiring layer, the second wiring layer, and the third wiring layer of the second type of packaging substrate provided in the embodiments of this application;

[0037] Figure 11A , Figure 11B and Figure 11C These are schematic diagrams showing the planar layout of the first wiring layer, the second wiring layer, and the third wiring layer of the third type of packaging substrate provided in the embodiments of this application;

[0038] Figure 11D A top view schematic diagram of the third type of packaging substrate provided in the embodiments of this application;

[0039] Figure 12A and Figure 12B These are schematic diagrams of the planar layout of the first wiring layer and the second wiring layer of the fourth type of packaging substrate provided in the embodiments of this application;

[0040] Figure 13A and Figure 13B This is a second schematic diagram showing the planar layout of the first wiring layer and the second wiring layer of the fourth type of packaging substrate provided in the embodiments of this application. Detailed Implementation

[0041] The technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0042] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present application.

[0043] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0044] It should be noted that the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0045] With the increasing demand for high-performance radio frequency devices, isolation is one of the key performance characteristics of duplexers. Therefore, obtaining duplexers with high isolation without sacrificing other performance characteristics is a topic of active research in the communications industry.

[0046] Coupling can easily occur between the wire-wound inductors of the transmit (TX) filter and the receive (RX) filter on the duplexer's package substrate, affecting the duplexer's isolation. To improve the duplexer's isolation, methods such as increasing the inductance value of the wire-wound inductors on the package substrate or connecting devices such as inductors or capacitors are commonly used. However, this introduces more losses and requires a larger footprint.

[0047] In view of this, embodiments of this application provide a duplexer packaging substrate and a duplexer, which can improve the isolation between the wire-wound inductors of the TX filter and the RX filter without changing the inductance value and volume of the wire-wound inductors on the packaging substrate.

[0048] Figure 1A An equivalent circuit diagram of an example of a duplexer using the first type of packaged substrate provided in the embodiments of this application. Figure 1A As shown, the duplexer 100 may include a resonator and a matching inductor, the matching inductor including the series inductance of the parallel resonator (e.g., the third resonator S3) of the TX filter (e.g., the first inductor L). TX The series inductance of the parallel resonator (e.g., the fourth resonator S4) of the RX filter (e.g., the second inductor L) RX The inductance between the resonator of the TX filter and the antenna terminal ANT (e.g., the third inductor L) TXA ), and the inductance between the resonator of the RX filter and the antenna terminal ANT (e.g., the fourth inductor L). RXA Among them, the series inductance of the parallel resonator (e.g., the third resonator S3) of the TX filter (e.g., the first inductor L) TX One end of the RX filter is grounded to GND, and the series inductance of the parallel resonator (e.g., the fourth resonator S4) of the RX filter (e.g., the second inductor L) is... RX One end of the device is grounded to GND.

[0049] Figure 1B An equivalent circuit diagram of an example of a duplexer using the second type of packaging substrate provided in the embodiments of this application. Figure 1BAs shown, the duplexer 100 may include a resonator and a matching inductor, the matching inductor including the series inductance of the parallel resonator (e.g., the third resonator S3) of the TX filter (e.g., the first inductor L). TX The series inductance of the parallel resonator (e.g., the fourth resonator S4) of the RX filter (e.g., the second inductor L) RX The series inductance (e.g., the fifth inductor L) between the first resonator S1 of the TX filter and the input / output I / O terminals. TXO The series inductance (e.g., the sixth inductor L) between the second resonator S2 of the RX filter and the input / output I / O terminals. RXO The inductance between the resonator of the TX filter and the antenna terminal ANT (e.g., the third inductor L) TXA ), and the inductance between the resonator of the RX filter and the antenna terminal ANT (e.g., the fourth inductor L). RXA Among them, the series inductance of the parallel resonator (e.g., the third resonator S3) of the TX filter (e.g., the first inductor L) TX One end of the RX filter is grounded to GND, and the series inductance of the parallel resonator (e.g., the fourth resonator S4) of the RX filter (e.g., the second inductor L) is... RX One end of the device is grounded to GND.

[0050] In some specific embodiments, the matching inductor may be formed in the form of a wire-wound inductor in the package substrate of the duplexer.

[0051] Those skilled in the art should recognize that, although Figure 1A and Figure 1B The duplexer 100 shown has five series resonators and four parallel resonators, as well as four matching inductors at both the transmitting and receiving ends. However, this application is not limited to this. Those skilled in the art can use other numbers and connection forms of resonators and corresponding matching inductors according to specific application scenarios and design requirements. All variations should be covered within the scope of this application.

[0052] Figure 2 This is a cross-sectional schematic diagram of a packaging substrate provided in an embodiment of this application. Figure 2 As shown, in a first aspect, embodiments of this application provide a duplexer packaging substrate 200, which includes a plurality of wiring layers and a plurality of conductive vias CV disposed between adjacent wiring layers; the plurality of wiring layers include a first wiring layer A, a second wiring layer B, and a third wiring layer C located in the middle wiring layer; at least a portion of a first inductor L is disposed on the first wiring layer A. TX and the first grounding part G TX First inductor L TX The transmitting filter is connected to the transmitting filter via a conductive via CV. The transmitting filter is connected to the first grounding part G via the conductive via CV.TX Grounding; at least a portion of the second inductor L is disposed on the second wiring layer B. RX Second grounding part G RX Second inductor L RX The receiver is connected to the receiving filter via a conductive via CV, and the receiving filter is grounded to the ground via the second grounding part G. RX A third inductor L is installed on the third wiring layer C. TXA With the fourth inductor L RXA Third inductor L TXA The fourth inductor L is connected to the transmitting filter and the antenna terminal ANT of the duplexer via conductive via CV. RXA The conductive via CV is connected to the receiving filter and the antenna terminal ANT of the duplexer, respectively; wherein, the first grounding part G TX The area and / or the second grounding part G RX The area is at least twice the area of ​​the conductive via CV connected to the inductor in the corresponding wiring layer.

[0053] In other embodiments, the third inductor L TXA Through the conductive via CV and the first inductor L TX After connection, connect it to the transmitting filter and the antenna terminal ANT of the duplexer, and the fourth inductor L. RXA Through the conductive via CV and the second inductor L RX After connection, connect it to the receiving filter and the antenna terminal ANT of the duplexer.

[0054] In some specific embodiments, the materials of the wiring layers and the conductive vias include conductive materials. For example, the materials of the first wiring layer A, the second wiring layer B, and the third wiring layer C, and the materials of the conductive vias CV, can be conductive metal materials, including but not limited to copper (Cu).

[0055] In some specific embodiments, the packaging substrate 200 further includes a dielectric layer disposed between adjacent wiring layers. Figure 2 (Not shown in the image), the material of the dielectric layer includes an insulating dielectric material. For example, the material of the dielectric layer may be an insulating dielectric material with a dielectric constant greater than 3.6.

[0056] Those skilled in the art should recognize that although this application describes an embodiment of the application using a package substrate 200 including a first wiring layer to a third wiring layer and conductive vias between adjacent wiring layers as an example, this application is not limited thereto. Those skilled in the art can use other numbers of wiring layers and corresponding conductive vias according to application scenarios and design needs, and all such variations should be covered within the scope of this application.

[0057] Figure 3A and Figure 3B These are schematic diagrams showing the planar layout of the first wiring layer and the second wiring layer of the packaging substrate, which serve as a first comparative example in the embodiments of this application. Figure 3C This is a perspective view of a packaging substrate provided as a first comparative example in an embodiment of this application.

[0058] Figure 4A , Figure 4B and Figure 4C These are schematic diagrams showing the planar layout of the first wiring layer, the second wiring layer, and the third wiring layer of the first type of packaging substrate provided in the embodiments of this application; Figure 4D A top view schematic diagram of the first type of packaging substrate provided in the embodiments of this application; Figure 4E This is a perspective view of the first type of packaging substrate provided in an embodiment of this application. It should be noted that... Figure 4E The conductive vias between adjacent wiring layers are not shown. The pattern of the contact portion of the conductive via (the portion in the wiring layer that contacts the conductive via) is shown in the wiring layer. For example, the conductive vias described in the following embodiments are presented in the form of the contact portion of the conductive via in the wiring layer that contacts the conductive via.

[0059] Compared to Figures 4A to 4E The first type of packaging substrate shown, Figures 3A to 3C In the package substrate shown as a first comparative example, the first wiring layer includes a first inductor and does not include a large area of ​​first ground portion, the second wiring layer includes a second inductor and does not include a large area of ​​second ground portion, and the first ground portion of the first wiring layer and the second ground portion of the second wiring layer are both arranged in the form of conductive vias.

[0060] Figure 5 One of the graphs shown compares the isolation between the TX and RX bands of a first packaging substrate and a packaging substrate used as a first comparative example. Specifically, Figure 5 It shows Figures 3A to 3C The packaging substrate shown as a first comparative example (hereinafter referred to as the first comparative example) and Figures 4A to 4E The graph shows the isolation of the first type of packaging substrate (hereinafter referred to as case1).

[0061] exist Figures 5 to 9 In the isolation curve of the duplexer shown, with Figure 5For example, the frequency band between 1.910GHz and 1.930GHz is the transition band between the TX filter and the RX filter, the frequency band between 1.850GHz and 1.910GHz is the frequency band of the TX filter (hereinafter referred to as "left"), and the frequency band between 1.930GHz and 1.990GHz is the frequency band of the RX filter (hereinafter referred to as "right"). Left isolation refers to isolation within the TX filter frequency band, and right isolation refers to isolation within the RX filter frequency band.

[0062] Figure 5 The differences between the first pair of proportions and case 1 include, compared to Figure 5 Case 1, Figure 5 The first comparison model does not include the third routing layer C as in case 1 (see reference). Figure 4E and Figure 4C The first grounding portion G in case 1 is not present in the first and second wiring layers. TX Second grounding part G RX (refer to Figure 4E , Figure 4A and Figure 4B ). Figure 5 The similarities between the first comparison example and case 1 include that the first inductor and the second inductor are separated and distributed on the first wiring layer and the second wiring layer, respectively. Figure 5 In the first pair and in case 1, the first and second inductors are located in different wiring layers.

[0063] like Figure 5 As shown, compared to the first comparative example, Case 1 includes a third wiring layer C and a first grounding portion G. TX Second grounding part G RX The isolation in both the TX and RX filter bands is significantly improved, meaning the overall isolation of the duplexer is significantly enhanced.

[0064] like Figure 4E , Figures 4A to 4D As shown, in some embodiments, the multiple wiring layers further include: a fifth inductor L TXO It is located on the first wiring layer A and connected to the input / output terminals (I / O) of the transmitting filter and duplexer respectively through conductive vias; the sixth inductor L RXO It is located on the second wiring layer B and is connected to the input / output terminals (I / O) of the receiving filter and duplexer through conductive vias.

[0065] like Figure 4E , Figures 4A to 4D As shown, in some embodiments, the first inductor L TX Third inductor L TXA and the fifth inductor LTXO The second inductor L is positioned on the first side of multiple wiring layers. RX Fourth inductor L RXA and the sixth inductor L RXO It is set on the second side of multiple wiring layers; wherein the first side and the second side are opposite sides of the multiple wiring layers.

[0066] like Figure 4A , Figure 4B and Figure 4C As shown, in some embodiments, the patterns of the first wiring layer A and the second wiring layer B both include inductor patterns, conductive via patterns, and grounding patterns; the grounding patterns are arranged in the plane of the first wiring layer A and / or the plane of the second wiring layer B, excluding the inductor patterns and conductive via patterns; wherein, in the plane of the first wiring layer A, the inductor pattern includes at least a portion of the first inductor L. TX The pattern includes a conductive via pattern connected to the first wiring layer, and the grounding pattern includes a first grounding portion G. TX The pattern; wherein, within the plane of the second wiring layer B, the inductance pattern includes at least a portion of the second inductor L. RX The pattern includes a conductive via pattern connected to the second wiring layer, and the grounding pattern includes a second grounding portion G. RX The pattern.

[0067] refer to Figure 4A , Figure 4B and Figure 4C In some specific embodiments, the pattern of the third wiring layer C includes a third ground portion G. AA The pattern, the third inductor L TXA The pattern, the fourth inductor L RXA The pattern, and, with the third inductor L TXA and the fourth inductor L RXA The pattern of the connected conductive vias CV1 and CV2; the pattern of the second wiring layer B includes the second ground portion G. RX The pattern, the second inductor L RX The pattern, with the second inductor L RX The pattern of the connected conductive via CV6, and the third inductor L TXA and the fourth inductor L RXA The patterns of the connected conductive vias CV4 and CV5; the pattern of the first wiring layer A includes the first ground portion G. TX The pattern, the first inductor L TX The pattern, with the first inductor L TX The pattern of the connected conductive via CV10 is consistent with that of the second inductor L. RXThe pattern of the connected conductive via CV9, and the connection with the third inductor L. TXA and the fourth inductor L RXA The pattern of the connected conductive vias CV7 and CV8.

[0068] Continue to refer to Figure 4A , Figure 4B and Figure 4C In some other embodiments, the first wiring layer A further includes a fifth inductor L. TXO The second wiring layer B also includes a sixth inductor L. RXO The pattern of the second wiring layer B also includes a sixth inductor L. RXO The pattern, and, with the sixth inductor L RXO The pattern of the connected conductive via CV21; the pattern of the first wiring layer A also includes the fifth inductor L. TXO With the fifth inductor L TXO The pattern of the connected conductive via CV23, and the connection with the sixth inductor L. RXO Pattern of the connected conductive via CV22.

[0069] Still referencing Figure 4A , Figure 4B and Figure 4C In other specific embodiments, the pattern of the first wiring layer A also includes a connection with the fifth inductor L. TXO The pattern of the connected conductive via CV36; the pattern of the second wiring layer B also includes the fifth inductor L. TXO The pattern of the connected conductive via CV35, and the connection with the sixth inductor L. RXO The pattern of the connected conductive via CV34; the pattern of the third wiring layer C also includes the connection with the third inductor L. TXA and the fourth inductor L RXA The pattern of the connected conductive via CV31 is related to the fifth inductor L. TXO The pattern of the connected conductive via CV33, and the connection with the sixth inductor L. RXO Pattern of the connected conductive via CV32.

[0070] like Figures 4A to 4D As shown, in some embodiments, the first grounding portion G TX The area and / or the second grounding part G RX The area is at least twice the area of ​​the conductive via connected to the inductor in the corresponding wiring layer. Preferably, the first ground portion G TX The area and / or the second grounding part G RX The area of ​​the ground portion G is at least twice the area of ​​all conductive vias in the corresponding wiring layer. Preferably, the first ground portion G... TX The area and / or the second grounding part G RXThe area ranges from 5 to 8 times the area of ​​all conductive vias in the corresponding wiring layer. First grounding portion G TX The area and / or the second grounding part G RX The area ranges from 40 to 50 times the area of ​​the conductive via connected to the inductor in the corresponding wiring layer.

[0071] like Figures 4A to 4D As shown, in some embodiments, a third grounding portion G is also provided on the third wiring layer C. AA Third grounding part G AA With the third inductor L TXA Fourth inductor L RXA All are isolated, including the third grounding part G. AA The area is at least twice the area of ​​the conductive via connected to the inductor in the third wiring layer C. Preferably, the third grounding portion G... AA The area ranges from 5 to 12 times the area of ​​the conductive via connected to the inductor in the third wiring layer C. Preferably, the third grounding portion G... AA The area of ​​the third ground portion G is at least twice the area of ​​all conductive vias in the third wiring layer C. Preferably, the third ground portion G... AA The area range is at least 10 times the area of ​​all conductive vias in the third wiring layer C.

[0072] In some specific embodiments, such as Figure 4A , Figure 4B and Figure 4C As shown, the pattern of the third wiring layer C includes an inductor pattern, a conductive via pattern, and a grounding pattern; within the plane of the third wiring layer C, all areas except for the inductor pattern and the conductive via pattern are arranged as grounding patterns; wherein, within the plane of the third wiring layer C, the inductor pattern includes a third inductor L. TXA and the fourth inductor L RXA The pattern, the conductive via pattern includes the third inductor L TXA and the third inductor L RXA The pattern of the connected conductive via, and the grounding pattern including the third grounding part G AA The pattern.

[0073] Figure 6 A graph comparing the isolation between the TX and RX bands of the first, third, and fifth packaging substrates of this application, and a packaging substrate serving as a second comparative example, is shown. Specifically, Figure 6 The second comparative example, case 1, and the third type of packaging substrate provided in the embodiments of this application are shown (reference). Figures 11A to 11D The graph shows a comparison of the isolation between the third type of packaging substrate (hereinafter referred to as case3) and the fifth type of packaging substrate (hereinafter referred to as case5) provided in the embodiments of this application. Figure 6 The differences between the second pair of examples and case 1 include, compared to Figure 6 Case 1, Figure 6 The first and second inductors in the second pair are located on the same wiring layer. Figure 6 The second pair of wiring layers has one less layer, making it four layers. In this case, since there are two inductors (the first inductor and the second inductor) in the same wiring layer, the proportion of the two inductors in the same wiring layer is relatively large, while the proportion of the grounding part is relatively small. Figure 6 The similarities between the second pair of examples and case 1 include: Figure 6 The second comparison example and case 1 both include a third routing layer C (see reference). Figure 4E and Figure 4C ). Figure 6 The differences between case 1 and case 3 include, compared to Figure 6 Case 1, Figure 6 The first grounding part G in case 3 TX The projection on the surface of the third wiring layer C and the second grounding part G RX The projections on the surface of the third wiring layer C do not overlap. Figure 6 The differences between case 1 and case 5 include, compared to Figure 6 Case 1, Figure 6 In case 5, the first wiring layer does not include a large area of ​​the first grounding portion, and the second wiring layer does not include a large area of ​​the second grounding portion. The first grounding portion of the first wiring layer and the second grounding portion of the second wiring layer are both arranged in the form of conductive vias.

[0074] like Figure 6 As shown, compared to the second comparison, the first and second inductors in cases 1, 3 and 5 are separated and distributed in the first and second wiring layers respectively. The isolation in the TX and RX filter bands is significantly improved, that is, the overall isolation of the duplexer is significantly improved.

[0075] like Figure 6 As shown, compared to case 1, case 5 exhibits worse isolation on the left and better isolation on the right. In practical applications, for those requiring higher bandwidth isolation of the RX filter, the design of case 5 should be considered as the preferred option.

[0076] like Figure 2 , Figures 4A to 4E As shown, in some embodiments, the first inductor L TX The first wiring layer A is provided, and the second inductor L is provided. RX Set in the second wiring layer B.

[0077] In other embodiments, the first inductor LTX The first part is disposed on the first wiring layer A, the second part is disposed on the second wiring layer B, and the second inductor L RX The first part is set in the second wiring layer B, and the second part is set in the first wiring layer A. Figure 2 and Figure 4E (Not shown).

[0078] Figure 7 A graph comparing the isolation between the TX and RX bands of the first type of packaging substrate, the sixth type of packaging substrate, and the packaging substrate used as a second comparative example of this application is shown. Specifically, Figure 7 The diagram shows a comparison of the isolation between the second comparative example, case 1, and the sixth type of packaging substrate (hereinafter referred to as case 6) provided in the embodiments of this application. For structural details of case 6 provided in this application, please refer to [link to relevant documentation]. Figure 4E First inductor L TX Second inductor L RX After adjusting the distribution, we get: the first inductor L TX The first part is disposed on the first wiring layer A, the second part is disposed on the second wiring layer B, and the second inductor L RX The first part is set in the second wiring layer B, and the second part is set in the first wiring layer A. Figure 7 The differences between the second pair of examples and case 1 include, compared to Figure 7 Case 1, Figure 7 The first and second inductors in the second pair are located on the same wiring layer. Figure 7 The second pair of wiring layers has one less layer, making it four layers. In this case, since there are two inductors (the first inductor and the second inductor) in the same wiring layer, the proportion of the two inductors in the same wiring layer is relatively large, while the proportion of the grounding part is relatively small. Figure 7 The similarities between the second pair of examples and case 1 include: Figure 7 The second comparison example and case 1 both include a third routing layer C (see reference). Figure 4E and Figure 4C ).

[0079] like Figure 7 As shown, compared to the second comparative example, the isolation between the RX and TX bands in cases 1 and 6 provided in this application is significantly better than the isolation between the RX and TX bands in the comparative example.

[0080] like Figure 7As shown, compared to case 1, the isolation between the RX and TX bands of case 7 provided in this application is better than that of case 1. Therefore, the sixth type of packaging substrate structure of case 6 provided in this application can be preferred for use in duplexers to improve the isolation between the RX and TX bands of duplexers.

[0081] like Figure 2 and Figure 4E As shown, in some embodiments, the first wiring layer A, the second wiring layer B, and the third wiring layer C are adjacent wiring layers among a plurality of wiring layers.

[0082] In some embodiments, the third wiring layer C is disposed between the first wiring layer A and the second wiring layer B. Figure 2 and Figure 4E (Not shown).

[0083] Figure 8 A graph comparing the isolation between the TX and RX bands of the first type of packaging substrate, the seventh type of packaging substrate, and the packaging substrate used as a second comparative example of this application is shown. Specifically, Figure 8 The diagram shows a comparison of the isolation between the second comparative example, case 1, and the seventh type of packaging substrate (hereinafter referred to as case 7) provided in the embodiments of this application. For structural details of case 7 provided in this application, please refer to [link to relevant documentation]. Figure 4E The positions of the second routing layer B and the third routing layer C are interchanged for understanding: the first routing layer A, the second routing layer B, and the third routing layer C are adjacent routing layers among multiple routing layers, and the third routing layer C is located between the first routing layer A and the second routing layer B.

[0084] like Figure 8 As shown, compared to the second comparative example, the isolation between the RX and TX bands in cases 1 and 7 provided in this application is significantly better than the isolation between the RX and TX bands in the comparative example.

[0085] like Figure 8 As shown, compared to case 1, the isolation between the RX and TX bands of case 7 provided in this application is better than the isolation between the Rx and Tx bands of case 1. The seventh type of packaging substrate structure of case 7 provided in this application can be preferentially adopted for use in duplexers to improve the isolation between the RX and TX bands of duplexers.

[0086] In some embodiments, in the first wiring layer, the first inductor is connected to or not connected to the first ground portion, and / or, in the second wiring layer, the second inductor is connected to or not connected to the second ground portion.

[0087] like Figure 4A and Figure 4B As shown, in some specific embodiments, in the first wiring layer A, the first inductor L TX With the first grounding part G TX Connected, and in the second wiring layer B, the second inductor L RX With the second grounding part G RX Connected.

[0088] like Figure 10A , Figure 10B and Figure 10C As shown, in some specific embodiments, in the first wiring layer A, the first inductor L TX With the first grounding part G TX Unconnected, first inductor L TX Through the conductive via and the first grounding part G TX Connected, and in the second wiring layer B, the second inductor L RX With the second grounding part G RX Unconnected, second inductor L RX Through the conductive via and the second grounding part G RX Connected.

[0089] like Figure 4A , Figure 4B , Figure 4C and Figure 4D As shown, in some embodiments, the first grounding portion G TX The projection on the surface of the third wiring layer C and the second grounding part G RX The projection portion overlaps on the surface of the third wiring layer C.

[0090] like Figure 11A , Figure 11B , Figure 11C and Figure 11D As shown, in some embodiments, the first grounding portion G TX The projection on the surface of the third wiring layer C and the second grounding part G RX The projections on the surface of the third wiring layer C do not overlap.

[0091] Continue to refer to Figure 11A , Figure 11B , Figure 11C and Figure 11D In some embodiments, the first grounding portion G TX The projection on the surface of the third wiring layer C and the second grounding part G RX The projections on the surface of the third wiring layer C do not overlap; and the first ground portion G TX The outer contour of the projection on the surface of the third wiring layer C covers the second inductor L. RX Projection onto the surface of the third wiring layer C, second grounding portion G RXThe outer contour of the projection on the surface of the third wiring layer C covers the first inductor L. TX Projection on the surface of the third wiring layer C.

[0092] Figure 9 A graph comparing the isolation between the TX and RX bands of the first type of packaging substrate, the third type of packaging substrate, and the packaging substrate used as a second comparative example of this application is shown. Specifically, Figure 9 The second comparative example, case 1, and the third type of packaging substrate provided in the embodiments of this application are shown (reference). Figures 11A to 11D The graph shows the isolation ratio between the third type of packaging substrate (hereinafter referred to as case 3).

[0093] Figure 9 The differences between the second pair of examples and case 1 include, compared to Figure 9 Case 1, Figure 9 The first and second inductors in the second pair are located on the same wiring layer. Figure 9 The second pair of wiring layers has one less layer, making it four layers. In this case, since there are two inductors (the first inductor and the second inductor) in the same wiring layer, the proportion of the two inductors in the same wiring layer is relatively large, while the proportion of the grounding part is relatively small. Figure 9 The similarities between the second pair of examples and case 1 include: Figure 9 The second comparison example and case 1 both include a third routing layer C (see reference). Figure 4E and Figure 4C ).

[0094] Figure 9 The differences between case 1 and case 3 include, compared to Figure 9 Case 1, Figure 9 The first grounding part G in case 3 TX The projection on the surface of the third wiring layer C and the second grounding part G RX The projections on the surface of the third wiring layer C do not overlap.

[0095] like Figure 9 As shown, compared to the second comparison, in cases 1 and 3, the first and second inductors are separated and distributed in the first and second wiring layers respectively. The isolation in the TX and RX filter bands is significantly improved, that is, the overall isolation of the duplexer is significantly improved.

[0096] like Figure 9 As shown, compared to case 1, case 3 offers better isolation on the left and worse isolation on the right. In practical applications, for those requiring higher bandwidth isolation for the TX filter, case 3 should be the preferred design.

[0097] In some embodiments, the outer contour of the pattern of the first ground portion includes a closed pattern, and all of the first wiring layer except for the pattern of the first ground portion is within the closed pattern; and / or, the outer contour of the pattern of the second ground portion includes a closed pattern, and all of the second wiring layer except for the pattern of the second ground portion is within the closed pattern.

[0098] like Figure 12A and Figure 12B ,as well as, Figure 13A and Figure 13B As shown, in some specific embodiments, the first grounding portion G TX The outer contour of the pattern includes a closed shape, excluding the first ground portion G in the first wiring layer A. TX The pattern outside the shape is entirely within a closed shape; and the second grounding part G RX The outer contour of the pattern includes a closed shape, and the second grounding portion G is removed from the second wiring layer B. RX The pattern is entirely within a closed shape. In some specific embodiments, such as... Figure 12A and Figure 12B As shown, in the first wiring layer A, the first inductor L TX With the first grounding part G TX They are not connected, and in the second wiring layer B, the second inductor L RX With the second grounding part G RX Not connected. In some specific embodiments, such as Figure 13A and Figure 13B As shown, in the first wiring layer A, the first inductor L TX With the first grounding part G TX Connected, and in the second wiring layer B, the second inductor L RX With the second grounding part G RX Connected.

[0099] like Figure 4A , Figure 4B , Figure 4C and Figure 4D As shown, in some embodiments, in the first wiring layer A, the first inductor L TX With the first grounding part G TX The minimum spacing between them is 0.5 times the minimum line width, and the conductive vias connected to the first wiring layer A and the first ground portion G are connected. TX The minimum spacing between them is 0.5 times the minimum line width; and / or, in the second wiring layer B, the second inductor L RX With the second grounding part G RX The minimum spacing between them is 0.5 times the minimum line width, and the conductive vias connected to the second wiring layer B are connected to the second ground portion G. RX The minimum spacing between them is 0.5 times the minimum line width.

[0100] In some specific embodiments, in the first wiring layer A or the second wiring layer B, the minimum distance between the portion of the inductor not connected to the ground and the ground is 0.5 times the minimum linewidth, and the minimum distance between the conductive via and the ground is 0.5 times the minimum linewidth; the first inductor L TX With the first grounding part G TX The minimum spacing between patterns at non-contact locations is 10μm, and the second inductor L RX With the second grounding part G RX The minimum spacing between patterns at non-contact locations is 10 μm.

[0101] In some embodiments, the number of conductive vias connected to the inductor in each wiring layer is at least 2; the number of conductive vias in the wiring layer is at least 5.

[0102] refer to Figure 4A , Figure 4B and Figure 4C In some specific embodiments, the pattern of the first wiring layer A includes the first inductor L. TX The pattern of the connected conductive via CV10 is consistent with that of the second inductor L. RX The pattern of the connected conductive via CV9 is related to the third inductor L. TXA and the fourth inductor L RXA The patterns of the connected conductive vias CV7 and CV8 are consistent with those of the fifth inductor L. TXO The pattern of the connected conductive via CV23, and the connection with the sixth inductor L. RXO The pattern of the connected conductive via CV22, and the fifth inductor L. TXO Pattern of the connected conductive via CV36.

[0103] refer to Figure 4A , Figure 4B and Figure 4C In some specific embodiments, the pattern of the second wiring layer B includes the pattern of the second inductor L. RX The pattern of the connected conductive via CV6 is related to the third inductor L. TXA and the fourth inductor L RXA The patterns of the connected conductive vias CV4 and CV5 are consistent with those of the sixth inductor L. RXO The pattern of the connected conductive via CV21, and the pattern of the second wiring layer B also include the fifth inductor L. TXO The pattern of the connected conductive via CV35, and the connection with the sixth inductor L. RXO Pattern of the connected conductive via CV34.

[0104] refer to Figure 4A , Figure 4B and Figure 4CIn some specific embodiments, the pattern of the third wiring layer C includes a pattern related to the third inductor L. TXA and the fourth inductor L RXA The patterns of the connected conductive vias CV1 and CV2 are consistent with those of the third inductor L. TXA and the fourth inductor L RXA The pattern of the connected conductive via CV31 is related to the fifth inductor L. TXO The pattern of the connected conductive via CV33, and the connection with the sixth inductor L. RXO Pattern of the connected conductive via CV32.

[0105] In some embodiments, the shape of the conductive via includes a circle, a rounded rectangle, or a dumbbell shape.

[0106] refer to Figure 4B In some specific embodiments, in the second wiring layer B, with the third inductor L TXA The connected conductive via CV4 is a rounded rectangle, and is connected to the fourth inductor L. RXA The connected conductive via CV5 is dumbbell-shaped and is connected to the fifth inductor L. TXO The connected conductive via CV35 is circular in shape.

[0107] In some embodiments, the number of first inductors and / or the number of second inductors may include one or more.

[0108] In some specific embodiments, multiple inductors connected together through conductive vias are used to achieve a large inductance value; the multiple inductors can be considered as a single inductor. For example, the first inductor has an inductance value of 1 nH (nanohenry), which can be formed by connecting two inductors with inductance values ​​of 0.3 nH and 0.7 nH through conductive vias.

[0109] Despite Figure 4E , Figure 4A , Figure 4B and Figure 4C As shown, the number of the first inductor and the number of the second inductor are both one. Those skilled in the art will recognize that the number of the first inductor and / or the number of the second inductor may include, for example, two, three, or more. Those skilled in the art can use multiple numbers of the first inductor and / or the second inductor in the packaging substrate 200 of the duplexer provided in the various embodiments of this application, depending on the specific application scenario and design requirements. All variations should be covered within the scope of this application.

[0110] In some embodiments, the third wiring layer C is located outside the first wiring layer A and the second wiring layer B as a whole; the plurality of wiring layers further include: a fourth wiring layer, located between the third wiring layer and the whole, for use as a separate ground layer.

[0111] refer to Figure 2 and Figure 4E To understand this, in some specific embodiments, a fourth wiring layer is provided between the third wiring layer C and the second wiring layer B. Figure 2 and Figure 4E (Not shown), the fourth wiring layer serves as a separate ground layer, and the package substrate includes a third wiring layer C, a fourth wiring layer, a second wiring layer B, and a first wiring layer A stacked in sequence.

[0112] like Figure 2 and Figure 4E As shown, in some embodiments, the plurality of wiring layers further include a first pad layer D and a second pad layer E located on opposite outer sides of the plurality of wiring layers; the first pad layer D is used to include connecting the transmit filter and the receive filter to the package substrate 200; the second pad layer E is used to include connecting the duplexer to other radio frequency devices.

[0113] Exemplarily, the first pad layer D is used to connect the inductor of the package substrate 200 to the transmitting filter and the receiving filter. Exemplarily, the second pad layer E is used to connect the inductor of the package substrate 200 to the antenna terminal ANT and the ground terminal GND of the duplexer. Exemplarily, the second pad layer E is also used to connect the inductor of the package substrate 200 to the input / output terminal I / O of the duplexer.

[0114] In some specific embodiments, the first inductor L is located directly below the TX filter. TX Large-area first grounding part G TX Located directly below the RX filter, similarly, directly below the RX filter is the second inductor L. RX Large-area second grounding part G RX Located directly below TX, making the first inductor L TX With the second inductor L RX Being far apart helps improve isolation.

[0115] In some specific embodiments, the third inductor L TXA and the fourth inductor L RXA They are located directly below the TX and RX filters, respectively, for ease of wiring. In some other embodiments, the third inductor L TXA and the fourth inductor L RXA The positions can be interchanged, located directly below the RX and TX filters respectively.

[0116] In some specific embodiments, the first pad layer D and the second pad layer E are provided with pins connected to the transmitting filter and the receiving filter, and one end of the ground portion is connected to the pins of the transmitting filter and the receiving filter through a conductive via and an inductor. For example, the first ground portion G...TX One end passes through a conductive via CV and a first inductor L. TX Connect to the pins of the transmit filter.

[0117] In some specific embodiments, the first pad layer D and the second pad layer E are provided with a ground pin (connected to an external ground), an I / O pin, an inductor pin, and a pin connected to an antenna. The other end of the ground portion is connected to the ground pin (connected to an external ground), the I / O pin, the inductor pin, and the antenna pin through a conductive via. For example, the first ground portion G... TX The other end is connected to the ground pin through a conductive via CV.

[0118] refer to Figure 2 and Figure 4E Secondly, embodiments of this application provide a duplexer, which includes: a package substrate 200 according to any one of the first aspects, and a transmit filter and a receive filter located on the package substrate 200; wherein, the transmit filter is used to transmit a transmit signal to an antenna terminal ANT; the receive filter is used to receive a signal from the antenna terminal ANT; the transmit filter and the receive filter are connected to an inductor of the package substrate 200.

[0119] It should be noted that the resonator structure of a duplexer can be specifically divided into: the first type of cavity-type thin-film bulk acoustic wave resonator (FBAR), the second type of cavity-type FBAR, and the solid-mounted resonator (SMR) type resonator structure, etc. The solution provided in this application can be applied to the above-mentioned different types of bulk acoustic wave resonator structures.

[0120] In some embodiments, when the bulk acoustic resonant structure includes a first type of cavity-type FBAR, the reflective structure includes a first electrode layer protruding upward to form a first cavity between it and the substrate surface.

[0121] In some embodiments, when the bulk acoustic resonant structure includes a second type of cavity-type FBAR, the reflective structure includes a second cavity formed between a downwardly recessed surface of the substrate and a first electrode layer.

[0122] In some embodiments, when the bulk acoustic resonant structure includes an SMR resonant structure, the reflection structure includes a plurality of first dielectric layers and second dielectric layers with different acoustic impedances that are alternately stacked.

[0123] It should be noted that the reflective structure can be either a cavity or a solid structure. When the reflective structure is a cavity, it includes a first cavity or a second cavity; when the reflective structure is a solid structure, it includes multiple alternating layers of first and second dielectric layers.

[0124] In some embodiments, the resonator of the duplexer includes an FBAR. In some embodiments, the package substrate includes multiple wiring layers and multiple conductive vias disposed between adjacent wiring layers; the multiple wiring layers include a first wiring layer, a second wiring layer, and a third wiring layer located in the middle wiring layer; the first wiring layer has at least a portion of a first inductor and a first ground portion, the first inductor being connected to a transmitting filter through the conductive vias, and the transmitting filter being grounded through the conductive vias and the first ground portion; the second wiring layer has at least a portion of a second inductor and a second ground portion, the second inductor being connected to a receiving filter through the conductive vias, and the receiving filter being grounded through the conductive vias and the second ground portion; the third wiring layer has a third inductor and a fourth inductor, the third inductor being connected to the transmitting filter and the antenna terminal of the duplexer respectively through conductive vias, and the fourth inductor being connected to the receiving filter and the antenna terminal of the duplexer respectively through conductive vias; wherein the area of ​​the first ground portion and / or the area of ​​the second ground portion is at least twice the area of ​​the conductive via connected to the inductor in the corresponding wiring layer.

[0125] In some specific embodiments, the multiple wiring layers further include: a fifth inductor disposed on the first wiring layer and connected to the I / O terminals of the transmitting filter and the duplexer respectively through conductive vias; and a sixth inductor disposed on the second wiring layer and connected to the I / O terminals of the receiving filter and the duplexer respectively through conductive vias.

[0126] In some specific embodiments, the first inductor, the third inductor, and the fifth inductor are disposed on the first side of the plurality of wiring layers, and the second inductor, the fourth inductor, and the sixth inductor are disposed on the second side of the plurality of wiring layers; wherein the first side and the second side are opposite sides of the plurality of wiring layers.

[0127] In some specific embodiments, the patterns of the first wiring layer and the second wiring layer both include inductor patterns, conductive via patterns, and grounding patterns; grounding patterns are arranged in the plane of the first wiring layer and / or in the plane of the second wiring layer, excluding the inductor patterns and conductive via patterns; wherein, in the plane of the first wiring layer, the inductor pattern includes at least a portion of the pattern of the first inductor, the conductive via pattern includes the pattern of the conductive via connected to the first wiring layer, and the grounding pattern includes the pattern of the first grounding portion; wherein, in the plane of the second wiring layer, the inductor pattern includes at least a portion of the pattern of the second inductor, the conductive via pattern includes the pattern of the conductive via connected to the second wiring layer, and the grounding pattern includes the pattern of the second grounding portion.

[0128] In some specific embodiments, a first inductor is disposed on a first wiring layer, and a second inductor is disposed on a second wiring layer; or, a first portion of the first inductor is disposed on the first wiring layer, a second portion is disposed on the second wiring layer, and a first portion of the second inductor is disposed on the second wiring layer, and a second portion is disposed on the first wiring layer.

[0129] In some specific embodiments, the first wiring layer, the second wiring layer, and the third wiring layer are adjacent wiring layers among a plurality of wiring layers.

[0130] In some specific embodiments, the third wiring layer is disposed between the first wiring layer and the second wiring layer.

[0131] In some specific embodiments, in the first wiring layer, the first inductor may or may not be connected to the first ground portion, and / or, in the second wiring layer, the second inductor may or may not be connected to the second ground portion.

[0132] In some specific embodiments, the projection of the first ground portion onto the surface of the third wiring layer may or may not overlap with the projection of the second ground portion onto the surface of the third wiring layer.

[0133] In some specific embodiments, the projection of the first ground portion on the surface of the third wiring layer does not overlap with the projection of the second ground portion on the surface of the third wiring layer; and the outer contour of the projection of the first ground portion on the surface of the third wiring layer covers the projection of the second inductor on the surface of the third wiring layer, and the outer contour of the projection of the second ground portion on the surface of the third wiring layer covers the projection of the first inductor on the surface of the third wiring layer.

[0134] In some specific embodiments, the outer contour of the pattern of the first ground portion includes a closed shape, and all of the first wiring layer except for the pattern of the first ground portion is within the closed shape; and / or, the outer contour of the pattern of the second ground portion includes a closed shape, and all of the second wiring layer except for the pattern of the second ground portion is within the closed shape.

[0135] In some specific embodiments, in the first wiring layer, the minimum spacing between the first inductor and the first ground portion is 0.5 times the minimum linewidth, and the minimum spacing between the conductive via connected to the first wiring layer and the first ground portion is 0.5 times the minimum linewidth; and / or, in the second wiring layer, the minimum spacing between the second inductor and the second ground portion is 0.5 times the minimum linewidth, and the minimum spacing between the conductive via connected to the second wiring layer and the second ground portion is 0.5 times the minimum linewidth.

[0136] In some specific embodiments, the number of conductive vias connected to the inductor in each wiring layer is at least 2; the number of conductive vias in the wiring layer is at least 5.

[0137] In some specific embodiments, the shape of the conductive via includes a circle, a rounded rectangle, or a dumbbell shape.

[0138] In some specific embodiments, the number of first inductors and / or the number of second inductors may include one or more.

[0139] In some specific embodiments, the third wiring layer is located outside the first wiring layer and the second wiring layer as a whole; the plurality of wiring layers also include: a fourth wiring layer, located between the third wiring layer and the whole, for use as a separate ground layer.

[0140] In some specific embodiments, the plurality of wiring layers further include a first pad layer and a second pad layer located on opposite outer sides of the plurality of wiring layers; the first pad layer is used to include connecting the transmit filter and the receive filter to the package substrate; the second pad layer is used to include connecting the duplexer to other radio frequency devices.

[0141] The packaging substrate in the duplexer provided in this application embodiment is similar to the packaging substrate in the embodiments of the first aspect described above. For technical features not disclosed in detail in this application embodiment, please refer to the embodiments of the first aspect described above for understanding. Here, they will not be repeated.

[0142] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0143] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0144] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A packaging substrate for a duplexer, characterized in that, The system includes multiple wiring layers and multiple conductive vias disposed between adjacent wiring layers. The multiple wiring layers include a first wiring layer, a second wiring layer, and a third wiring layer located in the middle wiring layer. The first wiring layer has at least a portion of a first inductor and a first grounding portion. The first inductor is connected to a transmitting filter through the conductive vias, and the transmitting filter is grounded through the conductive vias and the first grounding portion. The second wiring layer has at least a portion of a second inductor and a second grounding portion. The second inductor is connected to a receiving filter through the conductive vias, and the receiving filter is grounded through the conductive vias and the second grounding portion. The third wiring layer has a third inductor and a fourth inductor. The third inductor is connected to the transmitting filter and the antenna terminal of the duplexer through the conductive vias, respectively. The fourth inductor is connected to the receiving filter and the antenna terminal of the duplexer through the conductive vias, respectively. Wherein, the area of ​​the first grounding portion and / or the area of ​​the second grounding portion are at least twice the area of ​​the conductive via connected to the inductor in the corresponding wiring layer.

2. The packaging substrate according to claim 1, characterized in that, The plurality of wiring layers also include: The fifth inductor is disposed on the first wiring layer and is connected to the transmitting filter and the I / O terminal of the duplexer through the conductive via, respectively. The sixth inductor is disposed on the second wiring layer and is connected to the receiving filter and the I / O terminal of the duplexer through the conductive via, respectively.

3. The packaging substrate according to claim 2, characterized in that, The first inductor, the third inductor, and the fifth inductor are disposed on the first side of the plurality of wiring layers, and the second inductor, the fourth inductor, and the sixth inductor are disposed on the second side of the plurality of wiring layers; wherein the first side and the second side are opposite sides of the plurality of wiring layers.

4. The packaging substrate according to claim 1, characterized in that, The patterns of the first wiring layer and the second wiring layer both include inductor patterns, conductive via patterns, and grounding patterns; The grounding pattern is arranged in the plane of the first wiring layer and / or in the plane of the second wiring layer, except for the inductor pattern and the conductive via pattern. Wherein, within the plane of the first wiring layer, the inductor pattern includes at least a portion of the pattern of the first inductor, the conductive via pattern includes the pattern of a conductive via connected to the first wiring layer, and the grounding pattern includes the pattern of the first grounding portion; Wherein, within the plane of the second wiring layer, the inductor pattern includes at least a portion of the pattern of the second inductor, the conductive via pattern includes the pattern of a conductive via connected to the second wiring layer, and the grounding pattern includes the pattern of the second grounding portion.

5. The packaging substrate according to claim 1, characterized in that, The first inductor is disposed on the first wiring layer, and the second inductor is disposed on the second wiring layer; or, The first part of the first inductor is disposed on the first wiring layer, and the second part is disposed on the second wiring layer; and the first part of the second inductor is disposed on the second wiring layer, and the second part is disposed on the first wiring layer.

6. The packaging substrate according to claim 1, characterized in that, The first wiring layer, the second wiring layer, and the third wiring layer are adjacent wiring layers among the plurality of wiring layers.

7. The packaging substrate according to claim 6, characterized in that, The third wiring layer is disposed between the first wiring layer and the second wiring layer.

8. The packaging substrate according to claim 1, characterized in that, In the first wiring layer, the first inductor may or may not be connected to the first grounding portion, and / or, in the second wiring layer, the second inductor may or may not be connected to the second grounding portion.

9. The packaging substrate according to claim 1, characterized in that, The projection of the first grounding portion onto the surface of the third wiring layer may or may not overlap with the projection of the second grounding portion onto the surface of the third wiring layer.

10. The packaging substrate according to claim 9, characterized in that, The projection of the first ground portion on the surface of the third wiring layer does not overlap with the projection of the second ground portion on the surface of the third wiring layer; and the outer contour of the projection of the first ground portion on the surface of the third wiring layer covers the projection of the second inductor on the surface of the third wiring layer, and the outer contour of the projection of the second ground portion on the surface of the third wiring layer covers the projection of the first inductor on the surface of the third wiring layer.

11. The packaging substrate according to claim 1, characterized in that, The outer contour of the pattern of the first grounding part includes a closed shape, and all parts of the first wiring layer except the pattern of the first grounding part are within the closed shape; And / or, the outer contour of the pattern of the second ground portion includes a closed shape, and all parts of the second wiring layer except the pattern of the second ground portion are within the closed shape.

12. The packaging substrate according to claim 1, characterized in that, In the first wiring layer, the minimum spacing between the first inductor and the first ground portion is 0.5 times the minimum linewidth, and the minimum spacing between the conductive via connected to the first wiring layer and the first ground portion is 0.5 times the minimum linewidth; and / or, in the second wiring layer, the minimum spacing between the second inductor and the second ground portion is 0.5 times the minimum linewidth, and the minimum spacing between the conductive via connected to the second wiring layer and the second ground portion is 0.5 times the minimum linewidth.

13. The packaging substrate according to claim 1, characterized in that, The number of conductive vias connected to the inductors in each of the wiring layers is at least two; the number of conductive vias in the wiring layers is at least five.

14. The packaging substrate according to claim 1, characterized in that, The shape of the conductive via includes circular, rounded rectangle, or dumbbell shape.

15. The packaging substrate according to claim 1, characterized in that, The number of the first inductor and / or the number of the second inductor may include one or more.

16. The packaging substrate according to claim 1, characterized in that, The third wiring layer is located outside the first wiring layer and the second wiring layer as a whole; the plurality of wiring layers further include: The fourth wiring layer, located between the third wiring layer and the whole, is used as a separate grounding layer.

17. The packaging substrate according to claim 1, characterized in that, The plurality of wiring layers also includes a first pad layer and a second pad layer located on opposite sides of the plurality of wiring layers; The first pad layer is used to connect the transmitting filter and the receiving filter to the package substrate; The second pad layer is used to include connecting the duplexer to other radio frequency devices.

18. A duplexer, characterized in that, include: The packaging substrate and the transmitting filter and receiving filter located on the packaging substrate according to any one of claims 1 to 17; wherein, The transmitting filter is used to transmit the transmitted signal to the antenna end; The receiving filter is used to receive signals from the antenna end; The transmitting filter and the receiving filter are connected to the inductor of the packaging substrate.

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