Method, circuit, chip and electronic device for scrambling and descrambling an address

Abstract

The present disclosure provides a method, circuit, chip and electronic device for scrambling and descrambling an address. The method for scrambling an address comprises: receiving a first request message from a processing unit, wherein the first request message contains a data address; performing an address scrambling operation on a to-be-processed address group to obtain a scrambled address, the length of the scrambled address being greater than or equal to the length of the data address, wherein the to-be-processed address is the data address or an intermediate address during the address scrambling operation; and sending a second request message containing the scrambled address to a link layer, the second request message corresponding to the first request message and the second request message being a transaction layer packet. Through the method provided by the present disclosure, scrambling and descrambling of the address can be realized on the basis of the CXL protocol, and the security of data transmission can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a method, circuit, chip and electronic device for scrambling and descrambling an address, and in particular to a method for scrambling an address, a method for descrambling an address, a circuit for scrambling an address, a circuit for descrambling an address, a chip and an electronic device. BACKGROUND

[0002] Compute Express Link (CXL) protocol is a cache coherence interconnection protocol for processors, memory expansion and accelerators. The CXL protocol is based on the PCIe (Peripheral Component Interconnect Express) protocol, and extends and optimizes the memory consistency and high-speed data exchange capability by adding a new protocol layer.

[0003] The security of data transmission between a host (Host) and a device (Device) supporting the CXL protocol is very important. In the PCIe, encryption and address scrambling are usually used to ensure the security of data transmission, and there is no corresponding provision and implementation method for address scrambling in the CXL protocol. Therefore, how to implement address scrambling on the basis of the CXL protocol is a technical problem to be solved at present. SUMMARY

[0004] In order to solve the above technical problems, embodiments of the present disclosure provide a method for scrambling an address, a method for descrambling an address, a circuit, a chip and an electronic device, which implement address scrambling and descrambling on the basis of the CXL protocol, thereby improving the security of data transmission.

[0005] In a first aspect, at least one embodiment of the present disclosure provides a method for scrambling an address, comprising: receiving a first request message from a processing unit, wherein the first request message contains a data address; performing an address scrambling operation on a to-be-processed address group to obtain a scrambled address, the length of the scrambled address being greater than or equal to the length of the data address, wherein the to-be-processed address is the data address or an intermediate address during the address scrambling operation; and sending a second request message containing the scrambled address to a link layer, the second request message corresponding to the first request message and the second request message being a transaction layer data packet.

[0006] For example, in the method for scrambling an address provided in an embodiment of the present disclosure, the address scrambling operation includes at least one of the following operations: performing a doping operation on the to-be-processed address according to the identification information in the first request message; performing a pseudo-random exchange operation on the to-be-processed address according to the pseudo-random number characteristics and in a preset length; and performing a pseudo-random order adjustment operation on the grouping order of the to-be-processed address according to the pseudo-random number characteristics; wherein the to-be-processed address is a data address or an intermediate address during the address scrambling operation.

[0007] For example, in the method for scrambling an address provided in an embodiment of the present disclosure, before scrambling the address for the to-be-processed address group, the method further includes: determining whether the address scrambling is enabled and the operations included when the address scrambling is enabled according to the configuration information in the first request message.

[0008] For example, in the method for scrambling an address provided in an embodiment of the present disclosure, when the address scrambling operation includes at least two of the doping operation, the exchange operation and the order adjustment operation, the address scrambling operation is performed in the order of sequentially performing the doping operation, the exchange operation and the order adjustment operation.

[0009] For example, in the method for scrambling an address provided in an embodiment of the present disclosure, before performing the address scrambling operation for the to-be-processed address group, the method further includes: dividing the data address into N groups according to the position of the data address in the first request message, wherein N is an integer greater than or equal to 2.

[0010] For example, in the method for scrambling an address provided in an embodiment of the present disclosure, when the address scrambling operation includes the doping operation, performing the address scrambling operation for the to-be-processed address group to obtain the scrambled address includes: dividing the identification information into N groups according to the position of the identification information in the first request message; and doping the N groups of identification information with the N groups of to-be-processed addresses according to a preset arrangement mode, to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates the relative position relationship between the to-be-processed addresses and the identification information in each group of virtual addresses, and the relative position relationships corresponding to the N groups of virtual addresses are at least partially different.

[0011] For example, in the method for scrambling an address provided in an embodiment of the present disclosure, when the address scrambling operation includes the exchange operation, performing the address scrambling operation for the to-be-processed address group includes: obtaining a first pseudo-random number; and controlling the switching mode of N switch arrays by using the first pseudo-random number, so that the N switch arrays perform position exchange within the group on the N groups of to-be-processed addresses in a preset length.

[0012] For example, in the method for scrambling an address provided by an embodiment of the present disclosure, when the address scrambling operation includes the sequential adjustment operation, the address scrambling operation on the address packet to be processed includes: obtaining a second pseudo-random number; taking the second pseudo-random number as a control sequence, and adjusting the group order of the N groups of address to be processed according to the preset adjustment rule of the control sequence and the group order.

[0013] For example, in the method for scrambling an address provided by an embodiment of the present disclosure, when the lengths of the N groups of address to be processed are different, the N groups of virtual addresses are padded with a default value to make the lengths of the N groups of virtual addresses the same.

[0014] For example, in the method for scrambling an address provided by an embodiment of the present disclosure, the obtaining of the first pseudo-random number includes: generating a pseudo-random number in response to receiving a clock signal, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and not generating a pseudo-random number in response to stopping receiving the clock signal; and obtaining the pseudo-random number corresponding to the last clock cycle in the received clock signal as the first pseudo-random number.

[0015] In a second aspect, at least one embodiment of the present disclosure provides a method for descrambling an address, including: receiving a third request message from a link layer, wherein the third request message is a read request message or a write request message, the third request message is a transaction layer data packet and contains a scrambled address; when address descrambling is enabled, performing an address descrambling operation on a scrambled address packet to be processed to obtain a data address, the length of the data address being less than or equal to the length of the scrambled address, the address to be processed being the scrambled address or an intermediate address during the address descrambling operation; and sending a fourth request message containing the data address to a processing unit, the fourth request message corresponding to the third request message.

[0016] For example, in the method for descrambling an address provided by an embodiment of the present disclosure, the address descrambling operation includes at least one of the following operations: performing a de-doping operation on the address to be processed according to the identification information in the third request message; performing a pseudo-random reverse exchange operation on the address to be processed according to the pseudo-random number characteristics and a preset length; and performing a pseudo-random reverse sequential adjustment operation on the group order of the address to be processed according to the pseudo-random number characteristics; wherein the address to be processed is the scrambled address or an intermediate address during the address descrambling operation.

[0017] For example, in the method for descrambling an address provided by an embodiment of the present disclosure, before the address descrambling operation on the address packet to be processed, the method further includes: determining whether the address descrambling is enabled and the operations included when the address descrambling is enabled according to the configuration information in the third request message.

[0018] For example, in the method for address descrambling provided in an embodiment of the present disclosure, when the address descrambling operation comprises at least two of the operations of the de-doping operation, the reverse exchange operation and the reverse order adjustment operation, the address descrambling operation is performed in the order of the reverse order adjustment operation, the reverse exchange operation and the de-doping operation in sequence.

[0019] For example, in the method for address descrambling provided in an embodiment of the present disclosure, before the address descrambling operation is performed on the address group to be processed, the method further comprises: dividing the scrambled addresses into N groups according to the positions of the scrambled addresses in the third request message, wherein N is an integer greater than or equal to 2.

[0020] For example, in the method for address descrambling provided in an embodiment of the present disclosure, when the address descrambling operation comprises the de-doping operation, the address descrambling operation is performed on the address group to be processed, comprising: removing the N groups of identification information from the N groups of address to be processed respectively according to a preset arrangement mode to obtain N groups of data addresses; wherein the preset arrangement mode indicates the relative position relationship between the data addresses and the identification information in each group of address to be processed, and the relative position relationship corresponding to the N groups of address to be processed is at least partially different.

[0021] For example, in the method for address descrambling provided in an embodiment of the present disclosure, when the address descrambling operation comprises the reverse exchange operation, the address descrambling operation is performed on the address group to be processed, comprising: obtaining a first pseudo-random number; inverting the first pseudo-random number, and using the inverted result of the first pseudo-random number to control the switching mode of the N switch arrays respectively, so that the N switch arrays perform reverse exchange within the group according to the preset length on the N groups of address to be processed.

[0022] For example, in the method for address descrambling provided in an embodiment of the present disclosure, when the address descrambling operation comprises the reverse order adjustment operation, the address descrambling operation is performed on the address group to be processed, comprising: obtaining a second pseudo-random number; using the second pseudo-random number as a control sequence, and according to a preset adjustment rule of the control sequence and the group order, reversely adjusting the group order of the N groups of address to be processed.

[0023] For example, in the method for address descrambling provided in an embodiment of the present disclosure, when the N groups of address to be processed include a default value, the method further comprises: removing the default value from the N groups of address to be processed to obtain N groups of data addresses.

[0024] For example, in the method for address descrambling provided in an embodiment of the present disclosure, the obtaining of the first pseudo-random number comprises: in response to receiving a clock signal, generating a pseudo-random number, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and in response to stopping receiving the clock signal, not generating a pseudo-random number; obtaining the pseudo-random number corresponding to the last clock cycle in the received clock signal as the first pseudo-random number.

[0025] In a third aspect, the at least one embodiment of the present disclosure provides a circuit for scrambling an address, comprising: a receiving module configured to receive a first request message from a processing unit, wherein the first request message contains a data address; an address scrambling module connected with the receiving module and configured to perform an address scrambling operation on a to-be-processed address group to obtain a scrambled address, the length of the scrambled address being greater than or equal to the length of the data address, the to-be-processed address being the data address or an intermediate address during the address scrambling operation; and a sending module connected with the address scrambling module and configured to send a second request message containing the scrambled address to a link layer, the second request message corresponding to the first request message and the second request message being a transaction layer data packet.

[0026] For example, in the circuit for scrambling an address provided in an embodiment of the present disclosure, the address scrambling module comprises: a doping unit configured to perform a doping operation on the to-be-processed address according to identification information in the first request message; a swapping unit configured to perform a pseudo-random swapping operation on the to-be-processed address according to a pseudo-random number characteristic and according to a preset length; and a sequence adjustment unit configured to perform a pseudo-random sequence adjustment operation on a grouping sequence of the to-be-processed address according to the pseudo-random number characteristic; wherein the address scrambling operation comprises at least one of the doping operation, the swapping operation and the sequence adjustment operation.

[0027] For example, in the circuit for scrambling an address provided in an embodiment of the present disclosure, the circuit further comprises: a detection module connected with the receiving module and the address scrambling module and configured to determine whether the address scrambling is enabled and which units in the address scrambling module are enabled according to configuration information in the first request message, and to enable at least one unit in the address scrambling module when it is determined that the address scrambling is enabled.

[0028] For example, in the circuit for scrambling an address provided in an embodiment of the present disclosure, the detection module is further configured to disable the address scrambling module when it is determined that the address scrambling is disabled.

[0029] For example, in the circuit for scrambling an address provided in an embodiment of the present disclosure, when at least two of the doping unit, the swapping unit and the sequence adjustment unit are enabled, the address scrambling module is configured to perform the address scrambling operation on the data address in the order of the doping unit, the swapping unit and the sequence adjustment unit.

[0030] For example, in the circuit for scrambling an address provided in an embodiment of the present disclosure, the address scrambling module further comprises: a grouping unit connected with the receiving module, the doping unit, the swapping unit and the sequence adjustment unit and configured to divide the data address into N groups according to the position of the data address in the first request message before performing the address scrambling operation on the to-be-processed address group, wherein N is an integer greater than or equal to 2.

[0031] For example, in the circuit for scrambling addresses provided in an embodiment of the present disclosure, the doping unit is configured to: divide the identification information into N groups according to the positions of the identification information in the first request message; and dope the N groups of identification information with the N groups of addresses to be processed according to a preset arrangement mode to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates the relative position relationship between the addresses to be processed and the identification information in each group of virtual addresses, and the relative position relationships corresponding to the N groups of virtual addresses are at least partially different.

[0032] For example, in the circuit for scrambling addresses provided in an embodiment of the present disclosure, the exchange unit is configured to: obtain a first pseudo-random number; and control the switching mode of the N switch arrays by using the first pseudo-random number to make the N switch arrays perform position exchange within a group according to a preset length.

[0033] For example, in the circuit for scrambling addresses provided in an embodiment of the present disclosure, the sequence adjustment unit is configured to: obtain a second pseudo-random number; and use the second pseudo-random number as a control sequence, and adjust the grouping sequence of the N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

[0034] For example, in the circuit for scrambling addresses provided in an embodiment of the present disclosure, the doping unit is further configured to, when the lengths of the N groups of addresses to be processed are different, fill a default value to the N groups of virtual addresses to make the lengths of the N groups of virtual addresses the same.

[0035] For example, in the circuit for scrambling addresses provided in an embodiment of the present disclosure, the exchange unit includes: a linear feedback shift register configured to generate a first pseudo-random number; and N switch arrays, each of which includes a plurality of multi-control switches, wherein each switch array is configured to control the on or off of the plurality of multi-control switches according to the switching mode corresponding to the first pseudo-random number, so that a group of addresses to be processed input into one switch array is exchanged in position during the transmission in the switch array.

[0036] For example, in the circuit for scrambling addresses provided in an embodiment of the present disclosure, the linear feedback shift register is configured to: generate a pseudo-random number in response to receiving a clock signal, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and not generate a pseudo-random number in response to stopping receiving the clock signal; and take the pseudo-random number corresponding to the last clock cycle in the received clock signal as the first pseudo-random number.

[0037] For example, in the circuit for scrambling addresses provided in an embodiment of the present disclosure, the exchange unit further includes: a clock gate connected with the linear feedback shift register and configured to control the input of the clock signal of the linear feedback shift register.

[0038] In a fourth aspect, the present disclosure provides, in at least one embodiment, a circuit for address descrambling, comprising: a receiving module configured to receive a third request message from a link layer, wherein the third request message is a transaction layer packet and contains a scrambled address; an address descrambling module connected with the receiving module and configured to perform an address descrambling operation on a to-be-processed address group to obtain a data address, the data address having a length less than or equal to a length of the scrambled address, the to-be-processed address being the scrambled address or an intermediate address during the address descrambling operation; and a sending module connected with the address descrambling module and configured to send a fourth request message containing the data address to a processing unit, the fourth request message corresponding to the third request message.

[0039] For example, in an embodiment of the present disclosure, the address descrambling module comprises: a de-doping unit configured to perform a de-doping operation on the to-be-processed address according to identification information in the third request message; a reverse exchange unit configured to perform a pseudo-random reverse exchange operation on the to-be-processed address according to a pseudo-random number characteristic and according to a preset length; and a reverse order adjustment unit configured to perform a pseudo-random reverse order adjustment operation on a grouping order of the to-be-processed address according to the pseudo-random number characteristic; wherein the address descrambling operation comprises at least one of the de-doping operation, the reverse exchange operation, and the reverse order adjustment operation.

[0040] For example, in an embodiment of the present disclosure, the circuit further comprises: a detection module connected with the receiving module and the address descrambling module and configured to determine whether the address descrambling is enabled and which units in the address descrambling module are enabled according to configuration information in the third request message, and to enable at least one unit in the address descrambling module when it is determined that the address descrambling is enabled.

[0041] For example, in an embodiment of the present disclosure, the detection module is further configured to disable the address descrambling module when it is determined that the address descrambling is disabled.

[0042] For example, in an embodiment of the present disclosure, when at least two of the de-doping unit, the reverse exchange unit, and the reverse order adjustment unit are enabled, the address descrambling module is configured to perform the address descrambling operation on the scrambled address in an order of the reverse order adjustment unit, the reverse exchange unit, and the de-doping unit.

[0043] For example, in an embodiment of the present disclosure, the address descrambling module further comprises: a grouping unit connected with the receiving module, the de-doping unit, the reverse exchange unit, and the reverse order adjustment unit and configured to divide the scrambled address into N groups according to a position of the scrambled address in the third request message, wherein N is an integer greater than or equal to 2.

[0044] For example, in the circuit for address descrambling provided in an embodiment of the present disclosure, the doped-out unit is configured to remove N groups of identification information from N groups of to-be-processed addresses respectively according to a preset arrangement mode, to obtain N groups of data addresses; wherein the preset arrangement mode indicates a relative position relationship between a data address and the identification information in each group of to-be-processed addresses, and the relative position relationships corresponding to the N groups of to-be-processed addresses are at least partially different.

[0045] For example, in the circuit for address descrambling provided in an embodiment of the present disclosure, the reverse exchange unit is configured to obtain a first pseudo-random number; invert the first pseudo-random number, and control the switching mode of the N switch arrays respectively by using the inverted result of the first pseudo-random number, so that the N switch arrays perform position reverse exchange within a group according to a preset length on the N groups of to-be-processed addresses.

[0046] For example, in the circuit for address descrambling provided in an embodiment of the present disclosure, the reverse sequence adjustment unit is configured to obtain a second pseudo-random number; take the second pseudo-random number as a control sequence, and adjust the grouping order of the N groups of to-be-processed addresses in reverse according to a preset adjustment rule of the control sequence and the grouping order.

[0047] For example, in the circuit for address descrambling provided in an embodiment of the present disclosure, the doped-out unit is further configured to remove a default value from the N groups of to-be-processed addresses to obtain the N groups of data addresses when the N groups of to-be-processed addresses include the default value.

[0048] For example, in the circuit for address descrambling provided in an embodiment of the present disclosure, the linear feedback shift register is configured to generate a pseudo-random number in response to receiving a clock signal, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and not generate a pseudo-random number in response to stopping receiving the clock signal; and take the pseudo-random number corresponding to the last clock cycle in the received clock signal as the first pseudo-random number.

[0049] For example, in the circuit for address descrambling provided in an embodiment of the present disclosure, the reverse exchange unit further includes a clock gate connected with the linear feedback shift register and configured to control the input of the clock signal of the linear feedback shift register.

[0050] In a fifth aspect, at least one embodiment of the present disclosure provides a chip, such as the circuit for address scrambling in any one of the above third aspect and / or the circuit for address descrambling in any one of the above fourth aspect.

[0051] In a sixth aspect, at least one embodiment of the present disclosure provides an electronic device including the chip of the above fifth aspect.

[0052] In a seventh aspect, at least one embodiment of the present disclosure provides an electronic device, comprising a processor and a memory, the memory storing computer executable instructions, the instructions being executed by the processor to implement the method of any one of the above first aspect and / or the above second aspect.

[0053] In an eighth aspect, at least one embodiment of the present disclosure provides a computer readable storage medium, storing instructions, wherein the instructions are loaded and executed by a processor to implement the method of any one of the above first aspect and / or the above second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure and not limited to the present disclosure.

[0055] Figure 1 A flow chart of a method for scrambling an address according to an embodiment of the present disclosure is shown;

[0056] Figure 2 A flow chart of a method for descrambling an address according to an embodiment of the present disclosure is shown;

[0057] Figure 3a A schematic diagram of a circuit for scrambling an address according to an embodiment of the present disclosure is shown;

[0058] Figure 3b A schematic diagram of a circuit for scrambling an address according to an embodiment of the present disclosure is shown;

[0059] Figure 4 A schematic diagram of a multi-control switch according to an embodiment of the present disclosure is shown;

[0060] Figure 5 A schematic diagram of a switch array according to an embodiment of the present disclosure is shown;

[0061] FIG. 6a shows a schematic diagram of a linear feedback shift register according to an embodiment of the present disclosure;

[0062] Figure 6b A schematic diagram of a switching unit according to an embodiment of the present disclosure is shown.

[0063] Figure 7a A schematic diagram of a circuit for descrambling an address according to an embodiment of the present disclosure is shown;

[0064] Figure 7b A schematic diagram of another circuit for descrambling an address according to an embodiment of the present disclosure is shown;

[0065] Figure 7c FIG. 6 shows a schematic diagram of another circuit for descrambling an address according to an embodiment of the present disclosure;

[0066] Figure 8 FIG. 7 shows a schematic diagram of yet another switch array according to an embodiment of the present disclosure;

[0067] Figure 9 FIG. 8 shows a schematic diagram of a reverse exchange unit according to an embodiment of the present disclosure;

[0068] Figure 10 FIG. 9 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0069] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort fall within the scope of the present disclosure.

[0070] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms “one”, “a” or “the” and similar terms do not denote quantity restriction, but mean that there is at least one. The terms “include”, “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “up”, “down”, “left”, “right” and the like are only used to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0071] There are relevant provisions for address scrambling mechanisms since PCIe 1.0, for example, using a pseudo-random number to perform an exclusive or operation on the address, so that the signal capability can be more dispersedly distributed in the entire energy spectrum, increasing the anti-interference capability. In the evolution of PCIe, the role of address scrambling has changed from only being used to increase the anti-interference capability to also being used to improve the security of data transmission.

[0072] Although the CXL protocol is established on the basis of the PCIe, unlike the PCIe, there is no record of any address scrambling in the CXL protocol, so it is crucial to implement address scrambling suitable for the CXL protocol.

[0073] Based on this, at least one embodiment of the present disclosure provides a method of scrambling an address, a method of descrambling an address, a circuit, a chip, and an electronic device, which implement address scrambling and descrambling on the basis of the CXL protocol, thereby improving the security of data transmission.

[0074] The CXL protocol includes a CXL.mem sub-protocol and a CXL.cache sub-protocol. The CXL.mem sub-protocol has RWD and REQ channels, and the CXL.cache sub-protocol has H2D (Host to Device) Request, H2D Response, H2D Data, D2H (Device to Host) Request, D2H Response, and D2H Data channels. The RWD, REQ, and H2D Request channels in these channels are involved in address transmission. The application scenarios of the embodiments of the present disclosure mainly involve the RWD, REQ, and H2D Request channels. REQ can also be represented as M2S (Master to Subordinate) Request or Req, and RWD can also be represented as M2S Request with Data or RwD. Different representations with the same meaning in the present disclosure can be interchangeable. In the present disclosure, Host corresponds to Device, and Master corresponds to Subordinate. For example, Host is a controller supporting the CXL protocol, such as a CPU (Central Processing Unit), and Device is a device supporting the CXL protocol, such as a memory connected to the CPU. Master and Subordinate are interchangeable, for example, a CXL controller is connected to a memory, Master can be understood as a request initiator, and Subordinate is a corresponding request processor, so that the CXL controller can be Master or Subordinate, and the memory can be Master or Subordinate.

[0075] Figure 1 A flowchart of a method of scrambling an address according to an embodiment of the present disclosure is shown.

[0076] As shown in Figure 1 The method 100 of scrambling an address includes the following steps:

[0077] Step S101, receiving a first request message from a processing unit, wherein the first request message contains a data address.

[0078] Step S102, performing an address scrambling operation on a to-be-processed address to obtain a scrambled address, the length of the scrambled address being greater than or equal to the length of the data address, wherein the to-be-processed address is the data address or an intermediate address during the address scrambling operation.

[0079] Step S103, sending a second request message containing the scrambled address to a link layer, the second request message corresponding to the first request message and the second request message being a transaction layer packet.

[0080] In step S101, the first request message received from the processing unit can be a RWD, REQ and H2D Request message, which includes a read request message or a write request message, for example, the H2D Request can be a host-to-device read request or a write request. For example, the processing unit is a CPU or a controller.

[0081] Optionally, before step S102, it can also be determined whether the address scrambling is enabled. For example, according to the configuration information in the first request message, it is determined whether the address scrambling is enabled and the operations included when the address scrambling is enabled. For example, there is a reserved field in the RWD, REQ and H2D Request message, which is also called RSVD field, and the configuration information indicating whether the address scrambling is enabled and the specific operations included when the address scrambling is enabled can be added in the reserved field. For example, the address scrambling operation includes a doping operation, an exchange operation and a sequence adjustment operation, and the three operations can be enabled separately or in combination. For example, when the configuration information indicates that the address scrambling operation is disabled, all the operations included in the address scrambling operation are disabled, and when the configuration information indicates that the address scrambling operation is enabled, at least one of the doping operation, the exchange operation and the sequence adjustment operation is enabled.

[0082] For example, RSVD[5:2] in the reserved field is configuration information, RSVD[2] indicates whether the address scrambling operation is enabled, RSVD[3] indicates whether the doping operation is enabled, RSVD[4] indicates whether the exchange operation is enabled, and RSVD[5] indicates whether the order adjustment operation is enabled. The value of RSVD[x] is 0, indicating that the operation is disabled, and 1, indicating that the operation is enabled, where x is equal to 2, 3, 4, and 5. It can be understood that the value of RSVD[x] can also be set to 0 to indicate that the operation is enabled, and to 1 to indicate that the operation is disabled. In addition, which bits in the reserved field are set as configuration information can also be set according to requirements, which is not limited herein, for example, RSVD[11:8] in the reserved field can also be used to represent configuration information. The positions of the "words" in the reserved field indicating the above-mentioned operations can also be set arbitrarily, for example, RSVD[2] can correspond to the exchange operation, and RSVD[3] can indicate the doping operation.

[0083] Alternatively, whether the address scrambling operation is enabled can not be set, but the configuration information of the doping operation, the exchange operation, and the order adjustment operation can be used to indicate whether the address scrambling operation is enabled. For example, RSVD[5:3] in the reserved field is configuration information, RSVD[3] indicates whether the doping operation is enabled, RSVD[4] indicates whether the exchange operation is enabled, and RSVD[5] indicates whether the order adjustment operation is enabled. When the doping operation, the exchange operation, and the order adjustment operation are all disabled, it is implicitly indicated that the address scrambling operation is disabled, and when at least one of the doping operation, the exchange operation, and the order adjustment operation is enabled, it is indicated that the address scrambling operation is enabled.

[0084] The disabling of various operations in the embodiment can also be understood as bypassing. By setting the configuration information, the operations included in the address scrambling operation can be more flexibly selected to meet the use requirements in different scenarios. For example, in a scenario with high security requirements, the doping operation, the exchange operation, and the order adjustment operation can all be enabled. In a scenario with low security requirements, one or two of the doping operation, the exchange operation, and the order adjustment operation can be enabled. When there is no scrambling requirement, the address scrambling operation can be disabled as a whole. For example, when the Host is connected to a type 3 device in the CXL protocol, if it is desired that the data is stored in the memory in an out-of-order manner, the address scrambling can be performed on the Host side. For another example, when the memory has an address boundary requirement for out-of-order storage, the doping operation and the order adjustment operation can be disabled, and only the exchange operation is enabled, so that the scrambled address is in a small range to meet the address boundary requirement.

[0085] Optionally, the address scrambling operation can also be configured to be enabled or disabled by default. For example, the first request message can be set to not contain configuration information, and the address scrambling operation is set to be enabled, so that the address scrambling operation is enabled by default. For another example, the address scrambling operation is set to be disabled, so that the address scrambling operation is disabled by default.

[0086] The step S102 is performed, and when the address scrambling is enabled, the address scrambling operation is performed on the address group to be processed to obtain a scrambled address, and the length of the scrambled address is greater than or equal to the length of the data address.

[0087] Optionally, the address scrambling operation includes at least one of the following operations: a doping operation on the address to be processed according to the identification information in the first request message; a pseudo-random exchange operation on the address to be processed according to the pseudo-random number characteristics and in a preset length; and a pseudo-random order adjustment operation on the order of the address group to be processed according to the pseudo-random number characteristics; wherein the address to be processed is the data address or the intermediate address during the address scrambling operation.

[0088] For example, since the address scrambling operation can include one or more operations, the data address and the intermediate address obtained during the address scrambling operation are collectively referred to as the address to be processed. The doping operation is to dope the address to be processed with the identification information carried in the first request message, and the length of the address after doping will increase. The doping operation can also be referred to as the turbidity operation. The exchange operation is to perform a pseudo-random exchange within a group on the address to be processed, for example, in a length of "1 bit", and the length of the address after the exchange operation does not change. The order adjustment operation is to adjust the order of the address group to be processed, which can also be considered as a position exchange operation in a group. The order adjustment operation affects the position of the address group in the message, thereby affecting the order in which the address group is transmitted.

[0089] The data address in the embodiment can be a physical address or a logical address. For example, when the first request message is an RWD message, the length of the data address is 46 bits; when the first request message is an REQ message, the length of the data address is 47 bits; and when the first request message is an H2D Request message, the length of the data address is 46 bits.

[0090] Optionally, before performing the address scrambling operation on the address group to be processed, the method further comprises: dividing the data addresses into N groups according to the positions of the data addresses in the first request message, wherein N is an integer greater than or equal to 2. For example, the data addresses are unevenly divided into 8 groups according to low-to-high bits, such as 4-7 bits of data addresses per group. Optionally, instead of dividing the data addresses into N groups, the data addresses are directly grouped and subjected to the address scrambling operation according to the positions of the data addresses in the first request message and a preset grouping rule in the address scrambling operation.

[0091] In this embodiment, after the data addresses are grouped, all the addresses to be processed are processed according to the grouping of the data addresses, and the intermediate addresses during the address scrambling operation do not need to be repeatedly grouped.

[0092] Optionally, when the address scrambling operation includes the doping operation, performing the address scrambling operation on the address group to be processed to obtain a scrambled address comprises: dividing the identification information into N groups according to the positions of the identification information in the first request message; doping N groups of identification information with N groups of addresses to be processed according to a preset arrangement mode to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates the relative position relationship between the addresses to be processed and the identification information in each group of virtual addresses, and the relative position relationships corresponding to the N groups of virtual addresses are at least partially different.

[0093] When the first request message is an RWD message or a REQ message, the identification information is a tag tag, and the length is 16 bits. When the first request message is an H2D Request, the identification information is a UQID, and the length is 12 bits. The identification information can be unevenly divided into N groups according to the positions of the identification information in the first request message, such as from low-to-high bits. The length of each group of identification information can be 0-2 bits.

[0094] This embodiment implements the doping of identification information and addresses to be processed according to a preset arrangement mode. The preset arrangement mode can be different when the first request message is different. The following examples are provided for the RWD message, the REQ message, and the H2D Request message to illustrate the execution mode of the doping operation.

[0095] For example, when the first request message is an RWD message, the total length of the RWD message is 87 bits, wherein the data addresses are address[51:6], the identification information tag occupies 16 bits, and RSVD occupies 6 bits. The data addresses and the identification information are divided into 8 groups, and 8 groups of virtual addresses are obtained after doping. The 8 groups of virtual addresses are denoted as Group0~Group7, and the following doping scheme is adopted for Group0~Group3:

[0096] 1) Each Group is composed of 2 bits of identification information and 6 bits of data address;

[0097] 2) The high 4 bits and the low 4 bits of each Group are respectively doped with 1 bit of identification information;

[0098] 3) According to the numbering of the Groups, the position of the identification information in the virtual address moves from low bit to high bit, moving 1 bit each time.

[0099] The following doping scheme is adopted for Group 4~Group 7:

[0100] 1) Each Group is composed of 2 bits of identification information and 6 bits of data address, and when the data address is insufficient, it is filled with a default value, which is usually 0;

[0101] 2) The 2 bits of identification information in each Group are connected in position;

[0102] 3) According to the numbering of the Groups, the position of the identification information in the virtual address moves from low bit to high bit, moving 1 bit each time.

[0103] According to the above doping scheme, the following 8 Groups of virtual addresses can be obtained:

[0104] Group0{vir_address[7:0]}={ address[11:9], tag[1],address[8:6],tag[0]};

[0105] Group1{vir_addr[15:8]}={ address[17:16], tag[3], address[15:13], tag[2], address

[12] };

[0106] Group2{vir_addr[23:16]}={ address

[23] , tag[5], address[22:20], tag[4], address[19:18]};

[0107] Group3{vir_addr[31:24]}={ tag[7], address[29:27], tag[6], address[26:24]};

[0108] Group4{vir_addr[39:32]}={address[35:30],tag[9:8]};

[0109] Group5{vir_addr[47:40]}={address[41:37],tag[11:10], address

[36] };

[0110] Group6{vir_addr [55:48]}={address[47:44],tag[13:12], address[43:42]};

[0111] Group7{vir_addr[63:56]}={2’b00,address

[51] ,tag[15:14], address[50:48]}.

[0112] Wherein, vir_addr represents a virtual address, address represents a data address, tag represents identification information, and 2’b00 represents that the value of the high two bits is 0. address[] represents the position of the data address in the RWD message, tag[] represents the position of the identification information in the RWD message, and vir_addr[] represents the position of the obtained virtual address.

[0113] For example, when the first request message is a REQ message, the total length of the REQ message is 87 bits, wherein the data address is address[51:7], the identification information tag occupies 16 bits, and RSVD occupies 6 bits. The data address and the identification information are divided into 8 groups, and after doping, 8 groups of virtual addresses are obtained. The 8 groups of virtual addresses are represented as Group0~Group7, and the following doping scheme is adopted for Group0~Group3:

[0114] 1) Each Group is composed of 2 bits of identification information and 6 bits of data address;

[0115] 2) The high 4 bits and the low 4 bits of each Group are doped with 1 bit of identification information, respectively;

[0116] 3) According to the number of groups, the position of the identification information in the virtual address moves from low to high, and each time it moves 1 bit.

[0117] The following doping scheme is adopted for Group4~Group7:

[0118] 1) Each Group is composed of 2 bits of identification information and 6 bits of data address, wherein the data address is filled with a default value when it is insufficient, and the default value is usually 0;

[0119] 2) The 2 bits of identification information in each Group are connected;

[0120] 3) According to the number of the group, the position of the identification information in the virtual address moves from low bit to high bit, and moves 1 bit each time.

[0121] According to the above-mentioned doping scheme, the following 8 groups of virtual addresses can be obtained:

[0122] Group0{vir_address[7:0]}={ address[12:10], tag[1],address[9:7],tag[0]};

[0123] Group1{vir_addr[15:8]}={ address[18:17], tag[3], address[16:14], tag[2], address

[13] };

[0124] Group2{vir_addr[23:16]}={ address

[24] , tag[5], address[23:21], tag[4], address[20:19]};

[0125] Group3{vir_addr[31:24]}={ tag[7], address[30:28], tag[6], address[27:25]};

[0126] Group4{vir_addr[39:32]}={address[36:31],tag[9:8]};

[0127] Group5{vir_addr[47:40]}={address[42:38],tag[11:10], address

[37] };

[0128] Group6{vir_addr[55:48]}={address[48:45],tag[13:12], address[44:43]};

[0129] Group7{vir_addr[63:56]}={3’b00, tag[15:14], address[51:49]}.

[0130] Wherein, vir_addr represents a virtual address, address represents a data address, tag represents identification information, and 3'b00 represents that the high 3 bits are 0. address[] represents the position of the data address in the REQ message, tag[] represents the position of the identification information in the REQ message, and vir_addr[] represents the position of the obtained virtual address.

[0131] For example, when the first request message is an H2D Request message, the total length of the H2D Request message is 64 bits, wherein the data address is address[51:6], the identification information UQID occupies 12 bits, and RSVD occupies 6 bits. The data address and the identification information are divided into 8 groups, and after doping, 8 groups of virtual addresses can be obtained. The 8 groups of virtual addresses are represented as Group0~Group7, doping operations are performed on Group0~Group5, and a one-to-one mapping relationship is maintained for Group6~Group7. If the data address length is insufficient, the virtual address is filled with a default value.

[0132] The following doping scheme is adopted for Group0~Group3:

[0133] 1) Each group is composed of 2 bits of identification information and 6 bits of data address;

[0134] 2) The high 4 bits and the low 4 bits of each group are doped with 1 bit of identification information, respectively;

[0135] 3) According to the number of groups, the position of the identification information in the virtual address moves from low to high, and moves 1 bit each time.

[0136] The following doping scheme is adopted for Group4~Group5:

[0137] 1) Each group is composed of 2 bits of identification information and 6 bits of data address;

[0138] 2) The 2 bits of identification information in each group are connected;

[0139] 3) According to the number of groups, the position of the identification information in the virtual address moves from low to high, and moves 1 bit each time.

[0140] According to the above doping scheme, the following 8 groups of virtual addresses can be obtained:

[0141] Group0{vir_addr[7:0]}={ address[11:9], UQID [1],address[8:6],UQID[0]};

[0142] Group1{vir_addr15:8]}={ address[17:16], UQID[3], address[15:13], UQID[2],address

[12] };

[0143] Group2{vir_addr[23:16]}={ address

[23] , UQID[5], address[22:20], UQID[4],address[19:18]};

[0144] Group3{vir_addr[31:24]}={UQID[7],address[29:27],UQID[6],address[26:24]};

[0145] Group4{vir_addr[39:32]}={address[35:30], UQID [9:8]};

[0146] Group5{vir_addr [47:40]}={address[41:37],UQID[11:10], address

[36] };

[0147] Group6{vir_addr [55:48]}={address[49:42]};

[0148] Group7{vir_addr[63:56]}={4‘b000,address[51:50]}。

[0149] Wherein, vir_addr represents a virtual address, address represents a data address, UQID represents identification information, and 4’b00 represents that the value of the high 4 bits is 0. address[] represents the position of the data address in the H2D Request message, UQID[] represents the position of the identification information in the H2D Request message, and vir_addr[] represents the position of the obtained virtual address.

[0150] Optionally, when the address scrambling operation includes the exchange operation, the address scrambling operation is performed on the address groups to be processed, including: obtaining a first pseudo-random number; and respectively controlling the switching mode of the N switch arrays by using the first pseudo-random number, so that the N switch arrays respectively perform the position exchange within the groups on the N groups of addresses to be processed according to the preset length.

[0151] For example, the address to be processed has 8 groups, each group corresponds to 1 switch array, and the 8 switch arrays are controlled by the first pseudo-random number. The first pseudo-random number can only consist of 1 and 0, which is more suitable for the control of the switch. For example, the first pseudo-random number is 1011100011010001, which has a length of 16 bits, and each bit controls a switch. For example, the switch can be a multi-control switch, so that only 0 and 1 can be used to select the conduction path of the switch. For example, a group of addresses to be processed is "abcdefg", and after the position exchange in the group according to the preset length of 1 bit, "ahbdfecg" is obtained. Alternatively, one first pseudo-random number can be used to control N switch arrays, in which case the group exchange mode of each group of addresses to be processed is the same. In another optional implementation, a plurality of first pseudo-random numbers can be used to control N switch arrays, for example, N first pseudo-random numbers are used to control N switch arrays, in which case the group exchange mode of different groups of addresses to be processed can be different or the same.

[0152] Alternatively, obtaining the first pseudo-random number comprises: in response to receiving a clock signal, generating a pseudo-random number, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and in response to stopping receiving the clock signal, not generating a pseudo-random number; obtaining the pseudo-random number corresponding to the last clock cycle in the received clock signal as the first pseudo-random number.

[0153] In this embodiment, the generation of the pseudo-random number can be triggered by the clock signal, for example, the rising edge of the clock cycle in the clock signal is used to trigger the generation of the pseudo-random number, so that a pseudo-random number is generated every clock cycle. When the clock signal is stopped, that is, no new clock cycle is received, no pseudo-random number is generated. Each generated pseudo-random number can be used as the first pseudo-random number, so that the first pseudo-random number is updated following the clock cycle. When the clock signal is stopped, the pseudo-random number corresponding to the last clock cycle is obtained as the first pseudo-random number, and the first pseudo-random number will remain unchanged until the clock signal is received again. Through the scheme of this embodiment, the randomness of the first pseudo-random number can be increased, thereby improving the security of data transmission.

[0154] Alternatively, when the address scrambling operation includes a sequential adjustment operation, the address scrambling operation on the address to be processed is performed, comprising: obtaining a second pseudo-random number; taking the second pseudo-random number as a control sequence, and adjusting the group order of the N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the group order.

[0155] In the embodiment, the length of the second pseudo-random number is less than the first pseudo-random number. The second pseudo-random number can be obtained separately, or can be selected from the first pseudo-random number after the first pseudo-random number is obtained. For example, the third bit, the seventh bit and the ninth bit of the first pseudo-random number are selected as the second pseudo-random number. The way of obtaining the second pseudo-random number separately can refer to the way of obtaining the first pseudo-random number, which will not be described here.

[0156] For example, the N groups of to-be-processed addresses are the virtual addresses Group0~Group7 in the above, and the second pseudo-random number controls adjustment of the order of Group0~Group7. The preset adjustment rule in the embodiment can indicate an order adjustment manner of the N groups of to-be-processed addresses, such as a forward movement, a backward movement, a position exchange and the like. For example, the original order of Group0~Group7 is Group0, Group1, …, Group7, and the order after the forward movement is Group1, Group2, …, Group7, Group0.

[0157] Optionally, when the lengths of the N groups of to-be-processed addresses are different, a default value is used to fill to the N groups of virtual addresses, so that the lengths of the N groups of virtual addresses are the same.

[0158] In the embodiment, the length of the data address before the address scrambling can not be evenly divided into N groups. For example, the length of the data address is 46 bits, which can not be evenly divided into 8 groups. By filling the N groups of to-be-processed addresses to the same length, the same address scrambling operation can be performed on the N groups of to-be-processed addresses, so that the complexity of the processing process can be reduced.

[0159] Optionally, when the address scrambling operation includes at least two of the doping operation, the exchange operation and the order adjustment operation, the address scrambling operation is performed in the order of the doping operation, the exchange operation and the order adjustment operation in turn.

[0160] In the embodiment, the address scrambling operation can include the doping operation, the exchange operation and the order adjustment operation, or include the doping operation and the exchange operation, include the doping operation and the order adjustment operation, include the exchange operation and the order adjustment operation. When the address scrambling operation includes at least two operations, the at least two operations included can be executed in any order. For example, the doping operation is performed first, then the exchange operation is performed, and finally the order adjustment operation is performed. For another example, the exchange operation is performed first, then the doping operation is performed, and finally the order adjustment operation is performed. For another example, the order adjustment operation is performed first, then the exchange operation is performed, and finally the doping operation is performed.

[0161] In step S103, a second request message containing the scrambled address is sent to the link layer. The second request message corresponds to the first request message, and the second request message is a transaction layer packet.

[0162] After step S102 is performed, the scrambled address can be obtained, and the transaction layer data packet containing the scrambled address is continuously sent to the link layer to complete subsequent data transmission. In this embodiment, the first request message is received from the upper layer of the transaction layer, so that the information to be transmitted needs to be packaged into a transaction layer data packet and continuously transmitted to the link layer.

[0163] In the CXL protocol, the position of the data address in various messages is fixed, so that an attacker can intercept the power consumption curve of the address field by the characteristics of the address distribution in different messages or channels, and crack the address information by analyzing the power consumption. The doping operation can dope the address by means of other fields carried by the message itself, such as identification information, to reduce the regularity of the address distribution. The exchange operation can guarantee that the addresses in the messages sent within a certain time period have different scrambling modes by means of the characteristics of the random number, greatly reducing the regularity of the address distribution, so that the attacker cannot find the rule by analyzing the address power consumption and the like, and significantly improving the security of data transmission. The sequential exchange operation can further disrupt the address distribution and reduce the regularity of the address distribution.

[0164] The method for scrambling the address provided by the embodiment of the present disclosure can implement at least one of the doping, exchange and sequential adjustment operations on the data address, which is not only more suitable for the CXL protocol, but also can cope with more scenarios, improves the flexibility of the scheme while ensuring the security of data transmission.

[0165] Figure 2 A flowchart of a method for descrambling an address according to an embodiment of the present disclosure is shown.

[0166] As shown in Figure 2 The method 200 for descrambling an address includes the following steps:

[0167] Step S201 receives a third request message from the link layer, wherein the third request message is a transaction layer data packet and contains a scrambled address.

[0168] Step S202 performs an address descrambling operation on the to-be-processed address group to obtain a data address, the length of the data address being less than or equal to the length of the scrambled address, wherein the to-be-processed address is the scrambled address or an intermediate address during the address descrambling operation.

[0169] Step S203 sends a fourth request message containing the data address to the processing unit, wherein the fourth request message corresponds to the third request message.

[0170] The method for descrambling the address provided by the embodiment corresponds to the method for scrambling the address in the above. The descrambling of the address is the reverse operation of the address scrambling. In the present disclosure, the method 100 for scrambling the address can be performed by an electronic device or electronic equipment supporting the CXL protocol such as a chip, a processor, a controller, etc., and the method 200 for descrambling the address can be performed by an electronic device or electronic equipment supporting the CXL protocol such as a memory, a chip, a processor, a controller, etc. The method 100 for scrambling the address and the method 200 for descrambling the address can be implemented in the same device, or can be implemented in different devices connected to each other, or can be implemented separately.

[0171] The step S201 is performed to receive a third request message from the link layer, wherein the third request message is a transaction layer packet and contains a scrambled address.

[0172] In the embodiment, the third request message is a message from the link layer, which can be a link layer packet or a transaction layer packet obtained from the link layer packet. The third request message can have the same format as the second request message. The third request message is a read request message or a write request message and contains a scrambled address. The third request message can be a RWD, REQ and H2D Request message.

[0173] Optionally, before the step S202 is performed, it is further determined whether the address descrambling is enabled. For example, according to the configuration information in the third request message, it is determined whether the address descrambling is enabled and the operation included when the address descrambling is enabled.

[0174] In an optional implementation, similar to the configuration information in the first request message described above, the same configuration information can be used to indicate whether the address scrambling is enabled and whether the address descrambling is enabled at the same time. For example, when the configuration information indicates that the address scrambling is enabled, the address descrambling is also enabled correspondingly.

[0175] For example, RSVD[5:2] in the reserved field is the configuration information, RSVD[2] indicates whether the address scrambling and the address descrambling operation are enabled, RSVD[3] indicates whether the doping operation and the de-doping operation are enabled, RSVD[4] indicates whether the exchange operation and the reverse exchange operation are enabled, and RSVD[5] indicates whether the order adjustment operation and the reverse order adjustment operation are enabled. The value of RSVD[x] is 0 indicating disabled and 1 indicating enabled, and x is equal to 2, 3, 4 and 5. It can be understood that the value of RSVD[x] can also be set to 0 to indicate the enabled operation and to 1 to indicate the disabled operation.

[0176] In another optional implementation, different configuration information can be used to indicate whether the address scrambling is enabled and whether the address descrambling is enabled. For example, RSVD[5:2] in the reserved field is the configuration information of the address scrambling, RSVD[9:6] in the reserved field is the configuration information of the address descrambling, RSVD[2] indicates whether the address scrambling is enabled, RSVD[3] indicates whether the doping operation is enabled, RSVD[4] indicates whether the exchange operation is enabled, RSVD[5] indicates whether the order adjustment operation is enabled, RSVD[6] indicates whether the address descrambling operation is enabled, RSVD[7] indicates whether the de-doping operation is enabled, RSVD[8] indicates whether the reverse exchange operation is enabled, and RSVD[9] indicates whether the reverse order adjustment operation is enabled.

[0177] Optionally, whether the address descrambling operation is enabled can not be configured, but the configuration information of the de-doping operation, the reverse exchange operation and the reverse order adjustment operation can be used to indicate whether the address scrambling operation is enabled. For example, RSVD[5:3] in the reserved field is the configuration information of the address descrambling, RSVD[3] indicates whether the de-doping operation is enabled, RSVD[4] indicates whether the reverse exchange operation is enabled, and RSVD[5] indicates whether the reverse order adjustment operation is enabled. When the de-doping operation, the reverse exchange operation and the reverse order adjustment operation are all disabled, it is implicitly indicated that the address descrambling operation is disabled, and when at least one of the de-doping operation, the reverse exchange operation and the reverse order adjustment operation is enabled, it is indicated that the address descrambling operation is enabled.

[0178] In this embodiment, for the case that the data needs to be stored in the memory in a disordered manner, the address descrambling function can be selected to be disabled, thereby improving the flexibility of the scheme.

[0179] Optionally, the address descrambling operation can also be configured to be enabled or disabled by default. For example, the third request message can not contain the configuration information, and the address descrambling operation is configured to be in the enabled state, thereby enabling the address descrambling operation by default. For another example, the address descrambling operation is set to be in the disabled state, thereby disabling the address descrambling operation by default.

[0180] The step S202 is performed, and when the address descrambling is enabled, the address descrambling operation is performed on the address group to be processed to obtain the data address, and the length of the data address is less than or equal to the length of the scrambled address.

[0181] Optionally, the address descrambling operation includes at least one of the following operations: performing a de-doping operation on the address to be processed according to the identification information in the third request message; performing a pseudo-random reverse exchange operation on the address to be processed according to the pseudo-random number characteristics and in a preset length; and performing a pseudo-random reverse order adjustment operation on the order of the address group to be processed according to the pseudo-random number characteristics.

[0182] The address descrambling operation in the embodiment is the reverse operation of the address scrambling operation in the above embodiment, wherein the de-doping operation is to remove the identification information in the to-be-processed address and keep the address information. The reverse exchange operation is to restore the above exchange operation to obtain the unexchanged address information. The reverse order adjustment operation is to restore the grouping order of the to-be-processed address to the initial state to obtain the original grouping order.

[0183] Optionally, before the address descrambling operation is performed on the to-be-processed address groups, the method further comprises: dividing the scrambled address into N groups according to the position of the scrambled address in the third request message, wherein N is an integer greater than or equal to 2.

[0184] The scrambled address is an address scrambled through at least one of the above doping operation, exchange operation and order adjustment operation. The length of the scrambled address can be evenly divided into N groups, so the scrambled address can be directly divided into N groups from low to high. If the length of the scrambled address cannot be evenly divided into N groups, the third request message will have a specific grouping indication, so that the scrambled address is grouped according to the grouping indication.

[0185] Optionally, instead of dividing the scrambled address into N groups, the address descrambling operation is directly performed on the scrambled address grouped according to the position of the scrambled address in the third request message and the preset grouping rule in the address descrambling operation.

[0186] Optionally, when the address descrambling operation includes the de-doping operation, the address descrambling operation performed on the to-be-processed address groups comprises: removing N groups of identification information from N groups of to-be-processed addresses respectively according to a preset arrangement mode to obtain N groups of data addresses; wherein the preset arrangement mode indicates the relative position relationship between the data address and the identification information in each group of to-be-processed addresses, and the relative position relationship corresponding to the N groups of to-be-processed addresses is at least partially different.

[0187] Unlike the doping operation, the third request message does not have an area separately carrying the identification information, and the identification information is doped with the address. The de-doping operation is to remove N groups of identification information from N groups of to-be-processed addresses respectively according to a preset arrangement mode to obtain N groups of data addresses.

[0188] For example, when the third request message is an RWD message, the 8 groups of to-be-processed addresses are:

[0189] Group0{vir_address[7:0]}={ address[11:9], tag[1],address[8:6],tag[0]};

[0190] Group 1 {vir_addr[15:8]} = {address[17:16], tag[3], address[15:13], tag[2], address

[12] };

[0191] Group 2 {vir_addr[23:16]} = {address

[23] , tag[5], address[22:20], tag[4], address[19:18]};

[0192] Group 3 {vir_addr[31:24]} = {tag[7], address[29:27], tag[6], address[26:24]};

[0193] Group 4 {vir_addr[39:32]} = {address[35:30], tag[9:8]};

[0194] Group 5 {vir_addr[47:40]} = {address[41:37], tag[11:10], address

[36] };

[0195] Group 6 {vir_addr[55:48]} = {address[47:44], tag[13:12], address[43:42]};

[0196] Group 7 {vir_addr[63:56]} = {2'b00, address

[51] , tag[15:14], address[50:48]}.

[0197] Wherein, vir_addr represents a virtual address, address represents a data address, tag represents identification information, and 2'b00 represents that the values of the high two bits are 0. address[] represents the position of the data address in the RWD message, tag[] represents the position of the identification information in the RWD message, and vir_addr[] represents the position of the obtained virtual address.

[0198] The data address is extracted separately by removing the default value and the identification information:

[0199] Address[51:6] = {vir_addr

[61] , vir_addr[58:56], vir_addr[55:52], vir_addr[49:48], vir_addr[47:43], vir_addr

[40] , vir_addr[39:34] vir_addr[30:28], vir_addr[26:24], vir_addr

[23] , vir_addr[21:19], vir_addr[17:16], vir_addr[15:14], vir_addr[12:10], vir_addr[8], vir_addr[ 7:5], vir_addr[ 3:1]}.

[0200] For example, if the third request message is a H2D Request message, the eight groups of pending addresses are:

[0201] GroupO {vir_addr[7:0]} = {address[11:9], UQID [1], address[8:6], UQID[0]};

[0202] Groupl {vir_addr[15:8]} = {address[17:16], UQID[3], address[15:13], UQID[2], address

[12] };

[0203] Group2 {vir_addr[23:16]} = {address

[23] , UQID[5], address[22:20], UQID[4], address[19:18]};

[0204] Group3 {vir_addr[31:24]} = {UQID[7], address[29:27], UQID[6], address[26:24]};

[0205] Group4 {vir_addr[39:32]} = {address[35:30], UQID [9:8]};

[0206] Group5 {vir_addr[47:40]} = {address[41:37], UQID[11:10], address

[36] };

[0207] Group6 {vir_addr[55:48]} = {address[49:42]};

[0208] Group7{vir_addr[63:56]}={4‘b000,address[51:50]}。

[0209] Wherein, vir_addr represents a virtual address, address represents a data address, UQID represents identification information, and 4’b00 represents that the value of the high 4 bits is 0. address[] represents the position of the data address in the H2D Request message, UQID[] represents the position of the identification information in the H2D Request message, and vir_addr[] represents the position of the obtained virtual address.

[0210] Removing the default value and the identification information, the data address is extracted separately to obtain:

[0211] Address[51:6]={vir_addr[58:56],vir_addr[55:48],vir_addr[47:43],vir_addr

[40] ,vir_addr[39:34],vir_addr[30:28],vir_addr[26:24],vir_addr

[23] , vir_addr[21:19], vir_addr[17:16],vir_addr[15:14],vir_addr[12:10],vir_addr[8],vir_addr[ 7:5],vir_addr[ 3:1]}.

[0212] Optionally, when the address descrambling operation includes the reverse exchange operation, the address descrambling operation is performed on the address group to be processed, including: obtaining a first pseudo-random number; inverting the first pseudo-random number, and respectively controlling the switching mode of the N switch arrays by using the inverted result of the first pseudo-random number, so that the N switch arrays respectively perform position reverse exchange within the group according to the preset length on the N groups of address to be processed.

[0213] The reverse exchange operation corresponds to the exchange operation described above. For example, a set of addresses to be processed is "ahbdfecg", and after the reverse exchange operation of the positions in the group according to the preset length of 1 bit, "abcdefg" is obtained. "abcdefg" is the state before the exchange operation. The first pseudo-random number in this embodiment is the same as the first pseudo-random number described above, so as to ensure that the exchange operation and the reverse exchange operation correspond. After obtaining the first pseudo-random number, it is inverted to obtain the control sequence of the reverse exchange operation. The way of inverting the first pseudo-random number in this embodiment is related to the structure of the switch array. For example, it can be group inversion. For example, the first pseudo-random number is "0010, 1100, 1011, 0100, 0101". The first pseudo-random number is divided into 5 groups, each group controls 4 switches, and there are 5 layers of switches. The inverted first pseudo-random number is "0101, 0100, 1011, 1100, 0010".

[0214] Optionally, when the address descrambling operation includes the reverse order adjustment operation, the address descrambling operation is performed on the address groups to be processed, including: obtaining a second pseudo-random number; taking the second pseudo-random number as a control sequence, and adjusting the order of the N groups of addresses to be processed in reverse according to a preset adjustment rule of the control sequence and the group order.

[0215] In this embodiment, the length of the second pseudo-random number is less than that of the first pseudo-random number. The second pseudo-random number can be obtained separately, or can be selected from the first pseudo-random number after the first pseudo-random number is obtained. For example, the 3rd, 7th and 17th bits of the first pseudo-random number are selected as the second pseudo-random number. The way of obtaining the second pseudo-random number separately can refer to the way of obtaining the first pseudo-random number, which will not be described here.

[0216] The preset adjustment rule in this embodiment can indicate the order adjustment mode of the N groups of addresses to be processed, such as the reverse order adjustment mode including forward movement, backward movement, position exchange, etc. For example, Group1, Group2, …, Group7, Group0 of Group0~Group7 are adjusted in reverse by backward movement to obtain the original order Group0, Group1, …, Group7.

[0217] Optionally, when the N groups of addresses to be processed include a default value, the method further includes: removing the default value from the N groups of addresses to be processed to obtain N groups of data addresses. The default value is generally filled in the highest several bits or the lowest several bits of each group of addresses to be processed, and the default value can be easily removed.

[0218] Optionally, when the address descrambling operation comprises at least two of the doped-out operation, the reverse exchange operation and the reverse sequential adjustment operation, the address descrambling operation is performed in the order of performing the reverse sequential adjustment operation, the reverse exchange operation and the doped-out operation in sequence.

[0219] In the embodiment, the order of the address descrambling operation is related to the order of the address scrambling operation, which needs to be completely opposite to the order of the address scrambling operation. For example, when the order of the address scrambling operation is performing the doping operation, the exchange operation and the sequential adjustment operation in sequence, the order of the address descrambling operation is the reverse sequential adjustment operation, the reverse exchange operation and the doped-out operation.

[0220] The step S203 is performed to send a fourth request message containing the data address to the processing unit, the fourth request message corresponding to the third request message.

[0221] After the step S202 is performed, the data address can be obtained, so that the message containing the data address is continuously sent back to the processing unit. For example, sent to the processing unit via the bus. The format of the fourth request message can be the same as that of the first request message.

[0222] Figure 3a A schematic diagram of a circuit for scrambling an address is shown according to an embodiment of the present disclosure.

[0223] As shown in Figure 3a The circuit 300 for scrambling an address comprises a receiving module 310, an address scrambling module 320 and a sending module 330. The receiving module 310 is connected with the processing unit, for example, directly connected to the processing unit or connected to the processing unit through the bus. The address scrambling module 320 is connected with the receiving module 310 and the sending module 330. The sending module 330 is connected to the link layer. The circuit 300 in the embodiment is arranged in the transaction layer, which is further away from the physical layer relative to the link layer, so that the possibility of an attacker analyzing and obtaining the address is further reduced.

[0224] The receiving module 310 is configured to receive a first request message from the processing unit, wherein the first request message contains a data address.

[0225] The address scrambling module 320 is configured to perform an address scrambling operation on a to-be-processed address group to obtain a scrambled address, the length of the scrambled address being greater than or equal to the length of the data address, wherein the to-be-processed address is the data address or an intermediate address during the address scrambling operation.

[0226] The sending module 330 is configured to send a second request message containing the scrambled address to the link layer, the second request message corresponding to the first request message and the second request message being a transaction layer data packet.

[0227] Optionally, the address scrambling module 320 comprises: a doping unit 321 configured to perform a doping operation on the to-be-processed address according to the identification information in the first request message;

[0228] a swapping unit 322 configured to perform a pseudo-random swapping operation on the to-be-processed address according to the pseudo-random number characteristic and with a preset length; and

[0229] a sequence adjusting unit 323 configured to perform a pseudo-random sequence adjusting operation on the grouping sequence of the to-be-processed address.

[0230] In this embodiment, the address scrambling operation comprises at least one of the doping operation, the swapping operation and the sequence adjusting operation.

[0231] Figure 3a The connection relationship inside the address scrambling module 320 is not shown in FIG. 3, because there can be multiple connection modes inside the address scrambling module 320. When the doping unit 321, the swapping unit 322 and the sequence adjusting unit 323 are all enabled, there are 6 connection modes, including: (1) the receiving module 310→the doping unit 321→the swapping unit 322→the sequence adjusting unit 323→the sending module 330; (2) the receiving module 310→the doping unit 321→the sequence adjusting unit 323→the swapping unit 322→the sending module 330; (3) the receiving module 310→the swapping unit 322→the doping unit 321→the sequence adjusting unit 323→the sending module 330; (4) the receiving module 310→the swapping unit 322→the sequence adjusting unit 323→the doping unit 321→the sending module 330; (5) the receiving module 310→the sequence adjusting unit 323→the doping unit 321→the swapping unit 322→the sending module 330; and (6) the receiving module 310→the sequence adjusting unit 323→the swapping unit 322→the doping unit 321→the sending module 330.

[0232] When the doping unit 321 and the swapping unit 322 are enabled, there are 2 connection modes, namely (1) the receiving module 310→the doping unit 321→the swapping unit 322→the sending module 330; and (2) the receiving module 310→the swapping unit 322→the doping unit 321→the sending module 330. Similarly, when the doping unit 321 and the sequence adjusting unit 323 are enabled, or when the swapping unit 322 and the sequence adjusting unit 323 are enabled, there are 2 connection modes respectively. When only one of the doping unit 321, the swapping unit 322 and the sequence adjusting unit 323 is enabled, the receiving module 310 is connected to the enabled unit and to the sending module 330.

[0233] Figure 3b A schematic diagram of a circuit for scrambling an address is shown.

[0234] As Figure 3b shown, the address scrambling circuit 300' includes a receiving module 310, an address scrambling module 320 and a sending module 330. The receiving module 310, the address scrambling module 320 and the sending module 330 are the same as those in the address scrambling circuit 300, and will not be described herein again. The address scrambling circuit 300' further includes a detecting module 340, connected with the receiving module 310 and the address scrambling module 320, configured to determine whether the address scrambling is enabled and the enabled units in the address scrambling module 320 according to the configuration information in the first request message, and enable at least one unit in the address scrambling module 320 when it is determined that the address scrambling is enabled. Figure 3a

[0235] For example, the detecting module 340 can be connected between the receiving module 310 and the address scrambling module 320, and the address scrambling module 320 can enable the corresponding units according to the indication of the detecting module, such as enabling the permutation unit 321, the exchange unit 322 and the sequence adjustment unit 323. In yet another implementation, the detecting module can be a module inside the address scrambling module 320, in which case the detecting module is connected to the permutation unit 321, the exchange unit 322 and the sequence adjustment unit 323, and enables the corresponding units according to the detection result.

[0236] Optionally, the detecting module 340 is further configured to disable the address scrambling module when it is determined that the address scrambling is disabled. The detecting module can disable the entire address scrambling module, so that the received first request message is directly sent to the link layer after being packaged into a transaction layer data packet, without experiencing address scrambling.

[0237] Optionally, when at least two of the permutation unit, the exchange unit and the sequence adjustment unit are enabled, the address scrambling module is configured to perform the address scrambling operation on the data address in the order of the permutation unit, the exchange unit and the sequence adjustment unit.

[0238] The permutation unit 321, the exchange unit 322 and the sequence adjustment unit 323 in the embodiment correspond to performing the permutation operation, the exchange operation and the sequence adjustment operation, and the specific execution manner can be referred to the description in the foregoing, which will not be described herein again. The foregoing has introduced various connection manners of the units inside the address scrambling module 320, and in the case of fixed connection relationship, the order of the address scrambling operation is also fixed.

[0239] Optionally, the address scrambling module 320 further includes a grouping unit 324, connected with the receiving module 310, the permutation unit 321, the exchange unit 322 and the sequence adjustment unit 323, and configured to divide the data address into N groups according to the position of the data address in the first request message before performing the address scrambling operation on the grouped addresses to be processed, where N is an integer greater than or equal to 2. ​

[0240] In this embodiment, the grouping unit 324 is connected with the receiving module 310, and is also connected to the three units of the doping unit 321, the switching unit 322 and the sequence adjusting unit 323. According to the enabled units and the connection mode, the grouping unit 324 selectively sends the grouped data address to one of the doping unit 321, the switching unit 322 and the sequence adjusting unit 323.

[0241] Optionally, the doping unit 321 is configured to: divide the identification information into N groups according to positions of the identification information in the first request message; and dope N groups of identification information with N groups of to-be-processed addresses respectively according to a preset arrangement mode, to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates a relative position relationship between the to-be-processed addresses and the identification information in each group of virtual addresses, and the relative position relationships corresponding to the N groups of virtual addresses are at least partially different.

[0242] In this embodiment, the doping unit 321 can dope the identification information and the to-be-processed addresses in the manner described in the above method embodiment, which will not be described here again.

[0243] Optionally, the switching unit 322 is configured to: obtain a first pseudo-random number; and control switching modes of N switch arrays respectively by using the first pseudo-random number, so as to make the N switch arrays respectively perform position switching within groups on the N groups of to-be-processed addresses according to a preset length.

[0244] Figure 4 A schematic diagram of a multi-control switch is shown.

[0245] Figure 4 Two connection states of the multi-control switch are shown, which are a straight-through state and a cross state. Both the straight-through state and the cross state belong to a conduction state, and the switch-off state of the switch is not discussed in this embodiment.

[0246] The multi-control switch 401 and the multi-control switch 402 both have four ports, and the port a and the port b are input ports, and the port c and the port d are output ports. The multi-control switch 401 is in a straight-through state, and the port a is connected to the port c, and the port b is connected to the port d. The multi-control switch 402 is in a cross state, and the port a is connected to the port d, and the port b is connected to the port c. The multi-control switch switches between the straight-through state and the cross state, for example, “0” and “1” are used to indicate the straight-through state and the cross state. When the control indication of the multi-control switch is “0”, the multi-control switch is controlled to be in the straight-through state, and when the control indication is “1”, the multi-control switch is controlled to be in the cross state.

[0247] Optionally, in addition to the above-mentioned connection mode, the multi-control switch can also be connected in the following connection mode. Figure 4The multi-control switch shown can also use other forms of switches to realize the connection and switching of the pass-through state and the exchange state. For example, two single-pole double-throw switches can be used to realize the function of the multi-control switch, the input ports of the two single-pole double-throw switches are port a and port b respectively, and the two single-pole double-throw switches are connected to port c and port d, but the control modes of the two single-pole double-throw switches are opposite, that is, “0” controls one single-pole double-throw switch to be connected to port c, and controls the other single-pole double-throw switch to be connected to port d at the same time, so as to realize the function of the multi-control switch as shown in Figure 4 .

[0248] Figure 5 A schematic diagram of a switch array provided according to an embodiment of the present disclosure is shown.

[0249] As shown in Figure 5 , the switch array 500 includes 4 rows * 5 columns, a total of 20 switches, and the switches constituting the switch array 500 can be multi-control switches as shown in Figure 4 .

[0250] The switch array 500 includes 5 columns of switches, each column including 4 switches, and there are 8 input ports and 8 input ports, which can process an address to be processed with a length of 8 bits. The “column” in the switch array 500 can also be referred to as “layer”, that is, there are 5 layers of switches.

[0251] Figure 5 L0, L1, L2, L3 and L4 are open relations numbers, which control a column of switches respectively. The open relations number can be obtained from a first pseudo-random number. For example, the length of the first pseudo-random number is 20 bits, and the first pseudo-random number is divided into 5 groups, that is, L0~L4. For example, the first pseudo-random number is “01101100101101000101”, the open relations number L0 is “0101”, L1 is “1100”, L2 is “1011”, L3 is “0100”, and L4 is “0101”. In this example, “0” controls the switch to present a cross state, and “1” controls the switch to present a pass-through state. It should be noted that the open relations number only controls the conduction mode of the switch, such as pass-through or cross, and the open relations number does not affect the connection mode between the switches. Figure 5 Only one possible switch array and connection mode between switches are shown, and there are many connection modes between switches in each column, which will not be listed one by one. Even if all the switches in the switch array 500 are in a pass-through state or in a cross state, the connection mode of each column of switches in the switch array 500 itself can exchange the input address.

[0252] Referring to Figure 5 the switch array 500 and the conduction mode of each switch, it is assumed that the input address is “abcdefgh”, and the exchange mode of each column of switches is as follows:

[0253] abcdefgh through L0 routing gets bacdefhg; bacdefhg through L1 routing gets bcehdagf; bcehdagf through L2 routing gets behcdgaf; behcdgaf through L3 routing gets hbecadfg; hbecadfg through L4 routing gets ahbdfecg.

[0254] As shown in the switch array 500, only the switching operation of a set of addresses to be processed with a length of 8 bits can be performed, and when there are N sets of addresses to be processed, N switch arrays are needed. For example, when there are 8 sets of addresses to be processed, 8 switch arrays are needed, and the 8 switch arrays can all use the switch array 500, or the 8 switch arrays can all use different switch arrays. Correspondingly, the N switch arrays can all use the same first pseudo-random number as the switch-on number, or N first pseudo-random numbers can be generated for the N switch arrays. Figure 5 In an implementation mode, for N sets of addresses to be processed, the same switch array can be reused, for example, inputting the N sets of addresses to be processed in time sequence into the switch array, and N sets of addresses after intra-group switching can be obtained. The embodiment can reduce the number of switch arrays needed and save hardware resources.

[0255] FIG. 6a shows a schematic diagram of a linear feedback shift register according to an embodiment of the present disclosure.

[0256] In FIG. 6a, the linear feedback shift register 600 is a 6-tap 20-bit linear feedback shift register, and the tap positions can be set according to requirements, which are not limited here. The linear feedback shift register 600 outputs a pseudo-random number with a length of 20 bits. Reg[m] in FIG. 6a represents a register, m is equal to 0-19, and each register in FIG. 6a can be a register composed of D flip-flops. The input of the linear feedback shift register 600 is a clock signal CLOCK, and the rising or falling edge of the clock period can trigger the generation of a new pseudo-random number.

[0257] Optionally, the switching unit comprises: a linear feedback shift register configured to generate a first pseudo-random number; and N switch arrays, each switch array comprising a plurality of multi-control switches, wherein each switch array is configured to control the on or off of the plurality of multi-control switches according to the switch mode corresponding to the first pseudo-random number, so that a set of addresses to be processed input into one switch array is switched in position during the transmission of one switch array.

[0258]

[0259] ​For example, the switching unit 322 can include a linear feedback shift register 600 and N switch arrays 500, and a first pseudo-random number output by the linear feedback shift register 600 controls the conduction mode of the switches in the N switch arrays.

[0260] In this embodiment, the length of the pseudo-random number output by the linear feedback shift register included in the switching unit depends on the number of switches in the switch array. For example, if the switch array includes 20 switches, a pseudo-random number with a length of 20 bits is required, and if the switch array includes 16 switches, a pseudo-random number with a length of 16 bits is required.

[0261] Alternatively, the linear feedback shift register is configured to generate a pseudo-random number in response to receiving a clock signal, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and not to generate a pseudo-random number in response to stopping receiving the clock signal; and the pseudo-random number corresponding to the last clock cycle in the received clock signal is taken as the first pseudo-random number.

[0262] In this embodiment, the linear feedback shift register is triggered by the clock signal, so that when there is no clock signal input, the generation of new pseudo-random numbers is stopped, and the property of the register can save the last generated pseudo-random number, so that when the first pseudo-random number is obtained, the pseudo-random number can always be obtained as the first pseudo-random number.

[0263] Alternatively, the switching unit further includes a clock gate connected with the linear feedback shift register and configured to control the input of the clock signal of the linear feedback shift register.

[0264] Figure 6b A schematic diagram of a switching unit according to an embodiment of the present disclosure is shown.

[0265] In Figure 6b , the switching unit 610 includes a linear feedback shift register 611 and N switch arrays 612 and a clock gate 613. The clock gate 613 is connected with the linear feedback shift register 611, and the linear feedback shift register 611 is connected with the N switch arrays 612.

[0266] The input of the clock gate 613 is a clock signal, and the clock gate 613 controls the input of the clock signal to the linear feedback shift register 611. The linear feedback shift register 611 generates a pseudo-random number according to the clock signal, and outputs the pseudo-random number to the N switch arrays 612 as a control signal. The N switch arrays 612 control the conduction and non-conduction of the switches inside each switch array 612 according to the switch mode corresponding to the pseudo-random number. For example, the linear feedback shift register 611 can be the linear feedback shift register 600 shown in FIG. 6a, and the switch array 612 can be the switch array 500 shown in FIG. 6b. Figure 5 The switch array 500 is shown.

[0267] For example, the above-mentioned switching unit 322 can be implemented by the switching unit 610 in FIG. 6b. Figure 6b

[0268] In this embodiment, a clock gating can be added, which is connected between the clock signal and the linear feedback shift register, for controlling the on or off of the clock signal. Setting the clock gating can further increase the randomness of the switching operation, and thus improve the security of data transmission.

[0269] Optionally, the sequential adjustment unit is configured to: obtain a second pseudo-random number; take the second pseudo-random number as a control sequence, and adjust the group order of the N groups of to-be-processed addresses according to a preset adjustment rule of the control sequence and the group order.

[0270] In this embodiment, the adjustment manner of the address group order is simpler than the switching operation, and the second pseudo-random number can be selected from several bits of the first pseudo-random number. For example, the 3-bit data of the 3, 9 and 17 taps shown in FIG. 6a can be selected as the second pseudo-random number.

[0271] The control sequence can be set as Trng_ctl={reg[3],reg[9], reg

[17] }. The sequential adjustment manner can adopt the following rules:

[0272] 1) Trng_ctl[2:0]=1, left shift 1 bit in each Group cycle; that is, Group0 becomes Group1, …, Group6 becomes Group7;

[0273] 2) Trng_ctl[2:0]=2, left shift 2 bits in each Group cycle; that is, Group0 becomes Group2, …, Group6 becomes Group0;

[0274] 3) Trng_ctl[2:0]=3, left shift 3 bits in each Group cycle; that is, Group0 becomes Group3, …, Group6 becomes Group1;

[0275] 4) Trng_ctl[2:0]=4, exchange adjacent Groups, that is, exchange Group0 and Group1, exchange Group2 and Group3, exchange Group4 and Group5, and exchange Group6 and Group7.

[0276] Optionally, the doping unit is further configured to, when the lengths of the N groups of to-be-processed addresses are different, fill a default value to the N groups of virtual addresses so as to make the lengths of the N groups of virtual addresses same.

[0277] ​In the embodiment, in order to facilitate the implementation of the address scrambling operation, the to-be-processed addresses can be padded so that the length of each group of to-be-processed addresses is the same. In addition to the doping unit, the switching unit and the order adjustment unit can be configured to pad the N groups of to-be-processed addresses, and the default value is usually "0" or "1". For example, when only the switching unit is enabled, if the length of the data address cannot be evenly divided into N groups, the padding of the default value can be performed first. Compared with the case where the length of each group of addresses is different, the same length of the addresses can make the switching operation easier to implement.

[0278] Figure 7a A schematic diagram of a circuit for descrambling addresses according to an embodiment of the present disclosure is shown.

[0279] As shown in Figure 7a The circuit 700a for descrambling addresses includes a receiving module 710, an address descrambling module 720, and a sending module 730. The receiving module 710 is connected to the link layer. The address descrambling module 720 is connected to the receiving module 710 and the sending module 730. The sending module 730 is connected to the processing unit, for example, directly connected to the processing unit or connected to the processing unit through a bus.

[0280] The receiving module 710 is configured to receive a third request message from the link layer, wherein the third request message is a transaction layer data packet and contains a scrambled address.

[0281] The address descrambling module 720 is configured to, when address descrambling is enabled, perform an address descrambling operation on a to-be-processed address group to obtain a data address, the length of the data address being less than or equal to the length of the scrambled address, wherein the to-be-processed address is the scrambled address or an intermediate address during the address descrambling operation.

[0282] The sending module 730 is connected to the address descrambling module and sends a fourth request message containing the data address to the processing unit, the fourth request message corresponding to the third request message.

[0283] Optionally, the address descrambling module 720 includes the following units:

[0284] The de-doping unit 721 is configured to perform a de-doping operation on the to-be-processed address according to the identification information in the third request message;

[0285] The reverse switching unit 722 is configured to perform a pseudo-random reverse switching operation on the to-be-processed address according to the pseudo-random number characteristics and a preset length; and

[0286] The reverse order adjustment unit 723 is configured to perform a pseudo-random reverse order adjustment operation on the grouping order of the to-be-processed address.

[0287] The address descrambling operation in this embodiment includes at least one of the de-doping operation, the reverse exchange operation, and the reverse order adjustment operation.

[0288] Figure 7a The connection relationship inside the address descrambling module 720 is not shown, similar to the address scrambling module 320, there can be multiple connection modes in the address descrambling module 720, and the specific connection mode is opposite to that of the address scrambling module 320, which will not be expanded here.

[0289] Optionally, the circuit 700b for descrambling the address further includes a detection module 740, connected with the receiving module 710 and the address descrambling module 720, configured to determine whether the address descrambling is enabled and the enabled units in the address descrambling module according to the configuration information in the third request message, and enable at least one unit in the address descrambling module when it is determined that the address descrambling is enabled.

[0290] For example, the detection module 740 can be connected between the receiving module 710 and the address descrambling module 720, and the address descrambling module 720 can enable the corresponding unit according to the indication of the detection module 740, such as enabling the reverse exchange unit 722.

[0291] Figure 7b A schematic diagram of a circuit for descrambling an address is shown.

[0292] As Figure 7b shown, the circuit 700b for descrambling the address includes a receiving module 710, an address descrambling module 720, a sending module 730, and a detection module 740. The receiving module 710 and the sending module 730 are the same as shown in Figure 7a , which will not be repeated here.

[0293] The detection module 740 is connected between the receiving module 710 and the address descrambling module 720, and determines whether the address descrambling is enabled and the enabled units in the address descrambling module 720 according to the configuration information in the third request message, and indicates to the address descrambling module 720 to enable the address descrambling and the corresponding enabled units when the address descrambling is enabled.

[0294] In yet another implementation, the detection module can be a module inside the address descrambling module, in which case the detection module is connected to the de-doping unit, the reverse exchange unit, and the reverse order adjustment unit, and enables the corresponding unit according to the detection result.

[0295] Figure 7c A schematic diagram of a circuit for descrambling an address is shown.

[0296] As Figure 7bAs shown, the circuit 700c for address descrambling includes a receiving module 710, an address descrambling module 720, and a sending module 730. The receiving module 710 and the sending module 730 are connected to the address descrambling module 720. Figure 7a As shown, the same is not described here.

[0297] The detection module 725 is connected to the de-doping unit 721, the reverse exchange unit 722, and the reverse sequence adjustment unit 723, and enables the corresponding unit according to the detection result.

[0298] Optionally, the detection module is further configured to disable the address descrambling module when it is determined that the address descrambling is disabled. The detection module can disable the entire address descrambling module, so that the received third request message is unpacked and directly sent to the processing unit without undergoing address descrambling.

[0299] Optionally, when at least two of the de-doping unit, the reverse exchange unit, and the reverse sequence adjustment unit are enabled, the address descrambling module is configured to perform the address descrambling operation on the scrambled address in the order of the reverse sequence adjustment unit, the reverse exchange unit, and the de-doping unit.

[0300] Optionally, the address descrambling module further includes a grouping unit connected to the receiving module, the de-doping unit, the reverse exchange unit, and the reverse sequence adjustment unit, and configured to divide the scrambled address into N groups according to the position of the scrambled address in the third request message, where N is an integer greater than or equal to 2. For example Figure 7b and Figure 7c As shown, the grouping unit 724 is connected to the receiving module 710, the de-doping unit 721, the reverse exchange unit 722, and the reverse sequence adjustment unit 723.

[0301] In this embodiment, the grouping unit 724 can be connected to the receiving module 710, and also connected to the de-doping unit 721, the reverse exchange unit 722, and the reverse sequence adjustment unit 723. According to the enabled units and the connection mode, the grouping unit selectively sends the grouped data address to one of the de-doping unit 721, the reverse exchange unit 722, and the reverse sequence adjustment unit 723.

[0302] Optionally, the de-doping unit is configured to remove N groups of identification information from N groups of to-be-processed addresses respectively according to a preset arrangement mode, to obtain N groups of data addresses; where the preset arrangement mode indicates the relative position relationship between the data address and the identification information in each group of to-be-processed addresses, and the relative position relationships corresponding to the N groups of to-be-processed addresses are at least partially different. In this embodiment, the de-doping unit 721 can refer to the description of the above method embodiments for the de-doping manner of the to-be-processed address, which is not described here

[0303] Optionally, the reverse switching unit is configured to: obtain a first pseudo-random number; invert the first pseudo-random number, and control the switching mode of the N switching arrays respectively by using the inverted result of the first pseudo-random number, so that the N switching arrays perform in-position reverse switching on the N groups of to-be-processed addresses in a preset length respectively.

[0304] Figure 8 A schematic diagram of yet another switching array is shown according to an embodiment of the present disclosure.

[0305] The connection mode between the switches in the switching array 800 is the same as that between the switches in the switching array 500, but the conduction mode of the switches is different from that shown in the switching array 500. In this example, the first pseudo-random number is "01101100101101000101", the first pseudo-random number is grouped and inverted, and the switching relationship number L0 is "0101", L1 is "0100", L2 is "1011", L3 is "1100", and L4 is "0110". The address input into the switching array 800 is "ahbdfecg", and the address after reverse switching is "abcdefgh".

[0306] Optionally, the reverse order adjustment unit is configured to: obtain a second pseudo-random number; take the second pseudo-random number as a control sequence, and reverse the grouping order of the N groups of to-be-processed addresses according to a preset adjustment rule of the control sequence and the grouping order.

[0307] Optionally, the de-doping unit is further configured to: when the N groups of to-be-processed addresses include a default value, remove the default value from the N groups of to-be-processed addresses to obtain N groups of data addresses.

[0308] Optionally, the linear feedback shift register is configured to: in response to receiving a clock signal, generate a pseudo-random number, wherein each clock cycle in the clock signal corresponds to a pseudo-random number, and in response to stopping receiving the clock signal, not generate a pseudo-random number; and take the pseudo-random number corresponding to the last clock cycle in the received clock signal as the first pseudo-random number.

[0309] Optionally, the reverse switching unit further includes: a clock gate connected with the linear feedback shift register and configured to control the input of the clock signal of the linear feedback shift register.

[0310] Figure 9 A schematic diagram of a reverse switching unit is shown according to an embodiment of the present disclosure.

[0311] In Figure 9In the reverse switching unit 910, there are linear feedback shift registers 911, N switch arrays 912, and a clock gate 913. The clock gate 913 is connected to the linear feedback shift register 911, and the linear feedback shift register 911 is connected to the N switch arrays 912.

[0312] The clock gate 913 receives a clock signal as input and controls the clock signal input to the linear feedback shift register 911. The linear feedback shift register 911 generates a pseudo-random number based on the clock signal and outputs this pseudo-random number to N switch arrays 912 as control signals. The N switch arrays 912 control the on / off state of the switches within each array according to the switching mode corresponding to the pseudo-random number. For example, the linear feedback shift register 911 can be the linear feedback shift register 600 shown in Figure 6a, and the switch arrays 912 can be... Figure 8 The switch array 800 is shown.

[0313] In this embodiment, the linear feedback shift register needs to be consistent with the linear feedback shift register in the switching unit to ensure that the generated random numbers are consistent.

[0314] Optionally, at least one embodiment of this disclosure provides an electronic device including a processor and a memory, wherein the memory stores computer-executable instructions, which are executed by the processor to implement any one of the methods described in the first method embodiment and / or the second method embodiment described above.

[0315] Figure 10 This is a schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure.

[0316] like Figure 10 As shown, the electronic device 1000 includes a processor 1001 and a memory 1002. The memory 1002 stores computer-executable instructions. When the processor 1001 executes the computer-executable instructions, it implements the method described in the above embodiments.

[0317] The terminal devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (such as in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 10 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0318] For example, in accordance with embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program comprising program code for carrying out the methods illustrated by the flowcharts.

[0319] Optionally, at least one embodiment of the present disclosure provides a computer-readable storage medium having stored thereon instructions, wherein the instructions are loaded and executed by a processor to implement the method of any one of the above first method embodiment and / or the above second method embodiment.

[0320] It should be noted that the above computer-readable medium of the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In embodiments of the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus or device. In embodiments of the present disclosure, the computer-readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take on many forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium that is not a storage medium and that can communicate, propagate or transport program for use by or in connection with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to a wire, an optical fiber, an RF (radio frequency) or the like, or any suitable combination of the above.

[0321] The above computer-readable medium can be included in the above electronic device; or can exist separately and not be assembled into the electronic device.

[0322] At least one embodiment of the present disclosure also provides a chip, such as the address scrambling circuit of any one of the above embodiments and / or the address descrambling circuit of any one of the above embodiments.

[0323] For example, the chip can include address scrambling circuitry, address descrambling circuitry, or both. For example, a controller in the memory can include only address descrambling circuitry.

[0324] The electronic device can be any device having a computing function, such as a computer, a server, a smart phone, a tablet computer, and the like, and embodiments of the present disclosure are not limited thereto.

[0325] The above describes the basic principles of the present application in conjunction with specific embodiments, but it should be noted that the advantages, advantages, effects, and the like mentioned in the present application are only examples and are not limiting, and these advantages, advantages, effects, and the like cannot be considered as the must-have of each embodiment of the present application. In addition, the above specific details are only for the purpose of example and for the purpose of understanding, and are not limiting, and the above details do not limit the present application to the must-use specific details.

[0326] It is worth noting that the step flowchart in the present application and the above method description are only exemplary examples and are not intended to require or imply that the steps of each embodiment must be performed in the order given; certain steps can be performed in parallel, independently of each other, or in other appropriate order. In addition, words such as "secondly", "then", "next", and the like are not intended to limit the order of steps; these words are only used to guide the reader to read through the description of these methods.

[0327] The block diagram of the device, apparatus, equipment, system involved in the present application is only an exemplary example and is not intended to require or imply that the connection, arrangement, configuration must be as shown in the block diagram. It should also be noted that in the apparatus and method of the present application, each component or step can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of the present application.

[0328] The following points need to be explained: (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the usual design. (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments. The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for scrambling an address, comprising: receiving a first request message from a processing unit, wherein the first request message contains a data address; performing an address scrambling operation on a group of to-be-processed addresses to obtain a scrambled address, the scrambled address having a length greater than or equal to that of the data address, wherein the to-be-processed address is the data address or an intermediate address during the address scrambling operation; sending a second request message containing the scrambled address to a link layer, the second request message corresponding to the first request message and being a transaction layer packet, wherein the address scrambling operation comprises at least one of the following operations: performing a doping operation on the to-be-processed address according to identification information in the first request message; performing a pseudo-random exchange operation on the to-be-processed address according to a pseudo-random number characteristic and according to a preset length; and performing a pseudo-random order adjustment operation on a group order of the to-be-processed address according to a pseudo-random number characteristic; when the address scrambling operation comprises the exchange operation, the performing of the address scrambling operation on the group of to-be-processed addresses comprises: obtaining a first pseudo-random number; controlling a switching mode of N switch arrays respectively by using the first pseudo-random number, so that the N switch arrays respectively perform a position exchange within N groups of to-be-processed addresses according to the preset length, wherein the to-be-processed address is pre-divided into the N groups of to-be-processed addresses, and N is an integer greater than or equal to 2.

2. The method of claim 1, wherein, Before the performing of the address scrambling operation on the group of data addresses, the method further comprises: determining whether address scrambling is enabled and operations included when address scrambling is enabled according to configuration information in the first request message.

3. The method of claim 1, wherein, When the address scrambling operation comprises at least two of the doping operation, the exchange operation and the order adjustment operation, the address scrambling operation is performed according to an order of sequentially performing the doping operation, the exchange operation and the order adjustment operation.

4. The method of claim 1, wherein, Before the performing of the address scrambling operation on the group of to-be-processed addresses, the method further comprises: dividing the data address into N groups according to a position of the data address in the first request message, wherein N is an integer greater than or equal to 2.

5. The method of claim 4, wherein, When the address scrambling operation comprises the doping operation, the performing of the address scrambling operation on the group of to-be-processed addresses to obtain a scrambled address comprises: dividing the identification information into N groups according to a position of the identification information in the first request message; performing doping on N groups of identification information and N groups of to-be-processed addresses respectively according to a preset arrangement mode to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates a relative position relationship between a to-be-processed address and identification information in each group of virtual addresses, and the relative position relationship corresponding to the N groups of virtual addresses is at least partially different.

6. The method of any one of claims 4-5, wherein, When the address scrambling operation comprises the order adjustment operation, the performing of the address scrambling operation on the group of to-be-processed addresses comprises: obtaining a second pseudo-random number; The second pseudo-random number is used as a control sequence, and a preset adjustment rule of the control sequence and the grouping order of the N groups of to-be-processed addresses is used to adjust the grouping order of the N groups of to-be-processed addresses.

7. The method of claim 5, wherein, When lengths of the N groups of to-be-processed addresses are different, default values are used to fill the N groups of virtual addresses, so that lengths of the N groups of virtual addresses are the same.

8. The method of claim 1, wherein, The first pseudo-random number is obtained by: In response to receiving a clock signal, a pseudo-random number is generated, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and in response to stopping receiving the clock signal, the pseudo-random number is not generated; The pseudo-random number corresponding to the last clock cycle in the received clock signal is obtained as the first pseudo-random number.

9. A method for address descrambling, comprising: receiving a third request message from a link layer, wherein the third request message is a transaction layer packet and contains a scrambled address; performing address descrambling on a to-be-processed address group to obtain a data address, the length of the data address being less than or equal to the length of the scrambled address, the to-be-processed address being the scrambled address or an intermediate address during the address descrambling; sending a fourth request message containing the data address to a processing unit, the fourth request message corresponding to the third request message, wherein the address descrambling includes at least one of the following operations: performing a de-doping operation on the to-be-processed address according to identification information in the third request message; performing a pseudo-random reverse exchange operation on the to-be-processed address according to pseudo-random number characteristics and a preset length; and performing a pseudo-random reverse order adjustment operation on the grouping order of the to-be-processed address according to pseudo-random number characteristics; when the address descrambling includes the reverse exchange operation, the address descrambling on the to-be-processed address group includes: obtaining a first pseudo-random number; inverting the first pseudo-random number, and using the inverted result of the first pseudo-random number to control the switching mode of N switch arrays respectively, so that the N switch arrays perform position reverse exchange within N groups of to-be-processed addresses according to the preset length, wherein the to-be-processed address is divided into the N groups of to-be-processed addresses in advance, and N is an integer greater than or equal to 2.

10. The method of claim 9, wherein, Before the address descrambling on the to-be-processed address group, the method further includes: determining whether address descrambling is enabled and the operations included when address descrambling is enabled according to configuration information in the third request message.

11. The method of claim 9, wherein, When the address descrambling includes at least two of the de-doping operation, the reverse exchange operation and the reverse order adjustment operation, the address descrambling is performed in the order of sequentially performing the reverse order adjustment, the reverse exchange operation and the de-doping operation.

12. The method of claim 9, wherein, Before the address descrambling on the to-be-processed address group, the method further includes: dividing the scrambled address into N groups according to the position of the scrambled address in the third request message, wherein N is an integer greater than or equal to 2.

13. The method of claim 12, wherein, In a case where the address descrambling operation comprises the de-doping operation, the address descrambling operation on the address group to be processed comprises: According to a preset arrangement mode, N groups of identification information are removed from N groups of to-be-processed addresses respectively to obtain N groups of data addresses; The preset arrangement mode indicates a relative position relationship between a data address and identification information in each group of to-be-processed addresses, and the relative position relationship corresponding to the N groups of to-be-processed addresses is at least partially different.

14. The method of any one of claims 12-13, wherein, In a case where the address descrambling operation comprises the reverse sequence adjustment operation, the address descrambling operation on the address group to be processed comprises: A second pseudo-random number is obtained; The second pseudo-random number is used as a control sequence, and a grouping sequence of the N groups of to-be-processed addresses is reversely adjusted according to a preset adjustment rule of the control sequence and the grouping sequence.

15. The method of claim 13, wherein, In a case where the N groups of to-be-processed addresses comprise a default value, the method further comprises: The default value is removed from the N groups of to-be-processed addresses to obtain the N groups of data addresses.

16. The method of claim 9, wherein, The first pseudo-random number is obtained by: In response to receiving a clock signal, a pseudo-random number is generated, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and in response to stopping receiving the clock signal, the pseudo-random number is not generated; The first pseudo-random number is obtained as a pseudo-random number corresponding to a last clock cycle in the received clock signal.

17. A circuit for scrambling an address, comprising: a receiving module configured to receive a first request message from a processing unit, wherein the first request message contains a data address; an address scrambling module connected with the receiving module and configured to perform an address scrambling operation on an address group to be processed to obtain a scrambled address, the length of the scrambled address being greater than or equal to the length of the data address, the to-be-processed address being the data address or an intermediate address during the address scrambling operation; a sending module connected with the address scrambling module and configured to send a second request message containing the scrambled address to a link layer, the second request message corresponding to the first request message and the second request message being a transaction layer data packet, wherein the address scrambling module comprises: a doping unit configured to perform a doping operation on the to-be-processed address according to identification information in the first request message; a swapping unit configured to perform a pseudo-random swapping operation on the to-be-processed address according to a pseudo-random number characteristic and a preset length; and a sequence adjustment unit configured to perform a pseudo-random sequence adjustment operation on a grouping sequence of the to-be-processed address according to a pseudo-random number characteristic; wherein the address scrambling operation comprises at least one of the doping operation, the swapping operation and the sequence adjustment operation; wherein the swapping unit is configured to: obtain a first pseudo-random number; control a switching mode of N switch arrays respectively by using the first pseudo-random number, so that the N switch arrays perform position swapping within groups on N groups of to-be-processed addresses according to the preset length, wherein the to-be-processed address is divided into the N groups of to-be-processed addresses in advance, and N is an integer greater than or equal to 2.

18. The circuit of claim 17, wherein, The circuit further comprises: The detection module is connected with the receiving module and the address scrambling module, and is configured to determine whether address scrambling is enabled and units enabled in the address scrambling module according to configuration information in the first request message, and enable at least one unit in the address scrambling module when it is determined that address scrambling is enabled.

19. The circuit of claim 18, wherein, The detection module is further configured to disable the address scrambling module when it is determined that address scrambling is disabled.

20. The circuit of claim 18, wherein, When at least two of the doping unit, the exchange unit and the sequence adjustment unit are enabled, the address scrambling module is configured to perform the address scrambling operation on the data address in the order of the doping unit, the exchange unit and the sequence adjustment unit.

21. The circuit of claim 18, wherein, The address scrambling module further comprises: A grouping unit connected with the receiving module, the doping unit, the exchange unit and the sequence adjustment unit, and configured to divide the data address into N groups according to the position of the data address in the first request message before performing the address scrambling operation on the groups of addresses to be processed, wherein N is an integer greater than or equal to 2.

22. The circuit of claim 21, wherein, The doping unit is configured to: divide the identification information into N groups according to the position of the identification information in the first request message; dope N groups of identification information with N groups of addresses to be processed according to a preset arrangement mode, to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates the relative position relationship between the addresses to be processed and the identification information in each group of virtual addresses, and the relative position relationship corresponding to the N groups of virtual addresses is at least partially different.

23. The circuit of claim 21, wherein, The sequence adjustment unit is configured to: obtain a second pseudo-random number; use the second pseudo-random number as a control sequence, and adjust the grouping order of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping order.

24. The circuit of claim 22, wherein, The doping unit is further configured to fill a default value to the N groups of virtual addresses when the lengths of the N groups of addresses to be processed are different, so that the lengths of the N groups of virtual addresses are the same.

25. The circuit of claim 17, wherein, The exchange unit comprises: a linear feedback shift register configured to generate the first pseudo-random number; N switch arrays, each switch array comprising a plurality of multi-control switches, wherein each switch array is configured to control the on or off of the plurality of multi-control switches according to the switch mode corresponding to the first pseudo-random number, so that a group of addresses to be processed input into one switch array are exchanged in position during transmission in the one switch array.

26. The circuit of claim 25, wherein, The linear feedback shift register is configured to: generate a pseudo-random number in response to receiving a clock signal, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and not generate the pseudo-random number in response to stopping receiving the clock signal; take the pseudo-random number corresponding to the last clock cycle in the received clock signal as the first pseudo-random number.

27. The circuit of claim 26, wherein, The exchange unit further comprises: a clock gate connected with the linear feedback shift register and configured to control the input of the clock signal of the linear feedback shift register.

28. A circuit for descrambling an address, comprising: The receiving module is configured to receive a third request message from a link layer, wherein the third request message is a transaction layer packet and contains a scrambled address; The address descrambling module, connected with the receiving module, is configured to perform an address descrambling operation on a to-be-processed address to obtain a data address, the data address having a length less than or equal to that of the scrambled address, the to-be-processed address being the scrambled address or an intermediate address during the address descrambling operation; The sending module, connected with the address descrambling module, is configured to send a fourth request message containing the data address to a processing unit, the fourth request message corresponding to the third request message, wherein the address descrambling module comprises: The de-doping unit is configured to perform a de-doping operation on the to-be-processed address according to identification information in the third request message; The reverse exchange unit is configured to perform a pseudo-random reverse exchange operation on the to-be-processed address according to a pseudo-random number characteristic and a preset length; and The reverse order adjustment unit is configured to perform a pseudo-random reverse order adjustment operation on a grouping order of the to-be-processed address according to the pseudo-random number characteristic. The address descrambling operation comprises at least one of the de-doping operation, the reverse exchange operation and the reverse order adjustment operation. The reverse exchange unit is configured to: obtain a first pseudo-random number; invert the first pseudo-random number, and control switching modes of N switch arrays using the inverted result of the first pseudo-random number, so that the N switch arrays perform position reverse exchange within N groups of to-be-processed addresses according to the preset length, wherein the to-be-processed addresses are pre-divided into the N groups of to-be-processed addresses, and N is an integer greater than or equal to 2.

29. The circuit of claim 28, wherein, The circuit further comprises: The detection module, connected with the receiving module and the address descrambling module, is configured to determine whether address descrambling is enabled and which units in the address descrambling module are enabled according to configuration information in the third request message, and enable at least one unit in the address descrambling module when it is determined that address descrambling is enabled.

30. The circuit of claim 29, wherein, The detection module is further configured to disable the address descrambling module when it is determined that address descrambling is disabled.

31. The circuit of claim 28, wherein, When at least two of the de-doping unit, the reverse exchange unit and the reverse order adjustment unit are enabled, the address descrambling module is configured to perform the address descrambling operation on the scrambled address in the order of the reverse order adjustment unit, the reverse exchange unit and the de-doping unit.

32. The circuit of claim 28, wherein, The address descrambling module further comprises: The grouping unit, connected with the receiving module, the de-doping unit, the reverse exchange unit and the reverse order adjustment unit, is configured to divide the scrambled address into N groups according to a position of the scrambled address in the third request message, wherein N is an integer greater than or equal to 2.

33. The circuit of claim 32, wherein, The de-doping unit is configured to: remove N groups of identification information from N groups of to-be-processed addresses according to a preset arrangement mode to obtain N groups of data addresses; The preset arrangement mode indicates a relative position relationship between a data address and identification information in each group of to-be-processed addresses, and the relative position relationships corresponding to the N groups of to-be-processed addresses are at least partially different.

34. The circuit of any one of claims 32-33, wherein, The reverse order adjustment unit is configured to: obtain a second pseudo-random number; use the second pseudo-random number as a control sequence, and reversely adjust a grouping order of the N groups of to-be-processed addresses according to a preset adjustment rule of the control sequence and the grouping order.

35. The circuit of claim 33, wherein, The de-doping unit is further configured to: remove a default value from the N groups of to-be-processed addresses to obtain N groups of data addresses when the N groups of to-be-processed addresses include the default value.

36. The circuit of claim 28, wherein, The reverse exchange unit includes: a linear feedback shift register configured to: generate a pseudo-random number in response to receiving a clock signal, wherein each clock cycle in the clock signal corresponds to one pseudo-random number, and stop generating the pseudo-random number in response to stopping receiving the clock signal; use a pseudo-random number corresponding to a last clock cycle in the received clock signal as the first pseudo-random number.

37. The circuit of claim 36, wherein, The reverse exchange unit further includes: a clock gate connected with the linear feedback shift register and configured to control input of a clock signal of the linear feedback shift register.

38. A chip comprising the circuit for scrambling addresses according to any one of claims 17-27 and / or the circuit for descrambling addresses according to any one of claims 28-37.

39. An electronic device comprising the chip according to claim 38.

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