Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises a display area (AA), the display area (AA) comprising a light-transmitting display region (A1); the display substrate comprises a plurality of light-emitting elements and a plurality of pixel circuits, the plurality of light-emitting elements comprising a plurality of first-type light-emitting elements (L1) located in the light-transmitting display region (A1), the plurality of pixel circuits comprising a plurality of first-type pixel circuits (P1) located in the light-transmitting display region (A1), at least one first-type pixel circuit (P1) in the plurality of first-type pixel circuits (P1) is electrically connected with at least two first-type light-emitting elements (L1) emitting light of the same color, the first-type pixel circuit (P1) is configured to drive the at least two first-type light-emitting elements (L1) to emit light; a normal projection of the at least one first-type pixel circuit (P1) on a substrate and a normal projection of the at least one first-type light-emitting element (L1) on the substrate overlap.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Under-display camera technology is a novel technology proposed to improve the screen-to-body ratio of display devices. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure provides a display substrate, comprising: a display area and a peripheral area at least partially surrounding the display area, the display area including a light-transmitting display area and a conventional display area located on at least one side of the light-transmitting display area, wherein the light transmittance of the light-transmitting display area is greater than the light transmittance of the conventional display area;

[0005] The display substrate includes: a substrate and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the substrate. The plurality of light-emitting elements includes a plurality of first-type light-emitting elements located in the light-transmitting display area. The plurality of pixel circuits includes a plurality of first-type pixel circuits located in the light-transmitting display area. At least one of the plurality of first-type pixel circuits is electrically connected to at least two first-type light-emitting elements that emit light of the same color. The first-type pixel circuit is configured to drive the at least two first-type light-emitting elements to emit light.

[0006] The orthographic projection of the at least one first-type pixel circuit on the substrate overlaps with the orthographic projection of the at least one first-type light-emitting element on the substrate.

[0007] In an exemplary embodiment, the orthographic projection of the at least one first-type pixel circuit onto the substrate and the orthographic projection of at least a portion of the first-type light-emitting elements electrically connected to the at least one first-type pixel circuit onto the substrate overlap.

[0008] In an exemplary embodiment, it further includes: a plurality of first signal lines, wherein the at least one first type pixel circuit is electrically connected to at least one first signal line;

[0009] The plurality of first signal lines include at least one of the following: scan signal line, reset signal line, initial signal line, and light emission signal line.

[0010] In an exemplary embodiment, the plurality of first signal lines include a plurality of sub-signal lines; adjacent sub-signal lines of the first signal lines are electrically connected through an electrically connected first type of pixel circuit.

[0011] In an exemplary embodiment, it further includes: a plurality of second signal lines, wherein the at least one first type pixel circuit is electrically connected to at least one second signal line;

[0012] The plurality of second signal lines include at least one of the following: a data signal line and a first power line, wherein the plurality of data signal lines and the plurality of first power lines extend along a first direction; the data signal lines and the first power lines electrically connected to the first type of pixel circuit are located between adjacent sub-signal lines of the first signal lines, and the orthographic projections of the data signal lines and the first power lines electrically connected to the first type of pixel circuit on the substrate overlap with the orthographic projections of the first type of pixel circuit on the substrate.

[0013] In an exemplary embodiment, the orthographic projection of at least one of the scan signal line, the reset signal line, the initial signal line, the light emission signal line, the data signal line, and the first power line onto the substrate overlaps with the orthographic projection portion of the first type of light emission element onto the substrate.

[0014] In an exemplary embodiment, the plurality of first-type light-emitting elements include at least: a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light;

[0015] The anode area of ​​at least one of the plurality of first light-emitting elements is greater than the anode area of ​​at least one of the plurality of third light-emitting elements; the anode area of ​​at least one of the plurality of second light-emitting elements is greater than the anode area of ​​at least one of the plurality of third light-emitting elements; and the anode area of ​​at least one of the plurality of second light-emitting elements is greater than the anode area of ​​at least one of the plurality of first light-emitting elements.

[0016] The first color light is red light, the second color light is blue light, and the third color light is green light.

[0017] In an exemplary embodiment, the first type of pixel circuit includes: a plurality of transistors and at least one capacitor; in a direction perpendicular to the display substrate, the light-transmitting display area includes at least: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer disposed on the substrate.

[0018] The semiconductor layer includes at least: an active layer of a plurality of transistors of the first type of pixel circuit;

[0019] The first conductive layer includes at least: the control electrodes of a plurality of transistors of the first type of pixel circuit and the first plate of a capacitor;

[0020] The second conductive layer includes at least: the second plate of the capacitor of the first type of pixel circuit;

[0021] The third conductive layer includes at least: the first and second electrodes of a plurality of transistors of the first type of pixel circuit and a plurality of connection electrodes;

[0022] The transparent conductive layer includes at least: multiple first signal lines, multiple second signal lines, and multiple anode connection lines. At least one of the multiple anode connection lines is electrically connected to the anode of at least one first-type pixel circuit and at least two first-type light-emitting elements emitting light of the same color. The at least one first-type pixel circuit is electrically connected to at least one first signal line and at least one second signal line.

[0023] The fourth conductive layer includes at least a plurality of signal connection lines.

[0024] In an exemplary embodiment, the plurality of first-type light-emitting elements are arranged as follows:

[0025] The plurality of third light-emitting elements are arranged at certain intervals in the i-th row, the second light-emitting elements and the first light-emitting elements are alternately arranged in adjacent rows of the i-th row, the first light-emitting elements and the second light-emitting elements are alternately arranged in the j-th column, the plurality of third light-emitting elements are arranged at certain intervals in adjacent columns of the j-th column, the first light-emitting elements and the third light-emitting elements are alternately arranged along a third direction, the second light-emitting elements and the third light-emitting elements are alternately arranged along a fourth direction, the third direction and the fourth direction intersect the first direction and the second direction respectively, the first direction is the column direction and the second direction is the row direction.

[0026] In an exemplary embodiment, the plurality of first-type pixel circuits include: at least one first pixel circuit, at least one second pixel circuit, at least one third pixel circuit, and at least one fourth pixel circuit; the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements, the third pixel circuit is electrically connected to two third light-emitting elements, and the fourth pixel circuit is electrically connected to two third light-emitting elements, wherein the third light-emitting elements electrically connected to the third pixel circuit and the fourth pixel circuit are different.

[0027] In an exemplary embodiment, the two first light-emitting elements electrically connected to the first pixel circuit are located in the same row, the two second light-emitting elements electrically connected to the second pixel circuit are located in the same row, the two third light-emitting elements electrically connected to the third pixel circuit are located in the same row, and the two third light-emitting elements electrically connected to the fourth pixel circuit are located in the same row.

[0028] In an exemplary embodiment, the orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected first light-emitting element on the substrate.

[0029] The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection of the first light-emitting element on the substrate, which is located between the two electrically connected second light-emitting elements;

[0030] The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of the second light-emitting element on the substrate. The second light-emitting element overlapping with the third pixel circuit is located in the adjacent row of the two rows of the third light-emitting elements electrically connected by the third pixel circuit, and is located in the middle column of the two columns of the third light-emitting elements electrically connected by the third pixel circuit.

[0031] The orthographic projection of the fourth pixel circuit on the substrate overlaps with the orthographic projection of the second light-emitting element on the substrate. The second light-emitting element overlapping with the fourth pixel circuit is located in the adjacent row of the row containing the two third light-emitting elements electrically connected to the fourth pixel circuit, and is located in the middle column of the column containing the two third light-emitting elements electrically connected to the fourth pixel circuit. The second light-emitting element overlapping with the third pixel circuit and the second light-emitting element overlapping with the fourth pixel circuit are different light-emitting elements.

[0032] In an exemplary embodiment, the first signal line extends along a second direction;

[0033] The anode connection line includes: a first anode connection line, a second anode connection line, a third anode connection line, and a fourth anode connection line;

[0034] The first anode connection line is electrically connected to the first pixel circuit and the first light-emitting element, and at least a portion of the first anode connection line extends along the second direction; the second anode connection line is electrically connected to the second pixel circuit and the second light-emitting element, and at least a portion of the second anode connection line extends along the second direction; the third anode connection line is electrically connected to the third pixel circuit and the third light-emitting element, and at least a portion of the third anode connection line extends along the second direction, and the third anode connection line is located between the data signal line and the first power line electrically connected to the third pixel circuit; the fourth anode connection line is electrically connected to the fourth pixel circuit and the third light-emitting element, and at least a portion of the fourth anode connection line extends along the second direction, and the fourth anode connection line is located between the data signal line and the first power line electrically connected to the fourth pixel circuit.

[0035] In an exemplary embodiment, first power lines electrically connected to at least two adjacent first-type pixel circuits in the same column are spaced apart, and the spaced first power lines in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.

[0036] At least two adjacent first-type pixel circuits in the same column are electrically connected by data signal lines spaced apart, and the spaced data signal lines in the same column are electrically connected by at least one signal connection line located in the fourth conductive layer.

[0037] In an exemplary embodiment, the two first light-emitting elements electrically connected to the first pixel circuit are arranged along a third direction, the two second light-emitting elements electrically connected to the second pixel circuit are arranged along a fourth direction, the two third light-emitting elements electrically connected to the third pixel circuit are located in the same column, and the two third light-emitting elements electrically connected to the fourth pixel circuit are located in the same column.

[0038] The orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected first light-emitting element on the substrate;

[0039] The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected second light-emitting element on the substrate;

[0040] The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected third light-emitting element on the substrate.

[0041] The orthographic projection of the fourth pixel circuit on the substrate overlaps with the orthographic projection of a third light-emitting element electrically connected to the substrate. The third light-emitting element overlapping with the third pixel circuit and the third light-emitting element overlapping with the fourth pixel circuit are different light-emitting elements.

[0042] In an exemplary embodiment, the anode connection line includes: a first anode connection line, a second anode connection line, a third anode connection line, and a fourth anode connection line;

[0043] The first anode connection line is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connection line extends along the first direction; the second anode connection line is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connection line extends along the first direction; the third anode connection line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connection line extends along the first direction, and the third anode connection line is located on the side of the first power line electrically connected to the third pixel circuit away from the data signal line; the fourth anode connection line is electrically connected to the fourth pixel circuit and the third light-emitting element, respectively, and at least a portion of the fourth anode connection line extends along the first direction, and the fourth anode connection line is located on the side of the first power line electrically connected to the fourth pixel circuit away from the data signal line.

[0044] In an exemplary embodiment, the data signal lines electrically connected to the first type of pixel circuits in the same column are the same signal lines, the first power lines electrically connected to at least two adjacent first type of pixel circuits in the same column are spaced apart, and the spaced first power lines in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.

[0045] In an exemplary embodiment, the transparent conductive layer further includes: a power connection line, at least a portion of which extends along a second direction;

[0046] The power connection line is electrically connected to the first power line that is electrically connected to two adjacent first type pixel circuits located in the same row. The first power line and the power connection line are electrically connected through the connection electrode located in the third conductive layer.

[0047] In an exemplary embodiment, for the same first type of pixel circuit, the first power line includes: a power body portion extending along the first direction and a power connection portion extending along the second direction, wherein the power connection portion is located on the side of the power body portion away from the data signal line.

[0048] The power connection line is electrically connected to the power connection part of one of the first type pixel circuits and the power body part of the other first type pixel circuit in the same row.

[0049] In an exemplary embodiment, the plurality of first-type light-emitting elements are arranged as follows:

[0050] The plurality of second light-emitting elements are arranged in the j-th column, the first light-emitting element and the third light-emitting element are alternately arranged in adjacent columns of the j-th column, the plurality of second light-emitting elements are arranged in the i-th row, and the first light-emitting element and the third light-emitting element are arranged between adjacent second light-emitting elements in the same row.

[0051] In an exemplary embodiment, the plurality of first-type pixel circuits include: at least one first pixel circuit, at least one second pixel circuit, and at least one third pixel circuit; the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements, and the third pixel circuit is electrically connected to two third light-emitting elements.

[0052] In an exemplary embodiment, the two first light-emitting elements electrically connected to the first pixel circuit are located in the same row, the two second light-emitting elements electrically connected to the second pixel circuit are located in the same row, and the two third light-emitting elements electrically connected to the third pixel circuit are located in the same row.

[0053] In an exemplary embodiment, the orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected first light-emitting element on the substrate.

[0054] The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected second light-emitting element on the substrate;

[0055] The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of an electrically connected third light-emitting element on the substrate.

[0056] In an exemplary embodiment, at least two of the first light-emitting elements overlapping with the first pixel circuit, the second light-emitting elements overlapping with the second pixel circuit, and the third light-emitting elements overlapping with the third pixel circuit are adjacent to each other.

[0057] In an exemplary embodiment, the orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected first light-emitting element on the substrate.

[0058] The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected second light-emitting element on the substrate;

[0059] The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of the second light-emitting element on the substrate located between the two third light-emitting elements electrically connected to the third pixel circuit.

[0060] In an exemplary embodiment, the orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of the second light-emitting element located between the two first light-emitting elements electrically connected to the first pixel circuit on the substrate.

[0061] The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected second light-emitting element on the substrate;

[0062] The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of an electrically connected third light-emitting element on the substrate.

[0063] In an exemplary embodiment, the anode connection line includes: a first anode connection line, a second anode connection line, and a third anode connection line;

[0064] The first anode connection line is electrically connected to the first pixel circuit and the first light-emitting element, and at least a portion of the first anode connection line extends along the second direction; the second anode connection line is electrically connected to the second pixel circuit and the second light-emitting element, and at least a portion of the second anode connection line extends along the second direction; the third anode connection line is electrically connected to the third pixel circuit and the third light-emitting element, and at least a portion of the third anode connection line extends along the second direction.

[0065] In an exemplary embodiment, the data signal lines electrically connected to the first type of pixel circuits in the same column are the same signal lines, the first power lines electrically connected to at least two adjacent first type of pixel circuits in the same column are spaced apart, and the spaced first power lines in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.

[0066] In an exemplary embodiment, the plurality of light-emitting elements further includes a plurality of second-type light-emitting elements located in the conventional display area, and the plurality of pixel circuits further includes a plurality of second-type pixel circuits located in the conventional display area;

[0067] At least one of the plurality of second-type light-emitting elements and at least one of the plurality of second-type pixel circuits are electrically connected, and the orthographic projection of the second-type light-emitting element on the substrate and the orthographic projection of the electrically connected second-type pixel circuit on the substrate overlap.

[0068] Secondly, this disclosure also provides a display device including the aforementioned display substrate.

[0069] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0070] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0071] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0072] Figure 2 This is a schematic diagram of the arrangement of first type of light-emitting elements in the light-transmitting display area according to at least one embodiment of the present disclosure. Figure 1 ;

[0073] Figure 3 This is a schematic diagram of the arrangement of first type of light-emitting elements in the light-transmitting display area according to at least one embodiment of the present disclosure. Figure 2 ;

[0074] Figure 4 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 1 ;

[0075] Figure 5 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 2 ;

[0076] Figure 6 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 3 ;

[0077] Figure 7 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 4 ;

[0078] Figure 8 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 5 ;

[0079] Figure 9 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 6 ;

[0080] Figure 10 This is an equivalent circuit diagram of a first type of pixel circuit;

[0081] Figure 11 for Figure 10 The provided timing diagram for the first type of pixel circuit;

[0082] Figure 12 A partial top view of a light-transmitting display area provided in an exemplary embodiment Figure 1 ;

[0083] Figure 13 A partial top view of a light-transmitting display area provided in an exemplary embodiment Figure 2 ;

[0084] Figure 14 A partial top view of a light-transmitting display area provided in an exemplary embodiment Figure 3 ;

[0085] Figure 15A for Figure 12 A schematic diagram showing the semiconductor pattern formed in the provided light-transmitting display area;

[0086] Figure 15B for Figure 12 A schematic diagram of the pattern of the first conductive layer in the light-transmitting display area;

[0087] Figure 15C for Figure 12 A schematic diagram showing the light-transmitting display area after the first conductive layer pattern has been formed;

[0088] Figure 15D for Figure 12 A schematic diagram of the pattern of the second conductive layer in the light-transmitting display area;

[0089] Figure 15E for Figure 12 A schematic diagram showing the formation of the second conductive layer pattern in the provided light-transmitting display area;

[0090] Figure 15F for Figure 12 A schematic diagram showing the formation of the third insulating layer pattern in the provided light-transmitting display area;

[0091] Figure 15Gfor Figure 12 A schematic diagram of the pattern of the third conductive layer in the light-transmitting display area;

[0092] Figure 15H for Figure 12 A schematic diagram showing the formation of the third conductive layer pattern in the provided light-transmitting display area;

[0093] Figure 15I for Figure 12 A schematic diagram showing the formation of the fourth insulating layer pattern in the provided light-transmitting display area;

[0094] Figure 15J for Figure 12 A schematic diagram of the transparent conductive layer pattern in the light-transmitting display area;

[0095] Figure 15K for Figure 12 A schematic diagram showing the transparent conductive layer pattern formed in the provided light-transmitting display area;

[0096] Figure 15L for Figure 12 A schematic diagram showing the light-transmitting display area after the first planarization layer has been formed;

[0097] Figure 15M for Figure 12 A schematic diagram of the fourth conductive layer pattern in the light-transmitting display area;

[0098] Figure 15N for Figure 12 A schematic diagram showing the formation of the fourth conductive layer pattern in the provided light-transmitting display area;

[0099] Figure 15O for Figure 12 A schematic diagram showing the second planarization layer pattern formed in the provided light-transmitting display area;

[0100] Figure 15P for Figure 12 A schematic diagram of the anode conductive layer pattern in the light-transmitting display area;

[0101] Figure 15Q for Figure 12 A schematic diagram showing the formation of the anodic conductive layer pattern in the provided light-transmitting display area;

[0102] Figure 16A for Figure 13 A schematic diagram showing the semiconductor pattern formed in the provided light-transmitting display area;

[0103] Figure 16B for Figure 13 A schematic diagram of the pattern of the first conductive layer in the light-transmitting display area;

[0104] Figure 16C for Figure 13A schematic diagram showing the light-transmitting display area after the first conductive layer pattern has been formed;

[0105] Figure 16D for Figure 13 A schematic diagram of the pattern of the second conductive layer in the light-transmitting display area;

[0106] Figure 16E for Figure 13 A schematic diagram showing the formation of the second conductive layer pattern in the provided light-transmitting display area;

[0107] Figure 16F for Figure 13 A schematic diagram showing the formation of the third insulating layer pattern in the provided light-transmitting display area;

[0108] Figure 16G for Figure 13 A schematic diagram of the pattern of the third conductive layer in the light-transmitting display area;

[0109] Figure 16H for Figure 13 A schematic diagram showing the formation of the third conductive layer pattern in the provided light-transmitting display area;

[0110] Figure 16I for Figure 13 A schematic diagram showing the formation of the fourth insulating layer pattern in the provided light-transmitting display area;

[0111] Figure 16J for Figure 13 A schematic diagram of the transparent conductive layer pattern in the light-transmitting display area;

[0112] Figure 16K for Figure 13 A schematic diagram showing the transparent conductive layer pattern formed in the provided light-transmitting display area;

[0113] Figure 16L for Figure 13 A schematic diagram showing the light-transmitting display area after the first planarization layer has been formed;

[0114] Figure 16M for Figure 13 A schematic diagram of the fourth conductive layer pattern in the light-transmitting display area;

[0115] Figure 16N for Figure 13 A schematic diagram showing the formation of the fourth conductive layer pattern in the provided light-transmitting display area;

[0116] Figure 16O for Figure 13 A schematic diagram showing the second planarization layer pattern formed in the provided light-transmitting display area;

[0117] Figure 16P for Figure 13 A schematic diagram of the anode conductive layer pattern in the light-transmitting display area;

[0118] Figure 16Q for Figure 13 A schematic diagram showing the formation of the anodic conductive layer pattern in the provided light-transmitting display area;

[0119] Figure 17A for Figure 14 A schematic diagram showing the semiconductor pattern formed in the provided light-transmitting display area;

[0120] Figure 17B for Figure 14 A schematic diagram of the pattern of the first conductive layer in the light-transmitting display area;

[0121] Figure 17C for Figure 14 A schematic diagram showing the light-transmitting display area after the first conductive layer pattern has been formed;

[0122] Figure 17D for Figure 14 A schematic diagram of the pattern of the second conductive layer in the light-transmitting display area;

[0123] Figure 17E for Figure 14 A schematic diagram showing the formation of the second conductive layer pattern in the provided light-transmitting display area;

[0124] Figure 17F for Figure 14 A schematic diagram showing the formation of the third insulating layer pattern in the provided light-transmitting display area;

[0125] Figure 17G for Figure 14 A schematic diagram of the pattern of the third conductive layer in the light-transmitting display area;

[0126] Figure 17H for Figure 14 A schematic diagram showing the formation of the third conductive layer pattern in the provided light-transmitting display area;

[0127] Figure 17I for Figure 14 A schematic diagram showing the formation of the fourth insulating layer pattern in the provided light-transmitting display area;

[0128] Figure 17J for Figure 14 A schematic diagram of the transparent conductive layer pattern in the light-transmitting display area;

[0129] Figure 17K for Figure 14 A schematic diagram showing the transparent conductive layer pattern formed in the provided light-transmitting display area;

[0130] Figure 17L for Figure 14 A schematic diagram showing the light-transmitting display area after the first planarization layer has been formed;

[0131] Figure 17M for Figure 14 A schematic diagram of the fourth conductive layer pattern in the light-transmitting display area;

[0132] Figure 17N for Figure 14 A schematic diagram showing the formation of the fourth conductive layer pattern in the provided light-transmitting display area;

[0133] Figure 17O for Figure 14 A schematic diagram showing the second planarization layer pattern formed in the provided light-transmitting display area;

[0134] Figure 17P for Figure 14 A schematic diagram of the anode conductive layer pattern in the light-transmitting display area;

[0135] Figure 17Q for Figure 14 A schematic diagram showing the formation of the anodic conductive layer pattern in the provided light-transmitting display area;

[0136] Figure 18 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0137] Figure 19 for Figure 18 Cross-sectional view along direction AA. Detailed Implementation

[0138] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0139] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0140] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0141] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0142] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0143] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0144] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0145] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0146] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0147] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0148] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0149] At least one embodiment of this disclosure provides a display substrate, including: a display area and a peripheral area at least partially surrounding the display area. The display area includes a light-transmitting display area and a conventional display area located on at least one side of the light-transmitting display area. The light transmittance of the light-transmitting display area is greater than that of the conventional display area. The display substrate includes: a substrate and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the substrate. The plurality of light-emitting elements includes a plurality of first-type light-emitting elements located in the light-transmitting display area. The plurality of pixel circuits includes a plurality of first-type pixel circuits located in the light-transmitting display area. At least one of the plurality of first-type pixel circuits is electrically connected to at least two first-type light-emitting elements that emit light of the same color. The first-type pixel circuit is configured to drive at least two first-type light-emitting elements to emit light. The orthographic projection of at least one first-type pixel circuit on the substrate overlaps with the orthographic projection of at least one first-type light-emitting element on the substrate.

[0150] The display substrate provided in this embodiment reduces the number of first-type pixel circuits in the light-transmitting display area, using one first-type pixel circuit to drive at least two first-type light-emitting elements emitting light of the same color. This ensures consistent resolution (PPI) across the display area, improves light transmittance in the light-transmitting display area, and reduces diffraction in the light-transmitting display area during photography. The display substrate provided in this embodiment can be applied to QHD (Quarter High Definition) display devices. However, this embodiment is not limited thereto.

[0151] In an exemplary embodiment, there is an overlap between the orthographic projection of at least one first-type pixel circuit onto the substrate and the orthographic projection of at least a portion of the first-type light-emitting elements electrically connected to at least one first-type pixel circuit onto the substrate.

[0152] In an exemplary embodiment, the display substrate may further include: a plurality of first signal lines, wherein at least one first type pixel circuit is electrically connected to at least one of the first signal lines. The plurality of first signal lines include at least one of the following: a scan signal line, a reset signal line, an initial signal line, and a light-emitting signal line.

[0153] In an exemplary embodiment, the plurality of first signal lines include a plurality of sub-signal lines; adjacent sub-signal lines of the first signal lines are electrically connected through electrically connected first type pixel circuits.

[0154] In an exemplary embodiment, the display substrate may further include: a plurality of second signal lines, at least one first type pixel circuit being electrically connected to at least one of the second signal lines; the plurality of second signal lines include at least one of the following: a data signal line and a first power line, the plurality of data signal lines and the plurality of first power lines extending along a first direction.

[0155] In an exemplary embodiment, the data signal line and the first power line electrically connected to the first type of pixel circuit are located between adjacent sub-signal lines of the first signal line, and the orthographic projection of the data signal line and the first power line electrically connected to the first type of pixel circuit on the substrate overlaps with the orthographic projection of the first type of pixel circuit on the substrate.

[0156] In an exemplary embodiment, the orthographic projection of at least one of the scan signal line, reset signal line, initial signal line, light emission signal line, data signal line, and first power line onto the substrate overlaps with the orthographic projection portion of the first type of light emission element onto the substrate.

[0157] In an exemplary embodiment, the plurality of first-type light-emitting elements includes at least: a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light. The anode area of ​​at least one of the plurality of first light-emitting elements is larger than the anode area of ​​at least one of the plurality of third light-emitting elements, and the anode area of ​​at least one of the plurality of second light-emitting elements is larger than the anode area of ​​at least one of the third light-emitting elements. In some examples, the first color light can be red light, the second color light can be blue light, and the third color light can be green light.

[0158] The following examples illustrate the solution of this embodiment.

[0159] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In an exemplary embodiment, such as Figure 1As shown, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display substrate may include a light-transmitting display area A1 and a conventional display area A2 located on at least one side of the light-transmitting display area A1. In some examples, the light-transmitting display area A1 is the aforementioned light-transmitting display area, and may also be referred to as the under-display camera (UDC) area. The conventional display area A2 may also be referred to as the normal display area. For example, the orthographic projection of hardware such as a photosensor (e.g., a camera, infrared sensor) onto the display substrate may be located within the light-transmitting display area A1 of the display substrate. In some examples, such as... Figure 1 As shown, the light-transmitting display area A1 can be circular, and the size of the orthographic projection of the photosensor onto the display substrate can be smaller than or equal to the size of the light-transmitting display area A1. However, this embodiment is not limited in this respect.

[0160] In other examples, the light-transmitting display area can be rectangular, and the size of the orthographic projection of the photosensitive sensor onto the display substrate can be smaller than or equal to the size of the inscribed circle of the light-transmitting display area.

[0161] In an exemplary implementation, such as Figure 1 As shown, the light-transmitting display area A1 can be located at the top center of the display area AA. The conventional display area A2 can surround the light-transmitting display area A1. However, this embodiment is not limited to this. For example, the light-transmitting display area A1 can be located at other positions such as the upper left or upper right corner of the display area AA.

[0162] In an exemplary implementation, such as Figure 1 As shown, the display area AA can be rectangular, such as a rounded rectangle. The light-transmitting display area A1 can be circular or elliptical. However, this embodiment is not limited to this. For example, the light-transmitting display area can be other shapes such as rectangle, pentagon, or hexagon.

[0163] In an exemplary embodiment, the display area AA includes at least a plurality of regularly arranged pixel units, a plurality of gate lines extending along a first direction Y (e.g., scan signal lines, reset signal lines, and light emission signal lines), a plurality of data signal lines extending along a second direction X, and a first power line. The first direction Y and the second direction X are located in the same plane, and the first direction Y intersects the second direction X; for example, the first direction Y is perpendicular to the second direction X.

[0164] In an exemplary embodiment, a pixel unit of the display area AA may include three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

[0165] In an exemplary embodiment, the shape of a sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0166] In an exemplary embodiment, at least one sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the electrically connected light-emitting element. For example, the pixel circuit is configured to provide a drive current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor; for example, the pixel circuit may be a 3T1C (3 transistors and 1 capacitor) structure, an 8T1C (8 transistors and 1 capacitor) structure, a 7T1C (7 transistors and 1 capacitor) structure, or a 5T1C (5 transistors and 1 capacitor) structure. In some examples, the light-emitting element may be an organic light-emitting diode (OLED), which emits red, green, blue, or white light under the drive of its corresponding pixel circuit. The emission color of the light-emitting element can be determined as needed. The light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0167] In an exemplary implementation, such as Figure 1 As shown, the display substrate includes a substrate and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the substrate. The plurality of light-emitting elements may include a plurality of first-type light-emitting elements L1 located in the light-transmitting display area A1 and a plurality of second-type light-emitting elements L2 located in the conventional display area A2. The plurality of pixel circuits may include a plurality of first-type pixel circuits P1 located in the light-transmitting display area A1 and a plurality of second-type pixel circuits P2 located in the conventional display area A2.

[0168] In an exemplary embodiment, the light-transmitting display area A1 is provided with a plurality of first-type light-emitting elements and a plurality of first-type pixel circuits. At least one first-type pixel circuit is electrically connected to at least two first-type light-emitting elements that emit light of the same color. That is, at least two sub-pixels of the same color in the light-transmitting display area A1 share one first-type pixel circuit. The conventional display area A2 is provided with a plurality of second-type light-emitting elements and a plurality of second-type pixel circuits. The plurality of second-type light-emitting elements and the plurality of second-type pixel circuits are electrically connected in a one-to-one correspondence. The display substrate of this exemplary embodiment adopts a design in which one first-type pixel circuit drives at least two first-type light-emitting elements in the light-transmitting display area A1, which can improve the light transmittance of the light-transmitting display area and reduce diffraction during photography while ensuring the consistent resolution of the display area of ​​the display substrate. However, this embodiment is not limited in this respect.

[0169] Figure 2 This is a schematic diagram of the arrangement of first type of light-emitting elements in the light-transmitting display area according to at least one embodiment of the present disclosure. Figure 1 , Figure 3 This is a schematic diagram of the arrangement of first type of light-emitting elements in the light-transmitting display area according to at least one embodiment of the present disclosure. Figure 2 In an exemplary implementation, such as Figure 2 and Figure 3 As shown, the plurality of first-type light-emitting elements in the light-transmitting display area A1 may include: a plurality of first light-emitting elements 11 emitting a first color light, a plurality of second light-emitting elements 12 emitting a second color light, and a plurality of third light-emitting elements 13 emitting a third color light. For example, the first color light may be red light, the second color light may be blue light, and the third color light may be green light. That is, the first light-emitting element 11 may be a red light-emitting element, the second light-emitting element 12 may be a blue light-emitting element, and the third light-emitting element 13 may be a green light-emitting element. However, this embodiment is not limited in this respect.

[0170] In an exemplary implementation, such as Figure 2As shown, multiple first-type light-emitting elements in the light-transmitting display area A1 can be arranged according to a Pentile structure. Specifically, multiple third light-emitting elements 13 are arranged at certain intervals in the i-th row; second light-emitting elements 12 and first light-emitting elements 11 are alternately arranged in adjacent rows of the i-th row; first light-emitting elements 11 and second light-emitting elements 12 are alternately arranged in the j-th column; multiple third light-emitting elements 13 are arranged at certain intervals in adjacent columns of the j-th column; first light-emitting elements 11 and third light-emitting elements 13 are alternately arranged along a third direction F1; second light-emitting elements 12 and third light-emitting elements 13 are alternately arranged along a fourth direction F2; third direction F1 and fourth direction F4 intersect with the first direction Y and the second direction X, respectively; the first direction Y is the column direction, and the second direction X is the row direction. For example, multiple third light-emitting elements 13 are arranged at certain intervals in the i-th row, and the second light-emitting elements 12 and the first light-emitting elements 11 are alternately arranged in adjacent rows of the i-th row. This means that multiple third light-emitting elements 13 are arranged at certain intervals in the i-th row, the second light-emitting elements 12 and the first light-emitting elements 11 are alternately arranged in the (i+1)-th row adjacent to the i-th row, multiple third light-emitting elements 13 are arranged at certain intervals in the (i+2)-th row adjacent to the (i+1)-th row, and the first light-emitting elements 11 and the second light-emitting elements 12 are alternately arranged in the (i+3)-th row adjacent to the (i+2)-th row. Multiple rows of the first type of light-emitting elements can be repeatedly arranged according to this pattern. For example, the first light-emitting element 11 and the second light-emitting element 12 are alternately arranged in the j-th column. The arrangement of multiple third light-emitting elements 13 at certain intervals in adjacent columns of the j-th column means that the first light-emitting element 11 and the second light-emitting element 12 are alternately arranged in the j-th column, the multiple third light-emitting elements 13 are arranged at certain intervals in the (j+1)-th adjacent column of the j-th column, the first light-emitting element 11 and the second light-emitting element 12 are alternately arranged in the (j+2)-th adjacent column of the (j+1)-th column, and the multiple third light-emitting elements 13 are arranged at certain intervals in the (j+3)-th column. Multiple columns of the first type of light-emitting elements can be repeatedly arranged according to this pattern. In this example, the dimensions of the first light-emitting element 11 and the second light-emitting element 12 can both be larger than the dimensions of the third light-emitting element 13. Here, i and j are both integers.

[0171] In an exemplary implementation, such as Figure 2 As shown, the light-emitting areas 110 of the first light-emitting element 11, 120 of the second light-emitting element 12, and 130 of the third light-emitting element 13 can all be circular or elliptical. The light-emitting area 110 of the first light-emitting element 11 can be larger than the light-emitting area 130 of the third light-emitting element 13, and the light-emitting area 120 of the second light-emitting element 12 can be larger than the light-emitting area 130 of the third light-emitting element 13. In this example, the light-emitting area of ​​the light-emitting element can be the portion of the pixel opening located in the pixel definition layer.

[0172] In an exemplary embodiment, the light-emitting area of ​​the first type of light-emitting element in the light-transmitting display area A1 can be smaller than the light-emitting area of ​​the second type of light-emitting element emitting the same color light in the conventional display area A2. For example, the area of ​​the light-emitting area of ​​the first type of light-emitting element can be 40% to 60% of the area of ​​the light-emitting area of ​​the second type of light-emitting element emitting the same color light, such as approximately 50%. In this example, by reducing the aperture ratio of the light-transmitting display area A1, the light transmission area of ​​the light-transmitting display area A1 can be increased, thereby improving the light transmittance of the light-transmitting display area A1.

[0173] In an exemplary implementation, such as Figure 3 As shown, the multiple first-type light-emitting elements in the light-transmitting display area A1 can be arranged in a triangular pattern. Multiple second-type light-emitting elements 12 are arranged in the j-th column, and first-type light-emitting elements 11 and third-type light-emitting elements 13 are alternately arranged in adjacent columns of the j-th column. Multiple second-type light-emitting elements 12 are arranged in the i-th row, with first-type light-emitting elements 11 and third-type light-emitting elements 13 positioned between adjacent second-type light-emitting elements 12 in the same row. For example, "multiple second-type light-emitting elements 12 arranged in the j-th column, and first-type light-emitting elements 11 and third-type light-emitting elements 13 alternately arranged in adjacent columns of the j-th column" means that multiple second-type light-emitting elements 12 are arranged at certain intervals in the j-th column, first-type light-emitting elements 11 and third-type light-emitting elements 13 are alternately arranged in the (j+1)-th column adjacent to the j-th column, multiple second-type light-emitting elements 12 are arranged at certain intervals in the (j+2)-th column adjacent to the (j+1)-th column, and first-type light-emitting elements 11 and second-type light-emitting elements 12 are alternately arranged in the (j+3)-th column adjacent to the (j+2)-th column. Multiple columns of first-type light-emitting elements can be repeatedly arranged according to this pattern.

[0174] Figure 4 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 1 , Figure 5 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 2 , Figure 6 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 3 , Figure 7 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 4 , Figure 8 A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 5 , Figure 9A schematic diagram of the arrangement of the first type of pixel circuit and the first type of light-emitting element in a light-transmitting display area provided for an exemplary embodiment. Figure 6 .exist Figures 4 to 9 The rectangle in the middle indicates the location of the first type of pixel circuit. Figure 4 and Figure 5 This will be illustrated by taking the arrangement of multiple Type I light-emitting elements in the light-transmitting display area A1 according to a Pentile structure as an example. Figures 6 to 9 The following explanation uses the example of multiple first-type light-emitting elements in the light-transmitting display area A1 being arranged in a triangular pattern. Figures 4 to 9 The examples used are all based on the connection of one type 1 pixel circuit to two type 1 light-emitting elements.

[0175] In an exemplary implementation, such as Figures 4 to 9 As shown, the area of ​​the anode 111 of the first light-emitting element (e.g., the first light-emitting elements 11a and 11b) is larger than the area of ​​the anode 131 of the third light-emitting element (e.g., the third light-emitting elements 13a and 13b), and the area of ​​the anode 121 of the second light-emitting element (e.g., the second light-emitting elements 12a and 12b) is larger than the area of ​​the anode 131 of the third light-emitting element (e.g., the third light-emitting elements 13a and 13b).

[0176] In an exemplary embodiment, the plurality of first-type pixel circuits include: at least one first pixel circuit, at least one second pixel circuit, at least one third pixel circuit, and at least one fourth pixel circuit; the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements, the third pixel circuit is electrically connected to two third light-emitting elements, and the fourth pixel circuit is electrically connected to two third light-emitting elements, wherein the third light-emitting elements electrically connected to the third pixel circuit and the fourth pixel circuit are different.

[0177] In an exemplary implementation, such as Figure 4As shown, the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, a third pixel circuit 15c, and a fourth pixel circuit 15d. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b emitting first-color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light. The orthographic projection of the first pixel circuit 15a onto the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11a onto the substrate, but does not overlap with the orthographic projection of the anode of the first light-emitting element 11b onto the substrate. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b emitting second-color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light. The orthographic projection of the second pixel circuit 15b onto the substrate does not overlap with the orthographic projection of the anodes of the second light-emitting elements 12a and 12b onto the substrate, but overlaps with the orthographic projection of the first light-emitting element 11b located between the second light-emitting elements 12a and 12b. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third-color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light. The orthographic projection of the third pixel circuit 15c onto the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a onto the substrate, but does not overlap with the orthographic projections of the anodes of the two third light-emitting elements 13a and 13b onto the substrate. The second light-emitting element 12a that overlaps with the third pixel circuit 15c is located in the row above the row containing the two third light-emitting elements 13a and 13b, and is located in the middle column of the column containing the two third light-emitting elements 13a and 13b. The fourth pixel circuit 15d is electrically connected to two third light-emitting elements 13c and 13d that emit third-color light, and is configured to drive the two third light-emitting elements 13c and 13d to emit light. The orthographic projection of the fourth pixel circuit 15d onto the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12b onto the substrate, but does not overlap with the orthographic projections of the anodes of the two third light-emitting elements 13c and 13d onto the substrate. The second light-emitting element 12b, which overlaps with the fourth pixel circuit 15d, is located in the row above the row containing the two third light-emitting elements 13c and 13d, and is located in the middle column of the column containing the third light-emitting elements 13c and 13d.

[0178] In some exemplary embodiments, such as Figure 4 As shown, the first type of pixel circuit is located below the anode of the first or second light-emitting element with a larger anode area, and does not overlap with the anode of the third light-emitting element with a smaller anode area. In this example, placing the first type of pixel circuit below the first type of light-emitting element with a larger anode area, and not placing the first type of pixel circuit below the first type of light-emitting element with a smaller anode area, can improve the light transmittance of the light-transmitting display area.

[0179] In an exemplary implementation, such as Figure 4 As shown, the two first light-emitting elements 11a and 11b electrically connected to the first pixel circuit 15a are in the second direction X (i.e., the two first light-emitting elements 11a and 11b are located in the same row). The two second light-emitting elements 12a and 12b electrically connected to the second pixel circuit 15b are in the second direction X (i.e., the two second light-emitting elements 12a and 12b are located in the same row). The two third light-emitting elements 13a and 13b electrically connected to the third pixel circuit 15c are in the second direction X (i.e., the two third light-emitting elements 13a and 13b are located in the same row). The two third light-emitting elements 13c and 13d electrically connected to the fourth pixel circuit 15d are in the second direction X (i.e., the two third light-emitting elements 13c and 13d are located in the same row).

[0180] In an exemplary implementation, such as Figure 5 As shown, the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, a third pixel circuit 15c, and a fourth pixel circuit 15d. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b emitting first-color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light. The orthographic projection of the first pixel circuit 15a onto the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11a onto the substrate, but does not overlap with the orthographic projection of the anode of the first light-emitting element 11b onto the substrate. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b emitting second-color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light. The orthographic projection of the second pixel circuit 15b onto the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a onto the substrate, but does not overlap with the orthographic projection of the anode of the second light-emitting element 12b onto the substrate. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third-color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light. The orthographic projection of the third pixel circuit 15c onto the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13a onto the substrate, but does not overlap with the orthographic projection of the anode of the third light-emitting element 13b onto the substrate. The fourth pixel circuit 15d is electrically connected to two third light-emitting elements 13c and 13d that emit third-color light, and is configured to drive the two third light-emitting elements 13c and 13d to emit light. The orthographic projection of the fourth pixel circuit 15d onto the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13c onto the substrate, but does not overlap with the orthographic projection of the anode of the third light-emitting element 13d onto the substrate.

[0181] In an exemplary implementation, such as Figure 5As shown, the two first light-emitting elements 11a and 11b electrically connected to the first pixel circuit 15a are on the third direction F1. The two second light-emitting elements 12a and 12b electrically connected to the second pixel circuit 15b are on the third direction F1. The two third light-emitting elements 13a and 13b electrically connected to the third pixel circuit 15c are on the first direction Y (i.e., the two third light-emitting elements 13a and 13b are located in the same column). The two third light-emitting elements 13c and 13d electrically connected to the fourth pixel circuit 15d are on the first direction Y (i.e., the two third light-emitting elements 13c and 13d are located in the same column).

[0182] In an exemplary embodiment, the plurality of first-type pixel circuits may include: at least one first pixel circuit, at least one second pixel circuit, and at least one third pixel circuit; the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements, and the third pixel circuit is electrically connected to two third light-emitting elements.

[0183] In an exemplary implementation, such as Figure 6 As shown, the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b emitting first-color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light. The orthographic projection of the first pixel circuit 15a onto the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11a onto the substrate, but does not overlap with the orthographic projection of the anode of the first light-emitting element 11b onto the substrate. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b emitting second-color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light. The orthographic projection of the second pixel circuit 15b onto the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a onto the substrate, but does not overlap with the orthographic projection of the second light-emitting element 12b onto the substrate. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light. The orthographic projection of the third pixel circuit 15c onto the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13a onto the substrate, but does not overlap with the orthographic projection of the anode of the third light-emitting element 13b onto the substrate.

[0184] In an exemplary implementation, such as Figure 7As shown, the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b emitting first-color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light. The orthographic projection of the first pixel circuit 15a onto the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11b onto the substrate, but does not overlap with the orthographic projection of the anode of the first light-emitting element 11a onto the substrate. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b emitting second-color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light. The orthographic projection of the second pixel circuit 15b onto the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a onto the substrate, but does not overlap with the orthographic projection of the second light-emitting element 12b onto the substrate. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light. The orthographic projection of the third pixel circuit 15c onto the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13a onto the substrate, but does not overlap with the orthographic projection of the anode of the third light-emitting element 13b onto the substrate.

[0185] In an exemplary implementation, such as Figure 8 As shown, the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b emitting first-color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light. The orthographic projection of the first pixel circuit 15a onto the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11a onto the substrate, but does not overlap with the orthographic projection of the anode of the first light-emitting element 11b onto the substrate. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b emitting second-color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light. The orthographic projection of the second pixel circuit 15b onto the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a onto the substrate, but does not overlap with the orthographic projection of the second light-emitting element 12b onto the substrate. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light. The orthographic projection of the third pixel circuit 15c onto the substrate does not overlap with the orthographic projection of the anodes of the two third light-emitting elements 13a and 13b onto the substrate, but overlaps with the orthographic projection of the anode of the second light-emitting element 12b located between the two third light-emitting elements 13a and 13b onto the substrate.

[0186] In an exemplary implementation, such as Figure 9As shown, the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b emitting first-color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light. The orthographic projection of the first pixel circuit 15a onto the substrate does not overlap with the orthographic projection of the anode 111 of the first light-emitting elements 11a and 11b onto the substrate, but overlaps with the orthographic projection of the anode of the second light-emitting element 12b located between the first light-emitting elements 11a and 11b onto the substrate. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b emitting second-color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light. The orthographic projection of the second pixel circuit 15b onto the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a onto the substrate, but does not overlap with the orthographic projection of the second light-emitting element 12b onto the substrate. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light. The orthographic projection of the third pixel circuit 15c onto the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13a onto the substrate, but does not overlap with the orthographic projection of the anode of the third light-emitting element 13b onto the substrate.

[0187] In an exemplary implementation, such as Figures 6 to 9 As shown, the two first light-emitting elements 11a and 11b electrically connected to the first pixel circuit 15a are in the second direction X (i.e., the two first light-emitting elements 11a and 11b are located in the same row), the two second light-emitting elements 12a and 12b electrically connected to the second pixel circuit 15b are in the second direction X (i.e., the two second light-emitting elements 12a and 12b are located in the same row), and the two third light-emitting elements 13a and 13b electrically connected to the third pixel circuit 15c are in the second direction X (i.e., the two third light-emitting elements 13a and 13b are located in the same row).

[0188] In an exemplary embodiment, at least two of the first light-emitting element overlapping with the first pixel circuit, the second light-emitting element overlapping with the second pixel circuit, and the third light-emitting element overlapping with the third pixel circuit are adjacent to each other. Figure 7 The explanation will be based on the example of a first light-emitting element overlapping with the first pixel circuit, a second light-emitting element overlapping with the second pixel circuit, and a third light-emitting element overlapping with the third pixel circuit all located in the same light-emitting unit. Figure 6 , Figure 8 and Figure 9Taking the example of a first light-emitting element overlapping with the first pixel circuit, a second light-emitting element overlapping with the second pixel circuit, and a third light-emitting element overlapping with the third pixel circuit located in the same light-emitting unit, and two light-emitting units located in the same light-emitting unit, the light-emitting unit includes: a first light-emitting element, a second light-emitting element, and a third light-emitting element.

[0189] In an exemplary embodiment, in the light-transmitting display area, a first type pixel circuit drives at least two first type light-emitting elements that emit light of the same color, and the first type pixel circuit is disposed below the anode having a first light-emitting element, a second light-emitting element and a third light-emitting element, which can improve light transmittance while ensuring the resolution of the display substrate.

[0190] Figure 10 This is an equivalent circuit diagram of a first type of pixel circuit. In an exemplary embodiment, such as... Figure 10 As shown, the first type of pixel circuit in this exemplary embodiment can be an 8T1C structure, that is, including first transistors T1 to seventh transistors T7 and capacitor C. First type light-emitting elements EL1 and EL2 can emit light of the same color and can each include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. In this example, the third transistor T3 is a driving transistor.

[0191] In an exemplary implementation, such as Figure 10 As shown, the first type of pixel circuit is electrically connected to the scan signal line Gate, the reset signal line RST, the initial signal line INIT, the light emission signal line EM, the data signal line Data, the first power supply line VDD, and the second power supply line VSS. Exemplarily, the first power supply line VDD is configured to provide a constant first voltage signal to the first type of pixel circuit, and the second power supply line VSS is configured to provide a constant second voltage signal to the first type of pixel circuit, wherein the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal. The scan signal line Gate is configured to provide a scan signal to the first type of pixel circuit, the data signal line Data is configured to provide a data signal to the first type of pixel circuit, the light emission signal line EM is configured to provide a light emission control signal to the first type of pixel circuit, and the reset signal line RST is configured to provide a reset control signal to the first type of pixel circuit. In some examples, in the nth row of the first type of pixel circuit, the reset signal line RST can be connected to the scan signal line Gate of the (n-1)th row of the first type of pixel circuit. This reduces the number of signal lines on the display substrate, enabling a narrow bezel on the display substrate.

[0192] In an exemplary implementation, such as Figure 10As shown, the control electrode of the first transistor T1 is electrically connected to the reset signal line RST, the first electrode of the first transistor T1 is electrically connected to the initial signal line INIT, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the scan signal line Gate, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The control electrode of the fifth transistor T5 is electrically connected to the light emission signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal line EM. The first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the scan signal line Gate. The first electrode of the seventh transistor T7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The first plate of capacitor C is electrically connected to the first node N1, and the second plate of capacitor C is electrically connected to the first power supply line VDD.

[0193] In this example, the first node N1 is the connection point of capacitor C, first transistor T1 and third transistor T3; the second node N2 is the connection point of fifth transistor T5, fourth transistor T4 and third transistor T3; the third node N3 is the connection point of third transistor T3, second transistor T2 and sixth transistor T6; and the fourth node N4 is the connection point of sixth transistor T6, seventh transistor T7 and two first-type light-emitting elements EL1 and EL2.

[0194] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 of the first type pixel circuit can all be P-type transistors or all be N-type transistors.

[0195] In an exemplary embodiment, the first type of transistors in the first type of pixel circuit (e.g., first transistor T1 to seventh transistor T7) can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) or oxide thin-film transistors (OTTs). The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon, while the active layer of the OTT TFT is made of oxide. LTPS TFTs have advantages such as high mobility and fast charging, while OTT TFTs have advantages such as low leakage current. Integrating LTPS TFTs and OTT TFTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate allows for the utilization of both advantages, enabling low-frequency driving, reducing power consumption, and improving display quality. However, this embodiment is not limited to this. For example, all transistors in the first type of pixel circuit can be LTPS TFTs, or all can be OTT TFTs.

[0196] Figure 11 for Figure 10 The timing diagram for the first type of pixel circuit is provided below. Figure 11 right Figure 10 The operation of the first type of pixel circuit shown will be explained. The first transistor T1 to the seventh transistor T7 in the first type of pixel circuit are P-type transistors.

[0197] In an exemplary implementation, such as Figure 10 and Figure 11 As shown, during a single frame display period, the operation of the first type of pixel circuit may include: a first stage S1, a second stage S2, and a third stage S3.

[0198] The first stage, S1, is called the reset stage. The reset signal line RST provides a low-level signal, turning on the first transistor T1. The initial signal line INIT provides an initial signal to the first node N1, initializing N1 and clearing the original data voltage in capacitor C. The scan signal line Gate provides a high-level signal, and the light emission control signal EM provided by the light emission signal line EM is also high, turning off the fourth transistor T4, the second transistor T2, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6. During this stage, the first type of light-emitting elements EL1 and EL2 do not emit light.

[0199] The second stage, S2, is called the data writing stage or threshold compensation stage. The signal provided by the scan signal line Gate is a low-level signal, and the data signal line Data outputs data. During this stage, since the signal at the first node N1 is low, the third transistor T3 is turned on. The signal provided by the scan signal line Gate turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage Vdata output by the data signal line Data to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into capacitor C. The voltage at the first electrode of capacitor C (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, causing the initial signal Vinit provided by the initial signal line INIT to be supplied to the fourth node N4. This initializes (resets) the anodes of the two first-type light-emitting elements EL1 and EL2, clearing their internal pre-stored voltages and completing the initialization process, ensuring that the first-type light-emitting elements EL1 and EL2 do not emit light. The reset signal line RST provides a high-level signal, causing the first transistor T1 to turn off. The light-emitting signal line EM provides a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0200] The third stage, S3, is called the light-emitting stage. The light-emitting signal line EM provides a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The scan signal line Gate and the reset signal line RST provide high-level signals, turning off the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the first transistor T1. The first voltage signal output from the first power supply line VDD provides a driving voltage to the anodes of the first-type light-emitting elements EL1 and EL2 through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the two first-type light-emitting elements EL1 and EL2 to emit light.

[0201] During the driving process of the first type of pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode and its first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0202] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 ;

[0203] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the first type of light-emitting element, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line Data, and VDD is the first voltage signal output by the first power supply line PL1.

[0204] As can be seen from the above formula, the current flowing through the first type of light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the first type of pixel circuit in this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0205] Figure 12 A partial top view of a light-transmitting display area provided in an exemplary embodiment Figure 1 , Figure 13 A partial top view of a light-transmitting display area provided in an exemplary embodiment Figure 2 , Figure 14 A partial top view of a light-transmitting display area provided in an exemplary embodiment Figure 3 . Figure 12 Therefore Figure 4 The provided light-transmitting display area will be used as an example for explanation. Figure 13 Therefore Figure 5 The provided light-transmitting display area will be used as an example for explanation. Figure 14 Therefore Figure 6 The following explanation uses the provided light-transmitting display area as an example.

[0206] In an exemplary embodiment, the first type of pixel circuit includes: a plurality of transistors and at least one capacitor; in a direction perpendicular to the display substrate, the light-transmitting display area includes at least: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer disposed on the substrate.

[0207] The semiconductor layer includes at least: an active layer of multiple transistors of the first type of pixel circuit;

[0208] The first conductive layer includes at least: the control electrodes of a plurality of transistors of a first type of pixel circuit and the first plate of a capacitor;

[0209] The second conductive layer includes at least: the second plate of the capacitor of the first type pixel circuit;

[0210] The third conductive layer includes at least: the first and second electrodes of a plurality of transistors of the first type of pixel circuit and a plurality of connection electrodes;

[0211] The transparent conductive layer includes at least: multiple first signal lines, multiple second signal lines, and multiple anode connection lines, wherein at least one of the multiple anode connection lines is electrically connected to the anode of at least one first type pixel circuit and at least two first type light-emitting elements emitting light of the same color; at least one first type pixel circuit is electrically connected to at least one first signal line and at least one second signal line.

[0212] The fourth conductive layer includes at least: multiple signal connection lines.

[0213] In an exemplary implementation, such as Figures 12 to 14 As shown, at least one first signal line includes multiple sub-signal lines; adjacent sub-signal lines of the first signal line are electrically connected through a first type of pixel circuit. Exemplarily, the multiple first signal lines include at least one of the following: a scan signal line, a reset signal line, an initial signal line, and a light-emitting signal line. Figures 12 to 14 This explanation uses the following examples: the scan signal line includes two sub-signal lines Gate_1 and Gate_2; the reset signal line includes two sub-signal lines RST_1 and RST_2; the initial signal line includes two sub-signal lines INIT_1 and INIT_2; and the light emission signal line includes two sub-signal lines EM_1 and EM_2.

[0214] In an exemplary implementation, such as Figures 12 to 14 As shown, the multiple second signal lines include multiple data signal lines Data and multiple first power lines VDD, with at least a portion of the data signal lines Data and the first power lines VDD extending along a first direction Y. The data signal lines Data and the first power lines VDD, which are electrically connected to the first type of pixel circuit, are located between adjacent sub-signal lines of the first signal lines, and their orthographic projections on the substrate overlap with the orthographic projections of the first type of pixel circuit on the substrate.

[0215] In an exemplary implementation, such as Figure 12 As shown, the sub-signal line of the first signal line is a polygonal line, and at least a portion of the sub-signal line of the first signal line extends along the second direction X.

[0216] In an exemplary implementation, such as Figure 12As shown, the anode connection line may include: a first anode connection line AL1, a second anode connection line AL2, a third anode connection line AL3, and a fourth anode connection line AL4. The first anode connection line AL1, the second anode connection line AL2, the third anode connection line AL3, and the fourth anode connection line AL4 may be in a zigzag shape. Specifically, the first anode connection line AL1 is electrically connected to both the first pixel circuit and the first light-emitting element, and at least a portion of the first anode connection line AL1 may extend along the second direction X. The second anode connection line AL2 is electrically connected to both the second pixel circuit and the second light-emitting element, and at least a portion of the second anode connection line AL2 extends along the second direction X. The third anode connection line AL3 is electrically connected to both the third pixel circuit and the third light-emitting element, and at least a portion of the third anode connection line AL3 extends along the second direction X. The third anode connection line AL3 is located between the data signal line Data and the first power supply line VDD, which are electrically connected to the third pixel circuit. The fourth anode connection line AL4 is electrically connected to the fourth pixel circuit and the third light-emitting element, and at least a portion of the fourth anode connection line AL4 extends along the second direction X. The fourth anode connection line AL4 is located between the data signal line Data and the first power supply line VDD, which are electrically connected to the fourth pixel circuit.

[0217] In an exemplary implementation, such as Figure 12 As shown, at least two adjacent first-type pixel circuits in the same column are electrically connected by first power lines spaced apart, and the spaced first power lines in the same column are electrically connected by at least one signal connection line located in the fourth conductive layer.

[0218] In an exemplary implementation, such as Figure 12 As shown, at least two adjacent first-type pixel circuits in the same column are electrically connected by data signal lines Data, which are spaced apart, and the spaced data signal lines Data in the same column are electrically connected by at least one signal connection line located in the fourth conductive layer.

[0219] In an exemplary implementation, such as Figure 13 As shown, the sub-signal line of the first signal line is a polygonal line, and at least a portion of the sub-signal line of the first signal line extends along the first direction Y.

[0220] In an exemplary implementation, such as Figure 13As shown, the anode connection lines include: a first anode connection line AL1, a second anode connection line AL2, a third anode connection line AL3, and a fourth anode connection line AL4. The first anode connection line AL1, the second anode connection line AL2, the third anode connection line AL3, and the fourth anode connection line AL4 can be zigzag lines. The first anode connection line AL1 is electrically connected to both the first pixel circuit and the first light-emitting element, and at least a portion of the first anode connection line AL1 extends along the first direction Y. The second anode connection line AL2 is electrically connected to both the second pixel circuit and the second light-emitting element, and at least a portion of the second anode connection line AL2 extends along the first direction Y. The third anode connection line AL3 is electrically connected to both the third pixel circuit and the third light-emitting element, and at least a portion of the third anode connection line AL3 extends along the first direction Y. The third anode connection line AL3 is located on the side of the first power line VDD, which is electrically connected to the third pixel circuit, that is away from the data signal line Data. The fourth anode connection line AL4 is electrically connected to the fourth pixel circuit and the third light-emitting element, and at least a portion of the fourth anode connection line AL4 extends along the first direction Y. The fourth anode connection line AL4 is located on the side of the first power supply line VDD that is electrically connected to the fourth pixel circuit away from the data signal line Data.

[0221] In an exemplary implementation, such as Figure 13 As shown, the Data signal lines of the first type of pixel circuits located in the same column are the same signal line.

[0222] In an exemplary implementation, such as Figure 13 As shown, at least two adjacent first-type pixel circuits in the same column are electrically connected by first power lines VDD spaced apart, and the spaced first power lines VDD in the same column are electrically connected by at least one signal connection line located in the fourth conductive layer.

[0223] In an exemplary implementation, such as Figure 13 As shown, the transparent conductive layer may further include a power connection line VCL, at least a portion of which extends along the second direction X. The power connection line VCL is electrically connected to a first power line VDD, which is electrically connected to two adjacent pixel circuits located in the same row. The first power line VDD and the power connection line VCL are electrically connected through a connection electrode located in the third conductive layer.

[0224] In an exemplary implementation, such as Figure 13As shown, for the same first type pixel circuit, the first power line VDD may include: a power body portion VDDM extending along a first direction Y and a power connection portion VDDS extending at least partially along a second direction X, wherein the power connection portion VDDS is located on the side of the power body portion VDDM away from the data signal line. The power connection line VDDS is electrically connected to the power connection portion of one of the first type pixel circuits and the power body portion of another first type pixel circuit located in the same row.

[0225] In an exemplary implementation, such as Figure 14 As shown, the sub-signal line of the first signal line can be a polygonal line, and at least a portion of the sub-signal line of the first signal line can extend along the second direction X.

[0226] In an exemplary implementation, such as Figure 14 As shown, the anode connection line may include: a first anode connection line AL1, a second anode connection line AL2, and a third anode connection line AL3; the first anode connection line AL1, the second anode connection line AL2, and the third anode connection line AL3 may be in the form of a broken line. Specifically, the first anode connection line AL1 is electrically connected to the first pixel circuit and the first light-emitting element, and at least a portion of the first anode connection line AL1 extends along the second direction X; the second anode connection line AL2 is electrically connected to the second pixel circuit and the second light-emitting element, and at least a portion of the second anode connection line AL2 extends along the second direction X; the third anode connection line AL3 is electrically connected to the third pixel circuit and the third light-emitting element, and at least a portion of the third anode connection line AL3 extends along the second direction X.

[0227] In an exemplary implementation, such as Figure 14 As shown, the data signal lines (Data) electrically connected to the pixel circuits in the same column are the same signal lines.

[0228] In an exemplary implementation, such as Figure 14 As shown, at least two adjacent first-type pixel circuits in the same column are electrically connected by first power lines VDD spaced apart, and the spaced first power lines VDD in the same column are electrically connected by at least one signal connection line located in the fourth conductive layer.

[0229] The structure of a display substrate is illustrated below using an example of the fabrication process. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes organic material coating, mask exposure, and development. Deposition can be performed using sputtering, evaporation, or chemical vapor deposition; coating can be performed using spraying, spin coating, or inkjet printing; and etching can be performed using dry etching or wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0230] In an exemplary embodiment Figure 12 The fabrication process of the provided light-transmitting display area may include the following operations.

[0231] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film using a patterning process to form a semiconductor layer pattern, such as... Figure 15A As shown, Figure 15A for Figure 12 A schematic diagram showing the semiconductor pattern formed in the provided light-transmitting display area.

[0232] In an exemplary implementation, such as Figure 15A As shown, the semiconductor layer pattern includes: the active layer T11 of the first transistor to the active layer T71 of the seventh transistor. The active layers T11 of the first transistor to the active layer T71 of the seventh transistor are an integral structure interconnected.

[0233] In an exemplary implementation, such as Figure 15AAs shown, in the second direction X, the active layer T21 of the second transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor can be located on the same side of the active layer T31 of the third transistor in the sub-pixel; the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor can be located on the same side of the active layer T31 of the third transistor in the sub-pixel; and the active layer T21 of the second transistor and the active layer T41 of the fourth transistor can be located on different sides of the active layer T31 of the third transistor in the sub-pixel. In the first direction Y, the active layers T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor, and the active layer T71 of the seventh transistor can be located on the same side of the active layer T31 of the third transistor in the sub-pixel; and the active layers T51 of the fifth transistor and the active layer T61 of the sixth transistor can be located on the other side of the active layer T31 of the third transistor in the sub-pixel.

[0234] In an exemplary implementation, such as Figure 15A As shown, the active layer T11 of the first transistor can be shaped like an "n", the active layer T21 of the second transistor can be shaped like an "L", the active layer T31 of the third transistor can be shaped like an "Ω", and the active layers T41, T51, T61 of the sixth transistor, and T71 of the seventh transistor can be shaped like an "I".

[0235] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, such as... Figure 15B and Figure 15C As shown, where, Figure 15B for Figure 12 A schematic diagram of the pattern of the first conductive layer in the light-transmitting display area is provided. Figure 15C for Figure 12 This is a schematic diagram showing the light-transmitting display area after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0236] In an exemplary implementation, such as Figure 15B and Figure 15C As shown, the pattern of the first conductive layer may include: the control electrode T12 of the first transistor to the control electrode T72 of the seventh transistor and the first plate C1 of the capacitor.

[0237] In an exemplary implementation, such as Figure 15B and Figure 15CAs shown, the first plate C1 of the capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered. The orthographic projection of the first plate C1 of the capacitor onto the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor T3 onto the substrate. In an exemplary embodiment, the first plate C1 of the capacitor can also serve as the control electrode T32 of the third transistor.

[0238] In an exemplary implementation, such as Figure 15B and Figure 15C As shown, the shape of the control electrode T12 of the first transistor can be a line shape extending along the second direction X.

[0239] In an exemplary implementation, such as Figure 15B and Figure 15C As shown, the control electrode T22 of the second transistor, the control electrode T42 of the fourth transistor, and the control electrode T72 of the seventh transistor can be integrally formed structures, and their shapes can be linear shapes extending along the second direction X.

[0240] In an exemplary implementation, such as Figure 15B and Figure 15C As shown, the control electrode T52 of the fifth transistor and the control electrode T62 of the sixth transistor can be integrally formed, and their shapes can be linear shapes extending along the second direction X.

[0241] In an exemplary implementation, such as Figure 15C As shown, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7. The semiconductor layer in the area not shielded by the first conductive layer is conducted, that is, the first and second regions of the active layer of the first transistor to the active layer of the seventh transistor are all conducted. The first region of the active layer of the third transistor after conduction (which is also the second region of the active layer of the fourth transistor and the second region of the active layer of the fifth transistor) can simultaneously serve as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor, and the second electrode T54 of the fifth transistor. The second region of the active layer of the third transistor after conduction (which is also the second region of the active layer of the second transistor and the first region of the active layer of the sixth transistor) also simultaneously serves as the second electrode T24 of the second transistor, the second electrode T34 of the third transistor, and the first electrode T63 of the sixth transistor.

[0242] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on a substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the second insulating layer. Figure 15D and Figure 15EAs shown, Figure 15D for Figure 12 A schematic diagram of the pattern of the second conductive layer in the light-transmitting display area is provided. Figure 15E for Figure 12 This is a schematic diagram showing the formation of the second conductive layer pattern in the provided light-transmitting display area. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0243] In an exemplary implementation, such as Figure 15D and Figure 15E As shown, the pattern of the second conductive layer may include: a second electrode C2 that connects the first electrode VL1 and the capacitor.

[0244] In an exemplary implementation, such as Figure 15D and Figure 15E As shown, at least a portion of the first connecting electrode VL1 may extend along the second direction X.

[0245] In an exemplary implementation, such as Figure 15D and Figure 15E As shown, the outline shape of the second electrode C2 can be "L" shaped. The orthographic projection of the second electrode C2 onto the substrate overlaps with the orthographic projection of the first electrode C1 onto the substrate. The second electrode C2 serves as the other electrode of the capacitor. The first electrode C1 and the second electrode C2 constitute the capacitor of the pixel circuit.

[0246] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein the third insulating layer has a plurality of vias, such as... Figure 15F As shown, where, Figure 15F for Figure 12 A schematic diagram showing the formation of the third insulating layer pattern in the provided light-transmitting display area.

[0247] In an exemplary implementation, such as Figure 15FAs shown, the multiple vias may each include: first vias V1 to sixth vias V6 disposed in the first insulating layer to the third insulating layer, seventh vias V7 to thirteenth vias V13 disposed in the second insulating layer and the third insulating layer, and fourteenth vias V14 to sixteenth vias V16 disposed in the third insulating layer. Specifically, the first via V1 exposes the connection between the active layers of the first transistor and the active layers of the second transistor; the second via V2 exposes the connection between the active layers of the first transistor and the active layers of the seventh transistor; the third via V3 exposes the active layer of the fourth transistor; the fourth via V4 exposes the active layer of the fifth transistor; the fifth via V5 exposes the active layer of the sixth transistor; the sixth via V6 exposes the active layer of the seventh transistor; the seventh via V7 and the eighth via V8 expose the two ends of the control electrode of the first transistor; the ninth via V10 and the tenth via V10 expose the two ends of the integrally formed structure of the control electrodes of the second transistor, the fourth transistor, and the seventh transistor; the eleventh via V11 and the twelfth via V12 expose the two ends of the integrally formed structure of the control electrodes of the fifth transistor and the sixth transistor; the thirteenth via V13 exposes the first electrode of the capacitor; the fourteenth via V14 exposes the second electrode of the capacitor; and the fifteenth via V15 and the sixteenth via V16 expose the two ends of the first connecting electrode.

[0248] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on a third insulating layer. Figure 15G and Figure 15H As shown, Figure 15G for Figure 12 A schematic diagram of the pattern of the third conductive layer in the light-transmitting display area is provided. Figure 15H for Figure 12 This is a schematic diagram showing the formation of the third conductive layer pattern in the provided light-transmitting display area. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0249] In an exemplary implementation, such as Figure 15G and Figure 15H As shown, the third conductive layer pattern may include: the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the second connecting electrode VL2 to the eleventh connecting electrode VL11, and the shielding electrode SL.

[0250] In an exemplary implementation, such as Figure 15G and Figure 15H As shown, the first terminal T13 of the first transistor can simultaneously serve as the first terminal T73 of the seventh transistor; the second terminal T14 of the first transistor can simultaneously serve as the first terminal T23 of the second transistor; the second terminal T64 of the sixth transistor can simultaneously serve as the second terminal T74 of the seventh transistor; and the first terminals T43 of the fourth transistor and T53 of the fifth transistor can be individually configured. The first terminals T13 and T14 of the first transistor can be L-shaped; the first terminal T43 of the fourth transistor has a block structure; the first terminal T53 of the fifth transistor is a horizontally flipped L-shaped terminal; and the second terminal of the sixth transistor can be a zigzag shape extending along the first direction Y.

[0251] In an exemplary implementation, such as Figure 15G and Figure 15H As shown, the second connecting electrode VL2 to the eighth connecting electrode VL8 are block structures, and the ninth connecting electrode VL9 to the eleventh connecting electrode VL11 are linear or zigzag shapes extending along the first direction Y.

[0252] In an exemplary implementation, such as Figure 15G and Figure 15H As shown, the shielding electrode SL has a block structure, and its orthographic projection on the substrate overlaps with the orthographic projection of the control electrode of the first transistor on the substrate.

[0253] In an exemplary implementation, such as Figure 15G and Figure 15HAs shown, the first electrode T13 of the first transistor is electrically connected to the connection point of the active layer of the first transistor and the active layer of the seventh transistor through the second via, and is electrically connected to the first connection electrode through the sixteenth via. The second electrode T14 of the first transistor is electrically connected to the connection point of the active layers of the first transistor and the second transistor through the first via, and is electrically connected to the first plate of the capacitor through the thirteenth via. The first electrode T43 of the fourth transistor is electrically connected to the active layer of the fourth transistor through the third via. The first electrode T53 of the fifth transistor is electrically connected to the active layer of the fifth transistor through the fourth via, and is electrically connected to the second plate of the capacitor through the fourteenth via. The second electrode T64 of the sixth transistor is electrically connected to the active layer of the sixth transistor through the fifth via, and is electrically connected to the active layer of the seventh transistor through the sixth via. The second connection electrode VL2 is electrically connected to the control electrode of the first transistor through the seventh via. The third connection electrode VL3 is electrically connected to the control electrode of the first transistor through the eighth via. The fourth connection electrode VL4 is electrically connected to the control electrode of the fourth transistor through the ninth via. The fifth connection electrode VL5 is electrically connected to the control electrode of the fourth transistor through the tenth via. The sixth connection electrode VL6 is electrically connected to the control electrode of the fifth transistor through the eleventh via. The seventh connection electrode VL7 is electrically connected to the control electrode of the fifth transistor through the twelfth via. The eighth connection electrode VL8 is electrically connected to the first connection electrode through the fifteenth via.

[0254] (6) Forming a fourth insulating layer. In an exemplary embodiment, forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein the fourth insulating layer has a plurality of vias, such as... Figure 15I As shown. Figure 15I for Figure 12 A schematic diagram showing the formation of the fourth insulating layer pattern in the provided light-transmitting display area.

[0255] In an exemplary implementation, such as Figure 15IAs shown, the multiple vias in the fourth insulating layer pattern may each include: via seventeen V17 to via thirty-first V31. Specifically, via seventeen V17 exposes the first electrode of the first transistor, via eighteen V18 exposes the first electrode of the fourth transistor, via nineteen V19 exposes the first electrode of the fifth transistor, via twentieth V20 exposes the second electrode of the sixth transistor, via twenty-first V21 exposes the second connection electrode, via twenty-second V22 exposes the third connection electrode, via twenty-third V23 exposes the fourth connection electrode, via twenty-fourth V24 exposes the fifth connection electrode, via twenty-fifth V25 exposes the sixth connection electrode, via twenty-sixth V26 exposes the seventh connection electrode, via twenty-seventh V27 exposes the eighth connection electrode, via twenty-eighth V28 exposes the shielding electrode, via twenty-ninth V29 exposes the ninth connection electrode, via thirtyth V30 exposes the tenth connection electrode, and via thirty-first V31 exposes the eleventh connection electrode.

[0256] In an exemplary embodiment, there may be two 29th vias V29, which may be arranged along the first direction Y and located at both ends of the ninth connecting electrode.

[0257] In an exemplary embodiment, there may be two thirtieth vias V30, which may be arranged along the first direction Y and located at both ends of the tenth connecting electrode.

[0258] In an exemplary embodiment, there may be two 31 vias V31, which may be arranged along the first direction Y and located at both ends of the 11th connecting electrode.

[0259] (7) Forming a transparent conductive layer pattern. In an exemplary embodiment, forming a transparent conductive layer pattern may include: depositing a transparent conductive film on a substrate on which the aforementioned pattern is formed, patterning the transparent conductive film using a patterning process, and forming a transparent conductive layer disposed on a fourth insulating layer, such as... Figure 15J and Figure 15K As shown, Figure 15J for Figure 12 A schematic diagram of the transparent conductive layer pattern in the light-transmitting display area is provided. Figure 15K for Figure 12 A schematic diagram showing the formation of a transparent conductive layer pattern in the provided light-transmitting display area.

[0260] In an exemplary implementation, such as Figure 15J and Figure 15KAs shown, the transparent conductive layer pattern may include: a data signal line Data, a first power supply line VDD, a first anode connection line AL1, a second anode connection line AL2, a third anode connection line AL3, a fourth anode connection line AL4, two sub-signal lines INIT_1 and INIT_2 of the initial signal line, two sub-signal lines RST_1 and RST_2 of the reset signal line, two sub-signal lines Gate_1 and Gate_2 of the scan signal line, two sub-signal lines EM_1 and EM_2 of the light emission signal line, a twelfth connecting electrode VL12, and a thirteenth connecting electrode VL13.

[0261] In an exemplary implementation, such as Figure 15J and Figure 15K As shown, the data signal line Data and the first power line VDD can be located between two sub-signal lines of a plurality of first signal lines electrically connected to a first type pixel circuit electrically connected to the data signal line Data and the first power line VDD, and their orthogonal projections on the substrate overlap with the orthogonal projections of the first type pixel circuit on the substrate.

[0262] In an exemplary implementation, such as Figure 15J and Figure 15K As shown, the data signal line Data can be a polygonal line, and at least a portion of the data signal line Data can extend along the first direction Y. Adjacent data signal lines Data in the same column that are electrically connected to each other can be the same signal line, or they can be spaced apart. Two adjacent data signal lines Data in the same column that are spaced apart and electrically connected to each other can be electrically connected to the ninth connection electrode through the twenty-ninth via. Data signal lines Data in the same column that are spaced apart and electrically connected to each other can be electrically connected through the ninth connection electrode. The data signal line is electrically connected to the first electrode of the fourth transistor of the electrically connected first-type pixel circuit through the eighteenth via.

[0263] In an exemplary implementation, such as Figure 15J and Figure 15KAs shown, the first power line VDD can be a zigzag shape, and at least a portion of the first power line VDD can extend along the first direction Y. Adjacent first-type pixel circuits electrically connected in the same column can be spaced apart. The first power line is electrically connected to the first electrode of the fifth transistor of the electrically connected first-type pixel circuit through a nineteenth via, and electrically connected to the shielding electrode through a twenty-eighth via. Exemplarily, two adjacent first-type pixel circuits VDDs spaced apart in the same column can be directly electrically connected through a tenth connecting electrode, or they can be electrically connected through a tenth connecting electrode, a twelfth connecting electrode, and a tenth connecting electrode, respectively. The first power line VDD and the twelfth connecting electrode of the first-type pixel circuit can be electrically connected to the tenth connecting electrode through a thirtieth via.

[0264] In an exemplary embodiment, the first anode connection line AL1 to the fourth anode connection line AL4 can be in the form of a broken line.

[0265] In an exemplary implementation, such as Figure 15J and Figure 15K As shown, the first anode connection line AL1 is located between the spaced first power lines, and at least a portion of the first anode connection line AL1 extends along the second direction X. The first anode connection line AL1 is electrically connected to the second pole of the sixth transistor of the first type pixel circuit through the twentieth via.

[0266] In an exemplary implementation, such as Figure 15J and Figure 15K As shown, the second anode connection line AL2 is located between the spaced first power lines, and at least a portion of the second anode connection line AL2 extends along the second direction X. The second anode connection line AL2 is electrically connected to the second electrode of the sixth transistor of the first type pixel circuit through the twentieth via, and electrically connected to the eleventh connection electrode through the thirtieth via.

[0267] In an exemplary implementation, such as Figure 15J and Figure 15K As shown, the third anode connection line AL3 is located between the data signal line Data and the first power supply line VDD of the electrically connected first type pixel circuit, and at least a portion of the third anode connection line AL3 extends along the second direction X. The third anode connection line AL3 is electrically connected to the second pole of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via.

[0268] In an exemplary implementation, such as Figure 15J and Figure 15KAs shown, the fourth anode connection line AL4 is located between the data signal line Data and the first power supply line VDD of the electrically connected first type pixel circuit, and at least a portion of the fourth anode connection line AL4 extends along the second direction X. The fourth anode connection line AL4 is electrically connected to the second pole of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via.

[0269] In an exemplary implementation, such as Figure 15J and Figure 15K As shown, at least a portion of the thirteenth connecting electrode VL13 extends along the second direction X and is electrically connected to the eleventh connecting electrode through a thirty-first via. The second anode connecting line AL1 is electrically connected to the first type pixel circuit, the eleventh connecting electrode, and the thirteenth connecting electrode, respectively.

[0270] In an exemplary implementation, such as Figure 15J and Figure 15K As shown, the two sub-signal lines INIT_1 and INIT_2 of the initial signal line can be of a polygonal shape. At least a portion of the two sub-signal lines INIT_1 and INIT_2 can extend along the second direction X. Sub-signal line INIT_1 is electrically connected to the eighth connecting electrode through a twenty-seventh via, and sub-signal line INIT_2 is electrically connected to the first electrode of the first transistor through a seventeenth via. Sub-signal line INIT_1 is electrically connected to the first connecting electrode through the eighth connecting electrode. Sub-signal line INIT_2 is electrically connected to the first connecting electrode through the first electrode of the first transistor.

[0271] In an exemplary implementation, such as Figure 15J and Figure 15K As shown, the two sub-signal lines RST_1 and RST_2 of the reset signal line can be of a polygonal shape. At least a portion of the two sub-signal lines RST_1 and RST_2 can extend along the second direction X. Sub-signal line RST_1 is electrically connected to the second connection electrode through a twenty-first via, and sub-signal line RST_2 is electrically connected to the third connection electrode through a twenty-second via. Sub-signal line RST_1 is electrically connected to the control electrode of the first transistor through the second connection electrode, and sub-signal line RST_2 is electrically connected to the control electrode of the first transistor through the third connection electrode.

[0272] In an exemplary implementation, such as Figure 15J and Figure 15KAs shown, the two sub-signal lines Gate_1 and Gate_2 of the scan signal line can be polygonal. At least a portion of the two sub-signal lines Gate_1 and Gate_2 can extend along the second direction X. Sub-signal line Gate_1 is electrically connected to the fourth connection electrode through the twenty-third via, and sub-signal line Gate_2 is electrically connected to the fifth connection electrode through the twenty-fourth via. Sub-signal line Gate_1 is electrically connected to the control electrode of the fourth transistor through the fourth connection electrode, and sub-signal line Gate_2 is electrically connected to the control electrode of the fourth transistor through the fifth connection electrode.

[0273] In an exemplary implementation, such as Figure 15J and Figure 15K As shown, the two sub-signal lines EM_1 and EM_2 of the light-emitting signal line can be of a polygonal shape. At least a portion of the two sub-signal lines EM_1 and EM_2 can extend along the second direction X. Sub-signal line EM_1 is electrically connected to the sixth connecting electrode through the twenty-fifth via, and sub-signal line EM_2 is electrically connected to the seventh connecting electrode through the twenty-sixth via. Sub-signal line EM_1 is electrically connected to the control electrode of the fifth transistor through the sixth connecting electrode, and sub-signal line EM_2 is electrically connected to the control electrode of the fifth transistor through the seventh connecting electrode.

[0274] (8) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: depositing a first planarization film on a substrate on which the aforementioned pattern is formed to form a first planarization layer pattern disposed on a transparent conductive layer, the first planarization layer pattern including a plurality of vias, such as... Figure 15L As shown, Figure 15L for Figure 12 A schematic diagram showing the light-transmitting display area after the first flat layer has been formed.

[0275] In an exemplary implementation, such as Figure 15L As shown, the first planarization layer pattern may include: a 32nd via V32 and a 38th via V38. Specifically, the 32nd via V32 exposes the first anode connection line, the 33rd via V33 exposes the second anode connection line, the 34th via V34 exposes the third anode connection line, the 35th via V35 exposes the fourth anode connection line, the 36th via V36 exposes the 13th connection electrode, the 37th via V37 exposes the first power line VDD, and the 38th via V38 exposes the 12th connection electrode.

[0276] In an exemplary implementation, such as Figure 15LAs shown, there can be two vias, the thirty-second via V32, located at both ends of the first anode connection line. There can be two vias, the thirty-third via V33, located at both ends of the second anode connection line. There can be two vias, the thirty-fourth via V34, located at both ends of the third anode connection line. There can be two vias, the thirty-fifth via V35, located at both ends of the fourth anode connection line.

[0277] (9) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first planarization layer, such as... Figure 15M and Figure 15N As shown, Figure 15M for Figure 12 A schematic diagram of the fourth conductive layer pattern in the light-transmitting display area is provided. Figure 15N for Figure 12 This is a schematic diagram showing the formation of the fourth conductive layer pattern in the provided light-transmitting display area. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0278] In an exemplary implementation, such as Figure 15M and Figure 15N As shown, the fourth conductive layer pattern may include: fourteenth connecting electrode VL14 to twenty-first connecting electrode VL21, first signal connecting line VDL1 and second signal connecting line VDL2.

[0279] In an exemplary implementation, such as Figure 15M and Figure 15N As shown, the fourteenth connecting electrode VL14 to the twenty-first connecting electrode VL21 have a block structure. The first signal connecting line VDL1 and the second signal connecting line VDL2 can be zigzag-shaped, and at least a portion of the first signal connecting line VDL1 and the second signal connecting line VDL2 extends along the first direction Y.

[0280] In an exemplary implementation, such as Figure 15M and Figure 15NAs shown, the fourteenth connecting electrode VL14 and the fifteenth connecting electrode VL15 are electrically connected to the first anode connecting line through the thirty-second via; the sixteenth connecting electrode VL1 is electrically connected to the second anode connecting line through the thirty-third via; the seventeenth connecting electrode VL17 is electrically connected to the thirteenth connecting electrode through the thirty-sixth via; the eighteenth connecting electrode VL18 and the nineteenth connecting electrode VL19 are electrically connected to the third anode connecting line through the thirty-fourth via; and the twentieth via V20 and the twenty-first via V21 are electrically connected to the fourth anode connecting line through the thirty-fifth via. The first signal connecting line VDL1 is electrically connected to the first power line VDD, which is electrically connected to the first type pixel circuit, through the thirty-seventh via; and the second signal connecting line VDL2 is electrically connected to the twelfth connecting electrode through the thirty-eighth via and to the first power line through the thirty-seventh via.

[0281] In an exemplary embodiment, the first power line of the first type of pixel circuits located in the same column is connected via a first power connection line, a tenth connection electrode, and a second power connection line. The data signal line of the first type of pixel circuits located in the same column is connected via a ninth connection electrode.

[0282] In an exemplary embodiment, such as Figure 15N As shown, the fourteenth connecting electrode VL14 is electrically connected to the fifteenth connecting electrode VL15 through the first anode connecting line; the sixteenth connecting electrode VL16 is electrically connected to the seventeenth connecting electrode VL17 through the second anode connecting line, the eleventh connecting electrode, and the thirteenth connecting electrode; the eighteenth connecting electrode VL18 is electrically connected to the nineteenth connecting electrode VL19 through the third anode connecting line; and the twentieth connecting electrode VL20 is electrically connected to the twenty-first connecting electrode VL21 through the fourth anode connecting line.

[0283] In the exemplary embodiment, multiple connecting electrodes serve as a support, which can avoid the unreliability of the connection caused by opening deep vias and improve the reliability of the display panel.

[0284] (10) Forming a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, patterning the second planarization film using a patterning process to form a second planarization layer covering a fourth conductive layer, wherein a plurality of vias are provided on the second planarization layer, such as... Figure 15O As shown, where, Figure 15O for Figure 12 A schematic diagram showing the formation of the second flattened layer pattern in the provided light-transmitting display area.

[0285] In an exemplary implementation, such as Figure 15OAs shown, the multiple vias in the second planarization layer pattern may each include: via 39 V39 to via 46 V46. Specifically, via 39 V39 exposes the fourteenth connecting electrode, via 40 V40 exposes the fifteenth connecting electrode, via 41 V41 exposes the sixteenth connecting electrode, via 42 V42 exposes the seventeenth connecting electrode, via 43 V43 exposes the eighteenth connecting electrode, via 44 V44 exposes the nineteenth connecting electrode, via 45 V45 exposes the twentieth connecting electrode, and via 46 V46 exposes the twenty-first connecting electrode.

[0286] At this point, the driving circuit layer is fabricated on the substrate. On a plane parallel to the display substrate, the driving circuit layer may include multiple first-type pixel circuits, scan signal lines, reset signal lines, light-emitting signal lines, data signal lines, initial signal lines, and first to fourth anode connection lines. On a plane perpendicular to the display panel, the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer, sequentially stacked on the substrate.

[0287] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0288] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0289] In an exemplary embodiment, the transparent conductive layer may be made of materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may be a multilayer composite structure such as ITO / Ag / ITO.

[0290] In exemplary embodiments, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer, the second insulating layer can be called a gate insulating (GI) layer, the third insulating layer can be called an interlayer insulating (ILD) layer, and the fourth insulating layer can be called a passivation (PVX) layer. The first and second planarization layers can be made of organic materials, such as resins. The semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc., meaning this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0291] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0292] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on a second planarization layer, such as... Figure 15P and 15Q As shown, Figure 15P for Figure 12 A schematic diagram of the anode conductive layer pattern in the light-transmitting display area is provided. Figure 15Q for Figure 12 A schematic diagram showing the formation of the anodic conductive layer pattern in the provided light-transmitting display area.

[0293] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0294] In an exemplary embodiment, the anode conductive layer pattern may include the anode 110 of the first light-emitting elements 11a and 11b, the anode 120 of the second light-emitting element, and the anode 130 of the third light-emitting elements 13a to 13d.

[0295] In an exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the fourteenth connecting electrode through the thirty-ninth via, the anode of the first light-emitting element 11b is electrically connected to the fifteenth connecting electrode through the fortieth via, the anode of the second light-emitting element 12b is electrically connected to the sixteenth connecting electrode through the forty-first via, the anode of the second light-emitting element 12a is electrically connected to the seventeenth connecting electrode through the forty-second via, the anode of the third light-emitting element 13a is electrically connected to the eighteenth connecting electrode through the forty-third via, the anode of the third light-emitting element 13b is electrically connected to the nineteenth connecting electrode through the forty-fourth via, the anode of the third light-emitting element 13c is electrically connected to the twentieth connecting electrode through the forty-fifth via, and the anode of the third light-emitting element 13d is electrically connected to the twenty-first connecting electrode through the forty-sixth via.

[0296] In an exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the anode of the first light-emitting element 11b via the fourteenth connecting electrode, the first anode connecting line, and the fifteenth connecting electrode. The anode of the second light-emitting element 12a is electrically connected to the anode of the second light-emitting element 12b via the sixteenth connecting electrode, the eleventh connecting electrode, the thirteenth connecting electrode, and the seventeenth connecting electrode. The anode of the third light-emitting element 13a is electrically connected to the anode of the third light-emitting element 13b via the eighteenth connecting electrode, the third anode connecting line, and the nineteenth connecting electrode. The anode of the third light-emitting element 13c is electrically connected to the anode of the third light-emitting element 13d via the twentieth connecting electrode, the fourth anode connecting line, and the twenty-first connecting electrode.

[0297] In an exemplary embodiment, at least one of the anodes 110 of the first light-emitting elements 11a and 11b, the anode 120 of the second light-emitting element, and the anodes 130 of the third light-emitting elements 13a to 13d may include a main body portion and a connecting portion connected to each other. The main body portion may be rectangular in shape, and the corners of the rectangular shape may be provided with rounded chamfers. The connecting portion may be a strip shape extending away from the main body portion.

[0298] In an exemplary embodiment, the subsequent fabrication process may include: first forming a pixel definition layer pattern, then forming an organic light-emitting layer using vapor deposition or inkjet printing, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0299] In an exemplary embodiment Figure 13 The fabrication process of the provided light-transmitting display area may include the following operations.

[0300] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film using a patterning process to form a semiconductor layer pattern, such as... Figure 16A As shown, Figure 16A for Figure 13 A schematic diagram showing the semiconductor pattern formed in the provided light-transmitting display area.

[0301] In an exemplary embodiment Figure 16A The provided semiconductor layer pattern and Figure 15A The provided semiconductor layer pattern is the same, so it will not be described again here.

[0302] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, such as... Figure 16B and Figure 16C As shown, where, Figure 16B for Figure 13 A schematic diagram of the pattern of the first conductive layer in the light-transmitting display area is provided. Figure 16C for Figure 13 This is a schematic diagram showing the light-transmitting display area after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0303] In an exemplary embodiment Figure 16B and Figure 16C The provided first conductive layer pattern and Figure 15B and Figure 15C The pattern of the first conductive layer provided is the same, and will not be described again here.

[0304] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on a substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the second insulating layer. Figure 16D and Figure 16E As shown, Figure 16D for Figure 13 A schematic diagram of the pattern of the second conductive layer in the light-transmitting display area is provided. Figure 16E for Figure 13 This is a schematic diagram showing the formation of the second conductive layer pattern in the provided light-transmitting display area. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0305] In an exemplary embodiment Figure 16D and Figure 16E The pattern of the provided second conductive layer is consistent with Figure 15D and Figure 15E The pattern of the second conductive layer is the same, and will not be described again here.

[0306] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein the third insulating layer has a plurality of vias, such as... Figure 16F As shown, where, Figure 16F for Figure 13 A schematic diagram showing the formation of the third insulating layer pattern in the provided light-transmitting display area.

[0307] In an exemplary implementation, such as Figure 16F The provided third insulating layer pattern and Figure 15F The pattern of the third insulating layer is the same, so it will not be described again here.

[0308] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on a third insulating layer. Figures 16G to 16H As shown, Figure 16G for Figure 13 A schematic diagram of the pattern of the third conductive layer in the light-transmitting display area is provided. Figure 16H for Figure 13 This is a schematic diagram showing the formation of the third conductive layer pattern in the provided light-transmitting display area. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0309] In an exemplary implementation, such as Figure 16G and Figure 16H As shown, the third conductive layer pattern may include: the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the second connecting electrode VL2 to the tenth connecting electrode VL10, the shielding electrode SL, and the power connection line VCL.

[0310] In an exemplary implementation, such as Figure 16G and Figure 16HThe provided first transistor has a first electrode T13 and a second electrode T14, the second transistor has a first electrode T23, the fourth transistor has a first electrode T43, the fifth transistor has a first electrode T53, the sixth transistor has a second electrode T64, the seventh transistor has a first electrode T73 and a second electrode T74, the second connecting electrode VL2 to the eighth connecting electrode VL8, and a shielding electrode. Figure 15G and 15H The first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the second connecting electrode VL2 to the eighth connecting electrode VL8, and the shielding electrode SL have the same pattern, and will not be described again here.

[0311] In an exemplary implementation, such as Figure 16G and Figure 16H As shown, at least portions of the ninth connecting electrode VL9 and the tenth connecting electrode VL10 extend along the second direction X. The power connection line VCL extends along the second direction X.

[0312] (6) Forming a fourth insulating layer. In an exemplary embodiment, forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein the fourth insulating layer has a plurality of vias, such as... Figure 16I As shown. Figure 16I for Figure 13 A schematic diagram showing the formation of the fourth insulating layer pattern in the provided light-transmitting display area.

[0313] In an exemplary implementation, such as Figure 16I As shown, the multiple vias in the fourth insulating layer pattern may all include: the seventeenth via V17 to the thirty-first via V31. Figure 16I The seventeenth via V17 to the twenty-eighth via V28 in the middle Figure 15I The seventeenth via V17 to the twenty-eighth via V28 are the same, except that the twenty-ninth via V29 exposes the ninth connection electrode, the thirtieth via V30 exposes the tenth connection electrode, and the thirty-first via V31 exposes the power connection line VCL.

[0314] In an exemplary embodiment, there may be two 29th vias V29, which may be arranged along the second direction X and located at both ends of the ninth connecting electrode.

[0315] In an exemplary embodiment, there may be two thirtieth vias V30, which may be arranged along the second direction X and located at both ends of the tenth connecting electrode.

[0316] In an exemplary embodiment, there may be two 31 vias V31, which may be arranged along the second direction X and located at both ends of the electrode connection line.

[0317] (7) Forming a transparent conductive layer pattern. In an exemplary embodiment, forming a transparent conductive layer pattern may include: depositing a transparent conductive film on a substrate on which the aforementioned pattern is formed, patterning the transparent conductive film using a patterning process, and forming a transparent conductive layer disposed on a fourth insulating layer, such as... Figure 16J and Figure 16K As shown, Figure 16J for Figure 13 A schematic diagram of the transparent conductive layer pattern in the light-transmitting display area is provided. Figure 16K for Figure 13 A schematic diagram showing the formation of a transparent conductive layer pattern in the provided light-transmitting display area.

[0318] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the transparent conductive layer pattern may include: a data signal line Data, a first power supply line VDD, a first anode connection line AL1, a second anode connection line AL2, a third anode connection line AL3, a fourth anode connection line AL4, two sub-signal lines INIT_1 and INIT_2 of the initial signal line, two sub-signal lines RST_1 and RST_2 of the reset signal line, two sub-signal lines Gate_1 and Gate_2 of the scan signal line, two sub-signal lines EM_1 and EM_2 of the light emission signal line, an eleventh connecting electrode VL11, and a twelfth connecting electrode VL12.

[0319] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the data signal line Data and the first power line VDD can be located between two sub-signal lines of a plurality of first signal lines electrically connected to a first type pixel circuit electrically connected to the data signal line Data and the first power line VDD, and their orthogonal projections on the substrate overlap with the orthogonal projections of the first type pixel circuit on the substrate.

[0320] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the data signal line Data is a polygonal line, with at least a portion extending along the first direction Y. Data signal lines Data that are electrically connected to adjacent first-type pixel circuits in the same column can be the same signal line. The data signal line is electrically connected to the first terminal of the fourth transistor of the electrically connected first-type pixel circuit through the eighteenth via.

[0321] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the first power line VDD is a zigzag line, at least a portion of which extends along the first direction Y. Adjacent first-type pixel circuits electrically connected in the same column can be spaced apart. The first power line is electrically connected to the first electrode of the fifth transistor of the electrically connected first-type pixel circuit through the nineteenth via, and electrically connected to the shielding electrode through the twenty-eighth via.

[0322] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the first power line VDD includes: a power body portion VDDM extending along a first direction Y and a power connection portion VDDS extending at least partially along a second direction X.

[0323] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, at least a portion of the power connection line VCL extends along the second direction X and is electrically connected to a first power line VDD electrically connected to an adjacent first-type pixel circuit in the same row. Specifically, the power connection portion of the first power line electrically connected to one of the adjacent first-type pixel circuits in the same row is electrically connected to the power connection line VCL via a thirty-first via, and the power body of the first power line electrically connected to the other adjacent first-type pixel circuit in the same row is connected to the power connection line VCL via a thirty-first via. The arrangement of the power connection line VCL, in conjunction with the first power line, forms a mesh structure, achieving display uniformity of the display substrate.

[0324] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the first anode connection line AL1 to the fourth anode connection line AL4 can be in the form of a broken line.

[0325] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the first anode connection line AL1 is located between the first power line VDD of the first type pixel circuit and the data signal line Data of the adjacent column of the first type pixel circuit. At least a portion of the first anode connection line AL1 extends along the second direction X. The first anode connection line AL1 is electrically connected to the second electrode of the sixth transistor of the first type pixel circuit through the twentieth via and electrically connected to the ninth connection electrode through the twenty-ninth via.

[0326] In an exemplary implementation, such as Figure 16J and Figure 16KAs shown, the second anode connection line AL2 is located between the first power line VDD of the first type pixel circuit and the data signal line Data of the adjacent column of the first type pixel circuit. At least a portion of the second anode connection line AL2 extends along the second direction X. The second anode connection line AL2 is electrically connected to the second electrode of the sixth transistor of the first type pixel circuit through the twentieth via, and electrically connected to the tenth connection electrode through the thirtieth via.

[0327] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the third anode connection line AL3 is located between the first power supply line VDD of the electrically connected first type pixel circuit and the data signal line Data of the adjacent first type pixel circuit in the same row. At least a portion of the third anode connection line AL3 extends along the first direction Y, and the third anode connection line AL3 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through a 20th via.

[0328] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the fourth anode connection line AL4 is located between the first power supply line VDD of the electrically connected first type pixel circuit and the data signal line Data of the adjacent first type pixel circuit in the same row. At least a portion of the fourth anode connection line AL4 may extend along the first direction Y, and the fourth anode connection line AL4 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through a 20th via.

[0329] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the two sub-signal lines INIT_1 and INIT_2 of the initial signal line can be zigzag-shaped. At least a portion of the two sub-signal lines INIT_1 and INIT_2 can extend along the first direction Y. Sub-signal line INIT_1 is electrically connected to the eighth connection electrode through the twenty-seventh via, and sub-signal line INIT_2 is electrically connected to the first electrode of the first transistor through the seventeenth via. Sub-signal line INIT_1 is electrically connected to the first connection electrode through the eighth connection electrode. Sub-signal line INIT_2 is electrically connected to the first connection electrode through the first electrode of the first transistor.

[0330] In an exemplary implementation, such as Figure 16J and Figure 16KAs shown, the two sub-signal lines RST_1 and RST_2 of the reset signal line can be zigzag-shaped. At least a portion of the two sub-signal lines RST_1 and RST_2 can extend along the second direction Y. Sub-signal line RST_1 is electrically connected to the second connection electrode through a twenty-first via, and sub-signal line RST_2 is electrically connected to the third connection electrode through a twenty-second via. Sub-signal line RST_1 is electrically connected to the control electrode of the first transistor through the second connection electrode, and sub-signal line RST_2 is electrically connected to the control electrode of the first transistor through the third connection electrode.

[0331] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the two sub-signal lines Gate_1 and Gate_2 of the scan signal line can be zigzag-shaped. At least a portion of the two sub-signal lines Gate_1 and Gate_2 can extend along the second direction Y. Sub-signal line Gate_1 is electrically connected to the fourth connection electrode through the twenty-third via, and sub-signal line Gate_2 is electrically connected to the fifth connection electrode through the twenty-fourth via. Sub-signal line Gate_1 is electrically connected to the control electrode of the fourth transistor through the fourth connection electrode, and sub-signal line Gate_2 is electrically connected to the control electrode of the fourth transistor through the fifth connection electrode.

[0332] In an exemplary implementation, such as Figure 16J and Figure 16K As shown, the two sub-signal lines EM_1 and EM_2 of the light-emitting signal line can be zigzag-shaped. At least a portion of the two sub-signal lines EM_1 and EM_2 can extend along the second direction Y. Sub-signal line EM_1 is electrically connected to the sixth connecting electrode through the twenty-fifth via, and sub-signal line EM_2 is electrically connected to the seventh connecting electrode through the twenty-sixth via. Sub-signal line EM_1 is electrically connected to the control electrode of the fifth transistor through the sixth connecting electrode, and sub-signal line EM_2 is electrically connected to the control electrode of the fifth transistor through the seventh connecting electrode.

[0333] (8) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: depositing a first planarization film on a substrate on which the aforementioned pattern is formed to form a first planarization layer pattern disposed on a transparent conductive layer, the first planarization layer pattern including a plurality of vias, such as... Figure 16L As shown, Figure 16L for Figure 13 A schematic diagram showing the light-transmitting display area after the first flat layer has been formed.

[0334] In an exemplary implementation, such as Figure 16LAs shown, the first planarization layer pattern may include: a 32nd via V32 and a 38th via V38. Specifically, the 32nd via exposes a first power line, the 33rd via V33 exposes a first anode connection line, the 34th via V34 exposes a second anode connection line, the 35th via V35 exposes a third anode connection line, the 36th via V36 exposes a fourth anode connection line, the 37th via V37 exposes an eleventh connection electrode, and the 38th via V38 exposes a twelfth connection electrode.

[0335] In an exemplary implementation, such as Figure 16L As shown, the number of vias V33 (thirty-third) can be two, and they are located at both ends of the first anode connection line. The number of vias V34 (thirty-fourth) can be two, and they are located at both ends of the second anode connection line. The number of vias V35 (thirty-fifth) can be two, and they are located at both ends of the third anode connection line. The number of vias V36 (thirty-sixth) can be two, and they are located at both ends of the fourth anode connection line.

[0336] (9) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first planarization layer, such as... Figure 16M and Figure 16N As shown, Figure 16M for Figure 13 A schematic diagram of the fourth conductive layer pattern in the light-transmitting display area is provided. Figure 16N for Figure 13 This is a schematic diagram showing the formation of the fourth conductive layer pattern in the provided light-transmitting display area. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0337] In an exemplary implementation, such as Figure 16M and Figure 16N As shown, the fourth conductive layer pattern may include: thirteenth connecting electrode VL13 to twentieth connecting electrode VL20 and signal connection line VDL.

[0338] In an exemplary implementation, such as Figure 16M and Figure 16N As shown, the thirteenth connecting electrode VL13 to the twentieth connecting electrode VL20 have a block structure. The signal connection line VDL can be a broken line, and at least a portion of the signal connection line VDL can extend along the first direction Y.

[0339] In an exemplary implementation, such as Figure 16M and Figure 16NAs shown, the thirteenth connecting electrode VL13 is electrically connected to the first anode connecting line through the thirty-third via; the fourteenth connecting electrode VL14 is electrically connected to the second anode connecting line through the thirty-fourth via; the fifteenth connecting electrode VL15 and the sixteenth connecting electrode VL16 are electrically connected to the third anode connecting line through the thirty-fifth via; the seventeenth connecting electrode VL17 and the eighteenth connecting electrode VL18 are electrically connected to the fourth anode connecting line through the thirty-sixth via; the nineteenth connecting electrode VL19 is electrically connected to the eleventh connecting electrode through the thirty-seventh via; and the twentieth connecting electrode VL20 is electrically connected to the twelfth connecting electrode through the thirty-eighth via. The signal connecting line VDL is electrically connected to the first power line of the first type pixel circuit through the thirty-second via.

[0340] In an exemplary embodiment, the first power lines of the first type of pixel circuits located in the same column are electrically connected via signal connection lines.

[0341] In an exemplary embodiment, such as Figure 16N As shown, the thirteenth connecting electrode VL13 is electrically connected to the nineteenth connecting electrode VL19 through the first anode connecting line, the ninth connecting electrode, and the eleventh connecting electrode; the fourteenth connecting electrode VL14 is electrically connected to the twentieth connecting electrode VL20 through the second anode connecting line, the tenth connecting electrode, and the twelfth connecting electrode; the fifteenth connecting electrode VL15 is electrically connected to the sixteenth connecting electrode VL16 through the third anode connecting line; and the seventeenth connecting electrode VL17 is electrically connected to the eighteenth connecting electrode VL18 through the fourth anode connecting line.

[0342] In the exemplary embodiment, multiple connecting electrodes serve as a support, which can avoid the unreliability of the connection caused by opening deep vias and improve the reliability of the display panel.

[0343] (10) Forming a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, patterning the second planarization film using a patterning process to form a second planarization layer covering a fourth conductive layer, wherein a plurality of vias are provided on the second planarization layer, such as... Figure 16O As shown, where, Figure 16O for Figure 13 A schematic diagram showing the formation of the second flattened layer pattern in the provided light-transmitting display area.

[0344] In an exemplary implementation, such as Figure 16OAs shown, the multiple vias in the second planarization layer pattern may each include: via 39 V39 to via 46 V46. Specifically, via 39 V39 exposes the 13th connecting electrode, via 40 V40 exposes the 14th connecting electrode, via 41 V41 exposes the 15th connecting electrode, via 42 V42 exposes the 16th connecting electrode, via 43 V43 exposes the 17th connecting electrode, via 44 V44 exposes the 18th connecting electrode, via 45 V45 exposes the 19th connecting electrode, and via 46 V46 exposes the 20th connecting electrode.

[0345] At this point, the driving circuit layer is fabricated on the substrate. On a plane parallel to the display substrate, the driving circuit layer may include multiple first-type pixel circuits, scan signal lines, reset signal lines, light-emitting signal lines, data signal lines, initial signal lines, and first to fourth anode connection lines. On a plane perpendicular to the display panel, the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer, sequentially stacked on the substrate.

[0346] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0347] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0348] In an exemplary embodiment, the transparent conductive layer may be made of materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may be a multilayer composite structure such as ITO / Ag / ITO.

[0349] In exemplary embodiments, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer, the second insulating layer can be called a gate insulating (GI) layer, the third insulating layer can be called an interlayer insulating (ILD) layer, and the fourth insulating layer can be called a passivation (PVX) layer. The first and second planarization layers can be made of organic materials, such as resins. The semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc., meaning this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0350] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0351] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on a second planarization layer, such as... Figure 16P and 16Q As shown, Figure 16P for Figure 13 A schematic diagram of the anode conductive layer pattern in the light-transmitting display area is provided. Figure 16Q for Figure 13 A schematic diagram showing the formation of the anodic conductive layer pattern in the provided light-transmitting display area.

[0352] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0353] In an exemplary embodiment, Figure 16P The provided anode conductive layer pattern and Figure 15P The provided anode conductive layer pattern is the same, so it will not be described again here.

[0354] In an exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the thirteenth connecting electrode through the thirty-ninth via, the anode of the first light-emitting element 11b is electrically connected to the nineteenth connecting electrode through the forty-fifth via, the anode of the second light-emitting element 12a is electrically connected to the fourteenth connecting electrode through the fortieth via, the anode of the second light-emitting element 12b is electrically connected to the twentieth connecting electrode through the forty-sixth via, the anode of the third light-emitting element 13a is electrically connected to the fifteenth connecting electrode through the forty-first via, the anode of the third light-emitting element 13b is electrically connected to the sixteenth connecting electrode through the forty-second via, the anode of the third light-emitting element 13c is electrically connected to the seventeenth connecting electrode through the forty-third via, and the anode of the third light-emitting element 13d is electrically connected to the eighteenth connecting electrode through the forty-fourth via.

[0355] In an exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the anode of the first light-emitting element 11b via a thirteenth connecting electrode, a first anode connecting line, a ninth connecting electrode, an eleventh connecting electrode, and a nineteenth connecting electrode. The anode of the second light-emitting element 12a is electrically connected to the anode of the second light-emitting element 12b via a fourteenth connecting electrode, a second anode connecting line, a tenth connecting electrode, a twelfth connecting electrode, and a twentieth connecting electrode. The anode of the third light-emitting element 13a is electrically connected to the anode of the third light-emitting element 13b via a fifteenth connecting electrode, a third anode connecting line, and a sixteenth connecting electrode. The anode of the third light-emitting element 13c is electrically connected to the anode of the third light-emitting element 13d via a seventeenth connecting electrode, a fourth anode connecting line, and an eighteenth connecting electrode.

[0356] In an exemplary embodiment, the subsequent fabrication process may include: first forming a pixel definition layer pattern, then forming an organic light-emitting layer using vapor deposition or inkjet printing, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0357] In an exemplary embodiment Figure 14 The fabrication process of the provided light-transmitting display area may include the following operations.

[0358] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film using a patterning process to form a semiconductor layer pattern, such as... Figure 17A As shown, Figure 17A for Figure 14 A schematic diagram showing the semiconductor pattern formed in the provided light-transmitting display area.

[0359] In an exemplary embodiment Figure 17A The provided semiconductor layer pattern and Figure 15A The provided semiconductor layer pattern is the same, so it will not be described again here.

[0360] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, such as... Figure 17B and Figure 17C As shown, where, Figure 17B for Figure 14 A schematic diagram of the pattern of the first conductive layer in the light-transmitting display area is provided. Figure 17C for Figure 14 This is a schematic diagram showing the light-transmitting display area after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0361] In an exemplary embodiment Figure 17B and Figure 17C The provided first conductive layer pattern and Figure 15B and Figure 15C The pattern of the first conductive layer provided is the same, and will not be described again here.

[0362] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on a substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the second insulating layer. Figure 17D and Figure 17E As shown, Figure 17D for Figure 14 A schematic diagram of the pattern of the second conductive layer in the light-transmitting display area is provided. Figure 17E for Figure 14 This is a schematic diagram showing the formation of the second conductive layer pattern in the provided light-transmitting display area. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0363] In an exemplary embodiment Figure 17D and Figure 17E The pattern of the provided second conductive layer is consistent with Figure 15D and Figure 15E The pattern of the second conductive layer is the same, and will not be described again here.

[0364] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein the third insulating layer has a plurality of vias, such as... Figure 17F As shown, where, Figure 17F for Figure 14 A schematic diagram showing the formation of the third insulating layer pattern in the provided light-transmitting display area.

[0365] In an exemplary implementation, such as Figure 17F The provided third insulating layer pattern and Figure 15F The pattern of the third insulating layer is the same, so it will not be described again here.

[0366] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on a third insulating layer. Figures 17G to 17H As shown, Figure 17G for Figure 14 A schematic diagram of the pattern of the third conductive layer in the light-transmitting display area is provided. Figure 17H for Figure 14 This is a schematic diagram showing the formation of the third conductive layer pattern in the provided light-transmitting display area. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0367] In an exemplary implementation, such as Figure 17G and Figure 17H As shown, the third conductive layer pattern may include: the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the second connecting electrode VL2 to the twelfth connecting electrode VL12, and the shielding electrode SL.

[0368] In an exemplary implementation, such as Figure 17G and Figure 17H The provided first transistor has a first electrode T13 and a second electrode T14, the second transistor has a first electrode T23, the fourth transistor has a first electrode T43, the fifth transistor has a first electrode T53, the sixth transistor has a second electrode T64, the seventh transistor has a first electrode T73 and a second electrode T74, the second connecting electrode VL2 to the eighth connecting electrode VL8, and a shielding electrode. Figure 15G and 15HThe first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the second connecting electrode VL2 to the eighth connecting electrode VL8, and the shielding electrode SL have the same pattern, and will not be described again here.

[0369] In an exemplary implementation, such as Figure 17G and Figure 17H As shown, the ninth connecting electrode VL9 and the twelfth connecting electrode VL12 extend along the second direction X, and at least a portion of the tenth connecting electrode VL10 and the eleventh connecting electrode VL11 extend along the second direction X.

[0370] (6) Forming a fourth insulating layer. In an exemplary embodiment, forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein the fourth insulating layer has a plurality of vias, such as... Figure 17I As shown. Figure 17I for Figure 14 A schematic diagram showing the formation of the fourth insulating layer pattern in the provided light-transmitting display area.

[0371] In an exemplary implementation, such as Figure 17I As shown, the multiple vias in the fourth insulating layer pattern may all include: the seventeenth via V17 to the thirty-second via V32. Figure 17I The seventeenth via V17 to the twenty-eighth via V28 in the middle Figure 15I The seventeenth via V17 to the twenty-eighth via V28 are the same, except that the twenty-ninth via V29 exposes the ninth connecting electrode, the thirtieth via V30 exposes the tenth connecting electrode, the thirty-first via V31 exposes the eleventh connecting electrode, and the thirty-second via V32 exposes the twelfth connecting electrode.

[0372] In an exemplary embodiment, there may be two 29th vias V29, which may be arranged along the second direction X and located at both ends of the ninth connecting electrode.

[0373] In an exemplary embodiment, there may be two thirtieth vias V30, which may be arranged along the second direction X and located at both ends of the tenth connecting electrode.

[0374] In an exemplary embodiment, there may be two thirty-first vias V31, which may be arranged along the second direction X and located at both ends of the eleventh connecting electrode.

[0375] In an exemplary embodiment, there may be two thirtieth-second vias V32, which may be arranged along the second direction X and located at both ends of the twelfth connecting electrode.

[0376] (7) Forming a transparent conductive layer pattern. In an exemplary embodiment, forming a transparent conductive layer pattern may include: depositing a transparent conductive film on a substrate on which the aforementioned pattern is formed, patterning the transparent conductive film using a patterning process, and forming a transparent conductive layer disposed on a fourth insulating layer, such as... Figure 17J and Figure 17K As shown, Figure 17J for Figure 14 A schematic diagram of the transparent conductive layer pattern in the light-transmitting display area is provided. Figure 17K for Figure 14 A schematic diagram showing the formation of a transparent conductive layer pattern in the provided light-transmitting display area.

[0377] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the transparent conductive layer pattern may include: a data signal line Data, a first power supply line VDD, a first anode connection line AL1, a second anode connection line AL2, a third anode connection line AL3, two sub-signal lines INIT_1 and INIT_2 of the initial signal line, two sub-signal lines RST_1 and RST_2 of the reset signal line, two sub-signal lines Gate_1 and Gate_2 of the scan signal line, two sub-signal lines EM_1 and EM_2 of the light emission signal line, and thirteenth connecting electrodes VL13 to seventeenth connecting electrodes VL17.

[0378] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the data signal line Data and the first power line VDD can be located between two sub-signal lines of a plurality of first signal lines electrically connected to a first type pixel circuit electrically connected to the data signal line Data and the first power line VDD, and their orthogonal projections on the substrate overlap with the orthogonal projections of the first type pixel circuit on the substrate.

[0379] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the data signal line Data can be linear, at least a portion of the data signal line Data can extend along the first direction Y, and adjacent first type pixel circuits in the same column can be the same signal line. The data signal line is electrically connected to the first pole of the fourth transistor of the electrically connected first type pixel circuit through the eighteenth via.

[0380] In an exemplary implementation, such as Figure 17J and Figure 17KAs shown, the first power line VDD can be linear, at least a portion of the first power line VDD can extend along the first direction Y, and the first power lines VDD of adjacent first type pixel circuits in the same column can be spaced apart. The first power line is electrically connected to the first electrode of the fifth transistor of the first type pixel circuit through the nineteenth via, and electrically connected to the shielding electrode through the twenty-eighth via.

[0381] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the first anode connection line AL1 to the fourth anode connection line AL4 are broken lines.

[0382] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the first anode connection line AL1 is located between the first power line VDD of the first type pixel circuit and the data signal line Data of the adjacent column of the first type pixel circuit. At least a portion of the first anode connection line AL1 can extend along the second direction X. The first anode connection line AL1 is electrically connected to the second electrode of the sixth transistor of the first type pixel circuit through the twentieth via and electrically connected to the tenth connection electrode through the thirtieth via.

[0383] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the second anode connection line AL2 is located between the first power line VDD of the first type pixel circuit and the data signal line Data of the adjacent column of the first type pixel circuit. At least a portion of the second anode connection line AL2 can extend along the second direction X. The second anode connection line AL2 is electrically connected to the second electrode of the sixth transistor of the first type pixel circuit through the twentieth via and electrically connected to the ninth connection electrode through the twentieth-ninth via.

[0384] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the third anode connection line AL3 is located between the first power line VDD of the first type pixel circuit electrically connected and the data signal line Data of the adjacent first type pixel circuit electrically connected in the same row, and at least a portion of the third anode connection line AL3 can extend along the first direction Y. The third anode connection line AL3 is electrically connected to the twelfth connection electrode through the thirty-second via.

[0385] In an exemplary implementation, such as Figure 17J and Figure 17KAs shown, the two sub-signal lines INIT_1 and INIT_2 of the initial signal line can be zigzag-shaped. At least a portion of the two sub-signal lines INIT_1 and INIT_2 can extend along the first direction Y. Sub-signal line INIT_1 is electrically connected to the eighth connection electrode through the twenty-seventh via, and sub-signal line INIT_2 is electrically connected to the first electrode of the first transistor through the seventeenth via. Sub-signal line INIT_1 is electrically connected to the first connection electrode through the eighth connection electrode. Sub-signal line INIT_2 is electrically connected to the first connection electrode through the first electrode of the first transistor.

[0386] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the two sub-signal lines RST_1 and RST_2 of the reset signal line can be zigzag-shaped. At least a portion of the two sub-signal lines RST_1 and RST_2 can extend along the second direction Y. Sub-signal line RST_1 is electrically connected to the second connection electrode through a twenty-first via, and sub-signal line RST_2 is electrically connected to the third connection electrode through a twenty-second via. Sub-signal line RST_1 is electrically connected to the control electrode of the first transistor through the second connection electrode, and sub-signal line RST_2 is electrically connected to the control electrode of the first transistor through the third connection electrode.

[0387] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the two sub-signal lines Gate_1 and Gate_2 of the scan signal line can be zigzag-shaped. At least a portion of the two sub-signal lines Gate_1 and Gate_2 can extend along the second direction Y. Sub-signal line Gate_1 is electrically connected to the fourth connection electrode through the twenty-third via, and sub-signal line Gate_2 is electrically connected to the fifth connection electrode through the twenty-fourth via. Sub-signal line Gate_1 is electrically connected to the control electrode of the fourth transistor through the fourth connection electrode, and sub-signal line Gate_2 is electrically connected to the control electrode of the fourth transistor through the fifth connection electrode.

[0388] In an exemplary implementation, such as Figure 17J and Figure 17KAs shown, the two sub-signal lines EM_1 and EM_2 of the initial light-emitting signal line can be zigzag-shaped. At least a portion of the two sub-signal lines EM_1 and EM_2 can extend along the second direction Y. Sub-signal line EM_1 is electrically connected to the sixth connecting electrode through the twenty-fifth via, and sub-signal line EM_2 is electrically connected to the seventh connecting electrode through the twenty-sixth via. Sub-signal line EM_1 is electrically connected to the control electrode of the fifth transistor through the sixth connecting electrode, and sub-signal line EM_2 is electrically connected to the control electrode of the fifth transistor through the seventh connecting electrode.

[0389] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the thirteenth connecting electrode VL13 is electrically connected to the tenth connecting electrode through the thirtieth via, and is electrically connected to the eleventh connecting electrode through the thirty-first via.

[0390] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the fourteenth connecting electrode VL14 is electrically connected to the eleventh connecting electrode through the thirty-first via. The thirteenth connecting electrode is electrically connected to the fourteenth connecting electrode through the first anode connecting line, the tenth connecting electrode, the thirteenth connecting electrode, and the eleventh connecting electrode.

[0391] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the fifteenth connecting electrode VL15 is electrically connected to the second electrode of the sixth transistor of the first type pixel circuit through the twentieth via.

[0392] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the sixteenth connecting electrode VL16 is electrically connected to the ninth connecting electrode through the twenty-ninth via. The sixteenth connecting electrode is electrically connected to the second anode connecting line AL2 through the ninth connecting electrode.

[0393] In an exemplary implementation, such as Figure 17J and Figure 17K As shown, the seventeenth connecting electrode VL17 is electrically connected to the twelfth connecting electrode through the thirty-second via. The seventeenth connecting electrode VL17 is also electrically connected to the third anode connecting line AL3 through the twelfth connecting electrode.

[0394] (8) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: depositing a first planarization film on a substrate on which the aforementioned pattern is formed to form a first planarization layer pattern disposed on a transparent conductive layer, the first planarization layer pattern including a plurality of vias, such as... Figure 17L As shown, Figure 17L for Figure 14 A schematic diagram showing the light-transmitting display area after the first flat layer has been formed.

[0395] In an exemplary implementation, such as Figure 17L As shown, the first planarization layer pattern may include: a 33rd via V33 and a 40th via V40. Specifically, the 33rd via V33 exposes the first power line, the 34th via V34 exposes the first anode connection line, the 35th via V35 exposes the 14th connection electrode, the 36th via V36 exposes the 16th connection electrode, the 37th via V37 exposes the second anode connection line, the 38th via V38 exposes the 15th connection electrode, the 39th via V39 exposes the third anode connection line, and the 40th via V40 exposes the 17th connection electrode.

[0396] (9) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first planarization layer, such as... Figure 17M and Figure 17N As shown, Figure 17M for Figure 14 A schematic diagram of the fourth conductive layer pattern in the light-transmitting display area is provided. Figure 17N for Figure 14 This is a schematic diagram showing the formation of the fourth conductive layer pattern in the provided light-transmitting display area. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0397] In an exemplary implementation, such as Figure 17M and Figure 17N As shown, the fourth conductive layer pattern may include: eighteenth connecting electrode VL18 to twenty-third connecting electrode VL23 and signal connection line VDL.

[0398] In an exemplary implementation, such as Figure 17M and Figure 17N As shown, the eighteenth connecting electrode VL18 to the twenty-first connecting electrode VL21 and the twenty-third connecting electrode VL23 are block structures. The twenty-second connecting electrode VL22 is a horizontally flipped "7" shape. The signal connection line VDL can be a broken line, and at least a portion of the signal connection line VDL can extend along the first direction Y.

[0399] In an exemplary implementation, such as Figure 17M and Figure 17N As shown, the signal connection line VDL is electrically connected to the first power line through the thirty-third via.

[0400] In an exemplary implementation, such as Figure 17M and Figure 17NAs shown, the eighteenth connecting electrode VL18 is electrically connected to the fourteenth connecting electrode through the thirty-fifth via; the nineteenth connecting electrode VL19 is electrically connected to the first anode connecting line through the thirty-fourth via; the twentieth connecting electrode VL20 is electrically connected to the sixteenth connecting electrode through the thirty-sixth via; the twenty-first connecting electrode VL21 is electrically connected to the second anode connecting line through the thirty-seventh via; the twenty-second connecting electrode VL22 is electrically connected to the fifteenth connecting electrode through the thirty-eighth via and to the third anode connecting line through the thirty-ninth via; and the twenty-third connecting electrode VL23 is electrically connected to the seventeenth connecting electrode through the fortieth via.

[0401] In an exemplary embodiment, the first power line of the first type of pixel circuit located in the same column is electrically connected via the signal connection line VDL.

[0402] In an exemplary embodiment, such as Figure 17N As shown, the eighteenth connecting electrode VL18 is electrically connected to the nineteenth connecting electrode VL19 through the fourteenth connecting electrode, the eleventh connecting electrode, the thirteenth connecting electrode, the tenth connecting electrode and the first anode connecting line; the twentieth connecting electrode VL20 is electrically connected to the twenty-first connecting electrode VL21 through the sixteenth connecting electrode, the ninth connecting electrode and the first anode connecting line; and the twenty-second connecting electrode VL22 is electrically connected to the twenty-third connecting electrode VL23 through the third anode connecting line, the twelfth connecting electrode and the seventeenth connecting electrode.

[0403] In the exemplary embodiment, multiple connecting electrodes serve as a support, which can avoid the unreliability of the connection caused by opening deep vias and improve the reliability of the display panel.

[0404] (10) Forming a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, patterning the second planarization film using a patterning process to form a second planarization layer covering a fourth conductive layer, wherein a plurality of vias are provided on the second planarization layer, such as... Figure 17O As shown, where, Figure 17O for Figure 14 A schematic diagram showing the formation of the second flattened layer pattern in the provided light-transmitting display area.

[0405] In an exemplary implementation, such as Figure 17OAs shown, the multiple vias in the second planarization layer pattern may each include: via 41 to via 46. Specifically, via 41 V41 exposes the 18th connecting electrode, via 42 V42 exposes the 19th connecting electrode, via 43 V43 exposes the 20th connecting electrode, via 44 V44 exposes the 21st connecting electrode, via 45 V45 exposes the 22nd connecting electrode, and via 46 V46 exposes the 23rd connecting electrode.

[0406] At this point, the driving circuit layer is fabricated on the substrate. On a plane parallel to the display substrate, the driving circuit layer may include multiple first-type pixel circuits, scan signal lines, reset signal lines, light-emitting signal lines, data signal lines, initial signal lines, and first to fourth anode connection lines. On a plane perpendicular to the display panel, the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer, sequentially stacked on the substrate.

[0407] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0408] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0409] In an exemplary embodiment, the transparent conductive layer may be made of materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may be a multilayer composite structure such as ITO / Ag / ITO.

[0410] In exemplary embodiments, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer, the second insulating layer can be called a gate insulating (GI) layer, the third insulating layer can be called an interlayer insulating (ILD) layer, and the fourth insulating layer can be called a passivation (PVX) layer. The first and second planarization layers can be made of organic materials, such as resins. The semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc., meaning this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0411] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0412] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on a second planarization layer, such as... Figure 17P and 16Q As shown, Figure 17P for Figure 14 A schematic diagram of the anode conductive layer pattern in the light-transmitting display area is provided. Figure 17Q for Figure 14 A schematic diagram showing the formation of the anodic conductive layer pattern in the provided light-transmitting display area.

[0413] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0414] In an exemplary embodiment, the anode of the first light-emitting element 11b is electrically connected to the eighteenth connecting electrode through the forty-first via, the anode of the first light-emitting element 11a is electrically connected to the nineteenth connecting electrode through the forty-second via, the anode of the second light-emitting element 12b is electrically connected to the twentieth connecting electrode through the forty-third via, the anode of the second light-emitting element 12a is electrically connected to the twenty-first connecting electrode through the forty-fourth via, the anode of the third light-emitting element 13a is electrically connected to the twenty-second connecting electrode through the forty-fifth via, and the anode of the third light-emitting element 13b is electrically connected to the twenty-third connecting electrode through the forty-sixth via.

[0415] In an exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the anode of the first light-emitting element 11b via the eighteenth, fourteenth, eleventh, thirteenth, and tenth connecting electrodes, the first anode connecting line, and the nineteenth connecting electrode. The anode of the second light-emitting element 12a is electrically connected to the anode of the second light-emitting element 12b via the twentieth, sixteenth, and ninth connecting electrodes, the first anode connecting line, and the twenty-first connecting electrode. The anode of the third light-emitting element 13a is electrically connected to the anode of the third light-emitting element 13b via the twenty-second connecting electrode VL22, the third anode connecting line, the twelfth connecting electrode, the seventeenth connecting electrode, and the twenty-third connecting electrode VL23.

[0416] In an exemplary embodiment, the subsequent fabrication process may include: first forming a pixel definition layer pattern, then forming an organic light-emitting layer using vapor deposition or inkjet printing, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0417] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0418] In exemplary embodiments, the display panel of this disclosure can be applied to display devices with pixel circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0419] Figure 18 This is a schematic diagram of the structure of the display device provided in the embodiments of this disclosure. Figure 19 for Figure 18 Cross-sectional view along direction AA. (See attached image.) Figure 18 and Figure 19 As shown, this disclosure also provides a display device, which includes a display substrate 1 and a photosensor 2 provided in any of the foregoing embodiments. The photosensor is located in the light-transmitting display area A1 of the display substrate 1 and is located on the side away from the light-emitting side of the display substrate 1.

[0420] In exemplary embodiments, the display substrate can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be any product or component with display function, such as an OLED display, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments disclosed herein are not limited thereto.

[0421] In an exemplary embodiment, when the light-transmitting display area A1 is rectangular, the orthographic projection area of ​​the photosensitive sensor 2 on the substrate is less than or equal to the area of ​​the inscribed circle of the light-transmitting display area A1.

[0422] In an exemplary embodiment, the photosensitive sensor 2 may include at least one of a camera module (e.g., a front-facing camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), and an infrared sensing module (e.g., an infrared sensing sensor).

[0423] In an exemplary embodiment, the front-facing camera module is typically activated when the user takes a selfie or makes a video call, and the display area of ​​the display device displays the image obtained from the selfie for the user to view. The front-facing camera module includes, for example, a lens, an image sensor, and an image processing chip. An optical image of the scene generated by the lens is projected onto the surface of the image sensor (image sensors include CCD and CMOS), converted into an electrical signal, and then converted into a digital image signal by the image processing chip. This digital signal is then processed by the processor and output as an image of the scene on the display screen.

[0424] In an exemplary embodiment, a 3D structured light sensor and a Time of Flight (ToF) sensor can be used for facial recognition to unlock a display device.

[0425] The display device provided in this disclosure embodiment can display images in the light-transmitting display area to maintain the display integrity of the entire display device.

[0426] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0427] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0428] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The display area includes a display area and a peripheral area at least partially surrounding the display area. The display area includes a light-transmitting display area and a conventional display area located on at least one side of the light-transmitting display area. The light transmittance of the light-transmitting display area is greater than the light transmittance of the conventional display area. The display substrate includes: a substrate and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the substrate, a plurality of first signal lines and a plurality of second signal lines. The first signal lines include a plurality of sub-signal lines. The plurality of light-emitting elements include a plurality of first-type light-emitting elements located in the light-transmitting display area. The plurality of pixel circuits include a plurality of first-type pixel circuits located in the light-transmitting display area. At least one of the plurality of first-type pixel circuits is electrically connected to at least two first-type light-emitting elements that emit light of the same color. The first-type pixel circuit is configured to drive the at least two first-type light-emitting elements to emit light. The orthographic projection of the at least one first-type pixel circuit on the substrate overlaps with the orthographic projection of the at least one first-type light-emitting element on the substrate; The at least one first-type pixel circuit is electrically connected to at least one first signal line and at least one second signal line. The plurality of first signal lines include at least one of the following: a scan signal line, a reset signal line, an initial signal line, and a light emission signal line. The plurality of second signal lines include at least one of the following: a data signal line and a first power supply line. The plurality of first signal lines and the plurality of second signal lines are located in the same film layer. The data signal line and the first power line electrically connected to the first type of pixel circuit are located between adjacent sub-signal lines of the first signal line, and the orthographic projection of the data signal line and the first power line electrically connected to the first type of pixel circuit on the substrate overlaps with the orthographic projection of the first type of pixel circuit on the substrate. 2.The display substrate of claim 1, wherein, The orthographic projection of the at least one first-type pixel circuit on the substrate and the orthographic projection of at least a portion of the first-type light-emitting elements electrically connected to the at least one first-type pixel circuit on the substrate overlap. 3.The display substrate of claim 2, wherein, The adjacent sub-signal lines of the first signal line are electrically connected through the first type of pixel circuit. 4.The display substrate according to claim 2 or 3, wherein, The plurality of data signal lines and the plurality of the first power lines extend along a first direction. 5.The display substrate of claim 4, wherein, The orthographic projection of at least one of the scan signal line, the reset signal line, the initial signal line, the light emission signal line, the data signal line, and the first power line onto the substrate overlaps with the orthographic projection portion of the first type of light emission element onto the substrate. 6.The display substrate of claim 5, wherein, The plurality of first-type light-emitting elements include at least: a plurality of first-type light-emitting elements emitting a first-color light, a plurality of second-type light-emitting elements emitting a second-color light, and a plurality of third-type light-emitting elements emitting a third-color light; The anode area of ​​at least one of the plurality of first light-emitting elements is greater than the anode area of ​​at least one of the plurality of third light-emitting elements; the anode area of ​​at least one of the plurality of second light-emitting elements is greater than the anode area of ​​at least one of the plurality of third light-emitting elements; and the anode area of ​​at least one of the plurality of second light-emitting elements is greater than the anode area of ​​at least one of the plurality of first light-emitting elements. The first color light is red light, the second color light is blue light, and the third color light is green light. 7.The display substrate of claim 6, wherein, The first type of pixel circuit includes: a plurality of transistors and at least one capacitor; in a direction perpendicular to the display substrate, the light-transmitting display area includes at least: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer disposed on the substrate. The semiconductor layer includes at least: an active layer of a plurality of transistors of the first type of pixel circuit; The first conductive layer includes at least: the control electrodes of a plurality of transistors of the first type of pixel circuit and the first plate of a capacitor; The second conductive layer includes at least: the second plate of the capacitor of the first type of pixel circuit; The third conductive layer includes at least: the first and second electrodes of a plurality of transistors of the first type of pixel circuit and a plurality of connection electrodes; The transparent conductive layer includes at least: a plurality of anode connection lines, at least one of the plurality of anode connection lines being electrically connected to the anode of at least one first type pixel circuit and at least two first type light-emitting elements emitting light of the same color; The fourth conductive layer includes at least a plurality of signal connection lines. 8.The display substrate of claim 7, wherein, The plurality of first-type light-emitting elements are arranged in the following manner: The plurality of third light-emitting elements are arranged at certain intervals in the i-th row, the second light-emitting elements and the first light-emitting elements are alternately arranged in adjacent rows of the i-th row, the first light-emitting elements and the second light-emitting elements are alternately arranged in the j-th column, the plurality of third light-emitting elements are arranged at certain intervals in adjacent columns of the j-th column, the first light-emitting elements and the third light-emitting elements are alternately arranged along a third direction, the second light-emitting elements and the third light-emitting elements are alternately arranged along a fourth direction, the third direction and the fourth direction intersect the first direction and the second direction respectively, the first direction is the column direction and the second direction is the row direction. 9.The display substrate of claim 8, wherein, The plurality of first-type pixel circuits include: at least one first pixel circuit, at least one second pixel circuit, at least one third pixel circuit, and at least one fourth pixel circuit; the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements, the third pixel circuit is electrically connected to two third light-emitting elements, and the fourth pixel circuit is electrically connected to two third light-emitting elements, wherein the third light-emitting elements electrically connected to the third pixel circuit and the fourth pixel circuit are different. 10.The display substrate of claim 9, wherein, The two first light-emitting elements electrically connected to the first pixel circuit are located in the same row, the two second light-emitting elements electrically connected to the second pixel circuit are located in the same row, the two third light-emitting elements electrically connected to the third pixel circuit are located in the same row, and the two third light-emitting elements electrically connected to the fourth pixel circuit are located in the same row. 11.The display substrate of claim 10, wherein, The orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected first light-emitting element on the substrate; The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection of the first light-emitting element on the substrate, which is located between the two electrically connected second light-emitting elements; The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of the second light-emitting element on the substrate. The second light-emitting element overlapping with the third pixel circuit is located in the adjacent row of the two rows of the third light-emitting elements electrically connected by the third pixel circuit, and is located in the middle column of the two columns of the third light-emitting elements electrically connected by the third pixel circuit. The orthographic projection of the fourth pixel circuit on the substrate overlaps with the orthographic projection of the second light-emitting element on the substrate. The second light-emitting element overlapping with the fourth pixel circuit is located in the adjacent row of the row containing the two third light-emitting elements electrically connected to the fourth pixel circuit, and is located in the middle column of the column containing the two third light-emitting elements electrically connected to the fourth pixel circuit. The second light-emitting element overlapping with the third pixel circuit and the second light-emitting element overlapping with the fourth pixel circuit are different light-emitting elements. 12.The display substrate according to any one of claims 9 to 11, wherein The anode connection line includes: a first anode connection line, a second anode connection line, a third anode connection line, and a fourth anode connection line; The first anode connection line is electrically connected to the first pixel circuit and the first light-emitting element, and at least a portion of the first anode connection line extends along the second direction; the second anode connection line is electrically connected to the second pixel circuit and the second light-emitting element, and at least a portion of the second anode connection line extends along the second direction; the third anode connection line is electrically connected to the third pixel circuit and the third light-emitting element, and at least a portion of the third anode connection line extends along the second direction, and the third anode connection line is located between the data signal line and the first power line electrically connected to the third pixel circuit; the fourth anode connection line is electrically connected to the fourth pixel circuit and the third light-emitting element, and at least a portion of the fourth anode connection line extends along the second direction, and the fourth anode connection line is located between the data signal line and the first power line electrically connected to the fourth pixel circuit. 13.The display substrate of claim 12, wherein, The first power lines of at least two adjacent first type pixel circuits in the same column are spaced apart, and the spaced first power lines in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer. At least two adjacent first-type pixel circuits in the same column are electrically connected by data signal lines spaced apart, and the spaced data signal lines in the same column are electrically connected by at least one signal connection line located in the fourth conductive layer.

14. The display substrate according to claim 9, wherein, The two first light-emitting elements electrically connected to the first pixel circuit are arranged along a third direction, the two second light-emitting elements electrically connected to the second pixel circuit are arranged along a fourth direction, the two third light-emitting elements electrically connected to the third pixel circuit are located in the same column, and the two third light-emitting elements electrically connected to the fourth pixel circuit are located in the same column.

15. The display substrate according to claim 14, wherein, The orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected first light-emitting element on the substrate; The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected second light-emitting element on the substrate; The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected third light-emitting element on the substrate. The orthographic projection of the fourth pixel circuit on the substrate overlaps with the orthographic projection of a third light-emitting element electrically connected to the substrate. The third light-emitting element overlapping with the third pixel circuit and the third light-emitting element overlapping with the fourth pixel circuit are different light-emitting elements.

16. The display substrate according to claim 14 or 15, wherein, The anode connection line includes: a first anode connection line, a second anode connection line, a third anode connection line, and a fourth anode connection line; The first anode connection line is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connection line extends along the first direction; the second anode connection line is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connection line extends along the first direction; the third anode connection line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connection line extends along the first direction, and the third anode connection line is located on the side of the first power line electrically connected to the third pixel circuit away from the data signal line; the fourth anode connection line is electrically connected to the fourth pixel circuit and the third light-emitting element, respectively, and at least a portion of the fourth anode connection line extends along the first direction, and the fourth anode connection line is located on the side of the first power line electrically connected to the fourth pixel circuit away from the data signal line.

17. The display substrate according to claim 16, wherein, The data signal lines of the first type pixel circuits electrically connected in the same column are the same signal lines. The first power lines of at least two adjacent first type pixel circuits electrically connected in the same column are spaced apart, and the spaced first power lines in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.

18. The display substrate according to claim 17, wherein, The transparent conductive layer further includes: a power connection line, at least a portion of which extends along a second direction; The power connection line is electrically connected to the first power line that is electrically connected to two adjacent first type pixel circuits located in the same row. The first power line and the power connection line are electrically connected through the connection electrode located in the third conductive layer.

19. The display substrate according to claim 18, wherein, For the same first type of pixel circuit, the first power line includes: a power body portion extending along the first direction and a power connection portion extending along the second direction, wherein the power connection portion is located on the side of the power body portion away from the data signal line; The power connection line is electrically connected to the power connection part of one of the first type pixel circuits and the power body part of the other first type pixel circuit in the same row.

20. The display substrate according to claim 8, wherein, The plurality of first-type light-emitting elements are arranged in the following manner: The plurality of second light-emitting elements are arranged in the j-th column, the first light-emitting element and the third light-emitting element are alternately arranged in adjacent columns of the j-th column, the plurality of second light-emitting elements are arranged in the i-th row, and the first light-emitting element and the third light-emitting element are arranged between adjacent second light-emitting elements in the same row.

21. The display substrate according to claim 20, wherein, The plurality of first-type pixel circuits include: at least one first pixel circuit, at least one second pixel circuit, and at least one third pixel circuit; the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements, and the third pixel circuit is electrically connected to two third light-emitting elements.

22. The display substrate according to claim 21, wherein, The two first light-emitting elements electrically connected to the first pixel circuit are located in the same row, the two second light-emitting elements electrically connected to the second pixel circuit are located in the same row, and the two third light-emitting elements electrically connected to the third pixel circuit are located in the same row.

23. The display substrate according to claim 22, wherein, The orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected first light-emitting element on the substrate; The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected second light-emitting element on the substrate; The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of an electrically connected third light-emitting element on the substrate.

24. The display substrate according to claim 23, wherein, At least two of the first light-emitting elements overlapping in the first pixel circuit, the second light-emitting elements overlapping in the second pixel circuit, and the third light-emitting elements overlapping in the third pixel circuit are adjacent to each other.

25. The display substrate according to claim 22, wherein, The orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected first light-emitting element on the substrate; The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected second light-emitting element on the substrate; The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of the second light-emitting element on the substrate located between the two third light-emitting elements electrically connected to the third pixel circuit.

26. The display substrate according to claim 22, wherein, The orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection portion of the second light-emitting element located between the two first light-emitting elements electrically connected to the first pixel circuit on the substrate; The orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection portion of an electrically connected second light-emitting element on the substrate; The orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of an electrically connected third light-emitting element on the substrate.

27. The display substrate according to any one of claims 22 to 26, wherein, The anode connection line includes: a first anode connection line, a second anode connection line, and a third anode connection line; The first anode connection line is electrically connected to the first pixel circuit and the first light-emitting element, and at least a portion of the first anode connection line extends along the second direction; the second anode connection line is electrically connected to the second pixel circuit and the second light-emitting element, and at least a portion of the second anode connection line extends along the second direction; the third anode connection line is electrically connected to the third pixel circuit and the third light-emitting element, and at least a portion of the third anode connection line extends along the second direction.

28. The display substrate according to claim 27, wherein, The data signal lines of the first type pixel circuits electrically connected in the same column are the same signal lines. The first power lines of at least two adjacent first type pixel circuits electrically connected in the same column are spaced apart, and the spaced first power lines in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.

29. The display substrate according to claim 1, wherein, The plurality of light-emitting elements further includes a plurality of second-type light-emitting elements located in the conventional display area, and the plurality of pixel circuits further includes a plurality of second-type pixel circuits located in the conventional display area; At least one of the plurality of second-type light-emitting elements and at least one of the plurality of second-type pixel circuits are electrically connected, and the orthographic projection of the second-type light-emitting element on the substrate and the orthographic projection of the electrically connected second-type pixel circuit on the substrate overlap.

30. A display device comprising a display substrate as claimed in any one of claims 1 to 29.

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