Resource allocation method, processor and electronic device

Abstract

A resource allocation method, a processor and an electronic device. The resource allocation method is applied to a processor, the processor is configured to execute multiple threads concurrently, the processor includes a microinstruction cache, and the method includes: detecting the number of core instructions of each of the multiple threads, the instructions of each thread include core instructions and non-core instructions, and the importance of the core instructions is greater than the importance of the non-core instructions; and regulating the allocation of resources of the microinstruction cache according to the number of core instructions of each thread. The method can at least partially solve the problem of low microinstruction cache resource utilization caused by competition between multiple threads for microinstruction cache resources, and improve the utilization of microinstruction cache resources.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a resource allocation method, a processor, and an electronic device. Background Art

[0002] Traditional processors (CPUs) can only process one instruction sequence at a time, usually called a thread. During the thread processing, the CPU processing unit needs to continuously call in instructions and data for processing. With the development of CPU technology, the CPU's main frequency and performance continue to improve, and the speed of calling in instructions and data continues to increase. Unfortunately, the development of memory technology has not kept up with the speed of CPU development, and the memory usually cannot provide enough instructions and data for the CPU to process.

[0003] In order to improve the utilization of the CPU processing unit, thread-level parallel technology is proposed, that is, executing more than one instruction sequence in the core of the CPU. For the operating system, a physical processor is equivalent to multiple logical processors, realizing multi-threading technology. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a resource allocation method, which is applied to a processor, wherein the processor is configured to execute multiple threads concurrently, and the processor includes a microinstruction cache. The method includes: detecting the number of core instructions of each of the multiple threads, the instructions of each thread include the core instructions and non-core instructions, and the importance of the core instructions is greater than the importance of the non-core instructions; and regulating the allocation of resources of the microinstruction cache according to the number of core instructions of each thread.

[0005] For example, in a resource allocation method provided in an embodiment of the present disclosure, allocation of resources of the microinstruction cache is regulated according to the number of core instructions of each thread, including: determining a target thread from the multiple threads according to the number of core instructions of each thread; and writing the microinstructions of the target thread into the microinstruction cache, the microinstructions of the target thread being obtained by at least partially decoding the instructions of the target thread.

[0006] For example, in a resource allocation method provided in an embodiment of the present disclosure, the microinstructions of the target thread are obtained by decoding the core instructions of the target thread.

[0007] For example, in the resource allocation method provided in one embodiment of the present disclosure, a target thread is determined from the multiple threads according to the number of core instructions of each thread, including: obtaining the capacity of the microinstruction cache; and determining the target thread from the multiple threads based on the capacity and the number of core instructions of each thread.

[0008] For example, in the resource allocation method provided in an embodiment of the present disclosure, the target thread is determined from the multiple threads based on the capacity and the number of core instructions of each thread, including: in response to the sum of the numbers of core instructions of the multiple threads being less than or equal to the capacity, each of the multiple threads is used as the target thread.

[0009] For example, in a resource allocation method provided in an embodiment of the present disclosure, the target thread is determined from the multiple threads based on the capacity and the number of core instructions of each thread, including: in response to the sum of the numbers of the core instructions of the multiple threads being greater than the capacity, and the condition that the number of core instructions of each thread is greater than the capacity is not satisfied, sorting the multiple threads according to the number of core instructions of each thread; according to the sorting of the multiple threads, preferentially excluding the threads with the largest number among the multiple threads in turn, and calculating the sum of the numbers of the remaining threads after excluding the threads with the largest number, until the sum of the numbers is less than the capacity; and taking the remaining threads corresponding to the case where the sum of the numbers is less than the capacity as the target threads.

[0010] For example, in the resource allocation method provided in one embodiment of the present disclosure, the allocation of resources of the microinstruction cache is regulated according to the number of core instructions of each thread, and also includes: in response to the number of core instructions of each thread being greater than the capacity, none of the multiple threads are allocated the resources of the microinstruction cache.

[0011] For example, in a resource allocation method provided by an embodiment of the present disclosure, core instructions include instructions that are executed multiple times within a sampling window.

[0012] For example, in the resource allocation method provided in one embodiment of the present disclosure, the number of core instructions of each of the multiple threads is detected, including: obtaining the instruction address of the instruction executed by each thread in the sampling window; determining the number of executions of the instruction corresponding to the instruction address based on the number of accesses to the instruction address; and taking the number of instructions whose execution times are greater than N as the number of core instructions, where N is a positive integer.

[0013] For example, in a resource allocation method provided in an embodiment of the present disclosure, the sampling window includes a preset number of clock cycles or a preset number of instructions.

[0014] For example, in a resource allocation method provided in an embodiment of the present disclosure, the resources of the microinstruction cache include the storage space of the microinstruction cache.

[0015] At least one embodiment of the present disclosure provides a processor configured to execute multiple threads concurrently, the processor comprising: a microinstruction cache; and a controller coupled to the microinstruction cache and configured to: detect the number of core instructions of each of the multiple threads, the instructions of each thread comprising the core instructions and non-core instructions, and the importance of the core instructions is greater than the importance of the non-core instructions; and regulate the allocation of resources of the microinstruction cache according to the number of the core instructions of each thread.

[0016] For example, a processor provided in an embodiment of the present disclosure further includes: a decoder, which is coupled to the input end of the controller and configured to decode the instructions of each thread to obtain microinstructions of each thread; a buffer, whose input end is coupled to the output end of the controller, and whose output end is coupled to the microinstruction cache, wherein the buffer includes multiple buffers, and the multiple buffers correspond one-to-one to the microinstructions of the multiple threads and are configured to store the microinstructions of the multiple threads, and the buffer is configured to write the microinstructions in the buffer into the microinstruction cache, and the controller is configured to: determine a target thread from the multiple threads according to the number of core instructions of each thread; and write the microinstructions of the target thread into the buffer corresponding to the target thread.

[0017] At least one embodiment of the present disclosure provides an electronic device, including the processor provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0019] Figure 1 A flowchart of the CPU in SMT mode is shown;

[0020] Figure 2 A schematic diagram showing a plurality of threads competing for microinstruction cache space is shown;

[0021] Figure 3 A flow chart of a resource allocation method provided by at least one embodiment of the present disclosure is shown;

[0022] Figure 4 A flowchart of another resource allocation method provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 5 A schematic diagram of a processor provided by at least one embodiment of the present disclosure is shown;

[0024] Figure 6 A schematic diagram showing a microstructure of a processor provided by at least one embodiment of the present disclosure;

[0025] Figure 7 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure; and

[0026] Figure 8 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0029] Multithreading technology includes, for example, Simulate Multi-Threading (SMT). SMT, also known as Hyper-Threading, can make a single physical CPU core look like two or more independent processors. In this way, the processor can handle multiple tasks at the same time, greatly improving the efficiency of CPU use. SMT technology is an important technology to improve the overall performance of the CPU. It uses the multi-issue and out-of-order execution mechanisms of high-performance CPU cores to execute instructions of multiple threads simultaneously, so that a physical CPU core is presented to the software and operating system as multiple virtual CPU cores. When a modern multi-issue high-performance CPU core executes a single thread, its internal multiple execution units and hardware resources cannot be fully utilized most of the time; when the thread is paused for some reason (such as a miss in the secondary cache), the hardware execution unit can only run idle, which causes a waste of hardware resources and reduces the performance-to-power ratio. In SMT mode, when a thread is paused, other threads can still run, which improves the utilization of hardware resources, thereby improving the multi-threaded throughput, overall performance and performance-to-power ratio of the CPU core. Depending on the maximum number of active threads supported, SMT can be called SMT2 (up to two active threads), SMT4 (up to four active threads), and so on.

[0030] The CPU core includes multiple pipeline stages, such as branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, and instruction retirement.

[0031] Modern high-performance CPUs often have instruction caches (IC) and micro-instruction caches (OC). IC is used to cache undecoded instructions, and OC is used to cache micro-instructions. Micro-instructions are one or more micro-instructions that are decoded into instructions, which can be passed to subsequent pipelines and executed. When the instruction fetch pipeline finds that the instruction exists in the IC or OC based on the results of the branch prediction pipeline, it can directly obtain the undecoded instructions or micro-instructions (decoded instructions) from these two caches to avoid the high latency caused by accessing the lower-level storage area. In addition, obtaining micro-instructions directly from the OC can reduce the process of fetching undecoded instructions from the IC and decoding them, and can obtain higher instruction issuance bandwidth and faster running speed, thereby improving CPU core performance and effectively reducing power consumption.

[0032] OC is an important component of modern high-performance CPU cores. Using it can effectively reduce the CPU core pipeline front-end latency, reduce power consumption, and increase the value bandwidth, which is of great help to CPU core performance and power consumption. When the branch prediction unit provides new instruction segment information, if the corresponding instruction segment is found in the OC, there is no need to fetch instructions from the instruction cache (IC) and then decode them. Instead, the corresponding micro-operation segment is directly obtained from the OC and provided to the back-end pipeline.

[0033] Figure 1 A flowchart of the CPU's operation in SMT mode is shown.

[0034] like Figure 1 As shown, the operation of the CPU in the SMT mode includes steps S101 to S109.

[0035] Step S101: The branch predictor performs thread arbitration and selects the thread (thread 0 or thread 1) on the pipeline of the current clock cycle to the branch prediction pipeline for branch prediction, thereby obtaining a branch prediction result. Branch prediction is used to predict the target address of the branch instruction. The branch prediction result includes, for example, branch prediction information (Branch PredictionInfo, BPI), that is, the prediction information output by the branch predictor, including the target address of the instruction, the thread tag, the starting position of the storage space, etc. A BPI may include one or more consecutive instructions. For example, the SMT mode includes two active threads, thread 0 and thread 1. For example, the branch predictor performs arbitration according to polling or other methods to select the thread on the pipeline of the current clock cycle.

[0036] Step S102: Write the BPI into the branch prediction result acquisition queue of the corresponding thread. For example, if the branch predictor selects thread 0 for branch prediction in step S101, the BPI is written into the branch prediction result acquisition queue of thread 0. If the branch predictor selects thread 1 for branch prediction in step S101, the BPI is written into the branch prediction result acquisition queue of thread 1.

[0037] Step S103: The instruction cache performs thread arbitration, selects the thread (thread 0 or thread 1) on the pipeline of the current clock cycle, and sequentially obtains the BPI from the branch prediction result acquisition queue corresponding to the thread. If the thread selected by the instruction cache for thread arbitration has not been cached in the microinstruction cache 110, then the BPI is sent to the pipeline of the instruction cache, and the pipeline of the instruction cache is responsible for obtaining undecoded instructions from the instruction cache, and the instruction cache provides the obtained undecoded instructions to the decoder. For example, if the thread on the pipeline of the current clock cycle selected by the instruction cache is thread 1, then the BPI is sequentially obtained from the branch prediction result acquisition queue of thread 1, and the BPI is sent to the pipeline of the instruction cache, thereby obtaining the undecoded instructions of thread 1 from the instruction cache, and providing the undecoded instructions of thread 1 to the decoder. Similarly, the thread on the pipeline of the current clock cycle selected by the instruction cache may also be thread 0. For example, the instruction cache selects the thread on the pipeline of the current clock cycle by arbitration in a polling manner or other manner. If the BPI obtained by the thread selected by the instruction cache through thread arbitration has been cached in the microinstruction cache 110, the step jumps to the subsequent step S108.

[0038] Step S104: The decoder decodes the undecoded instruction into a microinstruction (UOP), and sends the decoded UOP to the microinstruction queue corresponding to the thread for back-end execution. For example, the decoder decodes the undecoded instruction of thread 0 to obtain the UOP of thread 0, and then the decoder provides the UOP of thread 0 to the microinstruction queue of thread 0, so that the UOP of thread 0 enters the microinstruction queue of thread 0.

[0039] Step S105: The decoder provides UOPs to the buffer at the same time. For example, the buffer includes multiple buffers, and the multiple buffers correspond to multiple threads one by one, and each buffer is used to store the UOPs of one thread. In step S105, the decoder performs arbitration and selects the buffer corresponding to which thread in the buffer the UOP obtained by the decoder is written to. For example, if the decoder obtains the UOP of thread 0, the decoder arbitrates and writes the UOP provided by the decoder into the buffer of thread 0.

[0040] For example, while the decoder provides the UOP of a certain thread to the microinstruction queue of the thread, it also performs decoder arbitration and writes the UOP of the thread into the buffer corresponding to the thread.

[0041] Step S106: The UOP of each thread accumulates multiple instructions in the buffer to form a microinstruction item.

[0042] Step S107: The pipeline of the microinstruction cache performs thread arbitration, selects the thread of the pipeline of the current clock cycle, takes out the microinstruction cache item that has been formed by the thread from the buffer, and writes it into the microinstruction cache. For example, if the thread of the pipeline of the current clock cycle selected by the pipeline of the microinstruction cache through thread arbitration is thread 1, the microinstruction cache item that has been formed by thread 1 is taken out from the buffer and written into the microinstruction cache 110.

[0043] Step S108: The microinstruction acquisition queue stores the BPI provided by the instruction cache. For example, if the BPI obtained by the thread selected after the instruction cache arbitration from the branch prediction result acquisition queue has been cached in the microinstruction cache 110, the BPI of the thread will no longer be sent to the instruction cache pipeline and decoder, but directly to the microinstruction acquisition queue of the corresponding thread.

[0044] For example, the BPI of thread 1 selected after instruction cache arbitration has been cached in the microinstruction cache 110, so the BPI of thread 1 is no longer provided to the instruction cache pipeline and decoder, but to the microinstruction acquisition queue of thread 1, so that the microinstruction acquisition queue of thread 1 stores the BPI of thread 1.

[0045] Step S109: The pipeline of the microinstruction cache performs thread arbitration, selects the thread of the pipeline of the current clock cycle, obtains BPI information from the microinstruction acquisition queue of the thread, searches for the corresponding UOP in the microinstruction cache 110, and sends the UOP to the corresponding microinstruction queue for use in back-end execution.

[0046] For example, the pipeline of the microinstruction cache performs thread arbitration and selects the thread of the pipeline in the current clock cycle as thread 0. Then, the BPI information is obtained from the microinstruction acquisition queue of thread 0, the corresponding UOP is found, and the UOP is sent to the corresponding microinstruction queue for use in back-end execution.

[0047] In this workflow, the microinstructions in the microinstruction queue of each thread may come from the decoder or from the microinstruction cache.

[0048] As described above, when filling the microinstruction cache, multiple threads share the entire microinstruction cache space, which means that multiple threads compete with each other for microinstruction cache resources. Since different threads of the processor run different program codes, different threads have different requirements for microinstruction cache resources.

[0049] Since the capacity of the microinstruction cache is limited, once the code of a thread is large and the capacity of the microinstruction cache is insufficient to cache the code of the entire core, the thread will try to occupy the entire microinstruction cache space. This results in other threads being unable to fetch instructions from the microinstruction cache even if the core code is small and should be able to fetch UOPs from the microinstruction cache well, because the microinstruction cache space is occupied by threads with larger core codes.

[0050] Figure 2 A schematic diagram showing multiple threads competing for microinstruction cache space is shown.

[0051] like Figure 2 As shown in the figure, the core instructions (also called core code) of thread 0 are the large loop of A, B, C, D, E, F, G, H, and the core instructions of thread 1 are the small loop of X, Y, Z. The capacity of the microinstruction cache is assumed to be 4 items. Assume that multithreading scheduling is performed in a standard round robin manner. As time changes, the update status of the instruction cache changes as follows Figure 2 shown.

[0052] When writing (also called "filling") a microinstruction into the microinstruction cache, if the microinstruction already exists, it means a fill hit. If the fill hits are preset times in succession, the instruction cache is switched to instruction fetch mode. Figure 2 As shown, if scheduled in a round-robin manner, since the core code of thread 0 competes with thread 1, neither thread 0 nor thread 1 can fill the preset number of hits, resulting in both threads being unable to enter the instruction fetch mode of the instruction cache.

[0053] Therefore, current processors have the problem of reduced microinstruction cache utilization due to competition among multiple threads for microinstruction cache resources, for example, a problem in which a certain thread affects other threads due to a large core instruction.

[0054] In this regard, an embodiment of the present disclosure provides a resource allocation method, which is applied to a processor. The processor is configured to execute multiple threads concurrently, and the processor includes a microinstruction cache. The method includes: detecting the number of core instructions of each of the multiple threads, the instructions of each thread include core instructions and non-core instructions, and the importance of the core instructions is greater than the importance of the non-core instructions; and regulating the allocation of resources of the microinstruction cache according to the number of core instructions of each thread. The embodiment of the present disclosure at least partially solves the problem that multiple threads compete with each other for OC resources, resulting in a low overall OC hit rate, which can not only accelerate the running speed of the entire CPU, but also save power consumption.

[0055] Figure 3 A flowchart of a resource allocation method provided by at least one embodiment of the present disclosure is shown.

[0056] like Figure 3 As shown, the resource allocation method includes step S301 and step S302. The resource allocation method is applied to a processor, and the processor is configured to execute multiple threads concurrently, for example, the processor executes multiple threads concurrently according to the SMT mode. The processor includes a microinstruction cache.

[0057] Step S301: Detect the number of core instructions of each of the multiple threads, where the instructions of each thread include core instructions and non-core instructions, and the importance of the core instructions is greater than that of the non-core instructions.

[0058] Step S302: According to the number of core instructions of each thread, the allocation of resources of the microinstruction cache is regulated.

[0059] For step S301, the importance of the instruction is, for example, represented by the number of times the instruction is executed during the complete execution of the program. The more times the instruction is executed, the more important the instruction is. For example, a program often includes a loop body, and the instructions in the loop body are often executed multiple times. Then the importance of the instructions in the loop body is higher than the importance of the instructions outside the loop body. In some embodiments of the present disclosure, core instructions refer to, for example, instructions in the loop body (i.e., loop instructions), and non-core instructions refer to instructions outside the loop body. Alternatively, core instructions refer to, for example, instructions that are executed more than once during the complete execution of the program, and non-core instructions refer to instructions that are only executed once during the complete execution of the program.

[0060] In some embodiments of the present disclosure, a sampling window is set to collect instructions executed by each thread within the sampling window, core instructions include instructions executed more than or equal to N times within the sampling window, and non-core instructions include instructions executed less than N times within the sampling window, where N is a positive integer. The sampling window includes a preset number of clock cycles or a preset number of instructions. N is equal to 1, for example.

[0061] For example, 1000 clock cycles are used as a sampling window, and the instructions executed by the processor in 1000 clock cycles are collected, and the number of executions of each instruction is counted to obtain the number of core instructions. For another example, 50,000 instructions are used as a sampling window, that is, the preset number of instructions is 50,000. After collecting 50,000 continuously executed instructions, the number of instructions with execution times greater than or equal to N in the 50,000 instructions is counted as the number of core instructions. In some embodiments of the present disclosure, the sampling window can be set as large as possible so that the loop body is executed at least once, so that the collected results are more accurate. In some embodiments of the present disclosure, the size of the sampling window can be configured according to the actual situation (for example, the size of the loop body in the program), so that the sampling window matches the currently executed program, and time is saved while ensuring that the loop body is executed at least once.

[0062] For example, step S301 includes obtaining the instruction address of the instruction executed by each thread in the sampling window; determining the execution count of the instruction corresponding to the instruction address according to the number of accesses to the instruction address; and the number of instructions with execution counts greater than N is the number of core instructions, where N is a positive integer.

[0063] During the thread execution process, each instruction has an instruction address. By counting the number of times the instruction address is accessed, the number of times the instruction corresponding to the instruction address is executed can be determined. For example, if an instruction address is accessed 100 times, then the instruction at the instruction address is executed 100 times. The number of instructions with execution times greater than N is taken as the number of core instructions. Those skilled in the art can set the value of N.

[0064] This embodiment obtains the number of executions of the instruction through the instruction address. The instruction address is relatively convenient to obtain, so the method of obtaining the number of executions of the instruction in this embodiment is relatively convenient.

[0065] For step S302, the resources of the microinstruction cache include storage space of the microinstruction cache. Regulating the allocation of resources of the microinstruction cache includes, for example, controlling which microinstructions of which thread the microinstruction cache is used to store and which microinstructions of which thread the microinstruction cache is not used to store.

[0066] For example, if the number of core instructions of one thread among the multiple threads is large, the microinstructions of the thread may not be stored in the microinstruction cache.

[0067] In some embodiments of the present disclosure, step S302 includes: determining a target thread from multiple threads based on the number of core instructions of each thread; and writing microinstructions of the target thread into a microinstruction cache, where the microinstructions of the target thread are obtained by at least partially decoding the instructions of the target thread.

[0068] For example, the microinstructions of the target thread are obtained by decoding the core instructions of the target thread. Only the microinstructions obtained by decoding the core instructions of the target thread are stored in the microinstruction cache, rather than storing all the microinstructions of the target thread in the microinstruction cache, which can save the storage space of the microinstruction cache for use by other threads.

[0069] For example, a target thread may have a smaller number of core instructions than multiple threads.

[0070] In some embodiments of the present disclosure, determining a target thread from a plurality of threads according to the number of core instructions of each thread includes: obtaining the capacity of the micro-instruction cache; and determining the target thread from the plurality of threads based on the capacity and the number of core instructions of each thread. This method determines the target thread according to the capacity of the micro-instruction cache, enabling the method to be applicable to various micro-instruction caches, adaptively determining the target thread according to the micro-instruction cache, and making full use of the resources of the micro-instruction cache.

[0071] For example, in response to the sum of the number of core instructions of a plurality of threads being less than or equal to the capacity, each of the plurality of threads is taken as the target thread. For example, if the number of core instructions of thread 0 is S0 + the number of core instructions of thread 1 is S1 ≤ the capacity S of the micro-instruction cache, then both thread 0 and thread 1 are taken as the target threads.

[0072] For example, in response to the sum of the number of core instructions of a plurality of threads being greater than the capacity and not satisfying that the number of core instructions of each thread is greater than the capacity, sort the plurality of threads according to the number of core instructions of each thread; sort the plurality of threads and sequentially exclude the thread with the largest number among the plurality of threads preferentially, and calculate the sum of the number of remaining threads after excluding the thread with the largest number until the sum is less than the capacity; and take the corresponding remaining threads when the sum is less than the capacity as the target threads.

[0073] For example, the processor concurrently executes 4 threads, namely thread 1, thread 2, thread 3, and thread 0; the number of core instructions of these 4 threads are S1, S2, S3, and S0 respectively. Determine whether S0 + S1 + S2 + S3 > S and do not satisfy S0 > S, S1 > S, S2 > S, and S3 > S, then sort the threads 1, 2, 0, and 3 according to the magnitudes of S1, S2, S3, and S0. For example, the sorting result in descending order is thread 1, thread 2, thread 0, and thread 3. After excluding the front-ranked thread 1, calculate the sum of the number of core instructions of the remaining threads (thread 2, thread 0, and thread 3) S2 + S0 + S3. If S2 + S0 + S3 > S, then continue to exclude thread 2 and calculate the sum of the number of core instructions of the remaining threads (thread 0 and thread 3) S0 + S3. If S0 + S3 < S, then thread 0 and thread 3 are taken as the target threads. If S0 + S3 > S, then continue to exclude thread 0 until the sum of the number of remaining threads is less than the capacity.

[0074] In some embodiments of the present disclosure, regulating the allocation of resources of the microinstruction cache also includes: each of the multiple threads is not allocated the resources of the microinstruction cache. For example, in response to the number of core instructions of each thread being greater than the capacity, each of the multiple threads is not allocated the resources of the microinstruction cache. For example, the fact that each of the multiple threads is not allocated the resources of the microinstruction cache means that the microinstructions of each thread are not stored in the microinstruction cache. If the number of core instructions of each thread is greater than the capacity of the microinstruction cache, the capacity of the microinstruction cache is insufficient to accommodate the microinstructions of any thread. In order to avoid the microinstruction cache from being filled and hit all the time, the microinstructions of each thread are not written into the microinstruction cache.

[0075] Combine the following Figure 4 An embodiment of the present disclosure is described in which the resources of the microinstruction cache are allocated to a target thread and the resources of the microinstruction cache are not allocated to any thread.

[0076] Figure 4 A flowchart of another resource allocation method provided by at least one embodiment of the present disclosure is shown.

[0077] like Figure 4 As shown, the resource allocation method includes steps S401 to S411.

[0078] Step S401: Detect the number of core instructions S0 of thread 0 and the number of core instructions S1 of thread 1. This step is similar to Figure 3 Step S301.

[0079] Step S402: compare the core instruction number S0 and the core instruction number S1 with the microinstruction cache capacity S. If the core instruction number S0 and the core instruction number S1 are both greater than the capacity S, that is, S0>S and S1>S, then execute step S403.

[0080] Step S403: neither thread 0 nor thread 1 fills the microinstruction cache. That is, in some embodiments of the present disclosure, in response to the number of core instructions of each thread being greater than the capacity of the microinstruction cache, each of the multiple threads is not allocated resources of the microinstruction cache.

[0081] Step S404: Compare the sum of the number of core instructions S0 and the number of core instructions S1 with the microinstruction cache capacity S. For example, determine whether S0+S1 satisfies ≤ S. If S0+S1 is satisfied ≤ S, then execute step S405.

[0082] Step S405: The microinstructions of thread 0 and thread 1 are both filled into the microinstruction cache. That is, in response to the sum of the number of core instructions of the multiple threads being less than or equal to the capacity, each of the multiple threads is used as a target thread.

[0083] Step S406: If S0 + S1 > < S, execute Step S407 and Step S408.

[0084] It should be noted that Step S402, Step S406, and Step S404 can be executed simultaneously, or Step S402 can be executed first and then Step S404. If the judgment result of Step S404 is negative, Step S406 does not need to be compared again and directly executes Step S407 and Step S408.

[0085] Step S407: Determine whether S0 < S and S1 > S are satisfied. If S0 < S and S1 > S are satisfied, execute Step S410. If not, execute Step S409.

[0086] Step S408: Determine whether S0 > S and S1 < S are satisfied. If S0 > S and S1 < S are satisfied, execute Step S411. If not, execute Step S409.

[0087] Step S409: Determine whether S0 > S1 is satisfied. If S0 > S1 is satisfied, execute Step S410. If not, execute Step S411.

[0088] Step S410: Only fill the microinstructions of thread 0 into the microinstruction cache.

[0089] Step S411: Only fill the microinstructions of thread 1 into the microinstruction cache.

[0090] Another aspect of the present disclosure provides a processor configured to concurrently execute multiple threads. The processor includes: a microinstruction cache; and a controller coupled to the microinstruction cache and configured to: detect the number of core instructions of each of the multiple threads, where the instructions of each thread include core instructions and non-core instructions, and the importance of the core instructions is greater than that of the non-core instructions; and regulate the allocation of resources of the microinstruction cache according to the number of core instructions of each thread. The processor can at least partially solve the problem that the overall microinstruction cache hit rate is not high due to multiple threads competing for microinstruction cache resources with each other, and can not only accelerate the running speed of the entire CPU, but also save power consumption.

[0091] An embodiment of the present disclosure proposes a processor for allocating microinstruction cache resources in a concurrent multi-threaded mode. A monitoring device (i.e., the above-mentioned controller) is added before the microinstruction cache to monitor the core code sizes of different threads. The microinstructions of each thread are controlled to be filled into the microinstruction cache according to the detected core code sizes.

[0092] It should be noted that although the embodiments of the present disclosure illustrate the disclosed implementation method by executing two threads (thread 0 and thread 1) in parallel, this has no limiting effect on the present disclosure, and the resource allocation method provided by the present disclosure can be applied to the concurrent execution of any number of threads.

[0093] Figure 5 A schematic diagram of a processor 500 provided by at least one embodiment of the present disclosure is shown.

[0094] like Figure 5 As shown, the processor 500 includes a microinstruction cache 501 and a controller 502 .

[0095] The microinstruction cache 501 is coupled to the controller 502. For example, an input terminal of the microinstruction cache 501 is coupled to an output terminal of the controller 502.

[0096] The controller 502 is configured to detect the number of core instructions of each of the multiple threads, where the instructions of each thread include core instructions and non-core instructions, and the importance of the core instructions is greater than that of the non-core instructions; and to regulate the allocation of resources of the microinstruction cache according to the number of core instructions of each thread.

[0097] Please refer to the above description for the microinstruction cache 501. The controller 502 can be hardware, software, firmware, and any feasible combination thereof. For example, the controller 502 can be a dedicated or general circuit, chip, or device, etc. Regarding the specific implementation form of each of the above-mentioned units, the embodiments of the present disclosure do not limit this. The controller 502 corresponds to each step of the aforementioned resource allocation method. For the specific functions of the controller 502, please refer to the relevant description of the resource allocation method, which will not be repeated here.

[0098] Figure 6 A schematic diagram of a microstructure of a processor provided by at least one embodiment of the present disclosure is shown.

[0099] like Figure 6 As shown in FIG. 1 , the processor includes a microinstruction cache 601 and a controller 602, as well as a decoder 603 and a buffer 604. The microinstruction cache 601 and the controller 602 are similar to the above Figure 5 The microinstruction cache 501 and the controller 502 are similar. The microinstruction cache 601 can also be used as described above. Figure 1 The microinstruction cache 110 in is similar.

[0100] The decoder 603 is coupled to the input terminal of the controller 602 and is configured to decode the instructions of each thread to obtain the microinstructions of each thread. Figure 1 Description.

[0101] The input end of the buffer 604 is coupled to the output end of the controller 602, and the output end of the buffer 604 is coupled to the microinstruction cache 601. The buffer 604 includes a plurality of buffers, and the plurality of buffers correspond to the microinstructions of the plurality of threads one by one, and are configured to store the microinstructions of the plurality of threads. The buffer 604 is configured to write the microinstructions in the buffer into the microinstruction cache 601. The controller 602 is configured to: determine a target thread from the plurality of threads according to the number of core instructions of each thread; and write the microinstructions of the target thread into the buffer corresponding to the target thread.

[0102] For example, the controller 602 includes a recording unit, which records the access instruction address of each thread, determines the execution number of the instruction corresponding to the instruction address according to the access number of the instruction address; and the number of instructions with execution times greater than N is the number of core instructions, where N is a positive integer. The controller 602 also includes a target thread determination unit, which determines the target thread from multiple threads according to the number of core instructions of each thread; and determines a resource allocation strategy for the target thread, and determines a resource allocation strategy when the target thread does not exist in the multiple threads. For example, when the target thread does not exist in the multiple threads, the resource allocation strategy is not to allocate microinstruction cache resources to any thread. When the target thread exists in the multiple threads, the resource allocation strategy is to allocate microinstruction cache resources to the target thread, that is, to store the microinstructions of the target thread in the microinstruction cache.

[0103] In this embodiment, the controller 602 first writes the microinstructions of the target thread into the buffer corresponding to the target thread in the buffer 604 according to the resource allocation strategy. After a certain number of microinstruction cache items are accumulated in the buffer, they are taken out from the buffer according to the arbitration of the microinstruction cache 601 and stored in the microinstruction cache 601.

[0104] For example, the controller 602 obtains the microinstructions of thread 0 from the decoder 603 and determines whether the microinstructions of thread 0 are stored in the buffer corresponding to thread 0. If the microinstructions of thread 0 are stored in the buffer corresponding to thread 0, step S601 is executed, that is, the controller 602 arbitrates to store thread 0 in the buffer corresponding to thread 0.

[0105] like Figure 6 As shown, the microstructure of the processor includes the controller 602 outlined by the oval dotted line and the arbitration of step S601 performed by the controller, and the other structures and processes are similar to those of FIG. Figure 1 similar.

[0106] Figure 5 and Figure 6 The components and structures of the processor shown are merely exemplary and non-limiting. The processor may further include other components and structures as required.

[0107] The specific implementation forms of the above-mentioned units can be hardware, software, firmware, and any feasible combination thereof, which is not limited in the embodiments of the present disclosure.

[0108] It should be noted that the embodiments of the present disclosure are not only applicable to the SMT mode, but also to other concurrent multi-threaded execution modes. As long as the processor concurrently executes multiple threads, the resource allocation method provided by the embodiments of the present disclosure can be used.

[0109] Another aspect of the present disclosure provides an electronic device, which includes the process provided by any embodiment of the present disclosure.

[0110] Figure 7 A schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 7 As shown, the electronic device 700 includes a processor 710 and a memory 720. The memory 720 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 710 is used to run non-transitory computer-readable instructions, and when the non-transitory computer-readable instructions are run by the processor 710, one or more steps in the resource allocation method described above can be executed. The memory 720 and the processor 710 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0111] The processor 701 may be a processor provided by any embodiment of the present disclosure, for example, the microstructure of the processor 701 is similar to Figure 6 The microstructure of the processor in is similar.

[0112] For example, the processor 710 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X86 or ARM architecture, etc. The processor 710 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 700 to perform desired functions.

[0113] For example, the memory 720 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 710 may run one or more computer program modules to implement various functions of the electronic device 700. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0114] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 700 can refer to the above description of the resource allocation method, which will not be repeated here.

[0115] Figure 8 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 800 is suitable for implementing the resource allocation method provided in the embodiments of the present disclosure. The electronic device 800 may be a terminal device, etc. It should be noted that: Figure 8 The electronic device 800 shown is merely an example and does not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

[0116] like Figure 8 As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 810, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 820 or a program loaded from a storage device 880 to a random access memory (RAM) 830. The processing device 810 may be, for example, a processor provided in any embodiment of the present disclosure, such as a microstructure of the processor 810 and a processor 810 having a plurality of CPUs and CPUs. Figure 6 The microstructure of the processor in is similar.

[0117] In the RAM 830, various programs and data required for the operation of the electronic device 800 are also stored. The processing device 810, the ROM 820, and the RAM 830 are connected to each other through a bus 840. An input / output (I / O) interface 850 is also connected to the bus 840.

[0118] Typically, the following devices may be connected to the I / O interface 850: an input device 860 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 870 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 880 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 890. The communication device 890 may allow the electronic device 800 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 8 The electronic device 800 is shown to have various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 800 may alternatively implement or possess more or fewer devices.

[0119] There are a few points to note:

[0120] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0121] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0122] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A resource allocation method, applied to a processor, wherein: The processor is configured to execute multiple threads concurrently, the processor includes a microinstruction cache, and the method includes: Detecting the number of core instructions of each of the plurality of threads, wherein the instructions of each thread include the core instructions and non-core instructions, and the importance of the core instructions is greater than the importance of the non-core instructions; and According to the number of the core instructions of each thread, regulating the allocation of resources of the microinstruction cache; Wherein, regulating the allocation of resources of the microinstruction cache according to the number of the core instructions of each thread includes: Determining a target thread from the plurality of threads according to the number of the core instructions of each thread; and The microinstructions of the target thread are written into the microinstruction cache, wherein the microinstructions of the target thread are obtained by decoding at least a portion of the instructions of the target thread.

2. The method according to claim 1, wherein: The microinstructions of the target thread are obtained by decoding the core instructions of the target thread.

3. The method according to claim 1 or 2, wherein: Determining a target thread from the plurality of threads according to the number of the core instructions of each thread includes: Obtaining the capacity of the microinstruction cache; and A target thread is determined from among the plurality of threads based on the capacity and the number of the core instructions of each thread.

4. The method according to claim 3, wherein: Determining the target thread from the plurality of threads based on the capacity and the number of the core instructions of each thread includes: In response to the sum of the numbers of the core instructions of the multiple threads being less than or equal to the capacity, each of the multiple threads is taken as the target thread.

5. The method according to claim 3, wherein: Determining the target thread from the plurality of threads based on the capacity and the number of the core instructions of each thread includes: In response to the sum of the numbers of the core instructions of the multiple threads being greater than the capacity, and the condition that the number of the core instructions of each thread is greater than the capacity is not satisfied, sorting the multiple threads according to the number of the core instructions of each thread; Sorting the plurality of threads, preferentially excluding the largest number of threads among the plurality of threads, and calculating the sum of the numbers of remaining threads after excluding the largest number of threads, until the sum of the numbers is less than the capacity; and The remaining threads corresponding to the case where the sum of the numbers is less than the capacity are used as the target threads.

6. The method according to claim 3, wherein: According to the number of the core instructions of each thread, the allocation of resources of the microinstruction cache is regulated, and further comprising: In response to the number of the core instructions of each of the threads being greater than the capacity, each of the plurality of threads is not allocated resources of the microinstruction cache.

7. The method according to claim 1, wherein: The core instructions include instructions that are executed multiple times within a sampling window.

8. The method according to claim 7, wherein: Detecting the number of core instructions of each of the plurality of threads includes: Obtaining instruction addresses of instructions executed by each thread within the sampling window; Determining the number of executions of the instruction corresponding to the instruction address according to the number of accesses to the instruction address; and The number of instructions whose execution times is greater than N is defined as the number of core instructions, where N is a positive integer.

9. The method according to claim 7 or 8, wherein: The sampling window includes a preset number of clock cycles or a preset number of instructions.

10. The method according to claim 1, wherein: The resources of the microinstruction cache include storage space of the microinstruction cache.

11. A processor configured to execute multiple threads concurrently, wherein: The processor comprises: microinstruction cache; and A controller is coupled to the microinstruction cache and is configured to: Detecting the number of core instructions of each of the plurality of threads, wherein the instructions of each thread include the core instructions and non-core instructions, and the importance of the core instructions is greater than the importance of the non-core instructions; and According to the number of the core instructions of each thread, regulating the allocation of resources of the microinstruction cache; Wherein, regulating the allocation of resources of the microinstruction cache according to the number of the core instructions of each thread includes: Determining a target thread from the plurality of threads according to the number of the core instructions of each thread; and The microinstructions of the target thread are written into the microinstruction cache, wherein the microinstructions of the target thread are obtained by decoding at least a portion of the instructions of the target thread.

12. The processor of claim 11, further comprising: A decoder, the decoder is coupled to an input terminal of the controller and configured to decode the instruction of each thread to obtain a microinstruction of each thread; A buffer, wherein the input end of the buffer is coupled to the output end of the controller, the output end of the buffer is coupled to the microinstruction cache, the buffer includes a plurality of buffers, the plurality of buffers correspond one-to-one to the microinstructions of the plurality of threads, and are configured to store the microinstructions of the plurality of threads, and the buffer is configured to write the microinstructions in the buffer into the microinstruction cache.

13. An electronic device comprising: A processor as claimed in any one of claims 11 to 12.

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