Shift register, gate driving circuit and display device

Abstract

The application discloses a shift register, a gate drive circuit and a display device, and relates to the technical field of display. The shift register comprises at least an input circuit module, an output circuit module, a first noise reduction circuit module, a second noise reduction circuit module and a first adjustment module. The second noise reduction circuit module is connected with a first power voltage, a first pull-down node and an output signal end. The first adjustment circuit module is connected with a second power voltage, the first pull-down node and the output signal end. When the first pull-down node is at a high potential, the first adjustment circuit module is started, and the output signal end is connected to a potential between the first power voltage and the second power voltage. The first adjustment circuit module and the second noise reduction circuit module form a voltage division circuit. In a reliability process, the potential of the output signal end is reduced under the action of the voltage division circuit, so that the VGL is reduced in the reliability process, and threshold drift of a thin film transistor is effectively avoided.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] Liquid Crystal Display (LCD) panels have numerous advantages, including thinness, energy efficiency, and no radiation, leading to their widespread application. They are used in various applications such as LCD TVs, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens, and laptop screens, and dominate the flat panel display field.

[0003] The driving method of existing liquid crystal displays is usually GOA (Gate Driven on Array). The driving principle of GOA is that the GOA unit outputs gate driving pulses to drive the gate of the TFT (Thin Film Transistor) of the display area pixel to open, so that the data line data can be written into the pixel, driving the liquid crystal to deflect and complete the display.

[0004] For GOA cells, VGL (gate turn-off voltage) is a crucial voltage signal. The magnitude of VGL directly determines the leakage current of the TFT device, significantly impacting its operating characteristics. Especially in large-size LCD products, such as TVs, crosstalk frequently occurs. The most direct cause of V crosstalk is leakage current in the TFT device. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a shift register, a gate drive circuit and a display device to improve the problem of V crosstalk in the display screen.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] In a first aspect, this application provides a shift register, comprising at least an input circuit module, an output circuit module, a first noise reduction circuit module, a second noise reduction circuit module, and a first adjustment circuit module, wherein:

[0008] The input circuit module is connected to the input signal terminal and the pull-up node, and is used to output a pull-up signal to the pull-up node under the control of the input signal;

[0009] The output circuit module is connected to the clock signal terminal, the pull-up node, and the output signal terminal, and is used to output the output signal of the shift register under the control of the pull-up signal.

[0010] The first noise reduction circuit module is connected to the first modulation voltage signal terminal, the first power supply voltage terminal, the pull-up node, and the first pull-down node, and is used to continuously keep the pull-up node low;

[0011] The second noise reduction circuit module is connected to the first power supply voltage terminal, the first pull-down node, and the output signal terminal, and is used to continuously keep the output signal terminal low;

[0012] The first adjustment circuit module is connected to the second power supply voltage terminal, the first pull-down node, and the output signal terminal. When the first pull-down node is at a high potential, the first adjustment circuit module is turned on, so that the output signal terminal is connected to the intermediate potential of the first power supply voltage provided by the first power supply voltage terminal and the second power supply voltage provided by the second power supply voltage terminal, wherein the voltage values ​​of the first power supply voltage and the second power supply voltage are not equal.

[0013] Optionally, the first noise reduction circuit module and the second noise reduction circuit module are also connected to the second drop-down node;

[0014] The shift register further includes a second adjustment circuit module, which is connected to the second power supply voltage terminal, the second pull-down node, and the output signal terminal. When the second pull-down node is at a high potential, the second adjustment circuit module is activated, so that the output signal terminal is connected to the intermediate potential between the first power supply voltage and the second power supply voltage.

[0015] Optional, also includes:

[0016] The reset circuit module is connected to the reset signal terminal, the pull-up node, the output signal terminal, and the first power supply voltage, and is used to set the output signal terminal and the pull-up node low.

[0017] Optionally, the first noise reduction circuit module includes a first modulation sub-circuit module, a first suppression sub-circuit module, and a first noise reduction sub-circuit module, and the second noise reduction circuit module includes a second modulation sub-circuit module, a second suppression sub-circuit module, and a second noise reduction sub-circuit module, wherein:

[0018] The first modulation sub-circuit module is connected to the first modulation voltage signal terminal and is used to generate a first pull-down node signal to drive the first noise reduction sub-circuit module;

[0019] The first suppression sub-circuit module is connected to the pull-up node, the first pull-down node and the first power supply voltage, and is used to stop the first modulation sub-circuit module from working when the shift signal is output;

[0020] The first noise reduction sub-circuit module is connected to the first pull-down node, the pull-up node, the first power supply voltage and the output signal terminal, and is used to continuously pull down the output signal and the pull-up node signal after the shift signal output is completed;

[0021] The second modulation sub-circuit module is connected to the second modulation voltage signal terminal and is used to generate a second pull-down node signal to drive the second noise reduction sub-circuit module;

[0022] The second suppression sub-circuit module is connected to the pull-up node, the second pull-down node and the second power supply voltage, and is used to stop the second modulation sub-circuit module from working when the shift signal is output;

[0023] The second noise reduction sub-circuit module is connected to the second pull-down node, the aforementioned pull-up node, the second power supply voltage, and the output signal terminal, and is used to continuously pull down the output signal and pull up the node signal after the shift signal output is completed.

[0024] Optionally, the first modulation sub-circuit module includes a fifth transistor and a sixth transistor, wherein:

[0025] The fifth transistor has its gate connected to the second terminal of the sixth transistor, its first terminal connected to the first modulation voltage signal terminal, and its second terminal connected to the first pull-down node; the sixth transistor has its gate connected to the first terminal, its first terminal connected to the first modulation voltage signal terminal, and its second terminal connected to the first suppression sub-circuit module.

[0026] The first suppression sub-circuit module includes a seventh transistor and an eighth transistor, wherein:

[0027] The seventh transistor has its gate connected to a pull-up node, its first terminal connected to a first power supply voltage, and its second terminal connected to a first pull-down node; the eighth transistor has its gate connected to a pull-up node, its first terminal connected to a first power supply voltage, and its second terminal connected to the second terminal of the sixth transistor of the first modulator circuit module.

[0028] The first noise reduction sub-circuit module includes a tenth transistor and a sixteenth transistor, wherein:

[0029] The tenth transistor has its gate connected to a first pull-down node, its first terminal connected to a first power supply voltage, and its second terminal connected to a pull-up node; the sixteenth transistor has its gate connected to a first pull-down node, its first terminal connected to a first power supply voltage, and its second terminal connected to an output signal terminal.

[0030] The second modulation sub-circuit module includes a twelfth transistor and a thirteenth transistor, wherein:

[0031] The twelfth transistor has its gate connected to the second terminal of the thirteenth transistor, its first terminal connected to the second modulation voltage signal terminal, and its second terminal connected to the second pull-down node; the thirteenth transistor has its gate connected to its first terminal, its first terminal connected to the second modulation voltage signal terminal, and its second terminal connected to the second suppression sub-circuit module.

[0032] The second suppression sub-circuit module includes a fourteenth transistor and a fifteenth transistor, wherein:

[0033] The fourteenth transistor has its gate connected to a pull-up node, its first terminal connected to a first power supply voltage, and its second terminal connected to a second pull-down node; the fifteenth transistor has its gate connected to a pull-up node, its first terminal connected to a first power supply voltage, and its second terminal connected to the second terminal of the thirteenth transistor of the second modulator circuit module.

[0034] The second noise reduction sub-circuit module includes a ninth transistor and a seventeenth transistor, wherein:

[0035] The ninth transistor has its gate connected to a second pull-down node, its first terminal connected to a first power supply voltage, and its second terminal connected to a pull-up node; the seventeenth transistor has its gate connected to a second pull-down node, its first terminal connected to a first power supply voltage, and its second terminal connected to an output signal terminal.

[0036] The first modulation voltage signal and the second modulation voltage signal are long-period signals, and their waveforms are opposite.

[0037] Optionally, the first adjustment circuit module includes an eleventh transistor, whose gate is connected to the first pull-down node, whose first terminal is connected to the second power supply voltage, and whose second terminal is connected to the output signal terminal;

[0038] The second adjustment circuit module includes an eighteenth transistor, whose gate is connected to the second pull-down node, its first terminal is connected to the second power supply voltage, and its second terminal is connected to the output signal terminal.

[0039] Optionally, the channel width-to-length ratio of the eleventh transistor is smaller than that of the sixteenth transistor, and the channel width-to-length ratio of the eighteenth transistor is smaller than that of the seventeenth transistor.

[0040] Optionally, the input circuit module includes a first transistor, whose gate is connected to a first terminal, the first terminal is connected to the input signal terminal, and the second terminal is connected to the pull-up node;

[0041] The pull-up circuit module includes a third transistor and a first capacitor, wherein:

[0042] The third transistor has its gate connected to a pull-up node, its first terminal connected to a clock signal terminal, and its second terminal connected to an output signal terminal.

[0043] The first capacitor has one end connected to the pull-up node and the other end connected to the output signal terminal;

[0044] Optionally, the reset circuit module includes a first reset sub-circuit module and a second reset sub-circuit module, wherein the first reset sub-circuit module includes a second transistor, and the second reset circuit module includes a fourth transistor, wherein:

[0045] The second transistor has its gate connected to the first reset signal terminal, its first terminal connected to the first power supply voltage, and its second terminal connected to the pull-up node.

[0046] The fourth transistor has its gate connected to the second reset signal terminal, its first terminal connected to the first power supply voltage, and its second terminal connected to the output signal terminal.

[0047] Secondly, this application provides a gate driving circuit, characterized in that it includes a shift register as described in any one of the first aspects, wherein a plurality of the shift registers are cascaded, wherein: the output signal terminal of the upper-level shift register is connected to the input circuit module of the shift register, and the output signal terminal of the lower-level shift register is connected to the reset circuit module, the first noise reduction circuit module and the second noise reduction circuit module of the shift register.

[0048] Thirdly, this application provides a display device including the gate driving circuit as described in the second aspect.

[0049] As can be seen from the above description, the shift register, gate driving circuit, and display device provided in this application relate to the field of display technology. The shift register includes at least a first noise reduction circuit module, a second noise reduction circuit module, and a first adjustment module. The input circuit module is connected to the input signal terminal and the pull-up node, and is used to output a pull-up signal to the pull-up node under the control of the input signal.

[0050] The output circuit module, connected to the clock signal terminal, pull-up node, and output signal terminal, is used to output the output signal of the shift register under the control of the pull-up signal. The first noise reduction circuit module is connected to the first modulation voltage signal terminal, the first power supply voltage, and the first pull-down node. The second noise reduction circuit module is connected to the first power supply voltage, the first pull-down node, and the output signal terminal. The first adjustment circuit module is connected to the second power supply voltage, the first pull-down node, and the output signal terminal. When the first pull-down node is at a high potential, the first adjustment circuit module is activated, and the output signal terminal is connected to the intermediate potential between the first and second power supply voltages. The first adjustment circuit module and the second noise reduction circuit module form a voltage divider circuit. During the reliability process, the output signal terminal potential decreases under the action of the voltage divider circuit, thus reducing VGL during the reliability process, effectively avoiding threshold drift of the thin-film transistor, and reducing the problem of vertical crosstalk on the display screen. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a display screen with vertical crosstalk in the existing technology;

[0053] Figure 2 This is a structural block diagram of a shift register provided in an embodiment of this application;

[0054] Figure 3 A circuit schematic diagram of a shift register provided in an embodiment of this application;

[0055] Figure 4 This is a block diagram of another shift register provided in an embodiment of this application;

[0056] Figure 5 This is a circuit schematic diagram of another shift register provided in an embodiment of this application;

[0057] Figure 6 A timing diagram of a shift register provided in an embodiment of this application;

[0058] Figures 7A-7D The circuit diagram is for another shift register provided in the embodiments of this application.

[0059] In the attached diagram:

[0060] 1-Input circuit module;

[0061] 2-Pull-up circuit module;

[0062] 3-Reset circuit module; 31-First reset sub-circuit module; 32-Second reset sub-circuit module;

[0063] 4-First noise reduction circuit module; 41-First modulation sub-circuit module; 42-First suppression sub-circuit module; 43-First noise reduction sub-circuit module;

[0064] 5-Second noise reduction circuit module; 51-Second modulation sub-circuit module; 52-Second suppression sub-circuit module; 53-Second noise reduction sub-circuit module;

[0065] 6-First adjustment circuit module;

[0066] 7-Second adjustment circuit module. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0068] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0069] As described earlier, liquid crystal display panels consist of vertical and horizontal arrays of pixel matrices. During display, a gate scan signal is output through the gate driving circuit to scan and access each pixel line by line. The gate driving circuit generates the gate scan voltage for each pixel. GOA (Gate of Area) is a technology that integrates the gate driving circuit onto the TFT substrate. Each GOA unit acts as a shift register, sequentially transmitting the scan signal to the next GOA unit, turning on the TFT switch line by line to complete the data signal input for the pixel unit. After the previous line is output, the gate maintains a low potential (VGL) voltage to ensure that the pixel TFT is turned off. The pixel voltage latching enables display. However, due to prolonged operation, the TFT characteristics may drift to the left, leading to an increase in leakage current and V Crosstalk. V Crosstalk, or Vertical Crosstalk, refers to the vertical crosstalk phenomenon in a display screen. The most direct cause of V Crosstalk is leakage current in the TFT device. This leakage current causes changes in the voltage of the pixel electrodes in adjacent areas, resulting in changes in the display brightness of adjacent areas. Therefore, in current evaluations, whether V Crosstalk occurs after 1000 hours of reliability assessment is an important indicator of the reliability of existing products, as well as the size of the VGL margin at different time points.

[0070] Specifically, VGL is the turn-off voltage of the TFT, and the value of VGL directly determines the magnitude of the leakage current of the TFT device, which has a great impact on the operating characteristics of the TFT.

[0071] like Figure 1 As shown, the TV display device includes a display screen 102, a control board 100, and a flexible circuit board 101 for connecting the display screen 102 and the control board 100. A V Crosstalk phenomenon occurs when the display screen 102 displays certain special images; for example, when the display screen 102 displays... Figure 1 The image shown has a grayscale value of L255 for the central region L0 and L127 for the surrounding areas. Ideally, the brightness of regions LA and LB should be the same. However, due to the V Crosstalk phenomenon, the brightness of region LA is significantly greater than that of region LB. Therefore, when evaluating the quality of a display screen, the V Crosstalk effect is considered as one of the reference factors. The following formula can be used to evaluate the display screen's quality:

[0072]

[0073] The closer the brightness of area LA and area LB of a display screen are, the better the quality of the display screen; conversely, the greater the difference between the brightness of area LA and area LB, the worse the quality of the display screen.

[0074] To improve the V Crosstalk problem, existing technologies use the method of changing the value of VGL to reduce leakage current. However, changing the value of VGL will affect the characteristics of the TFT device and thus the reliability of the display.

[0075] The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0076] like Figure 2 As shown, Figure 2 This is a structural block diagram of a shift register provided in an embodiment of this application. The shift register 200 includes at least an input circuit module 201, a pull-up circuit module 202, a first noise reduction circuit module 203, a second noise reduction circuit module 204, and a first adjustment module 205, wherein:

[0077] The input circuit module 201 is connected to the input signal terminal and the pull-up node, and is used to pull up the pull-up node signal under the control of the input signal, that is, to charge the pull-up node.

[0078] The pull-up circuit module 202 is connected to the clock signal terminal, the output signal terminal, and the pull-up node, and is used to output the shift signal and pull the pull-up node signal high again, while completing the output process of the shift register circuit.

[0079] The first noise reduction circuit module 203 is connected to the first modulation voltage signal terminal, the first power supply voltage and the first pull-down node, and is used to continuously keep the pull-up node low;

[0080] The second noise reduction circuit module 204 is connected to the first power supply voltage, the first pull-down node and the output signal terminal, and is used to continuously keep the output signal terminal low;

[0081] The first adjustment circuit module 205 is connected to the second power supply voltage, the first pull-down node, and the output signal terminal. It is used to turn on the first adjustment circuit module when the first pull-down node is at a high potential, so that the output signal terminal is connected to the intermediate potential between the first power supply voltage and the second power supply voltage, wherein the voltage values ​​of the first power supply voltage and the second power supply voltage are not equal.

[0082] The first adjustment circuit module and the second noise reduction circuit module form a voltage divider circuit. During the reliability process, the output signal terminal potential will decrease under the action of the voltage divider circuit, thus realizing the reduction of VGL during the reliability process and effectively avoiding the threshold drift of the thin film transistor.

[0083] As one possible implementation, such as Figure 3 As shown, Figure 3 This is a circuit schematic diagram of a shift register provided in an embodiment of this application. The shift register further includes a reset circuit module, wherein:

[0084] The reset circuit module is connected to the reset signal terminal, the pull-up node, the output signal terminal, and the first power supply voltage, and is used to set the output signal terminal and the pull-up node low.

[0085] like Figure 4 As shown, Figure 4 This is a structural block diagram of another shift register provided in this application embodiment. The difference between the shift register in this embodiment and that in embodiment 1 is that the shift register in this embodiment has a first noise reduction circuit module and a second noise reduction circuit module with the same structure. The two noise reduction circuit modules have the same function and work alternately, thereby reducing the high-level time of the transistors (M9 / M17 or M16 / M10) in the noise reduction circuit module to half of the original time, avoiding severe drift caused by the long-term high-level signal on their gates.

[0086] like Figure 4 As shown, the shift register includes an input circuit module 1, a pull-up circuit module 2, a reset circuit module 3, a first noise reduction circuit module 4, a first noise reduction circuit module 5, a first adjustment module 6, and a second adjustment module 7, wherein:

[0087] The input circuit module 1 is connected to the input signal terminal and the pull-up node, and is used to pull up the pull-up node signal under the control of the input signal.

[0088] The pull-up circuit module 2 is connected to the clock signal terminal, the output signal terminal and the pull-up node, and is used to output the shift signal and pull up the pull-up node signal twice.

[0089] The reset circuit module 3 is connected to the reset signal terminal, the pull-up node, the output signal terminal, and the first power supply voltage, and is used to set the output signal terminal and the pull-up node low.

[0090] The first noise reduction circuit module 4 is connected to the first modulation voltage signal terminal, the first power supply voltage, the first pull-down node, and the second pull-down node, and is used to continuously keep the pull-up node low.

[0091] The second noise reduction circuit module 5 is connected to the first power supply voltage, the first pull-down node, the output signal terminal, the second modulation voltage signal terminal, and the second pull-down node. It is used to continuously set the output signal terminal low. In this embodiment, setting it low means that the low potential setting can be set to -8V, and setting it high means that the high potential can be set to 34V. It should be noted that this is only an example and not a limitation on the high and low potentials. Different circuits may have different settings for high and low potentials, which need to be determined according to actual use.

[0092] The first adjustment circuit module 6 is connected to the second power supply voltage, the first pull-down node, and the output signal terminal. It is used to turn on the first adjustment circuit module when the first pull-down node is at a high potential, so that the output signal terminal is connected to the intermediate potential between the first power supply voltage and the second power supply voltage, wherein the voltage values ​​of the first power supply voltage and the second power supply voltage are not equal.

[0093] The second adjustment circuit module 7 is connected to the second power supply voltage, the second pull-down node, and the output signal terminal. It is used to turn on the first adjustment circuit module when the second pull-down node is at a high potential, so that the output signal terminal is connected to the intermediate potential between the first power supply voltage and the second power supply voltage.

[0094] The following will combine Figure 5 Circuit schematic and Figure 4 Each circuit module is described in detail below:

[0095] The input circuit module 1 includes a first transistor M1, whose gate is connected to a first terminal, the first terminal is connected to the input signal terminal, and the second terminal is connected to the pull-up node;

[0096] The pull-up circuit module 2 includes a third transistor M3 and a first capacitor C1, wherein:

[0097] The third transistor M3 has its gate connected to the pull-up node PU, its first terminal connected to the clock signal terminal CLKA, and its second terminal connected to the output signal terminal Output.

[0098] The first capacitor C1 has one end connected to the pull-up node and the other end connected to the output signal terminal;

[0099] The reset circuit module 3 includes a first reset sub-circuit module 31 and a second reset circuit module 32. The first reset sub-circuit module includes a second transistor M2, and the second reset circuit module includes a fourth transistor M4, wherein:

[0100] The second transistor M2 has its gate connected to the first reset signal terminal, its first terminal connected to the first power supply voltage, and its second terminal connected to the pull-up node PU.

[0101] The fourth transistor M4 has its gate connected to the second reset signal terminal, its first terminal connected to the first power supply voltage, and its second terminal connected to the output signal terminal Output.

[0102] The first noise reduction circuit module 4 includes a first modulation sub-circuit module 41, a first suppression sub-circuit module 42, and a first noise reduction sub-circuit module 43. The second noise reduction circuit module 5 includes a second modulation sub-circuit module 51, a second suppression sub-circuit module 52, and a second noise reduction sub-circuit module 53, wherein:

[0103] The first modulation sub-circuit module 41 is connected to the first modulation voltage signal terminal VDDA and is used to generate the first pull-down node signal PD1 to drive the first noise reduction sub-circuit module 41.

[0104] The first modulation sub-circuit module includes a fifth transistor M5 and a sixth transistor M6, wherein:

[0105] The fifth transistor M5 has its gate connected to the second terminal of the sixth transistor M6, its first terminal connected to the first modulation voltage signal terminal VDDA, and its second terminal connected to the first pull-down node; the sixth transistor M6 has its gate connected to its first terminal, its first terminal connected to the first modulation voltage signal terminal VDDA, and its second terminal connected to the first suppression sub-circuit module 42.

[0106] The first suppression sub-circuit module 42 is connected to the pull-up node PU, the first pull-down node PD1 and the first power supply voltage VSS1, and is used to stop the first modulation sub-circuit module 41 from working when the shift signal is output.

[0107] The first noise reduction sub-circuit module 43 is connected to the first pull-down node PD1, the pull-up node PU, the first power supply voltage VSS1 and the output signal terminal Output, and is used to continuously pull down the output signal and the pull-up node signal after the shift signal output is completed;

[0108] The second modulation sub-circuit module 51 is connected to the second modulation voltage signal terminal VDDB and is used to generate a second pull-down node signal to drive the second noise reduction sub-circuit module 51.

[0109] The second suppression sub-circuit module 53 is connected to the pull-up node, the second pull-down node and the second power supply voltage, and is used to stop the second modulation sub-circuit module from working when the shift signal is output;

[0110] The second noise reduction sub-circuit module 52 is connected to the second pull-down node PD2, the pull-up node PU, the second power supply voltage VSS2, and the output signal terminal Output, and is used to continuously pull down the output signal and pull up the node signal after the shift signal output is completed.

[0111] The first suppression sub-circuit 42 module includes a seventh transistor M7 and an eighth transistor M8, wherein:

[0112] The seventh transistor M7 has its gate connected to the pull-up node PU, its first terminal connected to the first power supply voltage VSS1, and its second terminal connected to the first pull-down node PD1; the eighth transistor M8 has its gate connected to the pull-up node PU, its first terminal connected to the first power supply voltage VSS1, and its second terminal connected to the second terminal of the sixth transistor M6 of the first modulator circuit module 41.

[0113] The first noise reduction sub-circuit module 53 includes a tenth transistor M10 and a sixteenth transistor M16, wherein:

[0114] The tenth transistor M10 has its gate connected to the first pull-down node PD1, its first terminal connected to the first power supply voltage VSS1, and its second terminal connected to the pull-up node PU; the sixteenth transistor M16 has its gate connected to the first pull-down node PD1, its first terminal connected to the first power supply voltage VSS1, and its second terminal connected to the output signal terminal Output.

[0115] The second modulation sub-circuit module 51 includes a twelfth transistor M12 and a thirteenth transistor M13, wherein:

[0116] The twelfth transistor M12 has its gate connected to the second terminal of the thirteenth transistor, its first terminal connected to the second modulation voltage signal terminal VDDB, and its second terminal connected to the second pull-down node PD2; the thirteenth transistor M13 has its gate connected to its first terminal, its first terminal connected to the second modulation voltage signal terminal VDDB, and its second terminal connected to the second suppression sub-circuit module 53.

[0117] The second suppression sub-circuit module 53 includes a fourteenth transistor M14 and a fifteenth transistor M15, wherein:

[0118] The fourteenth transistor M14 has its gate connected to the pull-up node, its first terminal connected to the first power supply voltage VSS1, and its second terminal connected to the second pull-down node PD2; the fifteenth transistor M15 has its gate connected to the pull-up node PU, its first terminal connected to the first power supply voltage VSS1, and its second terminal connected to the second terminal of the thirteenth transistor M13 of the second modulator circuit module.

[0119] The second noise reduction sub-circuit module 52 includes a ninth transistor M9 and a seventeenth transistor M17, wherein:

[0120] The ninth transistor M9 has its gate connected to the second pull-down node PD2, its first terminal connected to the first power supply voltage VSS1, and its second terminal connected to the pull-up node; the seventeenth transistor has its gate connected to the second pull-down node, its first terminal connected to the first power supply voltage VSS1, and its second terminal connected to the output signal terminal Output.

[0121] The first and second modulation voltage signals are long-period signals with opposite waveforms. The output signals of the two noise reduction circuit modules are the first pull-down node signal PD1 and the second pull-down node signal PD2, respectively. PD1 is generated from the VDDA signal through M5 and M6, and is a long-period signal. The second pull-down node signal is generated from the VDDB signal through M12 and M13; when PD1 is high, PD2 is low. Using two noise reduction circuit modules can reduce the threshold voltage Vth drift of the transistors (M9, M10 and M16, M17) in the shift register.

[0122] The first adjustment circuit module 6 includes an eleventh transistor M11, whose gate is connected to the first pull-down node PD1, its first terminal is connected to the second power supply voltage VSS2, and its second terminal is connected to the output signal terminal Output.

[0123] The second adjustment circuit module 7 includes an eighteenth transistor M18, whose gate is connected to the second pull-down node PD2, its first terminal is connected to the second power supply voltage VSS2, and its second terminal is connected to the output signal terminal Output.

[0124] Taking the operation of the first noise reduction circuit module 4 as an example, PD1 is at a high potential, the ninth transistor M9, the sixteenth transistor M16, and the eleventh transistor M11 are turned on, and the PU point and the output point are at a low potential. The output point is connected to the intermediate potential between the first power supply voltage VSS1 (e.g., -10V) and VSS2 (e.g., -20V) through the sixteenth transistor M16 and the eleventh transistor M11. The magnitude of this potential is determined by the magnitude of the on-state current of M16 and M11, which forms a voltage divider circuit. During the reliability process, the output signal terminal potential will decrease under the action of the voltage divider circuit, thus achieving a reduction in VGL during the reliability process and effectively avoiding the threshold voltage drift of the thin-film transistor. This shift register can reduce the threshold voltage Vth drift of the transistors in the noise reduction circuit module. Therefore, the size of the noise reduction circuit module of the shift register can be appropriately reduced, which is beneficial for the narrow bezel of the display product, without increasing the production process and production cost.

[0125] The channel width-to-length ratio of the eleventh transistor M11 is smaller than that of the sixteenth transistor M16, and the channel width-to-length ratio of the eighteenth transistor M18 is smaller than that of the seventeenth transistor M17.

[0126] For example, the channel width-to-length ratio of the sixteenth transistor M16 is greater than that of the eleventh transistor M11. During the reliability process, the sixteenth transistor M16 drifts to the right more than the eleventh transistor M11. The equivalent resistance of M16 increases faster than that of M11. This effectively overcomes the problem that the TFT characteristics will drift to the left due to long-term operation, which leads to an increase in leakage current and V Crosstalk.

[0127] In this embodiment of the application, a test is used as an example. VSS1 = 10V, VSS2 = -20V, the channel width-to-length ratio of the sixteenth transistor M16 is 1000 / 4, Ion = 154uA, and after 1000 hours of reliability testing, Ion = 0.5uA. The channel width-to-length ratio of the eleventh transistor M11 is 38 / 4, Ion = 7uA, and after 1000 hours of reliability testing, Ion = 5uA. When the PD1 noise reduction unit is working, M9, M16, and M11 are turned on, the PU point is connected to Vss1, and the output is connected to Vss1 and Vss2 respectively through the sixteenth transistor M16 and the eleventh transistor M11, forming a voltage divider circuit. Before reliability: Ion11 / Ion12 = 154 / 7, R11 / R12 = 7 / 154, the output VGL = -10V + (-20V--10V) * [7 / (154+7)] = -10.434V; After reliability: Ion11 / Ion12 = 0.5 / 5, R11 / R12 = 5 / 0.5, the output VGL = -10V + (-20V--10V) * [5 / (0.5+5)] = -19V. As can be seen, the adjustment unit of this application changes the VGL voltage value through the characteristic drift of the eleventh transistor M11 and the sixteenth transistor M16 during the reliability process, and the VGL voltage decreases with time. This trend is synchronized with the left drift of the TFT characteristic in the active region. That is, the increase in leakage current caused by the left drift of the AA region characteristic can be reduced by reducing the VGL voltage, thereby increasing the VGL margin and improving product performance.

[0128] As one possible implementation, the transistors in this shift register are thin-film transistors. In terms of transistor type selection, all transistors can be N-type, all transistors can be P-type, or a combination of P-type and N-type transistors, as long as the corresponding terminals of the transistors are correctly connected. In the shift register provided in this embodiment, all transistors are described using N-type transistors as an example. It is conceivable that if P-type transistors were used instead of N-type transistors, the signal polarity would need to be reversed, while the connection method would remain unchanged; this will not be detailed here.

[0129] The timing diagram of the shift register in this embodiment is referenced. Figure 6 It includes four stages: pull-up stage, output stage, initial noise reduction stage, and noise reduction maintenance stage. The working principle is explained in detail below:

[0130] In the first stage, the pull-up stage, the input signal is valid and output to the pull-up node, causing the signal level of the pull-up node to rise. For example... Figure 7AAs shown, when the input signal INPUT is valid (high level), the first transistor M1 is turned on, and the input signal INPUT is output to the pull-up node. The pull-up node signal PU rises, and at this time, the pull-up node signal PU is pulled high for the first time. The third transistor M3, the seventh transistor M7, and the eighth transistor M8 are turned on, PD_CN and PD are pulled low, and the fifth transistor M5 is turned off; CLKA is at a low level at this time, and Output remains low. In the second stage, the output stage, the clock signal is valid, and the output signal terminal outputs a shift signal. Figure 7B As shown, the clock signal CLK is valid (high level). Due to the bootstrap effect of the first capacitor C1, the pull-up node signal PU is pulled high for the second time. The third transistor M3 is turned on, and the output signal terminal outputs a high-level shift signal Output, that is, the output VGH level.

[0131] The third stage, the reset stage, is also the initial stage of noise reduction. The reset signal RESET PU is active, resetting both the pull-up nodes and the output signal terminal. Simultaneously, the reset signal pulls either the first or second pull-down node signal high. For example... Figure 7C As shown, after the output signal OUT(n) of this stage is completed, the output signal OUT(n+1) of the next stage shift register becomes the reset signal RESET PU (high level). The second transistor M2 and the fourth transistor M4 are turned on respectively. RESET PU resets the pull-up node and the output signal terminal. The pull-up node signal PU and the output signal OutputT are low level, and the output VGH level stops.

[0132] The fourth stage, the noise reduction maintenance stage, involves reducing the voltage of either the first or second pull-down node signal to continuously reduce noise at the output signal terminal and the pull-up node. For example... Figure 7D As shown, to avoid potential noise in the pull-up node signal PU, the first pull-down node signal PD1 or the second pull-down node signal PD2 needs to be activated to continuously pull the pull-up node signal PU low. Either the first pull-down node signal PD1 or the second pull-down node signal PD2 is valid (only one pull-down node signal can be high at any given time). Taking the operation of the first noise reduction circuit module as an example, the first transistor M1 is off, the third transistor M3 is off, VDDA is pulled high by the activated sixth transistor M6 and fifth transistor M5 to pull the first pull-down node signal PD1 high, the ninth transistor M9 and the sixteenth transistor M16 are activated respectively to reduce noise in PU and Output, keeping VSS1 active, and the eleventh transistor M11 is activated. The output is connected to Vss1 and Vss2 respectively through the sixteenth transistor M16 and the eleventh transistor M11, forming a voltage divider circuit. During the reliability process, the output point potential will decrease under the voltage divider circuit, thus achieving automatic reduction of VGL during product reliability testing.

[0133] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0134] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0135] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0136] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0137] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A shift register, characterized in that, It includes at least an input circuit module, an output circuit module, a first noise reduction circuit module, a second noise reduction circuit module, and a first adjustment circuit module, wherein: The input circuit module is connected to the input signal terminal and the pull-up node, and is used to output a pull-up signal to the pull-up node under the control of the input signal; The output circuit module is connected to the clock signal terminal, the pull-up node, and the output signal terminal, and is used to output the output signal of the shift register under the control of the pull-up signal. The first noise reduction circuit module is connected to the first modulation voltage signal terminal, the first power supply voltage terminal, the pull-up node, and the first pull-down node, and is used to continuously keep the pull-up node low; The second noise reduction circuit module is connected to the first power supply voltage terminal, the first pull-down node, and the output signal terminal, and is used to continuously keep the output signal terminal low; The first adjustment circuit module is connected to the second power supply voltage terminal, the first pull-down node, and the output signal terminal. When the first pull-down node is at a high potential, the first adjustment circuit module is turned on, so that the output signal terminal is connected to the intermediate potential of the first power supply voltage provided by the first power supply voltage terminal and the second power supply voltage provided by the second power supply voltage terminal. The voltage values ​​of the first power supply voltage and the second power supply voltage are not equal, and the intermediate potential decreases with time.

2. The shift register according to claim 1, characterized in that, The first noise reduction circuit module and the second noise reduction circuit module are also connected to the second drop-down node; The shift register further includes a second adjustment circuit module, which is connected to the second power supply voltage terminal, the second pull-down node, and the output signal terminal. When the second pull-down node is at a high potential, the second adjustment circuit module is activated, so that the output signal terminal is connected to the intermediate potential between the first power supply voltage and the second power supply voltage.

3. The shift register according to claim 1, characterized in that, Also includes: The reset circuit module is connected to the reset signal terminal, the pull-up node, the output signal terminal, and the first power supply voltage, and is used to set the output signal terminal and the pull-up node low.

4. The shift register according to claim 3, characterized in that, The first noise reduction circuit module includes a first modulation sub-circuit module, a first suppression sub-circuit module, and a first noise reduction sub-circuit module; the second noise reduction circuit module includes a second modulation sub-circuit module, a second suppression sub-circuit module, and a second noise reduction sub-circuit module, wherein: The first modulation sub-circuit module is connected to the first modulation voltage signal terminal and is used to generate a first pull-down node signal to drive the first noise reduction sub-circuit module; The first suppression sub-circuit module is connected to the pull-up node, the first pull-down node and the first power supply voltage, and is used to stop the first modulation sub-circuit module from working when the shift signal is output; The first noise reduction sub-circuit module is connected to the first pull-down node, the pull-up node, the first power supply voltage and the output signal terminal, and is used to continuously pull down the output signal and the pull-up node signal after the shift signal output is completed; The second modulation sub-circuit module is connected to the second modulation voltage signal terminal and is used to generate a second pull-down node signal to drive the second noise reduction sub-circuit module; The second suppression sub-circuit module is connected to the pull-up node, the second pull-down node and the second power supply voltage, and is used to stop the second modulation sub-circuit module from working when the shift signal is output; The second noise reduction sub-circuit module is connected to the second pull-down node, the aforementioned pull-up node, the second power supply voltage, and the output signal terminal, and is used to continuously pull down the output signal and pull up the node signal after the shift signal output is completed.

5. The shift register according to claim 4, characterized in that, The first modulation sub-circuit module includes a fifth transistor and a sixth transistor, wherein: The fifth transistor has its gate connected to the second terminal of the sixth transistor, its first terminal connected to the first modulation voltage signal terminal, and its second terminal connected to the first pull-down node; the sixth transistor has its gate connected to the first terminal, its first terminal connected to the first modulation voltage signal terminal, and its second terminal connected to the first suppression sub-circuit module. The first suppression sub-circuit module includes a seventh transistor and an eighth transistor, wherein: The seventh transistor has its gate connected to a pull-up node, its first terminal connected to a first power supply voltage, and its second terminal connected to a first pull-down node; the eighth transistor has its gate connected to a pull-up node, its first terminal connected to a first power supply voltage, and its second terminal connected to the second terminal of the sixth transistor of the first modulator circuit module. The first noise reduction sub-circuit module includes a tenth transistor and a sixteenth transistor, wherein: The tenth transistor has its gate connected to a first pull-down node, its first terminal connected to a first power supply voltage, and its second terminal connected to a pull-up node; the sixteenth transistor has its gate connected to a first pull-down node, its first terminal connected to a first power supply voltage, and its second terminal connected to an output signal terminal. The second modulation sub-circuit module includes a twelfth transistor and a thirteenth transistor, wherein: The twelfth transistor has its gate connected to the second terminal of the thirteenth transistor, its first terminal connected to the second modulation voltage signal terminal, and its second terminal connected to the second pull-down node; the thirteenth transistor has its gate connected to its first terminal, its first terminal connected to the second modulation voltage signal terminal, and its second terminal connected to the second suppression sub-circuit module. The second suppression sub-circuit module includes a fourteenth transistor and a fifteenth transistor, wherein: The fourteenth transistor has its gate connected to a pull-up node, its first terminal connected to a first power supply voltage, and its second terminal connected to a second pull-down node; the fifteenth transistor has its gate connected to a pull-up node, its first terminal connected to a first power supply voltage, and its second terminal connected to the second terminal of the thirteenth transistor of the second modulator circuit module. The second noise reduction sub-circuit module includes a ninth transistor and a seventeenth transistor, wherein: The ninth transistor has its gate connected to a second pull-down node, its first terminal connected to a first power supply voltage, and its second terminal connected to a pull-up node; the seventeenth transistor has its gate connected to a second pull-down node, its first terminal connected to a first power supply voltage, and its second terminal connected to an output signal terminal. The first modulation voltage signal and the second modulation voltage signal are long-period signals, and their waveforms are opposite.

6. The shift register according to claim 2, characterized in that, The first adjustment circuit module includes an eleventh transistor, whose gate is connected to the first pull-down node, whose first terminal is connected to the second power supply voltage, and whose second terminal is connected to the output signal terminal; The second adjustment circuit module includes an eighteenth transistor, whose gate is connected to the second pull-down node, its first terminal is connected to the second power supply voltage, and its second terminal is connected to the output signal terminal.

7. The shift register according to claim 5, characterized in that, The first noise reduction circuit module and the second noise reduction circuit module are also connected to the second drop-down node; The shift register further includes a second adjustment circuit module, which is connected to the second power supply voltage terminal, the second pull-down node and the output signal terminal. It is used to enable the second adjustment circuit module when the second pull-down node is at a high potential, so that the output signal terminal is connected to the intermediate potential between the first power supply voltage and the second power supply voltage. The first adjustment circuit module includes an eleventh transistor, whose gate is connected to the first pull-down node, whose first terminal is connected to the second power supply voltage, and whose second terminal is connected to the output signal terminal; The second adjustment circuit module includes an eighteenth transistor, whose gate is connected to the second pull-down node, whose first terminal is connected to the second power supply voltage, and whose second terminal is connected to the output signal terminal; The channel width-to-length ratio of the eleventh transistor is smaller than that of the sixteenth transistor, and the channel width-to-length ratio of the eighteenth transistor is smaller than that of the seventeenth transistor.

8. The shift register according to claim 1, characterized in that, It also includes a pull-up circuit module; The input circuit module includes a first transistor, whose gate is connected to a first terminal, the first terminal is connected to the input signal terminal, and the second terminal is connected to the pull-up node. The pull-up circuit module includes a third transistor and a first capacitor, wherein: The third transistor has its gate connected to a pull-up node, its first terminal connected to a clock signal terminal, and its second terminal connected to an output signal terminal. The first capacitor has one end connected to the pull-up node and the other end connected to the output signal terminal.

9. The shift register according to claim 3, characterized in that, The reset circuit module includes a first reset sub-circuit module and a second reset circuit module. The first reset sub-circuit module includes a second transistor, and the second reset circuit module includes a fourth transistor, wherein: The second transistor has its gate connected to the first reset signal terminal, its first terminal connected to the first power supply voltage, and its second terminal connected to the pull-up node. The fourth transistor has its gate connected to the second reset signal terminal, its first terminal connected to the first power supply voltage, and its second terminal connected to the output signal terminal.

10. A gate driving circuit, characterized in that, The shift register includes any one of claims 1-9, wherein a plurality of the shift registers are cascaded, wherein: the output signal terminal of the upper-level shift register is connected to the input circuit module of the shift register, and the output signal terminal of the lower-level shift register is connected to the reset circuit module, the first noise reduction circuit module and the second noise reduction circuit module of the shift register.

11. A display device, characterized in that, Includes the gate drive circuit as described in claim 10.

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