Chip power network planning method, device, electronic device and storage medium

Abstract

The present application provides a chip power network planning method, device, electronic device and storage medium, which relates to the field of chip design and manufacturing technology, including: obtaining the line width of the placeholder metal line in the target metal layer; based on the line width of the placeholder metal line, determining multiple power segmentation lines corresponding to the power line in the target metal layer, and the line width of the power segmentation line; based on the line width of the power segmentation line and the layout area of ​​the placeholder metal line in the target metal layer, dynamically planning the layout area of ​​each power segmentation line to obtain the layout area of ​​each power segmentation line in the target metal layer; merging the layout areas of multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer. The method and device provided by the present application reasonably utilize the winding resources in the chip, avoid the local loss of the power grid line network due to the influence of the placeholder metal line, and avoid the risk of voltage drop.

Description

Technical Field

[0001] The present application relates to the technical field of chip design and manufacturing, and in particular to a chip power network planning method, device, electronic device and storage medium. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, intelligent scenarios are becoming more and more abundant. The market's requirements for chips are becoming more and more stringent, and chip technology is developing in the direction of larger scale, lower power consumption, smaller area, and better performance. The more complex the chip, the more significant the performance degradation caused by voltage drop (IR-drop), which will bring many problems in the process of physical implementation, such as difficulty in timing convergence, excessive local power consumption, high temperature, reduced product reliability and even chip failure.

[0003] In the related art, the layout of the power network in the chip is completed by circuit design tools. Without generating Design Rule Check (DRC) violations, the circuit design tools complete the planning of the power network in the chip through one layout. The resulting power network wastes winding resources and has a potential voltage drop risk. Winding resources refer to the number and space of wires or connections that can be used for wiring.

[0004] Therefore, how to reasonably utilize the winding resources in the chip and avoid the risk of voltage drop has become a technical problem that needs to be urgently solved in the industry. Summary of the invention

[0005] The present application provides a chip power network planning method, device, electronic device and storage medium, which are used to solve the technical problem of how to reasonably utilize the winding resources in the chip and avoid the risk of voltage drop.

[0006] The present application provides a chip power network planning method, including:

[0007] Obtaining the line width of a placeholder metal line in a target metal layer;

[0008] Based on the line width of the placeholder metal line, determining a plurality of power segmentation lines corresponding to the power line in the target metal layer, and the line width of the power segmentation lines;

[0009] Based on the line width of the power dividing line and the layout area of ​​the placeholder metal line in the target metal layer, dynamically plan the layout area of ​​each power dividing line to obtain the layout area of ​​each power dividing line in the target metal layer;

[0010] The layout areas of the multiple power segmentation lines corresponding to the power line are merged to obtain the layout area of ​​the power line in the target metal layer.

[0011] In some embodiments, determining a plurality of power segmentation lines corresponding to the power line in the target metal layer and the line width of the power segmentation lines based on the line width of the placeholder metal line includes:

[0012] Determining the line width of the power dividing line based on the line width of the placeholder metal line;

[0013] The number of power dividing lines corresponding to the power line is determined based on the set line width of the power line and the line width of the power dividing line.

[0014] In some embodiments, determining the line width of the power dividing line based on the line width of the placeholder metal line includes:

[0015] The line width of the placeholder metal line is determined as the minimum line width of the power dividing line.

[0016] In some embodiments, the layout area of ​​each power segmentation line is dynamically planned based on the line width of the power segmentation line and the layout area of ​​the placeholder metal line in the target metal layer to obtain the layout area of ​​each power segmentation line in the target metal layer, including:

[0017] Determine the layout area of ​​the power dividing line in the last dynamic planning, and the layout direction of the power dividing line;

[0018] Taking the layout area of ​​the power dividing line in the last dynamic planning as a reference, along the layout direction, taking the line width of the power dividing line as an offset, determining the layout area of ​​the power dividing line in the current dynamic planning;

[0019] The number of dynamic planning of the power supply is determined based on the number of power dividing lines corresponding to the power lines.

[0020] In some embodiments, the layout area of ​​the power dividing line in the previous dynamic planning is used as a reference, and the line width of the power dividing line is used as an offset along the layout direction to determine the layout area of ​​the power dividing line in the current dynamic planning, including:

[0021] Determining a layout area of ​​the placeholder metal line;

[0022] When a layout area of ​​the power dividing line in the current dynamic planning overlaps with a layout area of ​​the placeholder metal line, determining a layout spacing between the power dividing line and the metal line;

[0023] Based on the layout spacing and the layout area of ​​the placeholder metal line, the layout area of ​​the power dividing line in the current dynamic planning is adjusted.

[0024] In some embodiments, after merging the layout areas of the multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer, the method further includes:

[0025] A through hole is provided in the target metal layer; the through hole is used to connect the power supply network of the target metal layer with the power supply networks of other metal layers.

[0026] In some embodiments, the placeholder metal line includes a signal line and / or a clock line.

[0027] The present application provides a chip power network planning device, comprising:

[0028] An acquisition unit, used for acquiring the line width of a placeholder metal line in a target metal layer;

[0029] A segmentation unit, configured to determine a plurality of power segmentation lines corresponding to the power line in the target metal layer and the line width of the power segmentation lines based on the line width of the placeholder metal line;

[0030] A planning unit, configured to dynamically plan the layout area of ​​each power dividing line based on the line width of the power dividing line and the layout area of ​​the placeholder metal line in the target metal layer, so as to obtain the layout area of ​​each power dividing line in the target metal layer;

[0031] The merging unit is used to merge the layout areas of the multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer.

[0032] The present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the chip power network planning method is implemented when the processor executes the program.

[0033] The present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, and the computer program implements the chip power network planning method when executed by a processor.

[0034] The chip power network planning method, device, electronic device and storage medium provided in the present application determine multiple power dividing lines corresponding to the power line in the target metal layer and the line width of the power dividing line according to the line width of the placeholder metal line in the target metal layer; dynamically plan the layout area of ​​each power dividing line according to the line width of the power dividing line and the layout area of ​​the placeholder metal line in the target metal layer to obtain the layout area of ​​each power dividing line in the target metal layer; merge the layout areas of multiple power dividing lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer; because the power line is split to obtain power dividing lines with finer line widths, the positions of the power dividing lines with finer line widths are dynamically planned in the target metal layer, and the layout areas of the power dividing lines are merged to obtain the final layout area of ​​the power line, so that the power line obtained after the merger can make full use of the possible layout positions in the target metal layer, increase the layout area of ​​the power network and the number of layouts of the power line, reasonably utilize the winding resources in the chip, avoid the local loss of the power grid line network due to the influence of the placeholder metal line, and avoid the risk of voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 It is one of the flow charts of the chip power network planning method provided in this application;

[0038] Figure 2 is a schematic cross-sectional view of a chip provided in this application;

[0039] Figure 3 It is a schematic diagram of power supply network planning provided by related technologies;

[0040] Figure 4 It is a schematic diagram of the power network planning provided by this application;

[0041] Figure 5 This is the second flow chart of the chip power network planning method provided by this application;

[0042] Figure 6 It is a structural schematic diagram of the chip power network planning device provided by the present application;

[0043] Figure 7 It is a structural schematic diagram of the electronic device provided by this application. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0045] It should be noted that the terms "first", "second" etc. in the present application are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0046] Power grid mesh (PG mesh) is used to distribute power lines in integrated circuits such as chips. The power grid mesh achieves uniform power distribution by covering the entire chip surface with power lines in a grid. This layout technology can effectively reduce power consumption in the chip, provide a stable power supply, and reduce signal noise interference.

[0047] In the related art, the power grid line network of the chip is realized through mainstream circuit layout design software, and its main goals include: generating a power supply network that can meet the voltage drop (IR-drop) and electromigration (EM) standards; saving winding resources as much as possible, reserving enough merge space for signal lines and clock lines; and clearing DRC violations related to the power grid line network.

[0048] There is a strong correlation between voltage drop and power grid network design. A robust power grid network can significantly reduce the occurrence of voltage drop violations in the later stages of the project. In the physical implementation process, the chip generally undergoes two power grid network layouts. The first is for the functional module (block) level, making the power grid network of the metal layer below the top layer. At this time, the signal line and clock line have not been wound inside the functional module, so the power grid winding resources are sufficient, and the power grid network only needs to be laid out according to the pattern defined by the engineer; the second is to make the top-level power grid network for the chip level. At this stage, since each functional module has passed the timing engineering change order (timing ECO) link, in the case of some critical paths that are difficult to converge, high-level lines may be used to help timing convergence. At the same time, the interconnection between functional modules will also use high-level lines, so there will be signal lines or clock lines occupying the top metal layer. At this time, the power grid network is also laid out according to a fixed pattern. In the area where there is a spacer, due to DRC violations, the circuit layout design software will delete the relevant power network, resulting in a waste of power network winding resources and a potential voltage drop risk.

[0049] According to the above analysis, there are some shortcomings in the design of power grid network at the chip level in the relevant technology:

[0050] (1) When there are signal lines or clock lines occupying the upper layer, according to the DRC rules, the tool will completely delete the power lines in the corresponding area. However, the width of the signal line or clock line is usually much smaller than that of the power line, resulting in a waste of power line winding resources;

[0051] (2) The local loss of the high-level power grid network will reduce the power delivery capacity of the area, causing the voltage drop to deteriorate. If the signal line or clock line occupancy occurs in the voltage drop hot zone, the deterioration will be more serious.

[0052] In order to solve the shortcomings of related technologies, Figure 1 This is one of the flow charts of the chip power network planning method provided by this application, such as Figure 1 As shown, the method includes step 110 , step 120 , step 130 and step 140 .

[0053] Step 110: Obtain the line width of the placeholder metal line in the target metal layer.

[0054] Specifically, the execution subject of the chip power network planning method provided in the embodiment of the present application is a chip power network planning device. The device can be implemented by software, such as a chip power network planning program; or it can be a device for executing the chip power network planning method, such as a mobile terminal, a tablet computer, a desktop computer or a server.

[0055] Figure 2 is a schematic cross-sectional view of a chip provided in this application, such as Figure 2 As shown in FIG. 1 , a chip is usually composed of multiple modules. From a cross-sectional view, a chip is usually a hierarchical structure, that is, it includes multiple metal layers from bottom to top.

[0056] The metal layer is an important component for connecting electronic devices and circuit elements. It is usually made of metal (such as copper) and is plated or deposited on the surface of the substrate. The metal layer establishes physical connections between circuits in the chip through wires, connections and interconnect structures. In each metal layer, there are power lines, ground lines, signal lines and clock lines. For different types of wires, the wires in adjacent metal layers are connected by wires passing through through holes. There are positions for through holes formed on each metal layer, and corresponding welding points correspond to the positions of the through holes.

[0057] The chip power network is an important component of the chip, which is used to power various components in the chip. The target metal layer is the metal layer in the chip that needs to be planned for the chip power network. For example, the target metal layer can be the top layer of the chip. The top layer is used as an example only to facilitate the explanation of the meaning of the metal layer involved in this application, and it is not intended to make unnecessary restrictions on the position of the metal layer in the chip.

[0058] Placeholder metal lines refer to metal conductors that have occupied layout positions in the metal layer, including signal lines and clock lines, etc. Line width refers to the width of the conductor in a metal layer or multiple metal layers in a circuit.

[0059] After metal line layout is performed using circuit layout design software, information such as the position and line width of the placeholder metal line in the target metal layer can be determined based on the layout information.

[0060] Step 120 : determining a plurality of power segmentation lines corresponding to the power line in the target metal layer and the line width of the power segmentation lines based on the line width of the placeholder metal line.

[0061] Specifically, the power line is used in the target metal layer to provide power to the electronic components in the layer. In the chip, the power supply voltage types represented by the power line usually include VDD (Voltage at Drain to Drain) and VSS (Voltageat Source to Source). In the integrated circuit, VDD represents the positive power supply voltage. VSS represents the negative power supply voltage or ground.

[0062] Power lines usually have a certain width. A power splitting line refers to a line obtained by splitting a power line from the perspective of line width. For example, a wider power line can be split into multiple thinner power splitting lines.

[0063] When splitting the power line, the line width of the placeholder metal line may be referred to. For example, the power line may be split according to the line width of the placeholder metal line to obtain multiple power split lines, each of which has a line width equal to the line width of the placeholder metal line.

[0064] Step 130 : dynamically plan the layout area of ​​each power dividing line based on the line width of the power dividing line and the layout area of ​​the placeholder metal line in the target metal layer to obtain the layout area of ​​each power dividing line in the target metal layer.

[0065] Specifically, the layout area refers to the area where the metal line is laid out in the target metal layer. The layout area of ​​the placeholder metal line in the target metal layer is the area where the power dividing line cannot be laid out in the target metal layer.

[0066] First, according to the layout area of ​​the placeholder metal line in the target metal layer, the possible layout area of ​​the power dividing line in the target metal layer is determined; secondly, according to the line width of the power dividing line, dynamic planning is performed in the possible layout area to obtain the layout area of ​​each power dividing line in the target metal layer. The purpose of dynamic planning is to ensure that the layout area of ​​the power dividing line does not conflict with the layout area of ​​the placeholder metal line.

[0067] Step 140: merge the layout areas of the multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer.

[0068] Specifically, after the layout areas of the multiple power segmentation lines corresponding to the power line are determined, the layout areas of the multiple power segmentation lines belonging to the same power line may be merged to obtain the layout areas of the respective power lines in the target metal layer.

[0069] The chip power network planning method provided in the embodiment of the present application determines multiple power dividing lines corresponding to the power line in the target metal layer and the line width of the power dividing line according to the line width of the placeholder metal line in the target metal layer; dynamically plans the layout area of ​​each power dividing line according to the line width of the power dividing line and the layout area of ​​the placeholder metal line in the target metal layer to obtain the layout area of ​​each power dividing line in the target metal layer; merges the layout areas of multiple power dividing lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer; because the power line is split to obtain power dividing lines with finer line widths, the positions of the power dividing lines with finer line widths are dynamically planned in the target metal layer, and the layout areas of the power dividing lines are merged to obtain the final layout area of ​​the power line, so that the power line obtained after the merger can make full use of the possible layout positions in the target metal layer, increase the layout area of ​​the power network and the number of layouts of the power line, reasonably utilize the winding resources in the chip, avoid the local loss of the power grid line network due to the influence of the placeholder metal line, and avoid the risk of voltage drop.

[0070] It should be noted that each implementation method of the present application can be freely combined, the order can be changed, or it can be executed separately, and does not need to rely on or depend on a fixed execution order.

[0071] In some embodiments, based on the line width of the placeholder metal line, determining a plurality of power segmentation lines corresponding to the power line in the target metal layer and the line width of the power segmentation lines includes:

[0072] Determine the line width of the power dividing line based on the line width of the placeholder metal line;

[0073] Based on the set line width of the power line and the line width of the power dividing line, the number of power dividing lines corresponding to the power line is determined.

[0074] Specifically, the smaller the line width of the power dividing line, the smaller the layout area of ​​the power dividing line, and the more possible layout positions in the target metal layer can be utilized, which can improve the utilization rate of the winding resources in the chip. However, the smaller the line width of the power dividing line, the more times the power line is divided, and the more computing resources are required for dynamic planning of the layout area of ​​each power dividing line, and the time to execute dynamic planning using the program will also be longer.

[0075] Therefore, the line width of the power dividing line can be determined according to the line width of the placeholder metal line, for example, the line width of the power dividing line can be set equal to the line width of the placeholder metal line. The set line width of the power line can be divided by the line width of the power dividing line to obtain the number of power dividing lines corresponding to the power line. The set line width refers to the line width set by the user in the circuit layout design software.

[0076] The chip power network planning method provided in the embodiment of the present application determines the line width of the power segmentation line according to the line width of the placeholder metal line, and finally determines the number of power segmentation lines corresponding to the power line, thereby improving the efficiency of chip power network planning.

[0077] In some embodiments, determining the line width of the power dividing line based on the line width of the placeholder metal line includes:

[0078] The line width of the placeholder metal line is determined as the minimum line width of the power dividing line.

[0079] Specifically, in the process of segmenting the power line, the line width of the power segmentation line can also be flexibly set. For example, the line width of the placeholder metal line can be determined as the minimum line width of the power segmentation line, so that the circuit layout design software can be flexibly selected according to the layout needs, and a balance can be achieved between improving the utilization of winding resources and reducing the execution time of dynamic programming.

[0080] The chip power network planning method provided in the embodiment of the present application determines the line width of the placeholder metal line as the minimum line width of the power dividing line, takes into account the utilization rate of the winding resources and the influence of the execution time of dynamic planning, and improves the efficiency of the chip power network planning.

[0081] In some embodiments, based on the line width of the power segmentation line and the layout area of ​​the placeholder metal line in the target metal layer, the layout area of ​​each power segmentation line is dynamically planned to obtain the layout area of ​​each power segmentation line in the target metal layer, including:

[0082] Determine the layout area of ​​the power dividing line in the last dynamic planning, and the layout direction of the power dividing line;

[0083] Taking the layout area of ​​the power dividing line in the previous dynamic planning as a reference, along the layout direction, taking the line width of the power dividing line as an offset, determine the layout area of ​​the power dividing line in the current dynamic planning;

[0084] The number of dynamic planning times of the power supply is determined based on the number of power dividing lines corresponding to the power lines.

[0085] Specifically, the number of dynamic planning of the power supply can be determined according to the number of power dividing lines corresponding to the power supply line. The layout direction of the power dividing line refers to the moving direction of the power dividing line when it is laid out in the chip.

[0086] Before the current dynamic planning is performed, the layout area of ​​the power dividing line in the previous dynamic planning is obtained, and the layout direction of the power dividing line is determined according to the relevant settings in the circuit layout design software. The layout area of ​​the power dividing line in the previous dynamic planning is used as a reference, that is, the starting position of the power dividing line in the current dynamic planning, and the layout area of ​​the power dividing line in the current dynamic planning is determined along the layout direction with the line width of the power dividing line as an offset.

[0087] Through multiple dynamic planning, the layout area of ​​multiple power dividing lines corresponding to the power lines in the target metal layer is finally determined.

[0088] The chip power network planning method provided in the embodiment of the present application takes the layout area of ​​the power dividing line in the previous dynamic planning as a reference, and determines the layout area of ​​the power dividing line in the current dynamic planning along the layout direction with the line width of the power dividing line as an offset. Through multiple dynamic planning, the layout areas of multiple power dividing lines corresponding to the power lines in the target metal layer are determined, which can make maximum use of the possible layout positions in the target metal layer, thereby increasing the layout area of ​​the power network and the number of layouts of the power lines.

[0089] In some embodiments, the layout area of ​​the power dividing line in the previous dynamic planning is used as a reference, and the line width of the power dividing line is used as an offset along the layout direction to determine the layout area of ​​the power dividing line in the current dynamic planning, including:

[0090] Determine a layout area for a placeholder metal line;

[0091] When a layout area of ​​the power dividing line overlaps with a layout area of ​​the placeholder metal line in the current dynamic planning, determining a layout spacing between the power dividing line and the metal line;

[0092] Based on the layout spacing and the layout area of ​​the placeholder metal line, the layout area of ​​the power dividing line in the current dynamic planning is adjusted.

[0093] Specifically, in the process of determining the layout area of ​​the power dividing line in the current dynamic planning, it is first necessary to determine the layout area of ​​the placeholder metal line. If the layout area of ​​the power dividing line in the current dynamic planning overlaps with the layout area of ​​the placeholder metal line, it is necessary to determine the layout spacing between the power dividing line and the metal line. The layout spacing refers to the distance between the layout areas of different metal lines. In the circuit layout design software, the layout spacing can be determined by setting according to the electrical parameters of the power line and the placeholder metal line.

[0094] According to the layout spacing and the layout area of ​​the placeholder metal line, the layout area of ​​the power dividing line in the current dynamic planning is adjusted, for example, the layout area of ​​the placeholder metal line and the range of the layout spacing are determined as the non-layout area of ​​the power dividing line, and the power dividing line is no longer planned in this non-layout area. That is, in the current dynamic planning, the power dividing line may not be continuous, but disconnected.

[0095] If the layout area of ​​the power dividing line does not overlap with the layout area of ​​the placeholder metal line in the current dynamic planning, a complete and continuous power dividing line can be directly laid out.

[0096] The chip power network planning method provided in the embodiment of the present application determines the layout spacing between the power dividing line and the metal line when the layout area of ​​the power dividing line in the current dynamic planning overlaps with the layout area of ​​the placeholder metal line; according to the layout spacing and the layout area of ​​the placeholder metal line, the layout area of ​​the power dividing line in the current dynamic planning is adjusted, so that the power dividing line can make full use of the possible layout position in the target metal layer, thereby increasing the layout area of ​​the power network and the number of layouts of the power lines.

[0097] The following is a comparative explanation of the specific process of power line planning in the related technology and the present application.

[0098] In the related art, the power network planning in the chip is usually completed in one layout. Figure 3 It is a schematic diagram of power network planning provided by related technologies, such as Figure 3 As shown in the figure, it is a top view of the top layer of the chip, in which the dotted box is the placeholder metal line and the solid box is the power line. In the top layer of the chip, for the layout area where the placeholder metal line exists, due to the constraints of DRC rules, the circuit layout software tool will delete the related power line, resulting in a waste of winding resources and a potential voltage drop risk.

[0099] The power network planning provided in the present application is implemented through multiple dynamic planning, that is, a wider power line is divided into several thinner power dividing lines, and then implemented through multiple layouts. Figure 4 This is a schematic diagram of the power network planning provided by this application, such as Figure 4 As shown in the figure, it is a top view of the top layer of the chip. The dotted line frame in the figure is a placeholder metal line, and the solid line frame is a power line or a power dividing line. Taking the example of dividing a wider power line into three thinner power dividing lines, the layout process generally includes:

[0100] Step 410, layout the first power dividing line according to the layout area of ​​the placeholder metal line;

[0101] Step 420: layout the second power dividing line according to the layout area of ​​the first power dividing line, that is, shift the power dividing line obtained by the first layout upward by the line width of one power dividing line;

[0102] Step 430: layout the third power dividing line according to the layout area of ​​the second power dividing line, that is, shift the power dividing line obtained by the first layout upward by the line width of two power dividing lines;

[0103] Step 440: merge the layout areas where the three thinner power dividing lines are located to obtain the final layout area of ​​the wider power line in the top layer.

[0104] From a physical point of view, there is no substantial difference between multiple thinner power dividers and one wider power divider. However, from the perspective of back-end design, each power divider is an independent power divider, and its information needs to be recorded separately, wasting disk space. The integration method is: extract the shape of the layout area of ​​the power divider, create a new metal line based on this shape, give the metal line the properties of the power line, and delete the previous power divider.

[0105] In some embodiments, after merging the layout areas of the multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer, the method further includes:

[0106] A through hole is set in the target metal layer; the through hole is used to connect the power network of the target metal layer and the power network of other metal layers.

[0107] Specifically, vias can be set in the target metal layer. The power lines in adjacent metal layers are connected by wires passing through the vias, and the power network of the target metal layer and the power network of the remaining metal layers can be connected, so that the power lines of each metal layer in the chip can be connected to form a complete power network, providing better signal integrity and anti-interference performance, and reducing potential electromagnetic interference.

[0108] In some embodiments, the placeholder metal lines include signal lines and / or clock lines.

[0109] Specifically, in a chip, signal lines are lines used to transmit data or control information. They can transmit various types of signals, such as analog signals, digital signals, or control signals. Clock lines are used to synchronize the operation of various components in the circuit. Clock signals are usually used to indicate the timing of data transmission or the rhythm of operation. Clock signals are very important because they determine the operation time of each component so that data can be processed in the correct timing.

[0110] In the chip design process, when integrating various modules (Blocks) into a chip, signal lines and / or clock lines are usually first laid out on the top layer of the chip. Therefore, the signal lines and / or clock lines become placeholder metal lines.

[0111] Figure 5 This is the second flow chart of the chip power network planning method provided by this application, such as Figure 5 As shown, the method can be implemented by circuit design software, including:

[0112] Step 510, setting layout parameters of the power lines, including the line width (width) of VDD and VSS, the layout pitch (i.e., the distance between two adjacent VDD or VSS) and the offset (i.e., the distance between the first VDD and the first VSS and the edge of the chip);

[0113] Step 520, refer to the width of the placeholder metal line to set the minimum width of the power line after cutting. Theoretically, the narrower the cut power line is, the higher the power line winding resource utilization rate of the corresponding placeholder metal line area is. However, if the power line is too narrow, it will lead to a longer program execution time. Considering the balance between the power line winding resource utilization rate and the program execution time, it is more appropriate to set the minimum width of the cut power line close to the width of the placeholder metal line.

[0114] Step 530: Define the layout pattern and layout strategy of the power network according to the above-mentioned parameters. It is necessary to specify the metal layer, layout direction, line width, layout pitch, offset and power voltage type (net, including VDD or VSS) of the power line layout.

[0115] Step 540: Perform dynamic planning according to the defined layout strategy. The offset increment of each layout is the minimum power line width after cutting. After the layout is completed, each power line is in the form of multiple narrow power dividing lines together. At this time, the area near the placeholder metal line will also be filled with power lines, which greatly improves the utilization rate of winding resources.

[0116] Step 550, integrating the power split lines into one power line;

[0117] Step 560: Punch corresponding layers of vias for the power lines in the chip and connect them to ensure the continuity of the power lines.

[0118] The chip power network planning method provided in this application has the following beneficial effects:

[0119] (1) The chip power network planning method can be implemented through a scripting language (such as Tool Command Language, TCL) and implemented in multiple circuit design software, with strong portability;

[0120] (2) Through the dynamic programming method, without introducing DRC violations, the local power line missing caused by the high-level metal line occupation in the power network layout method in the related technology is filled. The power line cutting width can be flexibly set according to the characteristics of the occupied metal line to maximize the utilization of winding resources;

[0121] (3) By filling the missing power lines caused by high-level metal line occupation, the power line layout strength is increased without affecting the design timing, generating DRC violations, and occupying additional signal line or clock line winding resources, thus avoiding the risk of voltage drop. In particular, when the metal line occupation occurs in the voltage drop hot zone, the optimization effect of the voltage drop in the corresponding area is more obvious.

[0122] (4) The laid-out power lines are integrated. There is no need to record the layout information of each power line separately. Instead, only the layout information of the integrated power lines needs to be recorded, thereby avoiding a waste of disk space.

[0123] The device provided in the embodiment of the present application is described below. The device described below and the method described above can refer to each other.

[0124] Figure 6 is a schematic diagram of the structure of the chip power network planning device provided by the present application, such as Figure 6 As shown, the device comprises:

[0125] An acquisition unit 610 is used to acquire the line width of a placeholder metal line in a target metal layer;

[0126] A segmentation unit 620, configured to determine a plurality of power segmentation lines corresponding to the power lines in the target metal layer and the line widths of the power segmentation lines based on the line widths of the placeholder metal lines;

[0127] A planning unit 630, configured to dynamically plan the layout area of ​​each power dividing line based on the line width of the power dividing line and the layout area of ​​the placeholder metal line in the target metal layer, so as to obtain the layout area of ​​each power dividing line in the target metal layer;

[0128] The merging unit 640 is used to merge the layout areas of the multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer.

[0129] The chip power network planning device provided in the embodiment of the present application determines multiple power segmentation lines corresponding to the power line in the target metal layer and the line width of the power segmentation line according to the line width of the placeholder metal line in the target metal layer; dynamically plans the layout area of ​​each power segmentation line according to the line width of the power segmentation line and the layout area of ​​the placeholder metal line in the target metal layer to obtain the layout area of ​​each power segmentation line in the target metal layer; merges the layout areas of multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer; because the power line is split to obtain power segmentation lines with finer line widths, the positions of the power segmentation lines with finer line widths are dynamically planned in the target metal layer, and the layout areas of the power segmentation lines are merged to obtain the final layout area of ​​the power line, so that the power line obtained after the merger can make full use of the possible layout positions in the target metal layer, increase the layout area of ​​the power network and the number of layouts of the power line, reasonably utilize the winding resources in the chip, avoid the local loss of the power grid line network due to the influence of the placeholder metal line, and avoid the risk of voltage drop.

[0130] In some embodiments, the segmentation unit is configured to:

[0131] Determine the line width of the power dividing line based on the line width of the placeholder metal line;

[0132] Based on the set line width of the power line and the line width of the power dividing line, the number of power dividing lines corresponding to the power line is determined.

[0133] In some embodiments, the segmentation unit is configured to:

[0134] The line width of the placeholder metal line is determined as the minimum line width of the power dividing line.

[0135] In some embodiments, the planning unit is configured to:

[0136] Determine the layout area of ​​the power dividing line in the last dynamic planning, and the layout direction of the power dividing line;

[0137] Taking the layout area of ​​the power dividing line in the previous dynamic planning as a reference, along the layout direction, taking the line width of the power dividing line as an offset, determine the layout area of ​​the power dividing line in the current dynamic planning;

[0138] The number of dynamic planning times of the power supply is determined based on the number of power dividing lines corresponding to the power lines.

[0139] In some embodiments, the planning unit is configured to:

[0140] Determine a layout area for a placeholder metal line;

[0141] When a layout area of ​​the power dividing line overlaps with a layout area of ​​the placeholder metal line in the current dynamic planning, determining a layout spacing between the power dividing line and the metal line;

[0142] Based on the layout spacing and the layout area of ​​the placeholder metal line, the layout area of ​​the power dividing line in the current dynamic planning is adjusted.

[0143] In some embodiments, the device is also used to:

[0144] A through hole is set in the target metal layer; the through hole is used to connect the power network of the target metal layer and the power network of other metal layers.

[0145] In some embodiments, the placeholder metal lines include signal lines and / or clock lines.

[0146] Figure 7 is a schematic diagram of the structure of the electronic device provided by this application, such as Figure 7 As shown, the electronic device may include: a processor (Processor) 710, a communication interface (Communications Interface) 720, a memory (Memory) 730 and a communication bus (Communications Bus) 740, wherein the processor 710, the communication interface 720, and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic command in the memory 730 to execute the method described in the above embodiment, for example:

[0147] Obtain the line width of the placeholder metal line in the target metal layer; determine multiple power segmentation lines corresponding to the power line in the target metal layer and the line width of the power segmentation line based on the line width of the placeholder metal line; dynamically plan the layout area of ​​each power segmentation line based on the line width of the power segmentation line and the layout area of ​​the placeholder metal line in the target metal layer to obtain the layout area of ​​each power segmentation line in the target metal layer; merge the layout areas of the multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer.

[0148] In addition, the logic commands in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art, and the computer software product is stored in a storage medium, including several commands to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk.

[0149] The processor in the electronic device provided in the embodiment of the present application can call the logic instructions in the memory to implement the above method. Its specific implementation method is consistent with the implementation method of the aforementioned method and can achieve the same beneficial effects, which will not be repeated here.

[0150] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the methods provided in the above embodiments are implemented.

[0151] Its specific implementation is consistent with the aforementioned method implementation and can achieve the same beneficial effects, so it will not be repeated here.

[0152] An embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, the method provided in the above embodiments is implemented.

[0153] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0154] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip power network planning method, characterized in that: include: Obtaining the line width of a placeholder metal line in a target metal layer; Based on the line width of the placeholder metal line, determining a plurality of power segmentation lines corresponding to the power line in the target metal layer, and the line width of the power segmentation lines; Based on the line width of the power dividing line and the layout area of ​​the placeholder metal line in the target metal layer, dynamically plan the layout area of ​​each power dividing line to obtain the layout area of ​​each power dividing line in the target metal layer; Merging the layout areas of the multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer; The dynamically planning the layout area of ​​each power segmentation line based on the line width of the power segmentation line and the layout area of ​​the placeholder metal line in the target metal layer to obtain the layout area of ​​each power segmentation line in the target metal layer includes: Determine the layout area of ​​the power dividing line in the last dynamic planning, and the layout direction of the power dividing line; The layout area of ​​the power dividing line in the previous dynamic planning is used as a reference, and the layout area of ​​the power dividing line in the current dynamic planning is determined along the layout direction and with the line width of the power dividing line as an offset.

2. The chip power network planning method according to claim 1, characterized in that: The determining, based on the line width of the placeholder metal line, a plurality of power segmentation lines corresponding to the power line in the target metal layer and the line width of the power segmentation lines comprises: Determining the line width of the power dividing line based on the line width of the placeholder metal line; The number of power dividing lines corresponding to the power line is determined based on the set line width of the power line and the line width of the power dividing line.

3. The chip power network planning method according to claim 2, characterized in that: The determining the line width of the power dividing line based on the line width of the placeholder metal line includes: The line width of the placeholder metal line is determined as the minimum line width of the power dividing line.

4. The chip power network planning method according to claim 2, characterized in that: The number of dynamic planning of power supply is determined based on the number of power segmentation lines corresponding to the power lines.

5. The chip power network planning method according to claim 4, characterized in that: The method of determining the layout area of ​​the power dividing line in the current dynamic planning by taking the layout area of ​​the power dividing line in the previous dynamic planning as a reference and taking the line width of the power dividing line as an offset along the layout direction comprises: Determining a layout area of ​​the placeholder metal line; When a layout area of ​​the power dividing line in the current dynamic planning overlaps with a layout area of ​​the placeholder metal line, determining a layout spacing between the power dividing line and the metal line; Based on the layout spacing and the layout area of ​​the placeholder metal line, the layout area of ​​the power dividing line in the current dynamic planning is adjusted.

6. The chip power network planning method according to any one of claims 1 to 5, characterized in that: After merging the layout areas of the plurality of power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer, the method further includes: A through hole is provided in the target metal layer; the through hole is used to connect the power supply network of the target metal layer with the power supply networks of other metal layers.

7. The chip power network planning method according to any one of claims 1 to 5, characterized in that: The placeholder metal lines include signal lines and / or clock lines.

8. A chip power network planning device, characterized in that: include: An acquisition unit, used for acquiring the line width of a placeholder metal line in a target metal layer; A segmentation unit, configured to determine a plurality of power segmentation lines corresponding to the power line in the target metal layer and the line width of the power segmentation lines based on the line width of the placeholder metal line; A planning unit, configured to dynamically plan the layout area of ​​each power dividing line based on the line width of the power dividing line and the layout area of ​​the placeholder metal line in the target metal layer, so as to obtain the layout area of ​​each power dividing line in the target metal layer; A merging unit, used for merging the layout areas of the multiple power segmentation lines corresponding to the power line to obtain the layout area of ​​the power line in the target metal layer; The planning unit is used to determine the layout area of ​​the power dividing line and the layout direction of the power dividing line in the last dynamic planning; The layout area of ​​the power dividing line in the previous dynamic planning is used as a reference, and the layout area of ​​the power dividing line in the current dynamic planning is determined along the layout direction and with the line width of the power dividing line as an offset.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the chip power network planning method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the chip power network planning method according to any one of claims 1 to 7 is implemented.

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