Display device and display driving method

Abstract

A display apparatus and a display driving method are provided. The display apparatus can include a plurality of sub-pixels connected to the data lines, respectively; a data driving circuit configured to convert compensated digital image data into analog data voltages and to supply the analog data voltages to the data lines; a large capacity memory configured to store initial compensation data based on a characteristic value of each of the plurality of sub-pixels; a high speed memory configured to store sampled compensation data sampled from the initial compensation data of less than all of the plurality of sub-pixels in one frame; and a timing controller configured to control the data driving circuit, to determine final compensation data based on at least one of the sampled compensation data and the initial compensation data, and to output the compensated digital image data based on input image data and the final compensation data. Accordingly, the size of the memory and power consumption can be reduced.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0188775, filed on December 29, 2022, the disclosure of which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device and a display driving method, and more specifically, to a display device and a display driving method capable of reducing memory size and power consumption. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing. Various types of display devices, such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), are being utilized.

[0005] Among these display devices, organic light-emitting display devices use self-emissive organic light-emitting diodes (OLEDs) as light-emitting elements, thus providing advantages such as fast response and better contrast, luminous efficiency, brightness, and viewing angle.

[0006] An organic light-emitting diode (OLED) display includes organic light-emitting diodes arranged in sub-pixels on a display panel, and the brightness of each sub-pixel is controlled and an image is displayed by controlling the current flowing to the organic light-emitting diodes to make them emit light.

[0007] Subpixels are driven by a scan signal applied through gate lines, and gray levels are represented by data voltage applied through data lines when the scan signal is applied, thereby displaying an image.

[0008] Sub-pixels of a display device include driving transistors that control the current flowing through a light-emitting element. These driving transistors can be implemented as thin-film transistors (TFTs). In this case, it is preferable that the electrical characteristics of the driving transistors, such as threshold voltage and mobility, are designed to be the same across all sub-pixels. However, due to factors such as process conditions and driving environment, the electrical characteristics of the sub-pixels may be non-uniform.

[0009] Methods for compensating for variations in the eigenvalues ​​of sub-pixels can generally be categorized into internal compensation methods and external compensation methods. Internal compensation methods automatically compensate for threshold voltage deviations between the driving transistors within the sub-pixel circuit. For internal compensation, since the current flowing through the light-emitting element must be determined regardless of the threshold voltage of the driving transistors, the configuration of the sub-pixel circuit can become more complex.

[0010] The external compensation method senses the electrical characteristics between the driving transistors and, based on the sensing results, compensates for changes in the feature values ​​of each sub-pixel by modulating the data voltage through a compensation circuit outside the display panel. In this case, for external compensation, the compensation data used to compensate for changes in the feature values ​​of each sub-pixel is stored in memory.

[0011] Furthermore, with the improvement of display performance, the demand for large-area, high-resolution display devices is gradually increasing. Therefore, as the area or resolution of the display device increases, the size of the memory used to store compensation data for changes in the feature values ​​of the compensating sub-pixels can increase, and the power consumption can increase accordingly. Summary of the Invention

[0012] Therefore, embodiments of this disclosure relate to a display device and its driving method that substantially overcome one or more problems caused by limitations and drawbacks of related technologies. For example, the inventors of this disclosure have invented a low-power display device and display driving method capable of reducing the power consumption and size of the memory used to store compensation data for storing feature values ​​of compensation sub-pixels.

[0013] Embodiments of this disclosure may provide a low-power display device and display driving method capable of reducing the power consumption and size of memory used for high-speed processing by sampling and processing overall compensation data of feature values ​​of sub-pixels at regular intervals.

[0014] Embodiments of this disclosure may also provide a low-power display device and display driving method capable of enhancing the compensation performance of sub-pixel eigenvalues ​​by applying sampled compensation data on a per-frame basis and using predictive compensation data in the intervals between sampled compensation data.

[0015] The features and aspects of this disclosure are not limited to those described above. Additional features and aspects will be set forth in part in the description which follows, and in part from the description, which will become apparent to those skilled in the art, or may be learned from practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be recognized and obtained from the structures specifically pointed out in the specification, claims, and drawings, or may be inferred from the specification, claims, and drawings.

[0016] To achieve these and other advantages and for the purposes of this disclosure, as implemented and broadly described herein, a display device may include: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels respectively connected to the plurality of gate lines and the plurality of data lines; a gate driving circuit configured to supply a scan signal to the plurality of gate lines; a data driving circuit configured to convert compensated digital image data into an analog data voltage and configured to supply the analog data voltage to the plurality of data lines; a mass storage memory configured to store initial compensation data based on feature values ​​of each of the plurality of sub-pixels; a high-speed memory configured to store sampled compensation data sampled in a frame from the initial compensation data of fewer sub-pixels than all of the plurality of sub-pixels; and a timing controller configured to: control the gate driving circuit and the data driving circuit to determine final compensation data based on at least one of the sampled compensation data and the initial compensation data, and to output the compensated digital image data based on input image data and the final compensation data.

[0017] In another aspect of this disclosure, a method for driving a display device having a plurality of sub-pixels may include: storing initial compensation data of each of the plurality of sub-pixels in a large-capacity memory; sampling initial compensation data of sub-pixels with fewer sub-pixels than all of the plurality of sub-pixels in a frame; storing sampled compensation data of the sub-pixels with fewer sub-pixels than all of the plurality of sub-pixels in a high-speed memory in the frame; determining final compensation data of the plurality of sub-pixels based on at least one of the initial compensation data and the sampled compensation data; and compensating for changes in feature values ​​of the plurality of sub-pixels based on the final compensation data.

[0018] In another aspect of this disclosure, a display device may include: a display panel including a plurality of data lines and a plurality of sub-pixels respectively connected to the plurality of data lines; a data driving circuit configured to apply a data voltage to the plurality of data lines based on compensated image data; a mass storage memory configured to store initial compensation data based on feature values ​​of each of the plurality of sub-pixels; a high-speed memory configured to store sampled compensation data; and a timing controller configured to control the data driving circuit to determine final compensation data based on at least one of the sampled compensation data and the initial compensation data, and to output the compensated image data based on input image data and the final compensation data. The timing controller may be further configured to: sample the initial compensation data of the (n+1)th sub-pixel among the plurality of sub-pixels in the (n+1)th frame, and store the sampled compensation data of the (n+1)th sub-pixel in the high-speed memory; and sample the initial compensation data of the (n+2)th sub-pixel among the plurality of sub-pixels in the (n+2)th frame, and store the sampled compensation data of the (n+2)th sub-pixel in the high-speed memory; where n is an integer greater than or equal to 0.

[0019] According to embodiments of this disclosure, a low-power display device and display driving method can be provided that can reduce the power consumption and size of the memory used to store compensation data for storing feature values ​​of compensation sub-pixels.

[0020] According to embodiments of this disclosure, a low-power display device and display driving method can be provided that can reduce the power consumption and size of memory used for high-speed processing by sampling and processing overall compensation data of feature values ​​of sub-pixels at regular intervals.

[0021] According to embodiments of this disclosure, a low-power display device and display driving method can be provided that can enhance the compensation performance of sub-pixel eigenvalues ​​by applying sampling compensation data on a frame-by-frame basis and using prediction compensation data in the intervals between the sampling compensation data.

[0022] It will be understood that the foregoing general description and the following detailed description of this disclosure are both illustrative and intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0023] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and form a part of this application, illustrate various embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0024] Figure 1 This is a schematic diagram illustrating the configuration of a display device according to various exemplary embodiments of the present disclosure;

[0025] Figure 2 This is an example diagram illustrating a system of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 3 This is an illustration of an example of a circuit constituting a sub-pixel in a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 4 This is a diagram illustrating an example of a compensation circuit for a display device according to an embodiment of the present disclosure;

[0028] Figure 5 This is a block diagram illustrating an example of using compensation data stored in memory to compensate image data in a related technology display device;

[0029] Figure 6 This is a block diagram illustrating an example of generating image data by sampling compensation data stored in a memory in a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 7 This is a flowchart illustrating an exemplary embodiment of the display driving method according to the present disclosure;

[0031] Figure 8 This is an illustration of an example of initial compensation data stored in a large-capacity memory (LCM) in a display driving method according to an exemplary embodiment of the present disclosure;

[0032] Figure 9 This is a diagram illustrating an example process of sampling initial compensation data in units of 1 / 4 of each frame sub-pixel in a display driving method according to an exemplary embodiment of the present disclosure;

[0033] Figure 10 This is a diagram illustrating an example process of generating prediction compensation data in a display driving method according to an example embodiment of the present disclosure;

[0034] Figure 11 This is an illustration of an example of predicting compensation data in a display driving method according to an exemplary embodiment of the present disclosure;

[0035] Figure 12 This is a diagram illustrating the result of mitigating compensation errors by predicting compensation data in a display driving method according to an exemplary embodiment of the present disclosure;

[0036] Figure 13This is a diagram illustrating an example process of applying exception compensation data in a display driving method according to an exemplary embodiment of the present disclosure; and

[0037] Figure 14 This is an illustration of an example of generating final compensation data by applying exception compensation data to a specific frame in a display driving method according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0038] In the following description of exemplary embodiments of this disclosure, accompanying drawings illustrating specific exemplary embodiments that can be implemented are shown. However, such illustrations are by way of example, and this disclosure is not limited to such specific exemplary embodiments. Unless otherwise described, the same reference numerals and symbols refer to the same or similar parts, even if they are shown in different drawings.

[0039] Furthermore, in the following description, a detailed description of a known function or configuration may be omitted where such a description might obscure some important points of this disclosure.

[0040] When using terms such as “including,” “having,” “comprising,” “forming,” etc., one or more additional elements may be added, unless a more restrictive term such as “only” is used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context clearly indicates otherwise.

[0041] Although the terms “first,” “second,” A, B, (a), and (b), etc., may be used herein to describe various elements, these elements, such as their nature, order, sequence, or number, should not be construed as being limited by these terms as they are not used to define them. These terms are used only to distinguish one element from another. Without departing from the scope of the disclosure, for example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0042] When an element or layer is described as being “connected to,” “bonded to,” “adhere to,” “contact with,” or “overlapped” with another element or layer, the element or layer may not only be directly connected to, bonded to, or adhered to, or directly contact or overlap the other element or layer, but may also be indirectly connected to, bonded to, or adhered to, or directly contact or overlap the other element or layer by “setting” or “inserting” one or more intermediate elements or layers between these elements or layers, unless otherwise stated.

[0043] When the temporal relationship between processes, methods, operations, processes, steps, events, etc. is described as such as "after", "following", "next", or "before", the relationship covers not only continuous or sequential order, but also non-continuous or non-sequential relationships, unless more restrictive terms such as "immediately" or "directly" are also used.

[0044] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to describe various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the examples shown in the accompanying drawings.

[0045] Furthermore, when interpreting a component, even without an explicit description of such an error or tolerance range, the component (including its dimensions and relative size) should be interpreted as including a normal error or tolerance range. Tolerances or error ranges can be caused by a variety of factors, such as process factors, internal or external shocks, noise, etc. Additionally, the term "can" fully encompasses all the meanings of the term "can".

[0046] Implementations of this disclosure will now be described in detail with reference to examples thereof, which can be illustrated in the accompanying drawings.

[0047] Figure 1 This is a schematic diagram illustrating the configuration of a display device according to various exemplary embodiments of the present disclosure.

[0048] like Figure 1 As shown, a display device 100 according to an exemplary embodiment of this disclosure may include: a display panel 110, in which multiple gate lines GL and data lines DL are connected; and multiple sub-pixels SP arranged in a matrix. The display device 100 may further include: a gate driving circuit 120 for driving the multiple gate lines GL; a data driving circuit 130 for supplying data voltage through the multiple data lines DL; a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0049] The display panel 110 can display images based on scan signals transmitted from the gate drive circuit 120 via multiple gate lines GL and data voltages transmitted from the data drive circuit 130 via multiple data lines DL.

[0050] In the case of a liquid crystal display, the display panel 110 may include a liquid crystal layer formed between two substrates and can operate in any known mode such as twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or edge field switching (FFS) mode. In the case of an organic light-emitting display, the display panel 110 may be implemented as a top-emitting scheme, a bottom-emitting scheme, or a dual-emitting scheme.

[0051] In the display panel 110, multiple pixels can be arranged in a matrix, and each pixel can include sub-pixels SP with different colors, such as white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels. Each sub-pixel SP can be defined by multiple data lines DL and multiple gate lines GL.

[0052] A sub-pixel SP may include, for example, a thin-film transistor (TFT) formed at the intersection between a corresponding data line DL and a corresponding gate line GL, a light-emitting element such as an organic light-emitting diode charged with a data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the data voltage.

[0053] For example, if a display device 100 with a resolution of 2160 x 3840 includes three sub-pixels SP (red, green, and blue), then 3840 data lines DL can be connected to 2160 gate lines GL and the three sub-pixels RGB. Therefore, in this example configuration, 3840 x 3 = 11520 data lines DL can be provided. Each sub-pixel SP can be located at the intersection between the corresponding gate line GL and the corresponding data line DL.

[0054] The gate drive circuit 120 can be controlled by the timing controller 140 to sequentially output scan signals to multiple gate lines GL disposed in the display panel 110, thereby controlling the driving timing of multiple sub-pixels SP.

[0055] In the example display device 100 with a resolution of 2160 x 3840, sequentially outputting scan signals from the first gate line to the 2160th gate line GL can be referred to as a 2160-phase drive operation. Sequentially outputting scan signals to each unit of four gate lines GL, for example, after sequentially outputting scan signals to the first to fourth gate lines, sequentially outputting scan signals to the fifth to eighth gate lines, can be referred to as a 4-phase drive operation. In other words, sequentially outputting scan signals to every Nth gate line GL can be referred to as an N-phase drive operation.

[0056] The gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs). Depending on the implemented driving scheme, the gate driving circuit 120 may be located only on one side of the display panel 110, or it may be located on each of two opposite sides of the display panel 110. The gate driving circuit 120 may be implemented as a gate in-panel (GIP) and integrated into the bezel area of ​​the display panel 110.

[0057] The data driving circuit 130 can receive image data DATA from the timing controller 140 and convert the received image data DATA into an analog data voltage. Then, as the data voltage is output to each data line DL when a scan signal is applied through the corresponding gate line GL, each sub-pixel SP connected to the data line DL can display a light emission signal with a brightness corresponding to the data voltage.

[0058] Similarly, the data driver circuit 130 may include one or more source driver integrated circuits (SDICs). The source driver integrated circuits (SDICs) may be connected to the bonding pads of the display panel 110 in a tape-on-board (TAB) type or a chip-on-glass (COG) type, or may be directly disposed on the display panel 110.

[0059] In some cases, each source driver integrated circuit (SDIC) can be integrated and disposed on the display panel 110. Furthermore, each source driver integrated circuit (SDIC) can be implemented as a chip-on-film (COF) type, in which each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL of the display panel 110 via the circuit film.

[0060] The timing controller 140 can provide various control signals to the gate drive circuit 120 and the data drive circuit 130 and can control the operation of the gate drive circuit 120 and the data drive circuit 130. In other words, the timing controller 140 can control the gate drive circuit 120 to output a scan signal according to the timing implemented in each frame, and can transmit image data DATA received from an external source to the data drive circuit 130.

[0061] In this configuration, the timing controller 140 can receive various timing signals, including, for example, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the master clock MCLK, as well as image data DATA, from the external host system 200.

[0062] The host system 200 can be any of, but is not limited to, a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0063] Therefore, the timing controller 140 can generate control signals based on various timing signals received from the host system 200, and can transmit the control signals to the gate drive circuit 120 and the data drive circuit 130.

[0064] For example, timing controller 140 may output various gate control signals, including, for example, a gate start pulse (GSP), a gate clock (GCLK), and a gate output enable signal (GOE), to control gate drive circuit 120. The gate start pulse (GSP) may control the timing of the start of operation of one or more gate driver integrated circuits (GDICs) constituting gate drive circuit 120. The gate clock (GCLK) may be a clock signal commonly input to one or more gate driver integrated circuits (GDICs) to control the shift timing of scan signals. The gate output enable signal (GOE) may specify timing information regarding one or more gate driver integrated circuits (GDICs).

[0065] The timing controller 140 can also output various data control signals, including, for example, a source start pulse (SSP), a source clock (SCLK), and a source output enable signal (SOE), to control the data drive circuit 130. The source start pulse (SSP) can control the timing of data sampling for one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source clock (SCLK) can be a clock signal that controls the timing of data sampling in the source driver integrated circuits (SDICs). The source output enable signal (SOE) can control the output timing of the data drive circuit 130.

[0066] The display device 100 may further include a power management circuit 150, which is configured to supply various voltages or currents to, for example, the display panel 110, the gate driving circuit 120, and the data driving circuit 130, or to control the various voltages or currents to be supplied.

[0067] The power management circuit 150 can regulate the DC input voltage Vin supplied from the host system 200, thereby providing the power required to drive the display panel 110, the gate drive circuit 120 and the data drive circuit 130.

[0068] Each sub-pixel SP can be located at the intersection between the corresponding gate line GL and the corresponding data line DL. A light-emitting element can be provided in each sub-pixel SP. For example, an organic light-emitting diode display can include a light-emitting element such as an organic light-emitting diode in each sub-pixel SP, and an image can be displayed by controlling the current flowing to the light-emitting element according to the corresponding data voltage.

[0069] The display device 100 may be one of various types of devices, such as a liquid crystal display, an organic light-emitting diode display, or a plasma display panel, but is not limited thereto.

[0070] Figure 2 This is an example diagram illustrating a system of a display device according to an exemplary embodiment of the present disclosure.

[0071] like Figure 2As shown, in the display device 100 according to the example embodiment of the present disclosure, the source driver integrated circuit SDIC included in the data driver circuit 130 and the gate driver integrated circuit GDIC included in the gate driver circuit 120 can be implemented as a chip-on-film (COF) type among various types (e.g., TAB, COG, or COF).

[0072] One or more gate driving integrated circuits (GDICs) included in the gate driving circuit 120 can each be mounted on a gate film GF, and one side of the gate film GF can be electrically connected to the display panel 110. Lines for electrically connecting the gate driving integrated circuits (GDICs) and the display panel 110 can be provided on the gate film GF.

[0073] Similarly, one or more source driver integrated circuits (SDICs) included in the data driver circuit 130 can each be mounted on a source film SF, and one side of the source film SF can be electrically connected to the display panel 110. Lines for electrically connecting the source driver integrated circuits (SDICs) and the display panel 110 can be provided on the source film SF.

[0074] The display device 100 may include at least one source printed circuit board (SPCB) for circuit connections between one or more source driver integrated circuits (SDICs) and other devices. The display device 100 may also include a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0075] The other side of the source film SF, on which the active driver integrated circuit SDIC is mounted, can be connected to at least one source printed circuit board SPCB. In other words, one side of the source film SF, on which the active driver integrated circuit SDIC is mounted, can be electrically connected to the display panel 110, and the other side of the source film SF can be electrically connected to the source printed circuit board SPCB.

[0076] The timing controller 140 and the power management circuit 150 can be mounted on the control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gate drive circuit 120. The power management circuit 150 can supply drive voltage or current to the display panel 110, the data drive circuit 130, and the gate drive circuit 120, and can control the supplied voltage or current.

[0077] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be circuitally connected via at least one connecting member. The connecting member may include, for example, a flexible printed circuit board (FPC) or a flexible flat cable (FFC). In this case, the connecting member connecting the at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may vary depending on the size and type of the display device 100. In some example configurations, at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0078] In a display device 100 configured in this way, for example, as Figure 2 As shown, the power management circuit 150 can transmit the driving voltage used for display driving or feature value sensing to the source printed circuit board SPCB via a flexible printed circuit (FPC) or a flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board SPCB can be supplied to specific sub-pixels SP in the display panel 110 via the source driver integrated circuit (SDIC) to make the sub-pixels SP emit light or sense feature values ​​of the sub-pixels SP.

[0079] Each sub-pixel SP in the display panel 110 arranged in the display device 100 may include an organic light-emitting diode as a light-emitting element and circuit elements for driving the organic light-emitting diode, such as a driving transistor.

[0080] Depending on the functions and design schemes to be provided, the type and number of circuit elements constituting each sub-pixel SP can vary.

[0081] Figure 3 This is an illustration of an example of a circuit constituting a sub-pixel in a display device according to an exemplary embodiment of the present disclosure.

[0082] Reference Figure 3 In the display device 100 according to the exemplary embodiment of the present disclosure, the sub-pixel SP may include one or more transistors, capacitors, and an organic light-emitting diode (OLED) as a light-emitting element ED.

[0083] For example, a subpixel SP may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light-emitting element ED.

[0084] The driving transistor DRT may include a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT may be the gate node to which a data voltage Vdata is applied from the data driving circuit 130 via the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT may be electrically connected to the anode electrode of the light-emitting element ED, and may be one of the source node and the drain node. The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL to which the driving voltage EVDD is applied, and may be the other of the source node and the drain node.

[0085] In this case, during the display driving period, the driving voltage EVDD for displaying the image can be supplied to the driving voltage line DVL. For example, the driving voltage EVDD for displaying the image can be 27V, but this disclosure is not limited thereto.

[0086] The switching transistor SWT can be electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and can have a gate node connected to the gate line GL. Therefore, the switching transistor SWT can operate according to the scan signal SCAN supplied through the gate line GL. When turned on, the switching transistor SWT can transmit the data voltage Vdata supplied through the data line DL to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0087] The sensing transistor SENT may be electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and may have a gate node connected to the gate line GL. The sensing transistor SENT may operate according to the sensing signal SENSE supplied through the gate line GL. When the sensing transistor SENT is turned on, the sensing reference voltage Vref supplied through the reference voltage line RVL can be transmitted to the second node N2 of the driving transistor DRT.

[0088] In other words, when the switching transistor SWT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the second node N2 of the driving transistor DRT can be controlled so that the current available for driving the light-emitting element ED can be applied.

[0089] The gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to a common gate line GL or to different gate lines GL. Figure 3 The diagram illustrates an example where the respective gate nodes of the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL. In this example configuration, the switching transistor SWT and the sensing transistor SENT can be independently controlled by a scan signal SCAN and a sensing signal SENSE transmitted through different gate lines GL.

[0090] Conversely, if the switching transistor SWT and the sensing transistor SENT are connected to a gate line GL, the switching transistor SWT and the sensing transistor SENT can be simultaneously controlled by the scan signal SCAN or the sensing signal SENSE transmitted through a gate line GL, and the aperture ratio of the sub-pixel SP can be increased.

[0091] The transistors located in the sub-pixel SP can be either n-type or p-type transistors. Figure 3 In the example shown, the transistor is an n-type transistor.

[0092] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and can maintain the data voltage Vdata during a frame.

[0093] Depending on the type of driving transistor DRT, the storage capacitor Cst can also be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode electrode of the light-emitting element ED can be electrically connected to the second node N2 of the driving transistor DRT, and the base voltage EVSS can be applied to the cathode electrode of the light-emitting element ED.

[0094] The base voltage EVSS can be ground voltage, or a voltage higher or lower than ground voltage. The base voltage EVSS can vary depending on the drive state. For example, the base voltage EVSS during display drive and the base voltage EVSS during sensing drive can be set to be different from each other.

[0095] The subpixel SP structure described above as an example is a 3T (transistor) 1C (capacitor) structure, which is merely an example for illustrative purposes. However, the structure of the subpixel SP is not limited to this specific example. For example, the subpixel SP may further include one or more transistors, or in some cases, it may further include one or more capacitors. Multiple subpixel SPs may have the same structure, or some of the multiple subpixel SPs may have different structures.

[0096] Figure 4 This is a diagram illustrating an example of a compensation circuit for a display device according to an exemplary embodiment of the present disclosure.

[0097] like Figure 4 As shown, the display device 100 according to an example embodiment of the present disclosure can sense changes in the characteristic values ​​of each driving transistor DRT to compensate for characteristic value deviations in the driving transistor DRT. For this purpose, the compensation circuit of the display device 100 according to an example embodiment of the present disclosure may include: a circuit for sensing changes in the characteristic values ​​of each driving transistor DRT, such as... Figure 4The example shown is a 3T1C structure, or any other possible structure of the subpixel SP, which is a component that senses changes in the characteristic value of the driving transistor DRT in the subpixel SP during the sensing period.

[0098] The display device 100 according to the example embodiment of this disclosure can sense the voltage of the reference voltage line RVL during a sensing period and can determine the characteristic value or change of characteristic value of the driving transistor DRT in the sub-pixel from the sensed voltage.

[0099] Specifically, in the display device 100 according to the exemplary embodiment of this disclosure, the characteristic value or change of the characteristic value of the driving transistor DRT can be reflected as the voltage (e.g., Vdata-Vth) of the second node N2 of the driving transistor DRT. When the sensing transistor SENT is in the on state, the voltage at the second node N2 of the driving transistor DRT can correspond to the voltage of the reference voltage line RVL. The line capacitor Cline on the reference voltage line RVL can be charged by the voltage at the second node N2 of the driving transistor DRT. Due to the charged line capacitor Cline, the reference voltage line RVL can have a voltage corresponding to the voltage at the second node N2 of the driving transistor DRT.

[0100] The compensation circuit of the display device 100 according to the example embodiment of this disclosure can control the on / off operation of the switching transistor SWT and the sensing transistor SENT in the sub-pixel SP respectively, thereby controlling the supply of data voltage Vdata and reference voltage Vref, so that the second node N2 of the driving transistor DRT is in a state that reflects the change of the characteristic value (threshold voltage or mobility) of the driving transistor DRT that can be sensed to determine the change of characteristic value.

[0101] The compensation circuit of the display device 100 according to an example embodiment of this disclosure may include: an analog-to-digital converter (ADC) that measures the voltage of a reference voltage line RVL corresponding to the voltage at the second node N2 of the driving transistor DRT and converts the voltage into a digital value. The display device may further include: switching circuits SAM and SPRE for controlling sensing drive; and a switching circuit RPRE for sensing characteristic values.

[0102] The switching circuits SAM and SPRE for controlling the sensing drive may include: a sensing reference switch SPRE for controlling the connection between each reference voltage line RVL and the sensing reference voltage node Npres to which the supplied reference voltage Vref is located. The switching circuits SAM and SPRE may further include: a sampling switch SAM for controlling the connection between each reference voltage line RVL and the analog-to-digital converter (ADC). The sensing reference switch SPRE may be a switch for controlling the sensing drive. When it is turned on (or off), the reference voltage Vref supplied to the reference voltage line RVL through the sensing reference switch SPRE may correspond to the sensing reference voltage VpreS.

[0103] The switching circuit for sensing characteristic values ​​may include a display reference switch RPRE for controlling image driving. The display reference switch RPRE controls the connection between each reference voltage line RVL and the display reference voltage node Nprer to which the supplied reference voltage Vref is located. The display reference switch RPRE may be a switch for display driving. When it is turned on (or off), the reference voltage Vref supplied to the reference voltage line RVL through the display reference switch RPRE may correspond to the display reference voltage VpreR.

[0104] In this example, the sensing reference switch SPRE and the display reference switch RPRE can be set separately or integrated into one. The sensing reference voltage VpreS and the display reference voltage VpreR can have the same voltage value or different voltage values.

[0105] In the compensation circuit of the display device 100 according to an example embodiment of the present disclosure, the timing controller 140 may include a memory system MEM and a compensator COMP. The memory system MEM may store sensed values ​​output from the analog-to-digital converter ADC or may pre-store reference sensed values. The compensator COMP may compare the sensed values ​​with the reference sensed values ​​stored in the memory system MEM to generate compensation data for compensating for feature value deviations. In this case, the compensation data generated by the compensator COMP may be stored in the memory system MEM.

[0106] Before the display device 100 is shipped, the memory system MEM can store compensation data for all sub-pixels SP of the display panel 110 generated by, for example, an optical compensation method. Alternatively, after the display device 100 is shipped, the generated compensation data can be updated and stored based on feature values ​​sensed during display driving.

[0107] The compensator COMP can use compensation data stored in the memory system MEM to compensate for the digital signal form of image data DATA, and can output the compensated image data DATA_comp to the data driver circuit 130. Therefore, the data driver circuit 130 can convert the compensated image data DATA_comp into an analog signal form of data voltage Vdata via a digital-to-analog converter (DAC). The converted data voltage Vdata can be output to the corresponding data line DL via the output buffer BUF. As a result, the eigenvalue deviation of the driving transistor DRT in the sub-pixel SP can be compensated.

[0108] The data driver circuit 130 may include a data voltage output circuit 132, which includes a latch circuit (not shown), a digital-to-analog converter (DAC), and an output buffer (BUF). In some examples, the data driver circuit 130 may further include an analog-to-digital converter (ADC) and various switches, SAM, SPRE, and RPRE. Alternatively, the ADC and various switches, SAM, SPRE, and RPRE, may be located external to the data driver circuit 130.

[0109] The compensator COMP can be located inside or outside the timing controller 140. The memory system MEM can be located outside the timing controller 140, or it can be implemented inside the timing controller 140 as a register.

[0110] In some examples, the period for sensing the characteristic values ​​of the driving transistor DRT can be performed after the power-on signal is generated and before the display driving begins. This sensing process is called a power-on sensing process. Alternatively, the period for sensing the characteristic values ​​of the driving transistor DRT can be performed after the power-off signal is generated. This sensing process is called a power-off sensing process.

[0111] Alternatively, the characteristic value sensing period of the driving transistor DRT can be performed in real time while driving the display. This sensing process is called real-time (RT) sensing. In real-time sensing, the sensing process can be performed on one or more sub-pixels SP in one or more sub-pixel SP rows during each blank period during the display driving period.

[0112] Since the saturation of the second node N2 voltage during the threshold voltage sensing process of the driving transistor DRT can take a relatively long time, a power-off sensing process that can be performed over a slightly longer period of time can be executed. In contrast, since the mobility sensing process of the driving transistor DRT requires a relatively short time compared to the threshold voltage sensing process, a real-time sensing process that can be performed over a shorter period of time can be executed.

[0113] Figure 5This is a block diagram illustrating an example of using compensation data stored in memory to compensate image data in a related technology display device. Figure 6 This is a block diagram illustrating an example of generating image data by sampling compensation data stored in a memory in a display device according to an exemplary embodiment of the present disclosure.

[0114] like Figure 5 and Figure 6 As shown, the display device 100 may include: a memory system MEM for storing initial compensation data OC generated before shipment or during display driving; a timing controller 140 for using the initial compensation data OC to compensate image data DATA received from the host system 200; and a data driving circuit 130 for converting the compensated image data DATA_comp into a data voltage Vdata and supplying it to the display panel 110.

[0115] Here, the memory system MEM may include: a large-capacity memory LCM for storing the initial compensation data OC of all sub-pixels SP, and a high-speed memory HSM for processing the initial compensation data OC at high speed.

[0116] For example, if the display device 100 is a 4K ultra-high resolution UHD display device with a resolution of 2160 x 3840 and four sub-pixels SP of white, red, green and blue, and the compensation data OC of each sub-pixel SP includes 16 bits of data, then the total compensation data OC has a data size of 2160 x 3840 x 4 x 16 = 66 MB.

[0117] In other words, a large-capacity memory (LCM) must have a memory size of at least 66MB or greater. Therefore, a large-capacity memory LCM can be formed from NAND memory capable of storing large amounts of data. However, since large-capacity memory LCMs such as NAND memory are difficult to process data at high speeds, a high-speed memory (HSM) capable of processing compensated data overload (OC) at high speeds can be used instead.

[0118] For example, high-speed memory (HSM) can use double data rate (DDR) memory capable of high-speed data processing. While HSMs offer high-speed data processing capabilities, they have relatively small data storage capacity.

[0119] Therefore, such as Figure 5 As shown, the related technology display device 100 utilizes multiple high-speed memories, such as HSM1, HSM2, HSM3 and HSM4, to process a large amount of compensation data OC.

[0120] Thus, if multiple high-speed memories HSM1, HSM2, HSM3 and HSM4 are used, the memory size and power consumption can be increased.

[0121] On the other hand, such as Figure 6 As shown, the display device 100 according to the exemplary embodiment of this disclosure can sample the overall compensation data OC stored in the large-capacity memory LCM at specified intervals and can store the sampled compensation data in a high-speed memory HSM. Therefore, the display device 100 according to the exemplary embodiment of this disclosure can use a large-capacity memory LCM and a high-speed memory HSM to perform compensation processing on all sub-pixels SP disposed on the display panel 110. Thus, the display device 100 according to the exemplary embodiment of this disclosure can reduce memory size and power consumption.

[0122] Figure 7 This is a flowchart illustrating an exemplary implementation of a display driving method according to the present disclosure.

[0123] like Figure 7 As shown, the display driving method according to an example embodiment of this disclosure may include: step S100 of storing initial compensation data in a large-capacity memory (LCM); step S200 of sampling the initial compensation data; step S300 of storing the sampled compensation data in a high-speed memory (HSM); step S400 of generating predicted compensation data; step S500 of comparing the difference between adjacent sampled compensation data with a reference value; step S600 of applying exceptional compensation data if the difference between adjacent sampled compensation data exceeds the reference value; step S700 of generating final compensation data; and step S800 of using the final compensation data to compensate for changes in the feature values ​​of sub-pixels SP disposed on the display panel 110.

[0124] Step S100, which stores the initial compensation data in the large-capacity memory LCM, may be a step of storing the initial compensation data generated by reflecting the feature values ​​of all sub-pixels SP set on the display panel 110 in the large-capacity memory LCM.

[0125] The initial compensation data may be data generated before the display device 100 is shipped using methods such as optical compensation. Alternatively, the initial compensation data may be data generated during the driving of the display device 100 by sensing the feature values ​​of the sub-pixels SP. Specifically, during display driving, the initial compensation data may be updated based on the sensing results of the feature values ​​of the sub-pixels SP.

[0126] Figure 8 This is an illustration of an example of initial compensation data stored in a mass storage LCM in a display driving method according to an exemplary embodiment of the present disclosure.

[0127] like Figure 8 As shown, the display device 100 according to the example embodiment of this disclosure may have a 4K ultra-high resolution (UHD) of 2160 x 3840, and one pixel may include four sub-pixels SP—white, red, green and blue.

[0128] In this case, if the initial compensation data OC for each sub-pixel SP consists of 16 bits, then the initial compensation data has a data size of 2160 x 3840 x 4 x 16 = 66 MB.

[0129] Therefore, the large-capacity memory LCM included in the display device 100 according to the example embodiment of this disclosure preferably has a sufficiently large memory capacity capable of storing compensation data (e.g., at least 66 MB) of all sub-pixels SP disposed on the display panel 110.

[0130] The step S200 of sampling the initial compensation data can be a step of sampling the initial compensation data of all sub-pixels SP set on the display panel 110 stored in the mass storage LCM at specified intervals.

[0131] For example, if the initial compensation data is sampled in units of 1 / 2 of the sub-pixels of each frame across two frames (e.g., odd-numbered pixels in one frame and even-numbered pixels in the next frame), then sampled compensation data corresponding to 1 / 2 of the initial compensation data can be generated. Similarly, if the initial compensation data is sampled in units of 1 / 4 of the sub-pixels of each frame across four frames (e.g., every four pixels in each frame), then sampled compensation data corresponding to 1 / 4 of the initial compensation data can be generated.

[0132] Figure 9 This is an illustration of an example process of sampling initial compensation data in units of 1 / 4 of each frame sub-pixel in a display driving method according to an exemplary embodiment of the present disclosure.

[0133] like Figure 9 As shown, in the display driving method according to the example embodiment of the present disclosure, the initial compensation data of all sub-pixels SP disposed on the display panel 110 can be stored in a large capacity memory LCM.

[0134] Here, the eight sub-pixel compensation data OC1-OC8 from the first to the eighth sub-pixel in the initial compensation data are shown as an example. If the initial compensation data for a sub-pixel includes 16 bits, then the eight sub-pixel compensation data OC1 to OC8 have a size of 128 bits.

[0135] In this example, if the compensation data OC1-OC8 of 8 subpixels are sampled in units of 1 / 4 of each frame's subpixels, then each frame's sampled compensation data includes 2 subpixel compensation data.

[0136] In this example, the sampling position of the initial compensation data can vary depending on the frame of the image data DATA supplied to the display panel 110.

[0137] For example, in the first frame, sampled compensation data including the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5 can be generated by sampling the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5. In the second frame, compensation data including the second sub-pixel compensation data OC2 and the sixth sub-pixel compensation data OC6 can be generated by sampling the second sub-pixel compensation data OC2 and the sixth sub-pixel compensation data OC6. In the third frame, compensation data including the third sub-pixel compensation data OC3 and the seventh sub-pixel compensation data OC7 can be generated by sampling the third sub-pixel compensation data OC3 and the seventh sub-pixel compensation data OC7. In the fourth frame, compensation data including the fourth sub-pixel compensation data OC4 and the eighth sub-pixel compensation data OC8 can be generated by sampling the fourth sub-pixel compensation data OC4 and the eighth sub-pixel compensation data OC8.

[0138] In this example, the sampling compensation data for each frame includes 2 sub-pixel compensation data, and thus has a size of 2 x 16 bits = 32 bits.

[0139] Thus, if the initial compensation data OC1 to OC8 are sampled in units of 1 / 4 of a subpixel, sampled compensation data corresponding to 1 / 4 of the size of the initial compensation data can be generated. For example, in the example 4K ultra-high resolution (UD) display panel 110, if the initial compensation data has a data size of 2160 x 3840 x 4 x 16 = 66 MB, then the sampled compensation data for each frame is reduced to a size of 66 / 4 MB = 16.5 MB.

[0140] The example shown here is of generating sampled compensation data by sampling the initial compensation data OC at equal intervals (e.g., every other subpixel or every four subpixels per frame), but the sampling period can vary and only specific portions of the initial compensation data OC can be sampled.

[0141] Step S300, which stores the sample compensation data in a high-speed memory (HSM), can be a step of storing the sample compensation data generated by the sampling process in a high-speed memory (HSM) capable of high-speed processing. In this case, since the high-speed memory (HSM) is used to store the sample compensation data, it can be selected to have a sufficient size to store the sample compensation data.

[0142] For example, in the example 4K ultra-high resolution (UD) display panel 110, if the initial compensation data can have a size of 2160 x 3840 x 4 x 16 = 66 MB, then the sampled compensation data can have a size of 66 / 4 = 16.5 MB. Therefore, the high-speed memory HSM can be selected to have a size capable of storing 16.5 MB of sampled compensation data.

[0143] Step S400, which generates the predicted compensation data, may be a step of predicting and generating compensation data located in the interval between compensation data sampled in units of 1 / N of each frame sub-pixel, where N is an integer greater than or equal to 2.

[0144] Figure 10 This is a diagram illustrating an example process of generating prediction compensation data in a display driving method according to an example embodiment of the present disclosure. Figure 11 This is a diagram illustrating an example of predictive compensation data.

[0145] like Figure 10 and Figure 11 As shown, the display driving method according to an example embodiment of this disclosure can add prediction compensation data to the interval between sampled compensation data sampled in units of 1 / N of each frame's sub-pixels (where N is a natural number equal to or greater than 2). In other words, prediction compensation data can be added to an additional (N-1) / N of each frame's sub-pixels (i.e., sub-pixels for which compensation data has not been sampled in a given frame).

[0146] For example, if the compensation data OC1-OC8 of 8 sub-pixels are sampled for each frame in units of 1 / 4 of the sub-pixels of each frame, then the sampled compensation data includes the compensation data of 2 sub-pixels in each frame.

[0147] When sampling the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5 among the eight sub-pixel compensation data OC1-OC8 in the first frame, prediction compensation data can be generated and added for the second to fourth sub-pixels and the sixth to eighth sub-pixels.

[0148] Since the operation of generating prediction compensation data can be performed by the timing controller 140, there is no need to increase the capacity of the high-speed memory HSM.

[0149] Since the subpixels to which the predictive compensation data is to be applied are located between the subpixels to which the sampled compensation data is to be applied, the predictive compensation data can be generated by interpolation.

[0150] For example, when sampling the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5 in the first frame, the prediction compensation data PC2-PC4 corresponding to the second to fourth sub-pixels can be selected as integers between the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5.

[0151] If the first sub-pixel compensation data OC1 sampled in the first frame has a value of 233 and the fifth sub-pixel compensation data OC5 has a value of 232, then the prediction compensation data PC2-PC4 corresponding to the second to fourth sub-pixels can have a value of 232 or 233.

[0152] Furthermore, when sampling the second sub-pixel compensation data OC2 and the sixth sub-pixel compensation data OC6 in the second frame, the integer between the second sub-pixel compensation data OC2 and the sixth sub-pixel compensation data OC6 can be selected as the prediction compensation data PC3-PC5 corresponding to the third to fifth sub-pixels.

[0153] Furthermore, when sampling the third sub-pixel compensation data OC3 and the seventh sub-pixel compensation data OC7 in the third frame, the integers located between the third sub-pixel compensation data OC3 and the seventh sub-pixel compensation data OC7 can be selected as the prediction compensation data PC4-PC6 corresponding to the fourth to sixth sub-pixels.

[0154] Similarly, when sampling the fourth sub-pixel compensation data OC4 and the eighth sub-pixel compensation data OC8 in the fourth frame, the integers between the fourth sub-pixel compensation data OC4 and the eighth sub-pixel compensation data OC8 can be selected as the prediction compensation data PC5-PC7 corresponding to the fifth to seventh sub-pixels.

[0155] Figure 12 This is a diagram illustrating the result of mitigating compensation errors by predicting compensation data in a display driving method according to an example embodiment of the present disclosure.

[0156] like Figure 12 As shown, since the display driving method according to the example embodiment of this disclosure can extract sampling compensation data at different positions of the frame, and can add prediction compensation data in the interval between the sampling compensation data, averaging the prediction compensation data can reduce the deviation in the initial compensation data between adjacent sub-pixels.

[0157] In other words, since the deviation in the predicted compensation data between adjacent sub-pixels in the example implementation of this disclosure is smaller than the deviation in the initial compensation data between adjacent sub-pixels, the potential compensation error caused by such deviation in the initial compensation data can be mitigated.

[0158] Here, an example of generating predictive compensation data by using an interpolation method between sampled compensation data has been described, but predictive compensation data can be generated in a variety of other ways.

[0159] Relatedly, if the feature values ​​between the sampled adjacent sub-pixels of the compensation data change drastically, the deviation between the predicted compensation data generated by interpolation and the initial compensation data of the sub-pixels between the adjacent sub-pixels can increase, resulting in poor compensation.

[0160] Therefore, if the difference between the feature values ​​of such adjacent sub-pixels exceeds a certain range, it is preferable not to apply prediction compensation data.

[0161] The step S500 of comparing the difference between adjacent sampled compensation data with a reference value may be a step of comparing the difference between adjacent sampled compensation data with a reference value to reduce potential compensation errors.

[0162] If the difference between adjacent sampled compensation data exceeds the baseline value, the step S600 of applying exception compensation data may be the step of applying exception compensation data instead of predictive compensation data to the interval between adjacent sampled compensation data.

[0163] Figure 13 This is a diagram illustrating an example process of applying exception compensation data in a display driving method according to an example embodiment of the present disclosure.

[0164] like Figure 13 As shown, if the difference between adjacent sampled compensation data exceeds a reference value, the display driving method according to the example embodiment of this disclosure may apply exception compensation data instead of predictive compensation data to the interval between adjacent sampled compensation data.

[0165] For example, when sampling the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5 in the first frame, the integer between the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5 can be selected as the prediction compensation data PC2-PC4 corresponding to the second to fourth sub-pixels.

[0166] If the first sub-pixel compensation data OC1 sampled in the first frame has a value of 233 and the fifth sub-pixel compensation data OC5 has a value of 260, then the prediction compensation data PC2-PC4 corresponding to the second to fourth sub-pixels can have values ​​of 240, 248 and 254, respectively.

[0167] However, if the difference between the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5 sampled in the first frame has a relatively large value, such as 27 here, it can represent a sudden change in the feature value in the interval between the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5.

[0168] Thus, if the difference between adjacent sampled compensation data (here, OC1 and OC5) exceeds the reference value, it can be determined that there is a sudden change in the sub-pixel feature value between the first sub-pixel and the fifth sub-pixel, and the exception compensation data instead of the predicted compensation data through interpolation can be applied to the second to fourth sub-pixels.

[0169] In this example, the initial compensation data can be used as the exception compensation data, thus reflecting abrupt changes in sub-pixel feature values.

[0170] For example, if the difference between the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5 sampled in the first frame exceeds the reference value, the initial compensation data OC2-OC4 corresponding to the second to fourth sub-pixels can be used as the exception compensation data, instead of generating the predicted compensation data PC2-PC4 for the second to fourth sub-pixels.

[0171] Step S700, which generates the final compensation data, may be a step of generating the final compensation data using sampled compensation data and predicted compensation data or exception compensation data.

[0172] If the difference between adjacent sampled compensation data in any frame is less than or equal to the reference value, the final compensation data can be generated based on the sampled compensation data and the predicted compensation data generated to be applied between the sampled compensation data.

[0173] Conversely, if the difference between at least some adjacent sampled compensation data in a particular frame exceeds a reference value, the final compensation data can be generated by applying initial compensation data between the corresponding adjacent sampled compensation data.

[0174] Figure 14 This is an illustration of an example of generating final compensation data by applying exception compensation data to a specific frame in a display driving method according to an exemplary embodiment of the present disclosure.

[0175] like Figure 14 As shown, if the difference between adjacent sampled compensation data exceeds a reference value, the display driving method according to the example embodiment of this disclosure may apply exception compensation data instead of predicted compensation data to the interval between adjacent sampled compensation data to generate final compensation data.

[0176] For example, if the difference between the first sub-pixel compensation data OC1 and the fifth sub-pixel compensation data OC5 sampled in the first frame exceeds the reference value, the final compensation data for the first frame can be generated by using the initial compensation data OC2-OC4 corresponding to the second to fourth sub-pixels as the exception compensation data, instead of generating the predicted compensation data PC2-PC4 for the second to fourth sub-pixels.

[0177] Thus, if the difference between adjacent sampled compensation data exceeds the reference value, the potential compensation error can be mitigated by applying the initial compensation data to the interval between adjacent sampled compensation data in the first frame.

[0178] Conversely, for example, if the difference between the second sub-pixel compensation data OC2 and the sixth sub-pixel compensation data OC6 sampled in the second frame, the difference between the third sub-pixel compensation data OC3 and the seventh sub-pixel compensation data OC7 sampled in the third frame, and the difference between the fourth sub-pixel compensation data (OC4) and the eighth sub-pixel compensation data OC8 sampled in the fourth frame are each less than or equal to a reference value, then the final compensation data can be generated in the second to fourth frames, for example, by applying the predicted compensation data generated by interval interpolation between adjacent sampled compensation data.

[0179] Step S800, which uses final compensation data to compensate for the feature values ​​of sub-pixels set on the display panel 110, may be a step of compensating the image data by applying final compensation data to the image data and converting the compensated image data into a data voltage to operate the display panel.

[0180] The exemplary implementation of this disclosure can be described as follows.

[0181] A display device according to an example embodiment of this disclosure may include: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels respectively connected to the plurality of gate lines and the plurality of data lines; a gate driving circuit configured to supply a scan signal to the plurality of gate lines; a data driving circuit configured to convert compensated digital image data into an analog data voltage and configured to supply the analog data voltage to the plurality of data lines; a mass storage memory configured to store initial compensation data based on feature values ​​of each of the plurality of sub-pixels; a high-speed memory configured to store sampled compensation data sampled from the initial compensation data of fewer sub-pixels than all of the plurality of sub-pixels in a frame; and a timing controller configured to: control the gate driving circuit and the data driving circuit to determine final compensation data based on at least one of the sampled compensation data and the initial compensation data, and to output the compensated digital image data based on input image data and the final compensation data.

[0182] In some example implementations, the feature value of one of the plurality of sub-pixels may reflect the threshold voltage or mobility of the driving transistor disposed in the sub-pixel.

[0183] In some example implementations, the initial compensation data may be generated in advance by an optical compensation method prior to shipment of the display device, or based on feature values ​​sensed while driving the display panel.

[0184] In some example implementations, the sampling compensation data may be for a group of subpixels among the plurality of subpixels in a single frame, and may be for different groups of subpixels among the plurality of subpixels in a subsequent frame.

[0185] In some example implementations, the mass storage may be a NAND memory with a capacity greater than or equal to the size of the initial compensation data, and the high-speed memory may be a double data rate (DDR) memory with a capacity smaller than the mass storage and greater than or equal to the size of the sampled compensation data in the frame.

[0186] In some example implementations, the timing controller may be further configured to determine prediction compensation data for at least one sub-pixel among the plurality of sub-pixels, which is disposed between adjacent sub-pixels, the sampled compensation data of the adjacent sub-pixels being sampled from initial compensation data in the frame, and the sampled compensation data of the adjacent sub-pixels being stored in the high-speed memory as adjacent sampled compensation data.

[0187] In some example implementations, the timing controller may be further configured to determine the prediction compensation data for the at least one sub-pixel based on interpolation of the adjacent sampled compensation data.

[0188] In some example implementations, the timing controller may be further configured to: determine whether the difference between the adjacent sampled compensation data exceeds a reference value; and if the difference between the adjacent sampled compensation data exceeds the reference value, determine the exception compensation data of the at least one sub-pixel based on the initial compensation data of the at least one sub-pixel, and apply the exception compensation data as the final compensation data to the at least one sub-pixel.

[0189] In some example implementations, the timing controller may be further configured to: sample the initial compensation data of the (n+1)th sub-pixel among the plurality of sub-pixels in the (n+1)th frame, and store the sampled compensation data of the (n+1)th sub-pixel in the high-speed memory; and sample the initial compensation data of the (n+2)th sub-pixel among the plurality of sub-pixels in the (n+2)th frame, and store the sampled compensation data of the (n+2)th sub-pixel in the high-speed memory; wherein n may be an integer greater than or equal to 0.

[0190] A method for driving a display device having a plurality of sub-pixels according to an example embodiment may include: storing initial compensation data of each of the plurality of sub-pixels in a large-capacity memory; sampling initial compensation data of sub-pixels with fewer sub-pixels than all of the plurality of sub-pixels in a frame; storing sampled compensation data of the sub-pixels with fewer sub-pixels than all of the plurality of sub-pixels in a high-speed memory in the frame; determining final compensation data of the plurality of sub-pixels based on at least one of the initial compensation data and the sampled compensation data; and compensating for changes in feature values ​​of the plurality of sub-pixels based on the final compensation data.

[0191] In some example implementations, the method may further include driving the plurality of sub-pixels based on input image data and the final compensation data.

[0192] In some example implementations, the initial compensation data is generated in advance by an optical compensation method prior to shipment of the display device, or by sensing data reflecting the feature values ​​while driving the display device.

[0193] In some example implementations, sampling the initial compensation data may include: sampling initial compensation data for a first group of sub-pixels among the plurality of sub-pixels in a frame; and sampling initial compensation data for a second group of sub-pixels among the plurality of sub-pixels that is different from the first group in another frame after the frame.

[0194] In some example implementations, the method may further include: determining prediction compensation data for at least one sub-pixel among the plurality of sub-pixels, which is disposed between adjacent sub-pixels, wherein initial compensation data of the adjacent sub-pixels is sampled in the frame, and the sampled compensation data of the adjacent sub-pixels is stored in the high-speed memory as adjacent sampled compensation data. Determining the final compensation data may include: determining the final compensation data of the plurality of sub-pixels based on at least one of the initial compensation data, the sampled compensation data, and the prediction compensation data.

[0195] In some example implementations, determining the prediction compensation data may include: determining the prediction compensation data of the at least one sub-pixel based on interpolation of the adjacent sampled compensation data.

[0196] In some example implementations, the method may further include: comparing the difference between adjacent sampled compensation data with a reference value; and if the difference between adjacent sampled compensation data exceeds the reference value, determining exceptional compensation data for the at least one sub-pixel based on the initial compensation data of the at least one sub-pixel. Determining the final compensation data may include: determining the exceptional compensation data as the final compensation data for the at least one sub-pixel.

[0197] In some example implementations, sampling the initial compensation data may include: sampling the initial compensation data of the (n+1)th sub-pixel among the plurality of sub-pixels in the (n+1)th frame; and sampling the initial compensation data of the (n+2)th sub-pixel among the plurality of sub-pixels in the (n+2)th frame. Storing the sampled compensation data may include: storing the sampled compensation data of the (n+1)th sub-pixel in the high-speed memory in the (n+1)th frame; and storing the sampled compensation data of the (n+2)th sub-pixel in the high-speed memory in the (n+1)th frame, where n is an integer greater than or equal to 0.

[0198] A display device according to an example embodiment may include: a display panel including a plurality of data lines and a plurality of sub-pixels respectively connected to the plurality of data lines; a data driving circuit configured to apply a data voltage to the plurality of data lines based on compensated image data; a mass storage memory configured to store initial compensation data based on feature values ​​of each of the plurality of sub-pixels; a high-speed memory configured to store sampled compensation data; and a timing controller configured to control the data driving circuit to determine final compensation data based on at least one of the sampled compensation data and the initial compensation data, and to output the compensated image data based on input image data and the final compensation data. The timing controller may be further configured to: sample the initial compensation data of the (n+1)th sub-pixel among the plurality of sub-pixels in the (n+1)th frame, and store the sampled compensation data of the (n+1)th sub-pixel in the high-speed memory; and sample the initial compensation data of the (n+2)th sub-pixel among the plurality of sub-pixels in the (n+2)th frame, and store the sampled compensation data of the (n+2)th sub-pixel in the high-speed memory; where n is an integer greater than or equal to 0.

[0199] In some example implementations, the high-speed memory may be configured to store sampled compensation data in a frame, sampled from initial compensation data of fewer sub-pixels than all of the plurality of sub-pixels.

[0200] In some example implementations, the timing controller may be further configured to output only the sampled compensation data of the (n+1)th sub-pixel in the high-speed memory during the (n+1)th frame.

[0201] Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit or scope of this disclosure. The above description and accompanying drawings are provided for illustrative purposes only, illustrating the technical concepts of this disclosure. That is, the disclosed embodiments are not intended to limit the scope of the principles or technical concepts of this disclosure. Therefore, the foregoing illustrative embodiments should not be construed as exhaustive in any respect.

[0202] It will be apparent to those skilled in the art that various modifications and changes may be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover such modifications and changes.

Claims

1. A display device, comprising: The display panel includes multiple gate lines, multiple data lines, and multiple sub-pixels respectively connected to the multiple gate lines and multiple data lines; A gate driving circuit configured to supply a scan signal to the plurality of gate lines; A data driving circuit, configured to convert compensated digital image data into analog data voltage and configured to supply the analog data voltage to the plurality of data lines; A large-capacity memory configured to store initial compensation data based on the feature values ​​of each of the plurality of sub-pixels; A high-speed memory configured to store sampled compensation data in a frame, sampled from initial compensation data of fewer sub-pixels than all of the plurality of sub-pixels; as well as Timing controller, the timing controller is configured as follows: Controlling the gate drive circuit and the data drive circuit, The final compensation data is determined based on at least one of the sampled compensation data and the initial compensation data, and The compensated digital image data is output based on the input image data and the final compensation data.

2. The display device according to claim 1, wherein the feature value of one of the plurality of sub-pixels reflects the threshold voltage or mobility of the driving transistor disposed in the sub-pixel.

3. The display device of claim 1, wherein the initial compensation data is generated in advance by an optical compensation method prior to shipment of the display device, or based on feature values ​​sensed while driving the display panel.

4. The display device according to claim 1, wherein the sampling compensation data is for a group of subpixels among the plurality of subpixels in the frame, and for a different group of subpixels among the plurality of subpixels in another frame after the frame.

5. The display device according to claim 1, wherein: The large-capacity memory is a NAND memory with a capacity greater than or equal to the size of the initial compensation data, and The high-speed memory is a double data rate (DDR) memory with a capacity smaller than that of the large-capacity memory and greater than or equal to the size of the sampled compensation data in the frame.

6. The display device according to claim 1, wherein: The timing controller is further configured to determine prediction compensation data for at least one sub-pixel among the plurality of sub-pixels, which is positioned between adjacent sub-pixels, the sampled compensation data of the adjacent sub-pixels being sampled from initial compensation data in the frame, and The sampling compensation data of the adjacent sub-pixels is stored in the high-speed memory as adjacent sampling compensation data.

7. The display device of claim 6, wherein the timing controller is further configured to determine the prediction compensation data of the at least one sub-pixel based on the interpolation of the adjacent sampled compensation data.

8. The display device according to claim 6, wherein the timing controller is further configured to: Determine whether the difference between the adjacent sampled compensation data exceeds a reference value; and If the difference between adjacent sampled compensation data exceeds the reference value, then the exception compensation data of the at least one sub-pixel is determined based on the initial compensation data of the at least one sub-pixel, and the exception compensation data is applied as the final compensation data to the at least one sub-pixel.

9. The display device according to claim 1, wherein the timing controller is further configured to: In the (n+1)th frame, initial compensation data for the (n+1)th sub-pixel among the plurality of sub-pixels is sampled, and the sampled compensation data of the (n+1)th sub-pixel is stored in the high-speed memory; and In the (n+2)th frame, initial compensation data for the (n+2)th sub-pixel among the plurality of sub-pixels is sampled, and the sampled compensation data of the (n+2)th sub-pixel is stored in the high-speed memory; and Where n is an integer greater than or equal to 0.

10. A method for driving a display device having a plurality of subpixels, the method comprising: The initial compensation data of each of the plurality of sub-pixels is stored in a large-capacity memory; In a frame, the initial compensation data samples of the sub-pixels with fewer sub-pixels among the plurality of sub-pixels are compared; In the frame, the sampled compensation data of the sub-pixels that are fewer than all the sub-pixels in the plurality of sub-pixels are stored in the high-speed memory; The final compensation data for the plurality of sub-pixels is determined based on at least one of the initial compensation data and the sampled compensation data; as well as The changes in the feature values ​​of the multiple sub-pixels are compensated based on the final compensation data.

11. The method of claim 10, further comprising: The multiple sub-pixels are driven based on the input image data and the final compensation data.

12. The method of claim 10, wherein the initial compensation data is generated in advance by an optical compensation method prior to shipment of the display device, or by sensing data reflecting the feature value while driving the display device.

13. The method of claim 10, wherein sampling the initial compensation data comprises: In the frame, initial compensation data is sampled for the first group of sub-pixels among the plurality of sub-pixels; and In a frame following the first frame, initial compensation data is sampled for a second group of sub-pixels that are different from the first group among the plurality of sub-pixels.

14. The method of claim 10, further comprising: Prediction compensation data is determined for at least one sub-pixel among the plurality of sub-pixels, which is positioned between adjacent sub-pixels. Initial compensation data for these adjacent sub-pixels is sampled in the frame, and the sampled compensation data for these adjacent sub-pixels is stored in the high-speed memory as adjacent sampled compensation data. Determining the final compensation data includes: determining the final compensation data for the plurality of sub-pixels based on at least one of the initial compensation data, the sampled compensation data, and the predicted compensation data.

15. The method of claim 14, wherein determining the prediction compensation data comprises: The prediction compensation data for the at least one sub-pixel is determined based on the interpolation of the adjacent sampled compensation data.

16. The method of claim 14, further comprising: The difference between the adjacent sampled compensation data is compared with the reference value; and If the difference between adjacent sampled compensation data exceeds the reference value, then exceptional compensation data for the at least one sub-pixel is determined based on the initial compensation data of the at least one sub-pixel. Determining the final compensation data includes: determining the exception compensation data as the final compensation data for the at least one sub-pixel.

17. The method of claim 10, wherein: The initial compensation data sampling includes: In the (n+1)th frame, initial compensation data is sampled for the (n+1)th sub-pixel among the plurality of sub-pixels; and In the (n+2)th frame, the initial compensation data of the (n+2)th sub-pixel among the plurality of sub-pixels is sampled. The storage of the sampling compensation data includes: In the (n+1)th frame, the sampling compensation data of the (n+1)th sub-pixel is stored in the high-speed memory; and In the (n+1)th frame, the sampling compensation data of the (n+2)th sub-pixel is stored in the high-speed memory, and Where n is an integer greater than or equal to 0.

18. A display device, comprising: The display panel includes multiple data lines and multiple sub-pixels respectively connected to the multiple data lines; A data driving circuit configured to apply a data voltage to the plurality of data lines based on compensated image data; A large-capacity memory configured to store initial compensation data based on the feature values ​​of each of the plurality of sub-pixels; A high-speed memory configured to store sampling compensation data; as well as A timing controller is configured to control a data driving circuit to determine final compensation data based on at least one of the sampled compensation data and the initial compensation data, and to output the compensated image data based on the input image data and the final compensation data. The timing controller is further configured as follows: In the (n+1)th frame, the initial compensation data of the (n+1)th sub-pixel among the plurality of sub-pixels is sampled, and the sampled compensation data of the (n+1)th sub-pixel is stored in the high-speed memory; and In the (n+2)th frame, initial compensation data for the (n+2)th sub-pixel among the plurality of sub-pixels is sampled, and the sampled compensation data of the (n+2)th sub-pixel is stored in the high-speed memory; and Where n is an integer greater than or equal to 0.

19. The display device of claim 18, wherein the high-speed memory is configured to store sampled compensation data in a frame, sampled from initial compensation data of fewer sub-pixels than all of the plurality of sub-pixels.

20. The display device of claim 19, wherein the timing controller is further configured to output only the sampling compensation data of the (n+1)th sub-pixel in the high-speed memory during the (n+1)th frame.

Images