Silicon wafer and processing method thereof

Abstract

The present application discloses a silicon wafer and a processing method thereof. The silicon wafer processing method comprises: polishing the silicon wafer to be processed; performing a first annealing treatment on the silicon wafer after the polishing treatment; performing a second annealing treatment on the silicon wafer after the first annealing treatment; wherein the first annealing treatment has a first annealing temperature T1 and a first annealing time t1, and the second annealing treatment has a second annealing temperature T2 and a second annealing time t2, satisfying: T1 ≥ T2, t2 ≥ t1. The present application eliminates the native oxygen precipitation of the silicon wafer by performing two annealing treatments after polishing the silicon wafer, and satisfies: T1 ≥ T2, t2 ≥ t1, thereby ensuring the uniformity of the radial nucleation and growth of oxygen precipitation during the annealing process, reducing the thermal stress effect on the contact position between the silicon wafer and the silicon carbide (SiC) boat teeth during the second annealing treatment, thereby avoiding the generation of slip lines at the contact position.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a silicon wafer and a processing method thereof. Background Art

[0002] Currently, argon annealed silicon wafers are an important product in the development of Czochralski silicon wafers to solve defects in silicon wafers. Defects in Czochralski silicon wafers can be divided into four categories: (1) point defects: vacancies, interstitial atoms, substitutional atoms; (2) line defects: dislocations, etc.; (3) surface defects: stacking faults, grain boundaries, etc.; (4) body defects: D defects (crystal primary particles, abbreviated as COP), body micro defects (BMD), etc. Among them, line defects and surface defects are harmful to the application of Czochralski silicon wafers and have been solved in the development of single crystal technology in the mid-20th century. COP has been plaguing the development of single crystal technology in the mid-to-late 20th century. TOSHIBA Ceramics Co.LTD developed hydrogen annealing technology to solve the problem of COP on the surface of silicon wafers and meet the requirements of device manufacturing processes. Due to the high risk of hydrogen, hydrogen annealing technology gradually developed into argon annealing. The argon annealing process solves the COP on the surface of the silicon wafer while forming a DZ (clean zone) layer and BMD layer inside the silicon wafer, meeting the device's requirements for internal impurities. In the late 20th century, crystal experts gradually optimized the single crystal process and annealing process to control the COP FREE depth and BMD density of silicon wafers to meet the process requirements of different devices.

[0003] Although the current single crystal process is stable and controllable, there is still the phenomenon of uneven radial distribution of oxygen precipitation, which leads to uneven density and size of radial BMD. During the argon annealing process, slip lines are easily generated at the contact point between the silicon carbide (SiC) boat teeth and the silicon wafer. This phenomenon cannot be rectified and causes great losses to production. Summary of the Invention

[0004] The purpose of this application is to provide a silicon wafer processing method, which eliminates the native oxygen precipitation of the silicon wafer, ensures the uniformity of the radial nucleation and growth of oxygen precipitation during the annealing process, reduces the thermal stress influence at the contact position between the silicon wafer and the silicon carbide boat teeth, and thus avoids the generation of slip lines at the contact position.

[0005] The present invention provides a method for processing a silicon wafer, comprising:

[0006] Polishing the silicon wafer to be processed;

[0007] performing a first annealing process on the silicon wafer after the polishing process;

[0008] performing a second annealing treatment on the silicon wafer after the first annealing treatment;

[0009] The first annealing treatment has a first annealing temperature T1 and a first annealing time t1, and the second annealing treatment has a second annealing temperature T2 and a second annealing time t2, satisfying: T1≥T2, t2≥t1.

[0010] In some embodiments, the first annealing temperature T1 is in the range of 1200-1300° C.; and / or,

[0011] In some embodiments, the second annealing temperature T2 ranges from 1000 to 1200°C.

[0012] In some embodiments, the first annealing time t1 ranges from 5 to 15 seconds.

[0013] In some embodiments, the second annealing time t2 ranges from 1 to 4 hours.

[0014] In some embodiments, after the polishing process, the silicon wafer is subjected to a first annealing process, comprising:

[0015] Placing the silicon wafer in a first annealing furnace, wherein the first annealing furnace has a first initial temperature T3;

[0016] introducing argon gas into the first annealing furnace;

[0017] The first annealing furnace is heated from the first initial temperature T3 to the first annealing temperature T1 at a first heating rate V1 to perform a first annealing treatment on the silicon wafer.

[0018] In some embodiments, after performing the first annealing treatment on the silicon wafer, the method further includes:

[0019] The first annealing furnace is cooled from the first annealing temperature T1 to the first standby temperature T4 at a first cooling rate V2.

[0020] In some embodiments, the first initial temperature T3 ranges from 500 to 700°C.

[0021] In some embodiments, the first standby temperature T4 ranges from 500 to 700°C.

[0022] In some embodiments, the first heating rate V1 ranges from 40 to 100° C. / s.

[0023] In some embodiments, the first cooling rate V2 is in the range of 80 to 120° C. / s.

[0024] In some embodiments, the gas flow rate of the argon gas ranges from 20 to 50 SLM.

[0025] In some embodiments, performing a second annealing process on the silicon wafer after the first annealing process comprises:

[0026] placing the silicon wafer in a second annealing furnace, wherein the second annealing furnace has a second initial temperature T5;

[0027] introducing argon gas into the second annealing furnace;

[0028] The second annealing furnace is heated from the second initial temperature T5 to the second annealing temperature T2 to perform a second annealing treatment on the silicon wafer.

[0029] In some embodiments, after the silicon wafer is subjected to a second annealing process, the method further comprises:

[0030] The second annealing furnace is cooled from the second annealing temperature T2 to a second standby temperature T6.

[0031] In some embodiments, the second initial temperature T5 is in the range of 400-700°C.

[0032] In some embodiments, the second standby temperature T6 ranges from 400 to 700°C.

[0033] In some embodiments, the gas flow rate of the argon gas is in the range of 5 to 25 SLM.

[0034] In some embodiments, after the first annealing treatment and before the second annealing treatment, the method further comprises:

[0035] The silicon wafer is cleaned.

[0036] In some embodiments, the cleaning agent used in the cleaning process includes at least one of deionized water, ozone, a hydrogen fluoride dilution solution, a first cleaning solution, and a second cleaning solution.

[0037] In some embodiments, the first cleaning solution includes ammonia water, hydrogen peroxide solution, and deionized water, and the mass ratio of the ammonia water, the hydrogen peroxide solution, and the deionized water is 0.1-2:2-5:10-50.

[0038] In some embodiments, the second cleaning solution includes hydrogen chloride, hydrogen peroxide and deionized water, and the mass ratio of the hydrogen chloride, the hydrogen peroxide and the deionized water is 0.5-1.5:2-5:10-50.

[0039] The present application also provides a silicon wafer, including a silicon wafer prepared by the silicon wafer processing method as described above, wherein the crystal orientation deviation of the silicon wafer is 0.15 to 0.45°.

[0040] The beneficial effects of this application are:

[0041] The present application provides a silicon wafer processing method, comprising: polishing a silicon wafer to be processed; performing a first annealing treatment on the silicon wafer after the polishing treatment; and performing a second annealing treatment on the silicon wafer after the first annealing treatment; wherein the first annealing treatment has a first annealing temperature T1 and a first annealing time t1, and the second annealing treatment has a second annealing temperature T2 and a second annealing time t2, satisfying: T1 ≥ T2, t2 ≥ t1. The present application eliminates native oxygen precipitation on the silicon wafer by performing two annealing treatments after polishing the silicon wafer, and satisfies: T1 ≥ T2, t2 ≥ t1, thereby ensuring the uniformity of radial nucleation and growth of oxygen precipitation during the annealing process, reducing the thermal stress effect on the contact position between the silicon wafer and the silicon carbide boat teeth during the second annealing treatment, thereby avoiding the generation of slip lines at the contact position. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A flow chart of the silicon wafer processing method provided in this application;

[0043] Figure 2 This is the XRT test image of the silicon wafer prepared in Example 1 of the present application;

[0044] Figure 3 This is the XRT test chart of the silicon wafer prepared in Comparative Example 1 of this application;

[0045] Figure 4 2 is a radial distribution diagram of the BMD density of the silicon wafers prepared in Example 1 and Comparative Example 1 of the present application. DETAILED DESCRIPTION

[0046] The technical solutions of the present application will be described clearly and completely below in conjunction with the embodiments and drawings of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. The various embodiments of the present application may be presented in the form of a range; it should be understood that the description in the form of a range is only for convenience and brevity and should not be understood as a rigid limitation on the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible ranges and single values ​​within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, which apply regardless of the range. In addition, whenever a numerical range is indicated in this article, it is meant to include any quoted number (fraction or integer) within the indicated range.

[0047] See Figure 1 , the present application provides a silicon wafer processing method, comprising:

[0048] S1: polishing the silicon wafer to be processed;

[0049] S2: After polishing, the silicon wafer is subjected to the first annealing process;

[0050] S3: performing a second annealing treatment on the silicon wafer after the first annealing treatment; wherein the first annealing treatment has a first annealing temperature T1 and a first annealing time t1, and the second annealing treatment has a second annealing temperature T2 and a second annealing time t2, satisfying: T1≥T2, t2≥t1.

[0051] Specifically, the processes of the silicon wafer to be processed include the following situations: first, the silicon wafer to be processed may be in a grinding process; second, the silicon wafer to be processed may be in a thinning process; third, the silicon wafer to be processed may be in a rough polishing process.

[0052] It can be understood that the present application eliminates native oxygen precipitation (BMD) of the silicon wafer by performing two annealing treatments after polishing the silicon wafer and satisfying: T1≥T2, t2≥t1, thereby ensuring the uniformity of radial nucleation and growth of oxygen precipitation during the annealing process, and reducing the thermal stress influence of the contact position between the silicon wafer and the silicon carbide (SiC) boat teeth during the second annealing treatment, thereby avoiding the generation of slip lines (Slip) at the contact position.

[0053] In some embodiments, the first annealing temperature T1 ranges from 1200° C. to 1300° C. Specifically, the first annealing temperature T1 can be any one of 1200° C., 1210° C., 1220° C., 1230° C., 1240° C., 1250° C., 1260° C., 1270° C., 1280° C., 1290° C., and 1300° C., or any two thereof.

[0054] It can be understood that the first annealing temperature T1 affects the native oxygen precipitation formed on the silicon wafer during the crystal pulling process, and at the same time changes the distribution of vacancies and interstitial silicon. The present application controls the range of the first annealing temperature T1 to 1200-1300°C to ensure the uniformity of radial nucleation and growth of oxygen precipitation during the second annealing process, thereby reducing the thermal stress influence at the contact position between the silicon wafer and the silicon carbide boat teeth, thereby avoiding the generation of slip lines at the contact position.

[0055] In some embodiments, the second annealing temperature T2 ranges from 1000° C. to 1200° C. Specifically, the second annealing temperature T2 can be any one of 1000° C., 1050° C., 1100° C., 1150° C., and 1200° C., or a range consisting of any two thereof. In some embodiments, the first annealing time t1 ranges from 5 to 15 seconds. Specifically, the first annealing time t1 can be any one of 5 seconds, 8 seconds, 10 seconds, 12 seconds, and 15 seconds, or a range consisting of any two thereof.

[0056] It can be understood that the first annealing time t1 affects the native oxygen precipitation formed on the silicon wafer during the crystal pulling process, and at the same time changes the distribution of vacancies and interstitial silicon. The present application controls the range of the first annealing time t1 to 5 to 15 seconds to ensure the uniformity of the radial nucleation and growth of oxygen precipitation during the second annealing process, thereby reducing the thermal stress influence at the contact position between the silicon wafer and the silicon carbide boat teeth, thereby avoiding the generation of slip lines at the contact position.

[0057] The second annealing time t2 ranges from 1 to 4 hours. Specifically, the second annealing time t2 can be any one of 1 hour, 2 hours, 3 hours, and 4 hours, or a range consisting of any two of the following.

[0058] In some embodiments, after the polishing process, the silicon wafer is subjected to a first annealing process, comprising:

[0059] Placing the silicon wafer in a first annealing furnace, wherein the first annealing furnace has a first initial temperature T3;

[0060] introducing argon gas into the first annealing furnace;

[0061] The first annealing furnace is heated from the first initial temperature T3 to the first annealing temperature T1 at a first heating rate V1 to perform a first annealing treatment on the silicon wafer.

[0062] Specifically, the first annealing process is a rapid thermal process (RTP), and the first annealing furnace is a rapid thermal process equipment, and the model of the first annealing furnace is Helios III. In addition, during the first annealing process, argon gas is introduced into the first annealing furnace instead of an oxidizing gas. This is because during the second annealing process, oxygen diffuses outward to form a sufficient clean area, so there is no need to introduce an oxidizing gas to control the clean area of ​​the product.

[0063] In some embodiments, after performing the first annealing process on the silicon wafer, the method further includes:

[0064] The first annealing furnace is cooled from the first annealing temperature T1 to the first standby temperature T4 at a first cooling rate V2.

[0065] In some embodiments, the first initial temperature T3 is in the range of 500-700° C. Specifically, the first initial temperature T3 may be any one of 500° C., 550° C., 600° C., 650° C., and 700° C., or any two of the range.

[0066] In some embodiments, the first standby temperature T4 is in a range of 500-700° C. Specifically, the first standby temperature T4 may be any one of 500° C., 550° C., 600° C., 650° C., and 700° C., or any two of the range.

[0067] In some embodiments, the first heating rate V1 ranges from 40 to 100°C / s. Specifically, the first heating rate V1 can be any one of 40°C / s, 50°C / s, 60°C / s, 70°C / s, 80°C / s, 90°C / s, and 100°C / s, or any two of the range.

[0068] It can be understood that the first heating rate V1 affects the native oxygen precipitation formed on the silicon wafer during the crystal pulling process, and at the same time changes the distribution of vacancies and interstitial silicon. The present application controls the range of the first heating rate V1 to 40-100°C / s to ensure the uniformity of radial nucleation and growth of oxygen precipitation during the second annealing process, thereby reducing the thermal stress influence at the contact position between the silicon wafer and the silicon carbide boat teeth, thereby avoiding the generation of slip lines at the contact position.

[0069] In some embodiments, the first cooling rate V2 is in the range of 80-120°C / s. Specifically, the first cooling rate V2 can be any one of 80°C / s, 90°C / s, 100°C / s, 110°C / s, and 120°C / s, or any two of the range.

[0070] It can be understood that the first cooling rate V2 affects the native oxygen precipitation formed on the silicon wafer during the crystal pulling process, and at the same time changes the distribution of vacancies and interstitial silicon. The present application controls the range of the first cooling rate V2 to 80-120°C / s to ensure the uniformity of radial nucleation and growth of oxygen precipitation during the second annealing process, thereby reducing the thermal stress influence at the contact position between the silicon wafer and the silicon carbide boat teeth, thereby avoiding the generation of slip lines at the contact position.

[0071] In some embodiments, the gas flow rate of argon gas ranges from 20 to 50 SLM. Specifically, the gas flow rate of argon gas can be any one of 20 SLM, 25 SLM, 30 SLM, 35 SLM, 40 SLM, 45 SLM, and 50 SLM, or any two of the range.

[0072] In some embodiments, a second annealing process is performed on the silicon wafer after the first annealing process, comprising:

[0073] placing the silicon wafer in a second annealing furnace, wherein the second annealing furnace has a second initial temperature T5;

[0074] introducing argon gas into the second annealing furnace;

[0075] The second annealing furnace is heated from the second initial temperature T5 to the second annealing temperature T2 to perform a second annealing treatment on the silicon wafer.

[0076] Specifically, the second annealing treatment is argon annealing, the second annealing furnace is a high-temperature annealing furnace, and the model of the second annealing furnace is Quixace-HT2.

[0077] It can be understood that the present application can eliminate the native BMD of the silicon wafer by performing another RTP annealing after polishing the silicon wafer and before argon annealing, thereby ensuring the uniformity of the radial nucleation and growth of BMD during the argon annealing process, reducing the influence of thermal stress at the contact position between the silicon wafer and the silicon carbide boat teeth, thereby avoiding the generation of slip lines at the contact position. On the one hand, it reduces the requirements of the argon annealed silicon wafer for the silicon crystal, which can improve the utilization rate of the silicon crystal and thus reduce the cost of the silicon crystal; on the other hand, it can increase the heating and cooling rate of the argon annealing process and improve the argon annealing capacity.

[0078] In some embodiments, after performing a second annealing process on the silicon wafer, the method further includes:

[0079] The second annealing furnace is cooled from the second annealing temperature T2 to the second standby temperature T6.

[0080] In some embodiments, the second initial temperature T5 ranges from 400 to 700° C. Specifically, the second initial temperature T5 may be any one of 400° C., 450° C., 500° C., 550° C., 600° C., 650° C., and 700° C., or any two thereof.

[0081] In some embodiments, the second standby temperature T6 ranges from 400 to 700° C. Specifically, the second standby temperature T6 may be any one of 400° C., 450° C., 500° C., 550° C., 600° C., 650° C., and 700° C., or any two of the ranges.

[0082] In some embodiments, the gas flow rate of argon gas ranges from 5 to 25 SLM. Specifically, the gas flow rate of argon gas can be any one of 5 SLM, 10 SLM, 15 SLM, 20 SLM, and 25 SLM, or any two of the ranges.

[0083] In some embodiments, heating the second annealing furnace from the second initial temperature T5 to the second annealing temperature T2 comprises:

[0084] heating the second annealing furnace from the second initial temperature T5 to the first temperature T7 at a second heating rate V3;

[0085] heating the second annealing furnace from the first temperature T7 to the second temperature T8 at a third heating rate V4;

[0086] heating the second annealing furnace from the second temperature T8 to the third temperature T9 at a fourth heating rate V5;

[0087] The second annealing furnace is heated from the third temperature T9 to the second annealing temperature T2 according to a fifth heating rate V6.

[0088] In some embodiments, the first temperature T7 is in a range of 800-950° C. Specifically, the first temperature T7 may be any one of 800° C., 850° C., 900° C., and 950° C., or any two of the range.

[0089] In some embodiments, the second temperature T8 is in the range of 1000-1050° C. Specifically, the second temperature T8 may be any one of 1000° C., 1010° C., 1020° C., 1030° C., 1040° C., and 1050° C., or any two of the range.

[0090] In some embodiments, the third temperature T9 is in a range of 1100-1150° C. Specifically, the third temperature T9 may be any one of 1100° C., 1110° C., 1120° C., 1130° C., 1140° C., and 1150° C., or any two of the range.

[0091] In some embodiments, the second heating rate V3 is in the range of 3 to 10°C / min. Specifically, the second heating rate V3 can be any one of 3°C / min, 4°C / min, 5°C / min, 6°C / min, 7°C / min, 8°C / min, 9°C / min, and 10°C / min, or any two of the range.

[0092] In some embodiments, the third heating rate V4 is in a range of 1 to 4°C / min. Specifically, the third heating rate V4 can be any one of 1°C / min, 1.5°C / min, 2°C / min, 2.5°C / min, 3°C / min, 3.5°C / min, 4°C / min, and 4.5°C / min, or any two thereof.

[0093] In some embodiments, the fourth heating rate V5 is in the range of 1.5 to 3° C. / min. Specifically, the fourth heating rate V5 can be any one of 1.5° C. / min, 2° C. / min, 2.5° C. / min, and 3° C. / min, or any two of the range.

[0094] In some embodiments, the fifth heating rate V6 is in the range of 0.5-2°C / min. Specifically, the fifth heating rate V6 can be any one of 0.5°C / min, 1°C / min, 1.5°C / min, and 2°C / min, or any two of them.

[0095] In some embodiments, cooling the second annealing furnace from the second annealing temperature T2 to the second standby temperature T6 comprises:

[0096] The second annealing furnace is cooled from the second annealing temperature T2 to the fourth temperature T according to the second cooling rate V7. 10 ;

[0097] The second annealing furnace is cooled from the fourth temperature T at the third cooling rate V8. 10 Cooling to the fifth temperature T 11 ;

[0098] The second annealing furnace is cooled from the fifth temperature T according to the fourth cooling rate V9. 11 The temperature is lowered to the second standby temperature T6.

[0099] In some embodiments, the fourth temperature T 10 The range of the fourth temperature T is 1100-1150°C. 10 The temperature may be any one of 1100°C, 1110°C, 1120°C, 1130°C, 1140°C, and 1150°C, or a range consisting of any two of them.

[0100] In some embodiments, the fifth temperature T 11 The range of the fifth temperature T is 1000-1050°C. 11 The temperature may be in the range of any one of 1000°C, 1010°C, 1020°C, 1030°C, 1040°C, and 1050°C, or a combination of any two of them.

[0101] In some embodiments, the second cooling rate V7 is in the range of 0.5-2°C / min. Specifically, the second cooling rate V7 can be any one of 0.5°C / min, 1°C / min, 1.5°C / min, and 2°C / min, or any two of the range.

[0102] In some embodiments, the third cooling rate V8 is in a range of 1 to 4°C / min. Specifically, the third cooling rate V8 can be any one of 1°C / min, 1.5°C / min, 2°C / min, 2.5°C / min, 3°C / min, 3.5°C / min, and 4°C / min, or any two thereof.

[0103] In some embodiments, the fourth cooling rate V9 is in a range of 2 to 8°C / min. Specifically, the fourth cooling rate V9 can be any one of 2°C / min, 3°C / min, 4°C / min, 5°C / min, 6°C / min, 7°C / min, and 8°C / min, or any two of the range.

[0104] In some embodiments, after the first annealing treatment and before the second annealing treatment, the method further comprises:

[0105] Clean the silicon wafer.

[0106] Specifically, the silicon wafer is cleaned in a cleaning machine, and the model of the cleaning machine is SCC.

[0107] In some embodiments, the cleaning agent used in the cleaning process includes at least one of deionized water, ozone, a hydrogen fluoride dilution solution, a first cleaning solution, and a second cleaning solution.

[0108] Specifically, the first cleaning liquid is RCA standard cleaning process liquid No. 1 (SC1), and the second cleaning liquid is RCA standard cleaning process liquid No. 2 (SC2).

[0109] In some embodiments, the first cleaning solution includes ammonia water, hydrogen peroxide, and deionized water, and the mass ratio of ammonia water, hydrogen peroxide, and deionized water is 0.1-2:2-5:10-50. Specifically, the mass ratio of ammonia water, hydrogen peroxide, and deionized water can be in the range of any one of 0.1:2:10, 0.8:3:30, 2:5:50, or any two of them.

[0110] In some embodiments, the second cleaning solution includes hydrogen chloride, hydrogen peroxide, and deionized water, and the mass ratio of hydrogen chloride, hydrogen peroxide, and deionized water is 0.5-1.5:2-5:10-50. Specifically, the mass ratio of hydrogen chloride, hydrogen peroxide, and deionized water can be in the range of any one of 0.5:2:10, 1:3:30, 1.5:5:50, or any two of them.

[0111] In some embodiments, the silicon wafer is cleaned, comprising:

[0112] The silicon wafer is cleaned for the first time using ozone water, and the first cleaning time is 180s;

[0113] The silicon wafer is cleaned for the second time using a hydrogen fluoride dilution solution, and the second cleaning time is 80 seconds;

[0114] The silicon wafer is cleaned for the third time using ozone water, and the third cleaning time is 180s;

[0115] The silicon wafer is cleaned for the fourth time using the first cleaning solution, and the fourth cleaning time is 600 s;

[0116] The silicon wafer was cleaned for the fifth time using deionized water, and the cleaning time was 360 seconds.

[0117] The silicon wafer is cleaned for the sixth time using the second cleaning solution, and the sixth cleaning time is 300 seconds;

[0118] The silicon wafer was cleaned for the seventh time using deionized water, and the cleaning time for the seventh time was 540 seconds.

[0119] It is understandable that the above cleaning method can effectively remove pollutants such as metal, oxide layer, particles, etc. on the surface of the silicon wafer, thereby avoiding contamination of the silicon wafer at high temperature.

[0120] The present application also provides a silicon wafer, including a silicon wafer produced by the aforementioned silicon wafer processing method, wherein the silicon wafer has a crystal orientation deviation of 0.15 to 0.45°. Specifically, the crystal orientation deviation of the silicon wafer is in the range of any one of 0.15°, 0.2°, 0.25°, 0.3°, 0.35°, 0.4°, and 0.45°, or any two thereof.

[0121] The silicon wafer provided in the present application controls the crystal orientation deviation by 0.15 to 0.45°, thereby avoiding X-shaped or fan-shaped particles caused by atomic rearrangement on the silicon wafer surface during high-temperature annealing.

[0122] The present application will be described below with reference to specific embodiments.

[0123] Example 1

[0124] The silicon wafer to be processed is first polished; then the polished silicon wafer is placed in a first annealing furnace, the first annealing furnace has a first initial temperature T3, the first initial temperature T3 is 600°C, argon gas is introduced into the first annealing furnace, and the gas flow rate of argon gas is 30SLM; at the same time, the first annealing furnace is heated from the first initial temperature T3 to the first annealing temperature T1 according to a first heating rate V1 to perform a first annealing treatment on the silicon wafer, the first heating rate V1 is 50°C / s, the first annealing temperature T1 is 1250°C, and the first annealing time t1 is 10s; then the first annealing furnace is cooled from the first annealing temperature T1 to the first standby temperature T4 according to a first cooling rate V2, the first cooling rate V2 is 100°C / s, and the first annealing time t1 is 10s. A standby temperature T4 is 600°C; the silicon wafer is taken out from the first annealing furnace and placed in a cleaning machine for cleaning. The cleaned silicon wafer is dried and placed in a second annealing furnace. The second annealing furnace has a second initial temperature T5, which is 600°C. At the same time, argon gas is introduced into the second annealing furnace, and the argon gas flow rate is 16SLM; the second annealing furnace is heated from the second initial temperature T5 to the second annealing temperature T2 to perform a second annealing treatment on the silicon wafer. The second annealing temperature T2 is 1200°C, and the second annealing time t2 is 2.5h. Then, the second annealing furnace is cooled from the second annealing temperature T2 to the second standby temperature T6, and the second standby temperature T6 is 600°C. The silicon wafer is taken out for performance testing.

[0125] Examples 2-3

[0126] The processing methods of Examples 2 to 3 are the same as those of Example 1, except that the first annealing temperature T1 is adjusted.

[0127] Examples 4-5

[0128] The processing methods of Examples 2 to 3 are the same as those of Example 1, except that the first annealing time t1 is adjusted.

[0129] Comparative Example 1

[0130] The processing method of Comparative Example 1 is the same as that of Example 1, except that the silicon wafer after the polishing process is directly subjected to the second annealing process.

[0131] Performance testing method:

[0132] (1) X-ray diffraction topography (XRT): The XRT tester, model Sensus-cs, was used to measure the slip line of the silicon wafer. The test results are shown in Table 1 and Figures 2-3 shown.

[0133] (2) Using a BMD tester, model LST2500, to measure the oxygen precipitation of silicon wafers, the test results are shown in Table 1 and Figure 4 shown.

[0134] (3) BMD measurement point selection method: a point is taken 2 mm from the center to the edge.

[0135] (4) Testing method for crystal orientation deviation of silicon wafer: crystal orientation meter

[0136] Table 1 shows the test results of silicon wafers prepared in Examples 1 to 5 and Comparative Example 1.

[0137]

[0138] Result analysis:

[0139] Figure 2 This is the XRT test chart of the silicon wafer prepared in Example 1. Figure 2 It can be seen that no slip line is generated at the contact position between the silicon carbide boat teeth and the silicon wafer.

[0140] Figure 3 This is the XRT test chart of the silicon wafer prepared in Comparative Example 1. Figure 3 It can be seen that slip lines are generated at the contact positions between the teeth of the silicon carbide boat and the silicon wafer.

[0141] Figure 4 The radial distribution diagram of the BMD density of the silicon wafers prepared in Example 1 and Comparative Example 1 is shown in Table 1 and Figure 4 It can be seen that the radial distribution curve of the BMD density of the silicon wafer in Example 1 is relatively smooth and has good radial uniformity. The radial distribution curve of the BMD density of the silicon wafer in Comparative Example 1 has more fluctuations, a large difference between the highest point and the lowest point, and poor radial uniformity.

[0142] It can be seen from the test results of Examples 1 to 3 and Table 1 that the temperature of the first annealing treatment has an impact on the slip line of the silicon wafer.

[0143] It can be seen from the test results of Examples 1, 4 and 5 and Table 1 that the time of the first annealing treatment has an impact on the slip line of the silicon wafer.

[0144] The above is a detailed introduction to the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the idea of ​​the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A silicon wafer processing method, characterized in that: include: Polishing the silicon wafer to be processed; performing a first annealing process on the silicon wafer after the polishing process; Cooling the first annealing furnace from the first annealing temperature T1 to the first standby temperature T4 at a first cooling rate V2, wherein the first cooling rate V2 is in the range of 80-90°C / s; performing a second annealing treatment on the silicon wafer after the first annealing treatment; The first annealing treatment has a first annealing temperature T1 and a first annealing time t1, and the second annealing treatment has a second annealing temperature T2 and a second annealing time t2, satisfying: T1 ≥ T2, t2 ≥ t1, the first annealing temperature T1 ranges from 1200 to 1300° C., the first annealing time t1 ranges from 5 to 15 seconds; the second annealing temperature T2 ranges from 1000 to 1200° C., and the second annealing time t2 ranges from 1 to 4 hours, so that the crystal orientation deviation of the silicon wafer is 0.15 to 0.45°, and no slip line is generated on the silicon wafer at the contact position between the silicon wafer and the silicon carbide boat teeth; Performing a second annealing treatment on the silicon wafer after the first annealing treatment comprises: heating the second annealing furnace from the second initial temperature T5 to the first temperature T7 at a second heating rate V3, wherein the second heating rate V3 is in the range of 3 to 10°C / min; heating the second annealing furnace from the first temperature T7 to the second temperature T8 at a third heating rate V4, wherein the third heating rate V4 is in the range of 1 to 4°C / min; heating the second annealing furnace from the second temperature T8 to the third temperature T9 at a fourth heating rate V5, wherein the fourth heating rate V5 is in the range of 1.5 to 3°C / min; The second annealing furnace is heated from the third temperature T9 to the second annealing temperature T2 at a fifth heating rate V6 to perform a second annealing treatment on the silicon wafer. The fifth heating rate V6 is in the range of 0.5-2°C / min.

2. The silicon wafer processing method according to claim 1, wherein: After the polishing process, the silicon wafer is subjected to a first annealing process, comprising: Placing the silicon wafer in a first annealing furnace, wherein the first annealing furnace has a first initial temperature T3; introducing argon gas into the first annealing furnace; The first annealing furnace is heated from the first initial temperature T3 to the first annealing temperature T1 at a first heating rate V1 to perform a first annealing treatment on the silicon wafer.

3. The silicon wafer processing method according to claim 2, wherein: The first initial temperature T3 is in the range of 500-700° C.; and / or, The first standby temperature T4 is in the range of 500-700° C.; and / or, The first heating rate V1 is in the range of 40 to 100° C. / s; and / or, The first cooling rate V2 is in the range of 80 to 120° C. / s; and / or, The flow rate of the argon gas ranges from 20 to 50 SLM.

4. The silicon wafer processing method according to claim 1, wherein: Performing a second annealing treatment on the silicon wafer after the first annealing treatment comprises: placing the silicon wafer in a second annealing furnace, wherein the second annealing furnace has a second initial temperature T5; Argon gas is introduced into the second annealing furnace.

5. The silicon wafer processing method according to claim 4, characterized in that: After the silicon wafer is subjected to a second annealing treatment, the method further comprises: The second annealing furnace is cooled from the second annealing temperature T2 to a second standby temperature T6.

6. The silicon wafer processing method according to claim 5, characterized in that: The second initial temperature T5 is in the range of 400-700° C.; and / or, The second standby temperature T6 is in the range of 400-700° C.; and / or, The flow rate of the argon gas ranges from 5 to 25 SLM.

7. The silicon wafer processing method according to claim 1, wherein: After the first annealing treatment and before the second annealing treatment, the method further comprises: The silicon wafer is cleaned.

8. The silicon wafer processing method according to claim 7, characterized in that: The cleaning agent used in the cleaning process includes at least one of deionized water, ozone, hydrogen fluoride dilution liquid, a first cleaning liquid and a second cleaning liquid.

9. The silicon wafer processing method according to claim 8, characterized in that: The first cleaning solution comprises ammonia water, hydrogen peroxide and deionized water, wherein the mass ratio of the ammonia water, the hydrogen peroxide and the deionized water is 0.1-2:2-5:10-50; and / or, The second cleaning solution includes hydrogen chloride, hydrogen peroxide and deionized water, and the mass ratio of the hydrogen chloride, the hydrogen peroxide and the deionized water is 0.5-1.5:2-5:10-50.

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