Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first conductor, a first insulating layer, a second conductor and a metal interconnection structure. The first conductor is arranged in a first dielectric layer. The first insulating layer is arranged on the first dielectric layer and covers the first conductor. The second conductor is arranged in a second dielectric layer and partially overlaps the first conductor. The metal interconnection structure is arranged in the second dielectric layer and the first insulating layer and physically contacts a top surface of the first conductor, a top surface of the second conductor and a sidewall on one side of the second conductor. Thus, the performance and reliability of the wiring structure are improved by arranging the metal interconnection structure under the premise of saving space, so that the semiconductor device achieves more optimized operation performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and provides a semiconductor device and a method for fabricating the same, particularly a semiconductor device with a metal interconnect structure and a method for fabricating the same. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. To enable miniaturized semiconductor devices to achieve high integration and high-speed operation, conventional techniques utilize miniaturized vias and interlayer dielectric layers to form multilayer interconnects. Generally, the fabrication of these interconnects begins with forming vias in the dielectric layer, followed by the sequential filling of a barrier layer and a conductive layer. However, to meet product demands, the cell density of semiconductor devices must continue to increase, making the placement and critical dimensions of these vias more stringent, thus increasing the difficulty and complexity of related fabrication processes and designs. Excessive deviations in the placement or critical dimensions of the vias can easily lead to component damage and affect the overall performance of the semiconductor device. Therefore, existing technologies and structures require further improvement to effectively enhance the performance and reliability of related semiconductor devices. Summary of the Invention

[0003] One objective of this application is to provide a semiconductor device and a method for manufacturing the same, which simultaneously electrically connects a second conductor and a first conductor located above and below an insulating layer through the arrangement of a metal interconnect structure. In this way, the semiconductor device of this application can improve the efficiency and structural reliability of the metal interconnects while saving space, thereby achieving more optimized operational performance.

[0004] To achieve the above objectives, one embodiment of this application provides a semiconductor device including a first conductive line, a first insulating layer, a second conductive line, and a metal interconnect structure. The first conductive line is disposed within a first dielectric layer. The first insulating layer is disposed on the first dielectric layer and covers the first conductive line. The second conductive line is disposed within a second dielectric layer and partially overlaps the first conductive line in the vertical direction. The metal interconnect structure is disposed within the second dielectric layer and the first insulating layer, and physically contacts the top surface of the first conductive line, the top surface of the second conductive line, and a sidewall on one side of the second conductive line.

[0005] To achieve the above objectives, one embodiment of this application provides a method for fabricating a semiconductor device, comprising the following steps: forming a first conductive line; forming a first dielectric layer on both sides of the first conductive line; forming a first insulating layer on the first dielectric layer, covering the first conductive line; forming a second conductive line on the first insulating layer, partially overlapping the first conductive line in the vertical direction; forming a second dielectric layer on both sides of the second conductive line; forming a metal interconnect structure within the second dielectric layer and the first insulating layer, physically contacting the top surface of the first conductive line, the top surface of the second conductive line, and a sidewall on one side of the second conductive line. Attached Figure Description

[0006] The accompanying drawings provide a more in-depth understanding of embodiments of this application and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams and are for illustrative and drawing convenience, and relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0007] Figure 1 The diagram shown is a cross-sectional schematic of a semiconductor device according to the first embodiment of this application.

[0008] Figures 2 to 6 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a preferred embodiment of this application, wherein:

[0009] Figure 2 This is a schematic cross-sectional view of a semiconductor device after the formation of the first metal material layer.

[0010] Figure 3 This is a cross-sectional view of a semiconductor device after the first conductive wire has been formed.

[0011] Figure 4 This is a schematic cross-sectional view of a semiconductor device after the formation of the second metal material layer.

[0012] Figure 5 This is a schematic cross-sectional view of the semiconductor device after the second conductive wire has been formed; and

[0013] Figure 6 This is a schematic cross-sectional view of a semiconductor device after a via has been formed.

[0014] Figure 7 The diagram shown is a cross-sectional schematic of a semiconductor device according to a second embodiment of this application.

[0015] Figure 8 The diagram shown is a cross-sectional schematic of a semiconductor device according to a third embodiment of this application.

[0016] Figure 9The diagram shown is a cross-sectional schematic of a semiconductor device according to the fourth embodiment of this application.

[0017] Figure 10 The diagram shown is a cross-sectional schematic of a semiconductor device according to the fifth embodiment of this application.

[0018] The reference numerals in the attached figures are explained as follows:

[0019] 10, 20, 30, 40, 50 semiconductor devices

[0020] 100 substrate

[0021] 101 Shallow Ditch Isolation

[0022] 103 Active Zone

[0023] 105 doped region

[0024] 110 gate structure

[0025] 111 Gate dielectric layer

[0026] 113 Semiconductor layer

[0027] 115 Barrier Layer

[0028] 117 Metal Layer

[0029] 119 cap layer

[0030] 120 gap wall structure

[0031] 121, 123, 125 Spacer walls

[0032] 130 interlayer dielectric layer

[0033] 132 Plug

[0034] 140 First conductor

[0035] 140e sidewall

[0036] 140t top surface

[0037] 141 Barrier Layer

[0038] 141a Barrier Material Layer

[0039] 143 Metal Layer

[0040] 143a First metallic material layer

[0041] 151 First Dielectric Layer

[0042] 153 First Insulation Layer

[0043] 155 Second Dielectric Layer

[0044] 157 Intermetallic Dielectric Layer

[0045] 157a, 157b sidewalls

[0046] 160, 460, 560 Second conductor

[0047] 160e, 160f, 460e, 460f sidewalls

[0048] 160t, 460t top surface

[0049] 161, 561 Barrier Layers

[0050] 161a Barrier Material Layer

[0051] 163, 563 metal layers

[0052] 163a Second metallic material layer

[0053] 170, 270, 370, 470, 570 metal interconnect structures

[0054] 170a, 270a, 470a First sidewall

[0055] 170b, 370b, 470b Second sidewall

[0056] 171 Barrier Layer

[0057] 173 Metal Layer

[0058] 180 plug

[0059] 190, 410 connection structure

[0060] 459 Second Insulation Layer

[0061] 490 Capacitor Structure

[0062] 491 Bottom Electrode Layer

[0063] 493 Capacitor Dielectric Layer

[0064] 495 Top Electrode Layer

[0065] 560b bottom surface

[0066] D1 Horizontal direction

[0067] D2 Vertical direction

[0068] O1, O2 through holes Detailed Implementation

[0069] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0070] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0071] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be used interchangeably where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0072] Please refer to Figure 1 As shown, Figure 1 This is a schematic cross-sectional view of the semiconductor device 10 in the first embodiment of this application. Figure 1 As shown, the semiconductor device 10 includes a first conductive line 140, a first insulating layer 153, a second conductive line 160, and a metal interconnect structure 170. The first conductive line 140 is disposed within a first dielectric layer 151. The first insulating layer 153 is disposed on the first dielectric layer 151 and covers the first conductive line 140. The second conductive line 160 is disposed within a second dielectric layer 155 and partially overlaps the first conductive line 140 in the vertical direction D2. In one embodiment, the second conductive line 160 includes a barrier layer 161 and a metal layer 163 stacked sequentially. The barrier layer 161 includes, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) and other conductive barrier materials, and the metal layer 163 includes, for example, copper (Cu), aluminum (Al), tungsten (W), or other suitable low resistivity conductive materials, but is not limited thereto. The first dielectric layer 151, the first insulating layer 153, and the second dielectric layer 155 include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. Preferably, the material of the first insulating layer 153 is different from the materials of the first dielectric layer 151 and the second dielectric layer 155, but this is not a limitation.

[0073] It should be noted that the metal interconnect structure 170 is simultaneously disposed within the second dielectric layer 155 and the first insulating layer 153, and physically contacts the top surface 160t of the second conductor 160, the sidewall 160e of one side of the second conductor 160, and the top surface 140t of the first conductor 140. In other words, by positioning the metal interconnect structure 170 at least partially overlapping the second conductor 160 and the first conductor 140, the metal interconnect structure 170 can simultaneously electrically connect the second conductor 160 located above the first insulating layer 153 and the first conductor 140 located below the first insulating layer 153. With this configuration, the metal interconnect structure 170 of this embodiment can simultaneously connect space-spaced metal interconnects (i.e., the first conductor 140 and the second conductor 160), which not only improves component performance and reliability but also enables the semiconductor device 10 to achieve more optimized operational performance.

[0074] Specifically, the metal interconnect structure 170 is simultaneously disposed within the first insulating layer 153, the second dielectric layer 155, and the intermetallic dielectric layer 157 covering the second conductor 160, and has a relatively large extension height in the vertical direction D2. The metal interconnect structure 170 has a first sidewall 170a and a second sidewall 170b in the vertical direction D2. In one embodiment, the portion of the first sidewall 170a that physically contacts the first conductor 140 preferably falls on the top surface 140t of the first conductor 140 in the vertical direction D2, that is, the point where the portion falls in the horizontal direction D1 does not exceed the sidewall 140e on one side of the first conductor 140. Figure 1 As shown. However, other parts of the first sidewall 170a that do not directly contact the first conductor 140 can selectively extend outward, even to a position beyond the sidewall 140e (not shown). In this way, the metal interconnect structure 170 can present an overall cross-sectional structure that is larger at the top and smaller at the bottom, such as... Figure 1 As shown, this simplifies the manufacturing process of the metal interconnect structure 170 and improves its component reliability. Similarly, the portion of the second sidewall 170b that physically contacts the second conductor 160 is preferably located on the top surface 160t of the second conductor 160 in the vertical direction D2, meaning that the point where the portion is located in the horizontal direction D1 does not exceed the sidewall 160f of the second conductor 160 on the other side. Other portions of the second sidewall 170b that do not directly contact the second conductor 160 can selectively extend outward, or even extend beyond the sidewall 160f.

[0075] like Figure 1As shown, the semiconductor device 10 also includes a substrate 100, and the aforementioned first conductive line 140, first dielectric layer 151, first insulating layer 153, second conductive line 160, second dielectric layer 155, and metal interconnect structure 170 are all disposed on the substrate 100. In one embodiment, the substrate 100 is, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. Furthermore, a plurality of shallow trench isolation (STI) structures 101 are also provided within the substrate 100 to define a plurality of active regions 103 on the substrate 100. For example... Figure 1 As shown, the semiconductor device 10 also includes a plurality of gate structures 110 and a plurality of plugs 132. The gate structures 110 are disposed on the substrate 100 with spacing between them and are located below the first conductive line 140. The gate structure 110 includes, in detail, a gate dielectric layer 111, a semiconductor layer 113, a barrier layer 115, a metal layer 117, and a capping layer 119 disposed in sequence. The gate dielectric layer 111 includes, for example, an insulating material such as silicon oxide; the semiconductor layer 113 includes, for example, a semiconductor material such as doped polycrystalline silicon or doped amorphous silicon; the barrier layer 115 includes, for example, a conductive barrier material such as titanium and / or titanium nitride, tantalum and / or tantalum oxide; the metal layer 117 includes, for example, copper, aluminum, tungsten, or other suitable low resistivity conductive material; and the capping layer 119 includes, for example, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

[0076] like Figure 1As shown, spacer wall structures 120 are also provided on the sidewalls of each gate structure 110, including spacer walls 121, 123, and 125 stacked sequentially on the sidewalls. In one embodiment, spacer walls 121 and 125 may contain the same insulating material, such as silicon nitride or silicon carbonitride, while spacer wall 123 may contain an insulating material different from that of spacer walls 121 and 125, such as silicon oxide or silicon oxynitride, but is not limited thereto. With this configuration, the gate structure 110 and the doped regions 105 disposed on both sides of the substrate 100 can together form a transistor assembly (not shown). On the other hand, plugs 132 are disposed in the interlayer dielectric layer 130 on the substrate 100 and the gate structure 110, respectively physically contacting the metal layer 117 of the gate structure 110 or the doped region 105 on one side of the gate structure 110. In one embodiment, the semiconductor device 10 includes, for example, a plurality of first conductive lines 140 and a plurality of second conductive lines 160. The first conductive lines 140 are disposed separately within a first dielectric layer 151, respectively physically contacting the plugs 132, while the second conductive lines 160 are disposed separately within a second dielectric layer 155. Preferably, each first conductive line 140 and each plug 132 is integrally formed and includes a barrier layer 141 and a metal layer 143 stacked sequentially, such as... Figure 1 As shown, but not limited to. The barrier layer 141 may include, for example, titanium and / or titanium nitride, tantalum and / or tantalum oxide, or other conductive barrier materials, and the metal layer 143 may include, for example, copper, aluminum, tungsten, or other suitable low-resistivity conductive materials, but not limited to. It should be noted that the first conductor 140 and the second conductor 160 can be directly electrically connected via the metal interconnect structure 170, or they can be indirectly electrically connected via two plugs 180 disposed within the intermetallic dielectric layer 157, which respectively connect the first conductor 140 and the second conductor 160, and then the first conductor 140 and the second conductor 160 are indirectly electrically connected via a connection structure 190 that simultaneously connects the two plugs 180. In one embodiment, the metal interconnect structure 170 and the plug 180 also include, in detail, a barrier layer 171 and a metal layer 173 stacked sequentially. The barrier layer 171 includes, for example, a conductive barrier material such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, and the metal layer 173 includes, for example, copper, aluminum, tungsten or other suitable low resistivity conductive materials, but is not limited thereto.

[0077] like Figure 1As shown, in the semiconductor device 10 according to this embodiment, a metal interconnect structure 170 is disposed at a position that at least partially overlaps the second conductor 160 and the first conductor 140, such that the metal interconnect structure 170 can simultaneously electrically connect the second conductor 160 located above the first insulating layer 153 and the first conductor 140 located below the first insulating layer 153, thereby simultaneously improving the configuration space and structural reliability of the metal interconnect lines. Thus, the first conductor 140 and the second conductor 160 of the semiconductor device 10 can be directly electrically connected through the metal interconnect structure 170, improving the component performance of the metal interconnect lines while saving space, resulting in a more optimized operating performance for the semiconductor device 10.

[0078] In order to enable those skilled in the art to easily understand the semiconductor device 10 of this application, the manufacturing method of the semiconductor device 10 of this application will be further described below.

[0079] Please see Figures 2 to 6 The diagram shown illustrates a method for fabricating the semiconductor device 10 in a preferred embodiment of this application. First, as... Figure 2As shown, a substrate 100 is provided, and a shallow trench isolation 101 is formed within the substrate 100 to define an active region 103. In one embodiment, the shallow trench isolation 101 is formed, for example, by first forming a plurality of trenches (not shown) in the substrate 100 using an etching process, and then filling the trenches with at least one insulating material (such as silicon oxide, silicon nitride, etc.) to form a shallow trench isolation 101 with a surface flush with the top surface of the substrate 100, but this is not a limitation. Next, a gate structure 110 is formed on the substrate 100, and a spacer wall structure 120 is formed on the sidewall of the gate structure 110. Then, a doped region 105 is formed in the substrate 100 on one side of the gate structure 110 and the spacer wall structure 120. The fabrication process of the gate structure 110 includes, for example, the following steps. First, a semiconductor material layer (not shown, such as polycrystalline silicon, doped amorphous silicon, etc.), a barrier material layer (not shown, such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc., conductive barrier materials), a metal material layer (not shown, such as tungsten, aluminum or copper, etc., low resistivity metal materials) and a capping material layer (not shown, such as silicon oxide, silicon nitride or silicon oxynitride, etc., insulating materials) are sequentially formed on the substrate 100. Finally, a gate structure 110 is formed by a patterning process. The fabrication process of the spacer structure 120 includes, for example, sequentially forming a first spacer material layer (not shown, such as silicon nitride or silicon carbonitride), a second spacer material layer (not shown, such as silicon oxide or silicon oxynitride), and a third spacer material layer (not shown, such as silicon nitride or silicon carbonitride) to integrally cover the gate structure 110, and then performing a back etching process to form spacers 121, 123, and 125 sequentially located on the sidewalls of the gate structure 110, thus forming the spacer structure 120.

[0080] Then, as Figure 2 As shown, a deposition process is performed to form an interlayer dielectric layer 130 on the substrate 100, integrally covering the gate structure 110 and the substrate 100. Multiple openings (not shown) are formed within the interlayer dielectric layer 130 through a mask layer (not shown), exposing the metal layer 117 of the gate structure 110 and the doped region 105 on one side of the gate structure 110, respectively. In one embodiment, the interlayer dielectric layer 130 includes, for example, an insulating material such as silicon oxide, but is not limited thereto. After completely removing the mask layer, a deposition process is performed to form a barrier material layer 141a (e.g., including titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc., conductive barrier materials) on the substrate 100, partially located within the openings and partially located outside the openings, such as... Figure 2As shown. Next, another deposition process is performed to form a first metal material layer 143a (e.g., including copper, aluminum, tungsten or other suitable low resistivity metal material) on the substrate 100, filling the remaining space of the opening and further covering the top surface of the interlayer dielectric layer 130.

[0081] like Figure 3 As shown, for Figure 2 The first metal material layer 143a and barrier material layer 141a shown are subjected to a first photolithography process to simultaneously form a first conductive line 140 located in the horizontal direction D1 and a plug 132 located in the vertical direction D2. Thus, the first conductive line 140 and the plug 132 can be integrally formed, together comprising a barrier layer 141 and a metal layer 143 stacked sequentially. Then, a deposition process and an etch-back process are performed to form a first dielectric layer 151 with its top surface 140t aligned with the top surface of the first conductive line 140, such that the first conductive line 140 is located within the first dielectric layer 151.

[0082] like Figure 4 As shown, a multi-deposition fabrication process is performed to sequentially form a first insulating layer 153, a barrier material layer 161a, and a second metal material layer 163a on the first conductor 140 and the first dielectric layer 151. The first insulating layer 153, the barrier material layer 161a, and the second metal material layer 163a are all integrally covered on the first conductor 140 and the first dielectric layer 151.

[0083] like Figure 5 As shown, a second photolithography process is performed on the second metal material layer 163a and the barrier material layer 161a to form a second conductive line 160 located in the horizontal direction D1. Then, a deposition process and an etch-back process are performed again to form a second dielectric layer 155 with its top surface 160t aligned with the top surface of the second conductive line 160, so that the second conductive line 160 is located within the second dielectric layer 155.

[0084] like Figure 6As shown, a deposition process is performed again to form an intermetallic dielectric layer 157 on the substrate 100, covering the second conductor 160 and the second dielectric layer 155. Furthermore, using a mask layer (not shown) and at least one second conductor 160 as a self-aligned mask, a plurality of vias O1 and O2 are formed within the intermetallic dielectric layer 157 using a self-aligned process. Via O1 sequentially penetrates the intermetallic dielectric layer 157, the second dielectric layer 155, and the first insulating layer 153 to simultaneously expose the top surface 160t and sidewall 160e of the second conductor 160, and the top surface 140t of the first conductor 140. Via O2 sequentially penetrates the intermetallic dielectric layer 157, the second dielectric layer 155, and / or the first insulating layer 153 to expose the top surface 160t of the second conductor 160 or the top surface 140t of the first conductor 140. It should be noted that, in another embodiment, the vias O1 and O2 can be integrated into the fabrication process of the connection structure electrically connecting other components, and have a relatively large length in the vertical direction D2, for example, approximately 10 to 20 times the length of the first conductor 140 or the second conductor 160, but not limited thereto. Furthermore, due to the loading effect of etching, the vias O1 and O2 may have a cross-section that is smaller at the top and larger at the bottom, such as... Figure 6 As shown. Specifically, the portion of the sidewall 157a of the through-hole O1 in the vertical direction D2 that physically contacts the first conductive wire 140 preferably falls on the top surface 140t of the first conductive wire 140, and does not exceed the sidewall 140e of the first conductive wire 140 in the horizontal direction D1. Similarly, the portion of the sidewall 157b of the through-hole O1 in the vertical direction D2 that physically contacts the second conductive wire 160 also preferably falls on the top surface 160t of the second conductive wire 160, and does not exceed the sidewall 160f of the second conductive wire 160 in the horizontal direction D1. This operation simplifies the fabrication process of the through-holes O1 and O2, avoids the influence of the critical size of the miniaturized through-holes during the fabrication of the through-holes O1 and O2, and effectively improves the component reliability of the subsequently formed metal interconnect structure 170.

[0085] Then, as Figure 6 As shown, after completely removing the mask layer, a deposition process is performed again to sequentially form a barrier material layer (not shown, such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc., conductive barrier materials) and a metal material layer (not shown, such as copper, aluminum, tungsten, or other suitable low resistivity metal materials) on the substrate 100, filling the vias O1 and O2, so that the barrier material layer physically contacts the top surface 140t of the first conductor 140 and the top surface 160t and sidewall 160e of the second conductor 160. Then, a planarization process is performed to form a layer in the vias O1 and O2 as shown in the figure. Figure 1The metal interconnect structure 170 and plug 180 are shown. In this way, the first wire 140 and the second wire 160 can be directly electrically connected through the metal interconnect structure 170. Alternatively, a connection structure 190 that connects the two plugs 180 can be further formed on the intermetallic dielectric layer 157 to indirectly electrically connect the first wire 140 and the second wire 160 through the connection structure 190.

[0086] According to the manufacturing method of this embodiment, a through-hole O1 is formed on the second conductor 160 and the second dielectric layer 155, simultaneously penetrating the second dielectric layer 155 and the first insulating layer 153, such that the through-hole O1 has a cross-section that is smaller at the top and larger at the bottom in the vertical direction D2. Thus, a metal interconnect structure 170 is formed within the through-hole O1, capable of simultaneously electrically connecting the second conductor 160 located above the first insulating layer 153 and the first conductor 140 located below the first insulating layer 153. In this operation, the metal interconnect structure 170 correspondingly has a cross-sectional structure that is smaller at the top and larger at the bottom, and simultaneously physically contacts the top surface 160t of the second conductor 160, the sidewall 160e of one side of the second conductor 160, and the top surface 140t of the first conductor 140. Furthermore, the first sidewall 170a and the second sidewall 170b contacting the top surface 140t and the top surface 160t do not exceed the sidewall 140e of the first conductor 140 and the sidewall 160e of the second conductor 160. Therefore, the manufacturing method of this embodiment can form metal interconnects with improved component performance and reliable structure under the premise of simplified process, effectively save the space for setting metal interconnects, and form a semiconductor device 10 with more optimized operation performance.

[0087] Those skilled in the art to which this application pertains will readily understand that, to meet actual product needs, the semiconductor device and its fabrication method of this application may have other forms and are not limited to those described above. The following will further describe other embodiments or variations of the semiconductor device and its fabrication method of this application. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, without repeating the similarities. Furthermore, the same components in the various embodiments of this application are designated with the same reference numerals to facilitate comparison between the embodiments.

[0088] Please refer to Figure 7The diagram shown is a cross-sectional view of the semiconductor device 20 in the second embodiment of this application. The structure of the semiconductor device 20 in this embodiment is largely the same as that of the semiconductor device 10 in the previous embodiment, and the similarities will not be repeated here. The main difference between the semiconductor device 20 in this embodiment and the previous embodiment is that the portion of the first sidewall 270a of the metal interconnect structure 270 that physically contacts the first conductive wire 140 is located on the top surface 140t of the first conductive wire 140 in the vertical direction D2, and is flush with the sidewall 140e of the first conductive wire 140. Thus, the metal interconnect structure 270 can also present a cross-sectional structure that is larger at the top and smaller at the bottom, which is beneficial for improving the reliability of the component while simplifying the manufacturing process of the metal interconnect structure 270.

[0089] In this embodiment, the semiconductor device 20 also places the metal interconnect structure 270 at a position that at least partially overlaps the second conductor 160 and the first conductor 140. The metal interconnect structure 270 directly and electrically connects the second conductor 160 located above the first insulating layer 153 and the first conductor 140 located below the first insulating layer 153, simultaneously improving the configuration space and structural reliability of the metal interconnect lines. Therefore, the semiconductor device 20 of this embodiment can still improve the component performance of the metal interconnect lines while saving space, achieving more optimized operational performance.

[0090] Please refer to Figure 8 The diagram shown is a cross-sectional view of the semiconductor device 30 in the third embodiment of this application. The structure of the semiconductor device 30 in this embodiment is largely the same as that of the semiconductor device 10 in the previous embodiment, and the similarities will not be repeated here. The main difference between the semiconductor device 30 in this embodiment and the previous embodiment is that the portion of the second sidewall 370b of the metal interconnect structure 370 that physically contacts the second conductive wire 160 is located on the top surface 160t of the second conductive wire 160 in the vertical direction D2, and is flush with the sidewall 160f of the second conductive wire 160. Thus, the metal interconnect structure 370 can also present a cross-sectional structure that is larger at the top and smaller at the bottom, which is beneficial for improving the reliability of the component while simplifying the manufacturing process of the metal interconnect structure 370.

[0091] In this embodiment, the semiconductor device 30 also places the metal interconnect structure 370 at a position that at least partially overlaps the second conductor 160 and the first conductor 140. The metal interconnect structure 370 directly and electrically connects the second conductor 160 located above the first insulating layer 153 and the first conductor 140 located below the first insulating layer 153, simultaneously improving the configuration space and structural reliability of the metal interconnect lines. Therefore, the semiconductor device 30 of this embodiment can still improve the component performance of the metal interconnect lines while saving space, achieving more optimized operational performance.

[0092] Please refer to Figure 9The diagram shown is a cross-sectional view of the semiconductor device 40 in the fourth embodiment of this application. The structure of the semiconductor device 40 in this embodiment is largely the same as that of the semiconductor device 10 in the previous embodiment, and the similarities will not be described again here. The main difference between the semiconductor device 40 in this embodiment and the previous embodiment is that the semiconductor device 40 further includes a capacitor structure 490, which is disposed on the second wire 460 and physically contacts the second wire 460.

[0093] Specifically, such as Figure 9 As shown, in this embodiment, the second conductor 460 can be disposed within the second dielectric layer 155 and located on the first insulating layer 153, and includes copper, aluminum, tungsten, or other suitable low-resistivity conductive materials, but is not limited thereto. A second insulating layer 459 is also disposed on the second conductor 460, at least partially covering the top surface 460t of the second conductor 460, while the capacitor structure 490 partially penetrates the second insulating layer 459 to electrically connect to the second conductor 460. The capacitor structure 490 includes, in detail, a plurality of bottom electrode layers 491, a capacitor dielectric layer 493, and a top electrode layer 495 arranged sequentially. Each bottom electrode layer 491 has a U-shaped cross-sectional structure and individually penetrates the second insulating layer 459 to physically contact and electrically connect to the second conductor 460 located below the second insulating layer 459.

[0094] It should be noted that in this embodiment, the metal interconnect structure 470 is disposed at a position that at least partially overlaps the second wire 460 and the physical contact doped region 105 with a first wire 140. By contacting the top surface 460t and sidewall 460e of the second wire 460 and the top surface 140t of the first wire 140, the first wire 140 and the second wire 460 can be directly electrically connected while saving space. Furthermore, the metal interconnect structure 470 also has a first sidewall 470a and a second sidewall 470b in the vertical direction D2. The portion of its physical contact with the top surface 140t and the top surface 460t is located in the horizontal direction D1 no more than the sidewall 140e on one side of the first wire 140 and the sidewall 460f on the other side of the second wire 460. Figure 9 As shown. In one embodiment, the portions of the first sidewall 470a and the second sidewall 470b of the metal interconnect structure 470 that physically contact the top surfaces 140t and 460t can also be selected to be flush with the sidewall 140e on one side of the first conductor 140 and the sidewall 460f on the other side of the second conductor 460, but are not limited thereto. In this way, the metal interconnect structure 470 can also present an overall cross-sectional structure that is larger at the top and smaller at the bottom, which helps to simplify its manufacturing process and improve the reliability of the component.

[0095] In another embodiment, the metal interconnect structure 470 can be fabricated after the capacitor structure 490 is formed, integrated with the fabrication process of the connection structure electrically connecting other components, and has a relatively large length in the vertical direction D2, for example, about 10 to 20 times the length of the first conductor 140 or the second conductor 460, but not limited thereto. Furthermore, as... Figure 9 As shown, in subsequent manufacturing processes, an additional connection structure 410 can be provided on the capacitor structure 490, and the capacitor structure 490 can be further electrically connected to different components through the connection structure 410 to form different devices to perform different operations.

[0096] In this configuration, the semiconductor device 40 of this embodiment can also be directly electrically connected via the metal interconnect structure 470 to the second conductor 460 located above the first insulating layer 153 and the first conductor 140 located below the first insulating layer 153, simultaneously improving the configuration space and structural reliability of the metal interconnect lines. Furthermore, the semiconductor device 40 of this embodiment can also be electrically connected via the metal interconnect structure 470 to the doped region 105 of the transistor assembly, allowing the capacitor structure 490 and the transistor assembly to jointly form the smallest memory cell of the memory device, receiving voltage information from the bit line (not shown) and word line (not shown). Moreover, the smallest memory cell can be further electrically connected to specific desired components via the connection structure 410 provided on the capacitor structure 490, enabling the semiconductor device 40 to function as a dynamic random access memory (DRAM) device, achieving more optimized operational performance.

[0097] Please refer to Figure 10 The diagram shown is a cross-sectional view of the semiconductor device 50 in the fifth embodiment of this application. The structure of the semiconductor device 50 in this embodiment is largely the same as that of the semiconductor device 10 in the previous embodiment, and the similarities will not be repeated here. The main difference between the semiconductor device 50 in this embodiment and the previous embodiment is that the metal interconnect structure 570 is disposed between the first wire 140 and the second wire 560, and simultaneously physically contacts the top surface 140t of the first wire 140 and the bottom surface 560b of the second wire 560.

[0098] Specifically, such as Figure 10 As shown, in this embodiment, the metal interconnect structure 570 is disposed within the first insulating layer 153, located below the second conductor 560. Furthermore, the metal interconnect structure 570 is preferably integrally formed with the second conductor 560, and together they include a barrier layer 561 and a metal layer 563 stacked sequentially, such as... Figure 10As shown, but not limited to. The barrier layer 561 may include, for example, titanium and / or titanium nitride, tantalum and / or tantalum oxide, or other conductive barrier materials, and the metal layer 563 may include, for example, copper, aluminum, tungsten, or other suitable low-resistivity conductive materials. Thus, the first conductor 140 and the second conductor 560 can also be directly electrically connected through the metal interconnect structure 570.

[0099] In this configuration, the semiconductor device 50 of this embodiment also places the metal interconnect structure 570 at a position that at least partially overlaps the second conductor 560 and the first conductor 140. The metal interconnect structure 570 directly and electrically connects the second conductor 560 located above the first insulating layer 153 and the first conductor 140 located below the first insulating layer 153, simultaneously improving the configuration space and structural reliability of the metal interconnect lines. Therefore, the semiconductor device 50 of this embodiment can still improve the component performance of the metal interconnect lines while saving space, achieving more optimized operational performance.

[0100] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: The first conductor is disposed within the first dielectric layer; A first insulating layer is disposed on the first dielectric layer and covers the first conductor; A gate structure is disposed below the first conductor; A plug is disposed on the gate structure and physically contacts the gate structure and the first conductor; The second conductor is disposed within the second dielectric layer and partially overlaps the first conductor in the vertical direction; as well as A metal interconnect structure is disposed within the second dielectric layer and the first insulating layer, and physically contacts the top surface of the second conductor, the sidewall of one side of the second conductor, and the top surface of the first conductor.

2. The semiconductor device according to claim 1, characterized in that, The portion of the first sidewall of the metal interconnect structure that physically contacts the top surface of the first conductor does not exceed the sidewall on one side of the first conductor.

3. The semiconductor device according to claim 2, characterized in that, The first sidewall of the metal interconnect structure is flush with the sidewall of the first conductor.

4. The semiconductor device according to claim 2, characterized in that, The portion of the second sidewall of the metal interconnect structure that physically contacts the top surface of the second conductor does not exceed the sidewall on the other side of the second conductor.

5. The semiconductor device according to claim 4, characterized in that, The second sidewall of the metal interconnect structure is flush with the other sidewall of the second conductor.

6. The semiconductor device according to claim 1, characterized in that, The metal interconnect structure includes a cross-sectional structure that is larger at the top and smaller at the bottom.

7. The semiconductor device according to claim 1, characterized in that, Also includes: A gate structure is disposed below the first conductor; as well as A plug is disposed below the first conductor and physically contacts the doped region on one side of the gate structure and the first conductor.

8. The semiconductor device according to claim 7, characterized in that, Also includes: A capacitor structure is disposed on the second conductor and in physical contact with the second conductor.

9. The semiconductor device according to claim 8, characterized in that, Also includes: A second insulating layer is disposed on the second conductor. The capacitor structure further includes a plurality of bottom electrode layers, a capacitor dielectric layer and a top electrode layer disposed in sequence. The bottom electrode layers penetrate the second insulating layer and physically contact the top surface of the second conductor.

10. A method for fabricating a semiconductor device, characterized in that, include: Form the first conductor; A first dielectric layer is formed on both sides of the first conductor; A first insulating layer is formed on the first dielectric layer, and the first insulating layer covers the first conductor; A second conductor is formed on the first insulating layer, the second conductor partially overlapping the first conductor in the vertical direction; A second dielectric layer is formed on both sides of the second conductor; as well as A metal interconnect structure is formed within the second dielectric layer and the first insulating layer, the metal interconnect structure physically contacting the top surface of the second conductor, a sidewall on one side of the second conductor, and the top surface of the first conductor; Before forming the first conductor, a gate structure is formed; as well as A plug is formed on the gate structure, wherein the plug is in physical contact with the gate structure and the first conductor.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The formation of the first conductor and the second conductor further includes: Forming the first metallic material layer; A first photolithography process is performed on the first metal material layer to form the first conductive line; After the first photolithography process, a second metal material layer is formed on the first insulating layer; and A second photolithography process is performed on the second metal material layer to form the second conductive wire.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The first dielectric layer is formed after the first photolithography process, the second dielectric layer is formed after the second photolithography process, and the metal interconnect structure is formed after the second dielectric layer is formed.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, The formation of the metal interconnect structure also includes: A through-hole is formed, penetrating the second dielectric layer and the first insulating layer; and A barrier material layer and a metal material layer are sequentially formed within the through hole to form the metal interconnect structure, wherein the barrier material layer physically contacts the top surface of the second conductor, the sidewall of the second conductor, and the top surface of the first conductor.

14. The method for fabricating a semiconductor device according to claim 10, characterized in that, Also includes: Before forming the first conductor, a gate structure is formed; as well as A plug is formed below the first conductor, wherein the plug physically contacts the doped region on one side of the gate structure and the first conductor.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, Also includes: A second insulating layer is formed on the second conductor; as well as A capacitor structure is formed on the second insulating layer, wherein the capacitor structure is in physical contact with the second conductor.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, The capacitor structure further includes a plurality of bottom electrode layers, a capacitor dielectric layer and a top electrode layer arranged in sequence, wherein the bottom electrode layer penetrates the second insulating layer and physically contacts the top surface of the second conductor.

17. The method for fabricating a semiconductor device according to claim 16, characterized in that, The portion of the first sidewall of the metal interconnect structure that physically contacts the top surface of the first conductor does not exceed or is flush with one sidewall of the first conductor.

18. The method for fabricating a semiconductor device according to claim 16, characterized in that, The portion of the second sidewall of the metal interconnect structure that physically contacts the top surface of the second conductor does not exceed or is flush with the sidewall of the other side of the second conductor.

19. A semiconductor device, characterized in that, include: The first conductor is disposed within the first dielectric layer; A first insulating layer is disposed on the first dielectric layer and covers the first conductor; The second conductor is disposed within the second dielectric layer and partially overlaps the first conductor in the vertical direction; as well as A metal interconnect structure is disposed within the second dielectric layer and the first insulating layer, and physically contacts the top surface of the second conductor, the sidewall of one side of the second conductor, and the top surface of the first conductor. A capacitor structure is disposed on the second conductor and in physical contact with the second conductor.

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