Display driving method, display panel and display device

Abstract

The present application proposes a display driving method, a display panel, and a display device, which belong to the technical field of display devices. In the process of driving in a hardware super-resolution mode, a corresponding n-th scan pulse is provided to the n-th scan line, a corresponding n+1-th scan pulse is provided to the n+1-th scan line, a corresponding n+2-th scan pulse and an n+2-th compensation pulse are provided to the n+2-th scan line, and a corresponding n+3-th scan pulse and an n+3-th compensation pulse are provided to the n+3-th scan line, wherein the n+2-th compensation pulse is a partial pulse of the n+4-th scan pulse corresponding to the n+4-th scan line, and the n+3-th compensation pulse is a partial pulse of the n+5-th scan pulse corresponding to the n+5-th scan line, wherein n=4m‑3, and m is a natural number greater than or equal to 1. By compensating the scan pulse signal of the current row covered by the previous row, the DRD product can achieve the HSR mode.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display driving method, a display panel, and a display device. Background Art

[0002] At present, in order to reduce costs, a dual-rate driver (DRD) driving method can be used. When using the DRD driving method, two sets of scanning signals are used to drive the pixels in the same row. Two adjacent signals are used to drive the pixels in the first row. Products using the DRD driving method can reduce the number of data lines and the number of COFs (Chip-On Film), thereby achieving the goal of reducing costs. In order to achieve a high refresh rate at a low cost, a new display mode, the Hardware Super Resolution (HSR) mode, has been introduced. The HSR mode uses the gate driver (GDL) signal multiplication method, the data signal remains unchanged, and the same data signal is used between adjacent rows, thereby reducing the vertical resolution and increasing the refresh rate of the screen.

[0003] However, since the HSR mode will cover part of the scan pulse of the next row when the current row is turned on, an erroneous signal will be charged when the DRD product turns on the HSR mode, that is, the DRD product cannot implement the HSR mode. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to propose a display driving method, a display panel and a display device, which aims to provide a corresponding n+2th scanning pulse to the n+2th scanning line while also providing a corresponding n+2th compensation pulse, and to provide a corresponding n+3th scanning pulse to the n+3th scanning line while also providing a corresponding n+3th compensation pulse, so as to compensate for the scanning pulse signal of the current row covered by the previous row, so that the DRD product can realize the HSR mode.

[0005] To achieve the above-mentioned object, a first aspect of an embodiment of the present application provides a display driving method for driving a display panel, the method comprising:

[0006] In the process of driving in hardware super-resolution mode, a corresponding nth scan pulse is provided to the nth scan line, a corresponding n+1th scan pulse is provided to the n+1th scan line, a corresponding n+2th scan pulse and an n+2th compensation pulse are provided to the n+2th scan line, and a corresponding n+3th scan pulse and an n+3th compensation pulse are provided to the n+3th scan line, wherein the n+2th compensation pulse is a partial pulse of the n+4th scan pulse corresponding to the n+4th scan line, and the n+3th compensation pulse is a partial pulse of the n+5th scan pulse corresponding to the n+5th scan line, wherein n=4m-3, and m is a natural number greater than or equal to 1.

[0007] In one embodiment of the present application, the pulse width of the n+2th compensation pulse is smaller than the pulse width of the n+4th scanning pulse, and the first time corresponding to the falling edge of the n+2th compensation pulse is no later than the second time corresponding to the falling edge of the n+4th scanning pulse;

[0008] The pulse width of the n+3th compensation pulse is smaller than the pulse width of the n+5th scan pulse, and the third time corresponding to the falling edge of the n+3th compensation pulse is no later than the fourth time corresponding to the falling edge of the n+5th scan pulse.

[0009] In one embodiment of the present application, the pulse width of the n+2th compensation pulse is between 10% and 90% of the pulse width of the n+4th scanning pulse, and the pulse width of the n+3th compensation pulse is between 10% and 90% of the pulse width of the n+5th scanning pulse.

[0010] In one embodiment of the present application, the pulse widths of the (n+2)th compensation pulses are different, and / or the pulse widths of the (n+3)th compensation pulses are different.

[0011] In one embodiment of the present application, the display panel has a plurality of regions sequentially arranged along a first direction, each region includes a plurality of scan lines, and adjacent regions are adjacent to each other; wherein:

[0012] The pulse width of the (n+2)th compensation pulse provided to the (n+2)th scan line falling in the same area is the same; and / or,

[0013] The pulse widths of the (n+3)th compensation pulses provided to the (n+3)th scan lines falling within the same region are the same.

[0014] In one embodiment of the present application, the display panel includes a first area, a second area, and a third area sequentially arranged in a first direction, and each area includes a plurality of scan lines; wherein:

[0015] The pulse width of the n+2th compensation pulse provided to the n+2th scan line falling within the first region is a first pulse width, the pulse width of the n+2th compensation pulse provided to the n+2th scan line falling within the second region is a second pulse width, and the pulse width of the n+3th compensation pulse provided to the n+2th scan line falling within the third region is a third pulse width, wherein both the first pulse width and the third pulse width are smaller than the second pulse width; and / or,

[0016] The pulse width of the n+3rd compensation pulse provided to the n+3th scan line falling into the first area is the fourth pulse width, the pulse width of the n+3th compensation pulse provided to the n+3th scan line falling into the second area is the fifth pulse width, and the pulse width of the n+3th compensation pulse provided to the n+3th scan line falling into the third area is the sixth pulse width, wherein the fourth pulse width and the sixth pulse width are both smaller than the fifth pulse width.

[0017] To achieve the above-mentioned object, a second aspect of the embodiments of the present application provides a display panel driven by the method described in the first aspect of the embodiments of the present application, the display panel comprising:

[0018] a plurality of scan lines spaced apart and arranged along a first direction;

[0019] a plurality of data lines spaced apart and arranged along a second direction, wherein the second direction intersects the first direction;

[0020] The scan lines and the data lines are insulated and intersect to define a plurality of pixel areas, each of the pixel areas is provided with two sub-pixels along the first direction, the gates of the two sub-pixels are connected to two different scan lines, the sources of the two sub-pixels are connected to the same data line, and the two sub-pixels are distributed on both sides of the same data line.

[0021] To achieve the above-mentioned objectives, a third aspect of the embodiments of the present application provides a display device, including:

[0022] The display panel according to the second aspect of the embodiment of the present application;

[0023] A timing controller is connected to the display panel and is used to execute the method described in the first aspect of the embodiment of the present application to drive the display panel.

[0024] In one embodiment of the present application, the timing controller includes a level conversion circuit, and the level conversion circuit is used to provide a corresponding scan pulse for each scan line.

[0025] To achieve the above-mentioned purpose, the fourth aspect of an embodiment of the present application proposes a display device, which includes a memory and a processor, the memory stores a computer program, and the processor implements the method described in the first aspect of the embodiment of the present application when executing the computer program.

[0026] In the technical solution provided in the embodiment of the present application, during the driving process using the hardware super-resolution mode, a corresponding nth scanning pulse is provided to the nth row of scan lines, a corresponding n+1th scanning pulse is provided to the n+1th row of scan lines, a corresponding n+2th scanning pulse and an n+2th compensation pulse are provided to the n+2th row of scan lines, and a corresponding n+3th scanning pulse and an n+3th compensation pulse are provided to the n+3th row of scan lines, wherein the n+2th compensation pulse is a partial pulse of the n+4th scanning pulse corresponding to the n+4th row of scan lines, and the n+3th compensation pulse is a partial pulse of the n+5th scanning pulse corresponding to the n+5th row of scan lines, wherein n=4m-3, and m is a natural number greater than or equal to 1. By using the partial pulse of the n+4th scan line corresponding to the n+4th scan pulse as the compensation pulse of the n+2th scan line, and using the partial pulse of the n+5th scan line corresponding to the n+5th scan pulse as the compensation pulse of the n+3th scan line, the scan pulse signal of the current row covered by the previous row can be compensated accordingly, so that the DRD product can achieve HSR mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a flow chart of a display driving method provided by an embodiment of the present application;

[0028] Figure 2 This is a schematic diagram of the gate signal waveform of a typical DRD product under normal conditions;

[0029] Figure 3 Schematic diagram of gate signal waveforms for the DRD product provided in an embodiment of the present application to implement the HSR mode;

[0030] Figure 4 is a first structural schematic diagram of a display panel provided in an embodiment of the present application;

[0031] Figure 5 is a second structural schematic diagram of a display panel provided in an embodiment of the present application;

[0032] Figure 6 is a structural example diagram of a display panel provided in an embodiment of the present application;

[0033] Figure 7 is a schematic diagram of a first structure of a display panel provided in an embodiment of the present application;

[0034] Figure 8is a schematic diagram of a second structure of a display panel provided in an embodiment of the present application;

[0035] Figure 9 This is a waveform diagram of a typical DRD product PCB end input change;

[0036] Figure 10 This is a waveform diagram of the HSR technology implemented after the input is changed on the DRD product PCB side;

[0037] Figure 11 This is another waveform diagram of the input change at the PCB end of a typical DRD product;

[0038] Figure 12 This is another waveform diagram of the HSR technology after the input is changed on the PCB side of the DRD product;

[0039] Figure 13 This is a schematic diagram of the hardware structure of the display device provided in an embodiment of the present application.

[0040] Reference numerals:

[0041] Scan line -10; data line 20. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0043] It should be noted that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps shown or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "second," and so on, in the specification, claims, and drawings, are used to distinguish similar items and are not necessarily used to describe a specific sequence or precedence.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0045] For the same product, the higher the frequency, the shorter the charging time, which can easily lead to insufficient charging. For the current display industry, HSR technology can achieve high refresh rate without affecting the charging time by adjusting the timing. When DRD products implement DLG technology, they can also achieve high refresh rate, but the picture will be rough. HSR technology can make the picture more delicate while achieving high refresh rate. For typical DRD products, the gate signal waveform under normal circumstances is as follows: Figure 2 However, HSR technology cannot be implemented for DRD products. This is because HSR technology consumes part of the scan pulse of the next row when the scan pulse of the current row is turned on. As a result, when the DRD product has HSR function enabled, erroneous signals are charged, resulting in incorrect charging.

[0046] Based on this, an embodiment of the present application provides a driving method, which uses the partial pulse of the n+4th scan pulse corresponding to the n+4th scan line as the compensation pulse of the n+2th scan line, and uses the partial pulse of the n+5th scan pulse corresponding to the n+5th scan line as the compensation pulse of the n+3th scan line. It can compensate the scan pulse signal of the current row covered by the previous row, so that the DRD product can realize the HSR mode.

[0047] Specifically, refer to Figure 1 , Figure 1 Flowchart of the display driving method provided in an embodiment of the present application, including but not limited to the following step S110.

[0048] Step S110, in the process of driving in hardware super-resolution mode, provides the corresponding nth scan pulse to the nth scan line, provides the corresponding n+1th scan pulse to the n+1th scan line, provides the corresponding n+2th scan pulse and n+2th compensation pulse to the n+2th scan line, provides the corresponding n+3th scan pulse and n+3th compensation pulse to the n+3th scan line, wherein the n+2th compensation pulse is a partial pulse of the n+4th scan pulse corresponding to the n+4th scan line, and the n+3th compensation pulse is a partial pulse of the n+5th scan pulse corresponding to the n+5th scan line, wherein n=4m-3, and m is a natural number greater than or equal to 1.

[0049] In the embodiment of the present application, each row of scan lines is provided with a corresponding scan pulse, such as the 1st row of scan lines is provided with the 1st scan pulse, the 2nd row of scan lines is provided with the 2nd scan pulse, the 3rd row of scan lines is provided with the 3rd scan pulse, and the nth row of scan lines is provided with the nth scan pulse. n=4m-3, m is a natural number greater than or equal to 1, that is, n is equal to 1, 5, 9, 13, 17, .... Correspondingly, the scan lines whose scan pulses are partially covered are the n+2th row of scan lines and the n+3th row of scan lines. n+2 corresponds to 3, 7, 11, 15, 19, ..., and n+3 corresponds to 3, 7, 11, 15, 19, .... Therefore, in the embodiment of the present application, while providing the corresponding n+2th scan pulse for the n+2th row of scan lines, it is also necessary to provide a compensation pulse, that is, the n+2th compensation pulse corresponding to the n+2th row of scan lines, to compensate for the covered portion accordingly. While providing the corresponding n+3rd scan pulse for the n+3rd scan line, a compensation pulse is also required, namely the n+3th compensation pulse corresponding to the n+3rd scan line, to compensate for the covered portion. Specifically, due to timing limitations, the n+2th compensation pulse provided to the n+2th scan line is a partial pulse of the n+4th scan pulse corresponding to the n+4th scan line, and the n+3th compensation pulse provided to the n+3rd scan line is a partial pulse of the n+5th scan pulse corresponding to the n+5th scan line. That is, during the driving process, by adding a partial pulse of the n+4th scan pulse to the n+2th scan pulse, and adding a partial pulse of the n+5th scan pulse to the n+3th scan pulse, a corresponding compensation pulse can be provided to each scan line that is covered by a scan pulse, enabling the DRD product to achieve HSR mode.

[0050] It should be noted that the pulse widths of the n+2th compensation pulses may be the same or different. Similarly, the pulse widths of the n+3th compensation pulses may be the same or different. The pulse width of the n+2th compensation pulse may be the same as or different from the pulse width of the n+3th compensation pulse. For example, the pulse width of the third compensation pulse corresponding to the third scan line may be the same as or different from the pulse width of the fourth compensation pulse corresponding to the fourth scan line. The pulse width of the third compensation pulse corresponding to the third scan line may be the same as or different from the pulse width of the seventh compensation pulse corresponding to the seventh scan line. The pulse width of the fourth compensation pulse corresponding to the fourth scan line may be the same as or different from the pulse width of the eighth compensation pulse corresponding to the eighth scan line.

[0051] Specifically, when m is 1, n is 1. In this case, the first scan pulse is provided to the first scan line, the second scan pulse is provided to the second scan line, and the third scan pulse and the third compensation pulse are provided to the third scan line. The third compensation pulse is a partial pulse of the fifth scan pulse. The fourth scan pulse and the fourth compensation pulse are provided to the fourth scan line. The fourth compensation pulse is a partial pulse of the sixth scan pulse. When m is 2, n is 5. In this case, the fifth scan pulse is provided to the fifth scan line, the sixth scan pulse is provided to the sixth scan line, and the seventh scan pulse and the seventh compensation pulse are provided to the seventh scan line. The seventh scan pulse is a partial pulse of the ninth scan pulse. The eighth scan pulse and the eighth compensation pulse are provided to the eighth scan line. The eighth compensation pulse is a partial pulse of the tenth scan pulse. And so on.

[0052] Specifically, the gate signal corresponding to the first row of scan lines (i.e., the first scan pulse) is represented by G1, the gate signal corresponding to the second row of scan lines (i.e., the second scan pulse) is represented by G2, and so on, the gate signal corresponding to the nth row of scan lines (i.e., the nth scan pulse) is represented by Gn. Normal gate signals are first provided to the first row of scan lines and the second row of scan lines, that is, a normal G1 signal is provided to the first row of scan lines, and a normal G2 signal is provided to the second row of scan lines. A normal G3 signal and a portion of the G5 signal are provided to the third row of scan lines, that is, a portion of the G5 signal is added to the G3 signal, and a normal G4 signal and a portion of the G6 signal are provided to the fourth row of scan lines, that is, a portion of the G6 signal is added to the G4 signal to compensate for the partially covered signals of the third row of scan lines and the fourth row of scan lines. A normal G5 signal is provided to the fifth row of scan lines, and a normal G6 signal is provided to the sixth row of scan lines. The 7th scan line is supplied with a normal G7 signal and a portion of the G9 signal, that is, a portion of the G9 signal is added to the G7 signal. The 8th scan line is supplied with a normal G8 signal and a portion of the G10 signal, that is, a portion of the G10 signal is added to the G8 signal, to compensate for the partially covered signals of the 7th and 8th scan lines. Similarly, the present application enables the DRD product to achieve the HSR mode by compensating for each covered gate signal.

[0053] Reference Figure 3 , Figure 3 Schematic diagram of gate signal waveform of DRD product realizing HSR mode provided by the embodiment of the present application. The embodiment of the present application is described by taking 8 scan lines as an example. Figure 3As shown, G1 corresponds to the scan pulse corresponding to the 1st scan line, G2 corresponds to the scan pulse corresponding to the 2nd scan line, G3 corresponds to the scan pulse corresponding to the 3rd scan line, G4 corresponds to the scan pulse corresponding to the 4th scan line, G5 corresponds to the scan pulse corresponding to the 5th scan line, G6 corresponds to the scan pulse corresponding to the 6th scan line, G7 corresponds to the scan pulse corresponding to the 7th scan line, and G8 corresponds to the scan pulse corresponding to the 8th scan line. G1 and G2 are normally supplied to the corresponding 1st and 2nd scan lines. For G3 corresponding to the 3rd scan line and G4 corresponding to the 4th scan line, when the pixels in the previous row are turned on, that is, when G1 and G2 are turned on, part of the scan pulse for turning on the pixels in the next row will be consumed, that is, G3 and G4 will be partially covered, resulting in insufficient charging of the pixels in the second row and failure to display normally. In this regard, the embodiment of the present application provides G3 to the 3rd row of scan lines while also providing a portion of G5 pulses, and provides G4 to the 4th row of scan lines while also providing a portion of G6 pulses to compensate for the covered G3 and G4, so that the second row of pixels can be displayed normally. Then, G5 and G6 are normally provided to the corresponding 5th row of scan lines and 6th row of scan lines. For G7 corresponding to the 7th row of scan lines and G8 corresponding to the 8th row of scan lines, since when the pixels in the previous row are turned on, that is, when G5 and G6 are turned on, part of the scan pulses for turning on the next row of pixels will be eaten up, that is, G7 and G8 will be partially covered, resulting in insufficient charging of the fourth row of pixels and inability to display normally. In this regard, the embodiment of the present application provides G7 to the 7th row of scan lines while also providing a portion of G9 pulses, and provides G8 to the 8th row of scan lines while also providing a portion of G10 pulses to compensate for the covered G7 and G8, so that the third row of pixels can be displayed normally. In this way, each covered gate signal can be compensated accordingly, so that the DRD product can achieve the HSR mode.

[0054] In one embodiment of the present application, the pulse width of the (n+2)th compensation pulse is smaller than the pulse width of the (n+4)th scanning pulse, and a first time corresponding to a falling edge of the (n+2)th compensation pulse is no later than a second time corresponding to a falling edge of the (n+4)th scanning pulse. The pulse width of the (n+3)th compensation pulse is smaller than the pulse width of the (n+5)th scanning pulse, and a third time corresponding to a falling edge of the (n+3)th compensation pulse is no later than a fourth time corresponding to a falling edge of the (n+5)th scanning pulse.

[0055] Specifically, continue to refer to Figure 3As shown by the waveform corresponding to gate signal G3, the solid line portion is the pulse waveform of G3 itself before compensation, and the dotted line portion is the corresponding compensated pulse waveform. The pulse width of this compensated pulse waveform is smaller than the pulse width of the pulse waveform corresponding to G5, and the first time T1 corresponding to the falling edge of this compensated pulse waveform is no later than the second time T2 corresponding to the falling edge of the pulse waveform of G5. Similarly, as shown by the waveform corresponding to gate signal G4, the solid line portion is the pulse waveform of G4 itself before compensation, and the dotted line portion is the corresponding compensated pulse waveform. The pulse width of this compensated pulse waveform is smaller than the pulse width of the pulse waveform corresponding to G6, and the third time T3 corresponding to the falling edge of this compensated pulse waveform is no later than the fourth time T4 corresponding to the falling edge of the pulse waveform of G6.

[0056] In one embodiment of the present application, the pulse width of the n+2th compensation pulse is between 10% and 90% of the pulse width of the n+4th scanning pulse, and the pulse width of the n+3th compensation pulse is between 10% and 90% of the pulse width of the n+5th scanning pulse.

[0057] Specifically, the pulse width of the third compensation pulse may be 10%-90% of the pulse width of the fifth scanning pulse, the pulse width of the seventh compensation pulse may be 10%-90% of the pulse width of the ninth scanning pulse, the pulse width of the eleventh compensation pulse may be 10%-90% of the pulse width of the thirteenth scanning pulse, and so on. Similarly, the pulse width of the fourth compensation pulse may be 10%-90% of the pulse width of the sixth scanning pulse, the pulse width of the eighth compensation pulse may be 10%-90% of the pulse width of the tenth scanning pulse, the pulse width of the twelfth compensation pulse may be 10%-90% of the pulse width of the fourteenth scanning pulse, and so on.

[0058] In the embodiment of the present application, the pulse width of the n+2 compensation pulse is between 10% and 90% of the pulse width of the n+4 scanning pulse. The specific value of the pulse width of the n+2 compensation pulse can be adjusted and determined based on the specific situation. As long as the value is between 10% and 90%, compensation for the n+2 scanning pulse can be effectively achieved. Similarly, the pulse width of the n+3 compensation pulse is between 10% and 90% of the pulse width of the n+5 scanning pulse. The specific value of the pulse width of the n+3 compensation pulse can be adjusted and determined based on the specific situation. As long as the value is between 10% and 90%, compensation for the n+3 scanning pulse can be effectively achieved.

[0059] In one embodiment of the present application, the pulse widths of the (n+2)th compensation pulses are different, and / or the pulse widths of the (n+3)th compensation pulses are different.

[0060] In the embodiments of the present application, considering that different scan lines are located at different positions on the display panel, their corresponding resistances and capacitances are different, and thus their effects on pixel charging are different, the embodiments of the present application set the pulse widths of each n+2 compensation pulse to be different, and / or the pulse widths of each n+3 compensation pulse to be different, that is, each n+2 compensation pulse and each n+3 compensation pulse are made to correspond to the corresponding charging effects. If the charging level is greatly reduced, the corresponding compensation is greater, that is, the width of the compensation pulse is set to be larger. If the charging level is reduced less, the corresponding compensation is also less, that is, the width of the compensation pulse can be set to be smaller.

[0061] Specifically, the pulse widths corresponding to the normal scanning pulses are the same, that is, the pulse widths of the scanning pulses that do not require compensation are the same, and the pulse widths corresponding to the n+2 compensation pulses, such as the 3rd compensation pulse, the 7th compensation pulse, the 11th compensation pulse, the 15th compensation pulse, the 19th compensation pulse, etc., may be different. For example, the pulse width of the 3rd compensation pulse is 70% of the pulse width of the 5th scanning pulse, the pulse width of the 7th compensation pulse is 60% of the pulse width of the 9th scanning pulse, the pulse width of the 11th compensation pulse is 50% of the pulse width of the 13th scanning pulse, the pulse width of the 15th compensation pulse is 40% of the pulse width of the 17th scanning pulse, and the pulse width of the 19th compensation pulse is 30% of the pulse width of the 21st scanning pulse.

[0062] Similarly, the pulse widths corresponding to the (n+3) compensation pulse, such as the 4th compensation pulse, the 8th compensation pulse, the 12th compensation pulse, the 16th compensation pulse, the 20th compensation pulse, etc. may all be different, such as the pulse width of the 4th compensation pulse is 70% of the pulse width of the 6th scanning pulse, the pulse width of the 8th compensation pulse is 60% of the pulse width of the 10th scanning pulse, the pulse width of the 12th compensation pulse is 50% of the pulse width of the 14th scanning pulse, the pulse width of the 16th compensation pulse is 40% of the pulse width of the 18th scanning pulse, and the pulse width of the 20th compensation pulse is 30% of the pulse width of the 22nd scanning pulse.

[0063] In one embodiment of the present application, referring to Figure 4 , Figure 4 : is a first structural diagram of a display panel provided by an embodiment of the present application. Figure 4 As shown, the display panel has multiple regions sequentially arranged along a first direction, each region including multiple scan lines, and adjacent regions bordering each other. In this case, the (n+2)th compensation pulse provided to the (n+2)th scan line within the same region has the same pulse width; and / or the (n+3)th compensation pulse provided to the (n+3)th scan line within the same region has the same pulse width.

[0064] Specifically, if the 3rd, 7th, 11th, and 15th scan lines fall within the same region, the compensation pulses provided to the 3rd, 7th, 11th, and 15th scan lines have the same pulse width. For example, the 3rd compensation pulse provided to the 3rd scan line is 40% of the 5th scan pulse, the 7th compensation pulse provided to the 7th scan line is 40% of the 9th scan pulse, the 11th compensation pulse provided to the 11th scan line is 40% of the 13th scan pulse, and the 15th compensation pulse provided to the 15th scan line is 40% of the 17th scan pulse. If the 19th, 23rd, 27th, and 31st scan lines fall within the same region, the compensation pulses provided to the 19th, 23rd, 27th, and 31st scan lines have the same pulse width. For example, the 19th compensation pulse provided to the 19th scan line is 50% of the 21st scan pulse, the 23rd compensation pulse provided to the 23rd scan line is 50% of the 25th scan pulse, the 27th compensation pulse provided to the 27th scan line is 50% of the 29th scan pulse, and the 31st compensation pulse provided to the 31st scan line is 50% of the 33rd scan pulse.

[0065] Similarly, if the 4th, 8th, 12th, and 16th scan lines fall within the same region, the compensation pulses provided to the 4th, 8th, 12th, and 16th scan lines have the same pulse width. For example, the 4th compensation pulse provided to the 4th scan line is 40% of the 6th scan pulse, the 8th compensation pulse provided to the 8th scan line is 40% of the 10th scan pulse, the 12th compensation pulse provided to the 12th scan line is 40% of the 14th scan pulse, and the 16th compensation pulse provided to the 16th scan line is 40% of the 18th scan pulse. If the 20th, 24th, 28th, and 32nd scan lines fall within the same region, the compensation pulses provided to the 20th, 24th, 28th, and 32nd scan lines have the same pulse width. For example, the 20th compensation pulse provided to the 20th scan line is 50% of the 22nd scan pulse, the 24th compensation pulse provided to the 24th scan line is 50% of the 26th scan pulse, the 28th compensation pulse provided to the 28th scan line is 50% of the 30th scan pulse, and the 32nd compensation pulse provided to the 32nd scan line is 50% of the 34th scan pulse.

[0066] It should be noted that the pulse width of the (n+2)th compensation pulse provided to the (n+2)th scan line and the pulse width of the (n+3)th compensation pulse provided to the (n+3)th scan line in the same area may be the same or different. For example, if the 3rd, 4th, 7th and 8th scan lines fall into the same area, the pulse width of the 3rd compensation pulse provided to the 3rd scan line may be the same as the pulse width of the 4th compensation pulse provided to the 4th scan line, the pulse width of the 7th compensation pulse provided to the 7th scan line, and the pulse width of the 8th compensation pulse provided to the 8th scan line. For example, the pulse width of the 3rd compensation pulse is 50% of the pulse width of the 5th scan pulse, the pulse width of the 4th compensation pulse is 50% of the pulse width of the 6th scan pulse, the pulse width of the 7th compensation pulse is 50% of the pulse width of the 9th scan pulse, and the pulse width of the 8th compensation pulse is 50% of the pulse width of the 10th scan pulse. Since the pulse width of the 5th scan pulse, the pulse width of the 6th scan pulse, the pulse width of the 9th scan pulse and the pulse width of the 10th scan pulse are the same, the pulse width of the 3rd compensation pulse, the pulse width of the 4th compensation pulse, the pulse width of the 7th compensation pulse and the pulse width of the 7th compensation pulse are the same.

[0067] In one embodiment of the present application, referring to Figure 5 , Figure 5 : is a second structural diagram of the display panel provided in the embodiment of the present application. Figure 5 As shown, the display panel is sequentially arranged in a first direction with a first area, a second area, and a third area, each area including a plurality of scan lines. In this case, the pulse width of the n+2th compensation pulse provided to the n+2th scan line falling in the first area is the first pulse width, the pulse width of the n+2th compensation pulse provided to the n+2th scan line falling in the second area is the second pulse width, and the pulse width of the n+3th compensation pulse provided to the n+2th scan line falling in the third area is the third pulse width, wherein both the first pulse width and the third pulse width are smaller than the second pulse width; and / or, the pulse width of the n+3th compensation pulse provided to the n+3th scan line falling in the first area is the fourth pulse width, the pulse width of the n+3th compensation pulse provided to the n+3th scan line falling in the second area is the fifth pulse width, and the pulse width of the n+3th compensation pulse provided to the n+3th scan line falling in the third area is the sixth pulse width, wherein both the fourth pulse width and the sixth pulse width are smaller than the fifth pulse width.

[0068] In the embodiment of the present application, considering that the positions of the scan lines on the display panel are different, the corresponding resistances and capacitances are different, resulting in different effects on pixel charging. The present application divides the display area of ​​the display panel into three areas. The resistances and capacitances corresponding to the first area and the third area close to the upper and lower edges of the display panel are smaller than those of the second area in the middle. Therefore, during the compensation process, the pulse width (i.e., the second pulse width) of the n+2 compensation pulse corresponding to the n+2 scan line falling in the middle second area is greater than the pulse width (i.e., the first pulse width) of the n+2 compensation pulse corresponding to the n+2 scan line falling in the first area close to the boundary and greater than the pulse width (i.e., the third pulse width) of the n+2 compensation pulse corresponding to the n+2 scan line falling in the third area close to the boundary, thereby making the compensation more uniform.

[0069] Similarly, during the compensation process, the pulse width of the n+3th compensation pulse corresponding to the n+3th scan line falling in the middle second area (i.e., the fifth pulse width) is greater than the pulse width of the n+3th compensation pulse corresponding to the n+3th scan line falling in the first area close to the boundary (i.e., the fourth pulse width) and greater than the pulse width of the n+3th compensation pulse corresponding to the n+3th scan line falling in the third area close to the boundary (i.e., the fourth pulse width), thereby making the compensation more uniform.

[0070] For example, referring to Figure 6 , Figure 6 This is an example diagram of the structure of the display panel provided by an embodiment of the present application. Assume that the display panel contains a total of 30 rows of scan lines, wherein the 1st to 10th scan lines fall into the first area, the 11th to 20th scan lines fall into the second area, and the 21st to 30th scan lines fall into the third area. The first area is adjacent to the upper boundary of the display panel, the third area is adjacent to the lower boundary of the display panel, and the second area belongs to the middle area. The second area is farther away from the upper and lower boundaries, so that the pixel charging corresponding to each scan line in the second area is more affected. More pulses need to be compensated to each scan line that needs to be compensated in the first area, so that the pixel charging level corresponding to each display area is close, so that each display area can be displayed uniformly. Specifically, for the first area, the compensation pulses provided to the 3rd and 7th scan lines are both 40% of the corresponding scan pulses, and the compensation pulses provided to the 4th and 8th scan lines are both 40% of the corresponding scan pulses. In the second region, the compensation pulses provided to the 11th, 15th, and 19th scan lines are all 60% of the corresponding scan pulses, and the compensation pulses provided to the 12th, 16th, and 20th scan lines are all 60% of the corresponding scan pulses. In the third region, the compensation pulses provided to the 23rd and 27th scan lines are all 40% of the corresponding scan pulses, and the compensation pulses provided to the 24th and 28th scan lines are all 40% of the corresponding scan pulses.

[0071] In one embodiment of the present application, the pulse width of the n+2th compensation pulse provided to the n+2th row scan line falling into the first area is the same as the pulse width of the n+3th compensation pulse provided to the n+3th row scan line falling into the first area, the pulse width of the n+2th compensation pulse provided to the n+2th row scan line falling into the second area is the same as the pulse width of the n+3th compensation pulse provided to the n+3th row scan line falling into the second area, and the pulse width of the n+2th compensation pulse provided to the n+2th row scan line falling into the third area is the same as the pulse width of the n+3th compensation pulse provided to the n+3th row scan line falling into the third area. Thus, providing compensation pulses of the same pulse width to the scan lines to be compensated in the same area can make the compensation in the same area the same and the display brightness close.

[0072] For example, different proportions of compensation can be given to scan lines in different areas to achieve the best effect. For example, the compensation pulses corresponding to the 1 / 5 scan lines that need to be compensated near the upper and lower boundaries (including the n+2 scan line and the n+3 scan line) can correspond to 20%-60% of the normal scan pulse; the compensation pulses corresponding to the next 1 / 5 scan lines that need to be compensated (including the n+2 scan line and the n+3 scan line) can correspond to 30%-70% of the normal scan pulse; the compensation pulses corresponding to the remaining 1 / 5 scan lines that need to be compensated in the middle (including the n+2 scan line and the n+3 scan line) can correspond to 40%-80% of the normal scan pulse, so as to achieve the best effect. Adjustments can be made here based on the specific actual effect, which is determined by the taste of the actual display panel.

[0073] Reference Figure 7-Figure 8 , Figure 7 is a schematic diagram of a first structure of a display panel provided in an embodiment of the present application, Figure 8 is a second structural diagram of a display panel provided in an embodiment of the present application. The present application also provides a display panel driven by the display driving method provided in any embodiment of the present application, the display panel comprising: a plurality of scan lines 10 spaced apart and arranged along a first direction; a plurality of data lines 20 spaced apart and arranged along a second direction, the second direction intersecting the first direction; the scan lines 10 and the data lines 20 being insulated and intersecting and defining a plurality of pixel regions, each pixel region being provided with two sub-pixels along the first direction, the gates of the two sub-pixels being connected to two different scan lines 10, the sources of the two sub-pixels being connected to a single data line 20, and the two sub-pixels being distributed on either side of the single data line 20.

[0074] In the embodiment of this application, Figure 7 and Figure 8 The architecture shown can realize the DRD driving mode, that is, Figure 7 and Figure 8The architecture shown is a DRD architecture product. This type of DRD architecture product can be applied to DLG (double frequency refresh technology) driven scenarios through timing adjustment, but it will cause the problem of thick images during the display process. This type of DRD architecture product can be applied to HSR driven scenarios through the display driving method provided by any embodiment of the present application, that is, by performing corresponding pulse compensation on the covered scan pulses. Compared with DLG drive, there will be a smooth transition between rows in the HSR drive process, which can reduce the jaggedness of the picture and make the picture look more delicate than the DLG driven picture.

[0075] It should be noted that for DRD architecture products, when feeding the scan pulse, the order of the scan pulse signal will be changed by adjusting the design of the PCB (printed circuit board) end. For example, the original order of G1, G2, G3, G4, G5, G6, G7, G8 is changed to the order of G1, G3, G2, G4, G5, G7, G6, G8, which can also be understood as changing G3 to G2, such as Figure 9 In this case, we only need to theoretically charge G3 with more pulses of G5 and G4 with more pulses of G6, as shown in the following example: Figure 10 As shown in , HSR technology can still be implemented. Figure 11 As shown, for the case where the original order of G1, G2, G3, G4, G5, G6, G7, G8 is changed to the order of G4, G1, G2, G3, G5, G8, G7, G6, similarly, G3 is charged with more pulses of G5, and G4 is charged with more pulses of G6, as shown in FIG. Figure 12 As shown, HSR technology can still be implemented.

[0076] The embodiment of the present application also provides a display device, including a display panel and a timing controller, wherein the timing controller is connected to the display panel and is used to execute the driving method provided in any embodiment of the present application to drive the display panel. Figure 7 or Figure 8 The display panel of the DRD architecture is shown.

[0077] In the embodiment of the present application, the timing controller of the display device can realize HSR driving using the DRD method by making corresponding pulse compensation for the covered scanning pulse. The refresh rate can be increased without increasing the cost, and the problem of rough image will not occur, which can effectively improve the competitiveness of the product.

[0078] In one embodiment of the present application, the timing controller includes a level conversion circuit, and the level conversion circuit is used to provide a corresponding scan pulse for each scan line.

[0079] In the embodiment of the present application, a level shift IC in the timing controller performs corresponding pulse compensation on the scan pulse that needs to be compensated, thereby enabling the DRD product to implement the HSR mode.

[0080] See also Figure 13 , Figure 13 : is a schematic diagram of the hardware structure of a display device provided in an embodiment of the present application, the display device includes:

[0081] The processor 1301 may be implemented using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is configured to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0082] The memory 1302 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1302 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1302 and is called by the processor 1301 to execute the display driving method of the embodiments of this application.

[0083] Input / output interface 1303, used to implement information input and output;

[0084] Communication interface 1304, used to implement communication interaction between this device and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, Wi-Fi, Bluetooth, etc.);

[0085] Bus 1305 , which transmits information between various components of the device (e.g., processor 1301 , memory 1302 , input / output interface 1303 , and communication interface 1304 );

[0086] The processor 1301 , the memory 1302 , the input / output interface 1303 and the communication interface 1304 are connected to each other in communication within the device via a bus 1305 .

[0087] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0088] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0089] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0090] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0091] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0092] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0093] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0094] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0095] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0096] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store programs.

[0097] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A display driving method for driving a display panel, characterized in that: The method comprises: In the process of driving in hardware super-resolution mode, a corresponding nth scan pulse is provided to the nth scan line, a corresponding n+1th scan pulse is provided to the n+1th scan line, a corresponding n+2th scan pulse and an n+2th compensation pulse are provided to the n+2th scan line, and a corresponding n+3th scan pulse and an n+3th compensation pulse are provided to the n+3th scan line, wherein the n+2th compensation pulse is a partial pulse of the n+4th scan pulse corresponding to the n+4th scan line, and the n+3th compensation pulse is a partial pulse of the n+5th scan pulse corresponding to the n+5th scan line, wherein n=4m-3, and m is a natural number greater than or equal to 1.

2. The method according to claim 1, wherein: The pulse width of the n+2 th compensation pulse is smaller than the pulse width of the n+4 th scanning pulse, and a first time corresponding to a falling edge of the n+2 th compensation pulse is no later than a second time corresponding to a falling edge of the n+4 th scanning pulse; The pulse width of the n+3th compensation pulse is smaller than the pulse width of the n+5th scan pulse, and the third time corresponding to the falling edge of the n+3th compensation pulse is no later than the fourth time corresponding to the falling edge of the n+5th scan pulse.

3. The method according to claim 1 or 2, characterized in that The pulse width of the n+2 th compensation pulse is between 10% and 90% of the pulse width of the n+4 th scan pulse, and the pulse width of the n+3 th compensation pulse is between 10% and 90% of the pulse width of the n+5 th scan pulse.

4. The method according to claim 1, wherein The pulse widths of the (n+2)th compensation pulses are different, and / or the pulse widths of the (n+3)th compensation pulses are different.

5. The method according to claim 1, wherein The display panel has a plurality of regions sequentially arranged along a first direction, each region includes a plurality of scan lines, and adjacent regions are adjacent to each other; wherein: The pulse width of the (n+2)th compensation pulse provided to the (n+2)th scan line falling within the same area is the same; And / or, the pulse widths of the (n+3)th compensation pulses provided to the (n+3)th scan lines falling within the same region are the same.

6. The method according to claim 1, characterized in that The display panel comprises a first area, a second area and a third area arranged in sequence in a first direction, each area comprising a plurality of scan lines; wherein: The pulse width of the n+2th compensation pulse provided to the n+2th scan line falling within the first region is a first pulse width, the pulse width of the n+2th compensation pulse provided to the n+2th scan line falling within the second region is a second pulse width, and the pulse width of the n+3th compensation pulse provided to the n+2th scan line falling within the third region is a third pulse width, wherein both the first pulse width and the third pulse width are smaller than the second pulse width; and / or, The pulse width of the n+3rd compensation pulse provided to the n+3th scan line falling into the first area is the fourth pulse width, the pulse width of the n+3th compensation pulse provided to the n+3th scan line falling into the second area is the fifth pulse width, and the pulse width of the n+3th compensation pulse provided to the n+3th scan line falling into the third area is the sixth pulse width, wherein the fourth pulse width and the sixth pulse width are both smaller than the fifth pulse width.

7. A display panel, characterized in that: Driven by the method according to any one of claims 1 to 6, the display panel comprises: a plurality of scan lines spaced apart and arranged along a first direction; a plurality of data lines spaced apart and arranged along a second direction, wherein the second direction intersects the first direction; The scan lines and the data lines are insulated and intersect to define a plurality of pixel areas, each of the pixel areas is provided with two sub-pixels along the first direction, the gates of the two sub-pixels are connected to two different scan lines, the sources of the two sub-pixels are connected to the same data line, and the two sub-pixels are distributed on both sides of the same data line.

8. A display device, characterized in that: include: The display panel according to claim 7; A timing controller is connected to the display panel and is used to execute the method according to any one of claims 1 to 6 to drive the display panel.

9. The display device according to claim 8, wherein The timing controller includes a level conversion circuit, and the level conversion circuit is used to provide a corresponding scan pulse for each scan line.

10. A display device, characterized in that: The display device includes a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 6 when executing the computer program.

Images