Display panel and display device

Abstract

The display panel and the display device provided by the embodiments of the present disclosure include a driving back plate, a plurality of pixel islands, and a plurality of first electrode pad groups. The driving back plate includes a substrate, a plurality of driving circuits arranged on the substrate, and a plurality of positive pad located on a side of the driving circuit away from the substrate. The pixel islands are located on the driving back plate and include a plurality of first sub-pixels. The first electrode pad groups are located between the pixel islands and the driving back plate, and the orthographic projection of the first electrode pad groups on the substrate is located within the orthographic projection range of the corresponding pixel islands on the substrate. The first electrode pad groups include a plurality of first electrode pads, and the first electrode pads are connected to the positive pad. The number of rows of the first electrode pads in the first electrode pad groups is greater than the number of rows of the first sub-pixels in the pixel islands, and the number of columns of the first electrode pads in the first electrode pad groups is less than the number of columns of the first sub-pixels in the pixel islands. The first electrode pads are electrically connected to the first sub-pixels through first lead lines, and the positive pad is electrically connected to the driving circuit through second lead lines.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] As a new display technology, light-emitting diode (LED) display technology has significant advantages over liquid crystal display (LCD) and organic light-emitting diode (OLED) displays in terms of image quality, refresh rate, power consumption, and brightness, making LED displays widely applicable. For example, LED displays can be used in traditional displays, near-eye displays, 3D displays, and transparent displays. However, limitations imposed by mass transfer technology restrict LED displays to some extent, especially for high-resolution (PPI) displays.

[0003] Light-emitting diode (LED) chips can include sub-millimeter LED (Mini LED) chips and micro LED (Micro LED) chips. Subdividing Mini LED pixel islands involves etching the P-electrode and P-type semiconductor layer within the island to divide a single Mini LED pixel island into multiple sub-pixels, each at the Micro LED level. This subdivision enables high PPI displays. The subdivided Mini LED pixel islands then need to be transferred to a driver backplane to form an LED display panel for display purposes. Summary of the Invention

[0004] This disclosure provides a display panel and a display device, the specific solutions of which are as follows:

[0005] This disclosure provides a display panel having a display area, the display area including:

[0006] A driving backplane includes a substrate, multiple driving circuits arrayed on the substrate, and multiple positive electrode pads located on the side of the driving circuits away from the substrate.

[0007] Multiple pixel islands are located on the driving backplate, and each pixel island includes multiple first sub-pixels of the same color;

[0008] Multiple first electrode pad groups are located between the multiple pixel islands and the driving backplane. Each first electrode pad group corresponds one-to-one with a pixel island, and the orthographic projection of the first electrode pad group onto the substrate lies within the orthographic projection range of the corresponding pixel island onto the substrate. Each first electrode pad group includes multiple first electrode pads, which are bonded to the positive electrode pad.

[0009] The number of rows of the first electrode pads in each first electrode pad group is greater than the number of rows of the first sub-pixel in each pixel island, and the number of columns of the first electrode pads in each first electrode pad group is less than the number of columns of the first sub-pixel in each pixel island.

[0010] The first electrode pad is electrically connected to the first sub-pixel via a first lead, and the positive electrode pad is electrically connected to the driving circuit via a second lead.

[0011] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the plurality of positive electrode pads are divided into a plurality of positive electrode pad groups, and the positive electrode pad groups correspond one-to-one with the first electrode pad group.

[0012] The plurality of driving circuits are divided into a plurality of driving circuit groups, and each driving circuit group corresponds one-to-one with the positive electrode pad group. The orthogonal projection area of ​​each positive electrode pad group on the substrate is smaller than the orthogonal projection area of ​​the driving circuit group on the substrate.

[0013] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the orthographic projection of the second lead on the substrate is located within the orthographic projection range of the gap between two adjacent rows of the first sub-pixels on the substrate, and / or, the orthographic projection of the second lead on the substrate is located within the orthographic projection range of the gap between two adjacent columns of the first sub-pixels on the substrate.

[0014] In one possible implementation, in the display panel provided in the embodiments of this disclosure, at least a portion of the second leads have overlapping areas with other second leads, and for two second leads having overlapping areas, one of the second leads is bridged by a bridging portion in the overlapping area.

[0015] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the driving backplane further includes a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer sequentially stacked between the driving circuit and the positive electrode pad, wherein the first insulating layer is close to the driving circuit; wherein...

[0016] A portion of the second lead is located in the first metal layer;

[0017] The other part of the second lead includes a first sub-lead, the bridging portion, and a second sub-lead. Both the first sub-lead and the second sub-lead are located in the first metal layer, and the bridging portion is located in the second metal layer. One end of the first sub-lead is electrically connected to the driving circuit through a via penetrating the first insulating layer, and the other end of the first sub-lead is electrically connected to one end of the bridging portion through a via penetrating the second insulating layer. One end of the second sub-lead is electrically connected to the other end of the bridging portion through a via penetrating the second insulating layer, and the other end of the second sub-lead is electrically connected to the positive electrode pad.

[0018] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the driving backplane further includes: a first planarization layer located between the second metal layer and the positive electrode pad, and a third insulating layer located between the first planarization layer and the positive electrode pad; the other end of the second sub-lead is electrically connected to the positive electrode pad through a via that sequentially penetrates the second insulating layer, the first planarization layer and the third insulating layer.

[0019] In one possible implementation, in the display panel provided in the embodiments of this disclosure, each first sub-pixel includes a first electrode, a first semiconductor layer, a quantum well layer, a second semiconductor layer, and a second electrode stacked together, with the first electrode close to the driving backplate;

[0020] The display panel further includes a fourth insulating layer located between the first electrode and the first electrode pad, one end of the first lead is electrically connected to the first electrode pad, and the other end of the first lead is electrically connected to the first electrode through a via penetrating the fourth insulating layer.

[0021] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the first electrode pad and the first lead are disposed on the same layer.

[0022] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the quantum well layers of each first sub-pixel within the same pixel island are integral structures, the second semiconductor layers of each first sub-pixel within the same pixel island are integral structures, and the second electrodes of each first sub-pixel within the same pixel island are integral structures.

[0023] In one possible implementation, the display panel provided in the embodiments of this disclosure further includes a second electrode pad disposed on the same layer as the first electrode pad, wherein the second electrode in the same pixel island is electrically connected to the same second electrode pad, and the second electrode in different pixel islands is electrically connected to different second electrode pads.

[0024] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the second electrode pad is located in the area between two adjacent columns of the first electrode pad group.

[0025] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the driving backplate further includes a negative electrode pad disposed on the same layer as the positive electrode pad, and the negative electrode pad is bonded to the second electrode pad.

[0026] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the driving backplane further includes: a fifth insulating layer located on the side of the positive electrode pad facing away from the substrate, and a second planarization layer located on the side of the fifth insulating layer facing away from the substrate; the fifth insulating layer and the second planarization layer have a first exposed area exposing the positive electrode pad and a second exposed area exposing the negative electrode pad, the first electrode pad being bonded to the positive electrode pad through the first exposed area, and the second electrode pad being bonded to the negative electrode pad through the second exposed area.

[0027] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the driving circuit includes a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, a second gate, an interlayer insulating layer, and source / drain electrodes stacked sequentially between the substrate and the first insulating layer; one end of the first sub-lead is electrically connected to the drain electrode of the driving circuit through a via penetrating the first insulating layer, the drain electrode is electrically connected to the active layer, and the source electrode of the driving circuit is electrically connected to the first gate and the second gate, respectively.

[0028] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the driving backplane further includes: a first conductive connection portion and a second conductive connection portion located in the first metal layer, a low-voltage power supply line and a high-voltage power supply line disposed in the same layer as the source and drain electrodes, a third conductive connection portion and a fourth conductive connection portion disposed in the same layer as the second gate, and a shielding electrode disposed in the same layer as the first gate.

[0029] The negative electrode pad is electrically connected to the first conductive connection portion through a via penetrating the third insulating layer, the first planarization layer, and the second insulating layer. The first conductive connection portion is electrically connected to the low-voltage power line through a via penetrating the first insulating layer. The low-voltage power line is electrically connected to the third conductive connection portion through a via penetrating the interlayer insulating layer. The second conductive connection portion is electrically connected to the high-voltage power line through a via penetrating the first insulating layer. The high-voltage power line is electrically connected to the fourth conductive connection portion through a via penetrating the interlayer insulating layer. The high-voltage power line is electrically connected to the shielding electrode through a via penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

[0030] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the plurality of pixel islands are spaced apart along the row and column directions. The negative electrode pads of each pixel island in the same column are electrically connected to the same low-voltage power line. The driving circuits of each pixel island in the same column are electrically connected to the same high-voltage power line. A high-voltage power line and a low-voltage power line are provided in the gap between two adjacent columns of pixel islands.

[0031] In one possible implementation, the display panel provided in the embodiments of this disclosure includes multiple rows and columns of pixel units with different light emission colors. The pixel units located in the same row have the same light emission color, and the pixel units with different light emission colors located in the same column are alternately arranged.

[0032] Each pixel unit includes at least two pixel islands spaced apart, the at least two pixel islands in each pixel unit are staggered along the row direction, and the outermost adjacent first sub-pixels of adjacent pixel islands in each pixel unit are staggered along the row direction.

[0033] In one possible implementation, in the display panel provided in the embodiments of this disclosure, a plurality of first sub-pixels in each pixel island are spaced apart along the row direction and the column direction, the first sub-pixels in each row of each pixel island are staggered sequentially along the row direction, and the distance between adjacent first sub-pixels in the same row is less than the width of the first sub-pixel along the row direction.

[0034] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the distance between any two adjacent first sub-pixels along the center line of the column direction is equal.

[0035] In one possible implementation, the display panel provided in the embodiments of this disclosure further includes a GOA driving circuit, an EOA driving circuit, and a MUX circuit. The GOA driving circuit and the EOA driving circuit are respectively disposed between two adjacent columns of the pixel units, and the MUX circuit is disposed between two adjacent rows of the pixel units.

[0036] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the pixel island includes a Mini LED pixel island.

[0037] Accordingly, this disclosure also provides a display device, including at least one of the display panels provided in this disclosure.

[0038] In one possible implementation, the display device provided in the embodiments of this disclosure further includes a plurality of lenses located on the light-emitting side of the display panel;

[0039] The plurality of lenses correspond one-to-one with the plurality of pixel islands, or each of the lenses corresponds one-to-one with each of the first sub-pixels in each of the pixel islands;

[0040] The light emitted from each of the first sub-pixels in each of the pixel islands is incident on the corresponding lens.

[0041] In one possible implementation, in the display device provided in the embodiments of this disclosure, the display panel further includes a splicing area disposed around the display area, and the display device includes at least two display panels spliced ​​together, wherein the splicing area of ​​the at least two display panels is provided with a plurality of second sub-pixels arranged in the same manner as the first sub-pixels. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure of a Mini LED pixel island subdivided into the first sub-pixel in a related technology.

[0043] Figure 2 A plan view of each Mini LED pixel island in a display panel provided in an embodiment of this disclosure;

[0044] Figure 3 for Figure 2 Enlarged view within the dashed box A;

[0045] Figure 4 for Figure 3 A planar diagram of a pixel island;

[0046] Figure 5 This is a cross-sectional schematic diagram of a pixel island in a display panel provided in an embodiment of the present disclosure;

[0047] Figure 6 for Figure 2 A planar schematic diagram of the specific film layers within the pixel island corresponding to the three pixel units (R, G, B);

[0048] Figure 7 for Figure 6 A planar schematic diagram corresponding to a pixel island;

[0049] Figure 8 To and Figure 2 A planar schematic diagram of the inner film layer of the driving backplate corresponding to the pixel island shown;

[0050] Figure 9 for Figure 8 Enlarged view within the dashed box B;

[0051] Figure 10 for Figure 9 A magnified view of a portion of the image;

[0052] Figure 11 for Figure 5 Local structures within;

[0053] Figure 12 for Figure 5 Local structures within;

[0054] Figure 13 for Figure 10 A planar schematic diagram of the drive circuit 12;

[0055] Figure 14 In order to be in Figure 13 Based on Figure 10 A planar schematic diagram of the second lead, the first sub-lead, and the second sub-lead included in the first metal layer;

[0056] Figure 15 In order to be in Figure 14 Based on Figure 10 A plan view of the second metal layer (bridging section);

[0057] Figure 16 for Figure 6 Another planar schematic diagram corresponding to a pixel island;

[0058] Figure 17 A plan view of yet another display panel provided in an embodiment of this disclosure;

[0059] Figure 18 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0060] Figure 19 This is a schematic diagram of the structure of another display device provided in an embodiment of the present disclosure;

[0061] Figure 20 This is a schematic diagram of the structure of a splicing display device provided in an embodiment of this disclosure. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0063] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0064] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0065] like Figure 1 As shown, Figure 1This is a schematic diagram of a Mini LED pixel island structure for subdividing the first sub-pixels in related technologies. A Mini LED pixel island can be subdivided into multiple first sub-pixels 21. Specifically, an etching process is used to divide the P-electrode layer of the Mini LED chip into first electrodes 211 of multiple first sub-pixels 21, and to divide the P-type semiconductor layer into first semiconductor layers 212 of multiple first sub-pixels 21. Multiple first sub-pixels 21 can share an N-type semiconductor layer (second semiconductor layer 214) and a quantum well layer (MQW) 213. This achieves the subdivision of a Mini LED pixel island into multiple first sub-pixels 21, each of which is of Micro LED-level size. After the Mini LED pixel island is subdivided into first sub-pixels 21, it needs to be transferred to a driving backplane on a glass substrate. The P-electrode pads (first electrode pads 31) of each first sub-pixel on the Mini LED pixel island and the common N-electrode pads (second electrode pads 31') are respectively bonded to the pre-reserved positive and negative electrode pads on the driving backplane.

[0066] In related technologies, multiple first sub-pixels with the same emission color in the same row are usually grouped into a pixel island. Since the pixel island needs to be transferred to the driving backplane, this undoubtedly increases the difficulty of alignment during the transfer process. For example Figure 2 and Figure 3 As shown, Figure 2 This is a plan view of each Mini LED pixel island in a display panel provided by an embodiment of the present disclosure. Figure 3 for Figure 2 The enlarged schematic diagram within the dashed box A includes multiple rows and columns of pixel units (R, G, B) with different emission colors. Pixel units in the same row have the same emission color, while pixel units (R, G, B) with different emission colors in the same column are alternately arranged. For example, pixel units in the same column are arranged in the order R, G, B, R, G, B, R, G, B... Each pixel unit (e.g., R) includes at least two pixel islands 2 (taking three as an example) spaced apart. The at least two pixel islands 2 within each pixel unit (e.g., R) are staggered along the row direction X, and the outermost adjacent first sub-pixels 21 of adjacent pixel islands 2 within each pixel unit (e.g., R) are staggered along the row direction X. This invention provides... Figure 2 The arrangement of pixel islands 2 shown can reduce the alignment difficulty when transferring pixel islands 2 to the driver backplane for bonding and connection.

[0067] Figure 2 Taking the example of each pixel island 2 being subdivided into 17 first subpixels 21, in actual production, each pixel island 2 is subdivided into even more first subpixels 21, for example, as Figure 4As shown, each pixel island 2 is subdivided into 65 sub-pixels 21. Theoretically, a corresponding pixel should be set vertically above each first sub-pixel 21. Figure 1 The P-electrode pads shown are used, but because the spacing of the first sub-pixels 21 subdivided within each pixel island 2 along the row direction X is very small, generally less than 10 μm, and the width of the P-electrode pads of each first sub-pixel 21 is generally greater than the width of the P-electrode, it is insufficient to fabricate P-electrode pads corresponding one-to-one with each first sub-pixel 21 vertically above each first sub-pixel 21. Furthermore, the P-electrode pads need to be bonded one-to-one with the positive pads on the driving backplane, and the positive pads on the driving backplane need to be electrically connected one-to-one with the driving circuits. Since the number of first sub-pixels 21 subdivided within each pixel island 2 is large, the number of driving circuits on the driving backplane also increases, and the area occupied by the driving circuits is large. Therefore, it is also impossible to fabricate each positive pad vertically above each driving circuit. Therefore, for the current scheme where each pixel island is subdivided into several first sub-pixels, how to achieve effective bonding between the pixel island and the driving backplane is a problem that urgently needs to be solved by those skilled in the art.

[0068] In view of this, embodiments of the present disclosure provide a display panel having a display area, such as Figure 2 , Figures 5-10 As shown, Figure 2 , Figures 5-10 Only the display area is shown. Figure 5 This is a cross-sectional diagram of a pixel island in the display panel. Figure 6 for Figure 2 A planar schematic diagram of the specific film layers within a pixel island corresponding to the three pixel units (R, G, B) (taking an example where the first sub-pixel of a pixel island consists of 65 pixels). Figure 7 for Figure 6 A planar diagram corresponding to one pixel island. Figure 8 To and Figure 2 The diagram shows a planar representation of the inner film layer of the driving backplane corresponding to the pixel island. Figure 9 for Figure 8 Enlarged view within the dashed box B. Figure 10 for Figure 9 The enlarged view shows a portion of the display panel, whose display area includes:

[0069] Drive backplane 1, such as Figure 5 , Figures 8-10 As shown, it includes a substrate 11, multiple driving circuits 12 arrayed on the substrate 11, and multiple positive electrode pads 13 located on the side of the driving circuits 12 away from the substrate 11.

[0070] Multiple pixel islands 2, such as Figure 2 , Figures 5-7As shown, located on the driving backplate 1, each pixel island 2 includes multiple first sub-pixels 21 of the same color;

[0071] Multiple first electrode pad groups 3, such as Figures 5-7 As shown, located between multiple pixel islands 2 and the driving backplate 1, the first electrode pad group 3 corresponds one-to-one with the pixel island 2, and the orthographic projection of the first electrode pad group 3 on the substrate 11 is within the orthographic projection range of the corresponding pixel island 2 on the substrate 11; each first electrode pad group 3 includes multiple first electrode pads 31, and the first electrode pads 31 are bonded to the positive electrode pad 13; wherein,

[0072] like Figure 6 and Figure 7 As shown, the number of rows of the first electrode pads 31 in each first electrode pad group 3 is greater than the number of rows of the first sub-pixels 21 in each pixel island 2, and the number of columns of the first electrode pads 31 in each first electrode pad group 3 is less than the number of columns of the first sub-pixels 21 in each pixel island 2.

[0073] like Figures 5-7 As shown, the first electrode pad 31 and the first sub-pixel 21 are electrically connected via the first lead 4; Figure 5 , Figure 9 and Figure 10 As shown, the positive electrode pad 13 is electrically connected to the drive circuit 12 via the second lead 5.

[0074] The display panel provided in this embodiment solves the problem in the related art of not being able to create a first electrode pad 31 corresponding to each first sub-pixel 21 vertically above each first sub-pixel 21 by setting the number of rows of the first electrode pad 31 in the first electrode pad group 3 corresponding to each pixel island 2 to be greater than the number of rows of the first sub-pixel 21 in each pixel island 2, and setting the number of columns of the first electrode pad 31 in the first electrode pad group 3 corresponding to each pixel island 2 to be less than the number of columns of the first sub-pixel 21 in each pixel island 2. For example, in this embodiment, each pixel island 2 includes 65 first sub-pixels and is arranged in 2 rows. The first row includes 33 first sub-pixels 21 and the second row includes 32 first sub-pixels. By arranging the 65 first electrode pads 31 corresponding to each pixel island 2 into 5 rows and 13 columns, and by electrically connecting each first electrode pad 31 to the corresponding first sub-pixel 21 through the first lead 4, the problem of insufficient first electrode pads 31 corresponding to each first sub-pixel 21 vertically above each first sub-pixel 21 can be solved.

[0075] It should be noted that, Figure 5 This diagram illustrates the situation where the drive backplate 1 and pixel island 2 have not yet been bound after alignment.

[0076] Optionally, such as Figure 6 and Figure 7 As shown, the multiple first electrode pads 31 corresponding to each pixel island 2 can be distributed at equal intervals. The distance between two adjacent first electrode pads 31 can be the same as or different from the distance between adjacent first sub-pixels 21.

[0077] It should be noted that in this embodiment, a pixel island is subdivided into 65 first sub-pixels, which are arranged in two rows. The first row has 33 first sub-pixels, and the second row has 32 first sub-pixels. The first sub-pixels in the two rows are staggered in the row direction. The first electrode pads are arranged in 5 rows and 13 columns as an example. If a pixel island is subdivided into 66 first sub-pixels, the first electrode pads can be arranged in 6 rows and 11 columns or in 3 rows and 22 columns. If a pixel island is subdivided into 61 first sub-pixels... If a pixel island is subdivided into 62 first subpixels, the first electrode pads can also be arranged in 5 rows and 13 columns (M must be greater than 2). In this case, the last column only needs to include 1 first electrode pad. If a pixel island is subdivided into 62 first subpixels, the first electrode pads can also be arranged in 5 rows and 13 columns. In this case, the last column only needs to include 2 first electrode pads. The arrangement of the first electrode pads corresponding to each pixel island can be determined according to the number of first subpixels subdivided within a pixel island.

[0078] In practical implementation, since the positive electrode pads of the driving backplane need to be bonded one-to-one with the first electrode pads electrically connected to the pixel islands, the positions of the positive electrode pads corresponding to each pixel island need to correspond one-to-one with the first electrode pads corresponding to that pixel island. Because the driving circuit occupies a large area, it is impossible to position each positive electrode pad vertically above each driving circuit. Therefore, in the display panel provided in the embodiments of this disclosure, as... Figure 8 and Figure 9 As shown, the multiple positive electrode pads 13 are divided into multiple positive electrode pad groups 10. Figure 9 Positive electrode pad group 10 and Figure 6 The first electrode pad group 3 in the middle corresponds one-to-one;

[0079] like Figure 9 As shown, the multiple driving circuits 12 are divided into multiple driving circuit groups 20, and each driving circuit group 20 corresponds one-to-one with a positive electrode pad group 10. The projected area of ​​each positive electrode pad group 10 on the substrate 11 is smaller than the projected area of ​​the driving circuit group 20 on the substrate 11. Specifically, as... Figure 9 As shown, the positions of each positive electrode pad group 10 need to be aligned with... Figure 6The positions of each first electrode pad group 3 shown are one-to-one. Because the driving circuit 12 occupies a large area, each positive electrode pad group 10 only occupies a local area above the corresponding driving circuit group 20. For example, each rectangle represents a driving circuit 12, and multiple driving circuits 12 are evenly distributed on the substrate. Figure 9 The 65 positive electrode pads in the upper left corner need to be connected with... Figure 6 The 65 first electrode pads 31 corresponding to the pixel island 2 in the upper left corner are bound one-to-one. Figure 9 The 65 positive electrode pads 13 in the upper left corner only occupy a local area above the corresponding driving circuit group 20. That is, the 65 first electrode pads 31 cannot be set vertically above each driving circuit 12. Therefore, the 65 first electrode pads 31 need to be electrically connected to the corresponding driving circuit 12 through the second lead 5. This solves the problem of how to electrically connect the positive electrode pads 13 and the driving circuit 12 because the position of the positive electrode pads 13 bound to each pixel island 2 needs to match the position of the first electrode pads 13. This achieves effective bonding and connection between the pixel island 2 and the driving backplate 1, and enables independent control of light emission for each first sub-pixel 21.

[0080] Therefore, in this embodiment of the present disclosure, each driving circuit 12 is electrically connected to the positive electrode pad 13 one by one through the second lead 5, so that one-to-one driving of multiple viewpoints can be realized during light field display.

[0081] Optionally, the driving circuit can be a driving circuit with compensation function, such as a PAM driver, a PWM driver, or a PAM+PWM driver, for example, a 3T1C pixel circuit, a 7T1C pixel circuit, etc.; the driving circuit can be one-to-one with the first sub-pixel, or it can be a time-division multiplexing circuit with one driving circuit corresponding to multiple first sub-pixels. In the embodiments of this disclosure, the driving circuit is one-to-one with the first sub-pixel.

[0082] Optionally, the substrate material can be formed from at least one of polymer materials such as polyimide (PI), polyethylene (PE), polypropylene (PP), polyethylene terephthalate (PET), polycarbonate (PC), and fiber-reinforced polymer (FRP).

[0083] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figures 8-10As shown, since each positive pad group 10 includes 5 rows and 13 columns of positive pads 13, the corresponding driving circuits 12 electrically connected to the positive pad group 10 are also arranged in 5 rows and 13 columns. For example, the first row of positive pads 13 in the 5 rows and 13 columns of positive pads 13 is electrically connected to the first row of driving circuits 12 through corresponding second leads 5; the second row of positive pads 13 is electrically connected to the second row of driving circuits 12 through corresponding second leads 5; the third row of positive pads 13 is electrically connected to the third row of driving circuits 12 through corresponding second leads 5; the fourth row of positive pads 13 is electrically connected to the fourth row of driving circuits 12 through corresponding second leads 5; and the fifth row of positive pads 13 is electrically connected to the fifth row of driving circuits 12 through corresponding second leads 5. To avoid each second lead 5 occupying the border area, each second lead 5 is arranged to run from the gap between two adjacent rows of first sub-pixels 21 and / or the gap between two adjacent columns of first sub-pixels. Therefore, in the above-mentioned display panel provided in the embodiments of this disclosure, as Figure 9 and Figure 10 As shown, the orthographic projection of the second lead 5 on the substrate 11 can be located within the orthographic projection range of the gap between two adjacent rows of first sub-pixels 21 on the substrate 11, and / or, the orthographic projection of the second lead 5 on the substrate 11 can be located within the orthographic projection range of the gap between two adjacent columns of first sub-pixels 21 on the substrate 11. For example, the orthographic projection of the second lead 5 corresponding to the positive pads 13 in the first and second rows on the substrate 11 is located within the orthographic projection range of the gap between two adjacent rows of first sub-pixels 21 on the substrate 11; the orthographic projection of the second lead 5 corresponding to the positive pads 13 in the third to fifth rows is partly located within the orthographic projection range of the gap between two adjacent rows of first sub-pixels 21 on the substrate 11, and partly located within the orthographic projection range of the gap between two adjacent columns of first sub-pixels 21 on the substrate 11. Of course, the orthographic projection of the second lead 5 on the substrate 11 can also be located within the orthographic projection range of the gap between two adjacent columns of first sub-pixels 21 on the substrate 11. The routing method of each second lead 5 can be set according to actual needs, as long as each positive electrode pad 13 can be electrically connected to the corresponding driving circuit 12 through the second lead 5.

[0084] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 , Figure 9 and Figure 10As shown, some positive pads 13 (e.g., the first, second, and fifth rows) can have their second leads 5 electrically connected to the same metal layer directly routed. However, the second leads 5 electrically connected to the third row of positive pads 13 will have overlapping areas with the second leads 5 corresponding to the fourth row of positive pads 13, and the second leads 5 electrically connected to the fourth row of positive pads 13 will have overlapping areas with the second leads 5 corresponding to the fifth row of positive pads 13. That is, at least some of the second leads 5 overlap with other second leads 5. If the second leads 5 electrically connected to the third and fourth rows of positive pads 13 use the same metal layer routed, they will be short-circuited with the corresponding second leads 5 electrically connected to the fourth and fifth rows. Therefore, the second leads 5 electrically connected to the third and fourth rows of positive pads 13 will be short-circuited with the second leads 5 electrically connected to other rows. The overlapping areas of the leads 5 need to be bridged. Therefore, for two second leads 5 with overlapping areas (for example, the second lead 5 electrically connected to the first positive pad 13 from the left in the fourth row and the second lead 5 electrically connected to the second positive pad 13 from the left in the fifth row have overlapping areas), one of the two second leads 5 needs to be bridged in the overlapping area using a bridging part 6. For example, the second lead 5 electrically connected to the second positive pad 13 from the left in the fifth row uses the same metal layer trace, while the second lead 5 electrically connected to the first positive pad 13 from the left in the fourth row needs to use two metal layer traces. That is, in the non-overlapping area (both sides of the overlapping area), the same metal layer trace as the second lead 5 electrically connected to the second positive pad 13 from the left in the fifth row is used, while in the overlapping area, another metal layer trace is used.

[0085] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 and Figure 11 As shown, Figure 11 This is only shown to clearly illustrate the structure of the drive backplate. Figure 5 In the partial structure of the drive backplane 1, a first insulating layer 14, a first metal layer 15, a second insulating layer 16, and a second metal layer 17 are sequentially stacked between the drive circuit 12 and the positive electrode pad 13, with the first insulating layer 14 close to the drive circuit 12; wherein,

[0086] Part of the second lead 5 (e.g.) Figure 11 The second lead 5) on the right side is located in the first metal layer 15;

[0087] Another part of the second lead 5 (e.g.) Figure 11The second lead 5) on the left side includes a first sub-lead 51, a bridging portion 53, and a second sub-lead 52. Both the first sub-lead 51 and the second sub-lead 52 are located in the first metal layer 15, and the bridging portion 53 is located in the second metal layer 17. One end of the first sub-lead 51 is electrically connected to the driving circuit 12 through a via penetrating the first insulating layer 14, and the other end of the first sub-lead 51 is electrically connected to one end of the bridging portion 53 through a via penetrating the second insulating layer 16. One end of the second sub-lead 52 is electrically connected to the other end of the bridging portion 53 through a via penetrating the second insulating layer 16, and the other end of the second sub-lead 52 is electrically connected to the positive electrode pad 13. For example... Figure 10 The second lead 5 electrically connected to the second positive pad 13 in the fifth row from the left is located in the first metal layer 15. The second lead 5 electrically connected to the first positive pad 13 in the fourth row from the left includes a first sub-lead 51, a bridging portion 53, and a second sub-lead 52.

[0088] like Figures 13-15 As shown, for a clearer illustration Figure 10 The driving circuit 12, the first metal layer 15, and the second metal layer 17 are located in the middle. Figure 13 for Figure 10 A planar schematic diagram of the drive circuit 12. Figure 13 The multiple small square boxes in the image represent the connection points between the subsequent second lead 5 and the drive circuit 12. Figure 14 In order to be in Figure 13 Based on Figure 10 A planar schematic diagram of the second lead 5, the first sub-lead 51, and the second sub-lead 52 included in the first metal layer 15. Figure 15 In order to be in Figure 14 Based on Figure 10 A plan view of the second metal layer 17 (bridging part 53). Figure 10 In order to be in Figure 15 A planar schematic diagram of setting up the positive electrode pad 13 based on the above.

[0089] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 and Figure 11 As shown, the drive backplane 1 also includes: a first planarization layer 18 located between the second metal layer 17 and the positive electrode pad 13, and a third insulating layer 19 located between the first planarization layer 18 and the positive electrode pad 13; the other end of the second sub-lead 52 is electrically connected to the positive electrode pad 13 through a via that sequentially penetrates the second insulating layer 16, the first planarization layer 18 and the third insulating layer 19.

[0090] Specifically, such as Figure 5 and Figure 11As shown, the second lead located directly in the first metal layer 15 is electrically connected to the positive electrode pad 13 through a via that passes through the second insulating layer 16, the first planarization layer 18 and the third insulating layer 19.

[0091] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 and Figure 12 As shown, Figure 12 This is only shown to clearly illustrate the structure of the pixel islands. Figure 5 The local structure of each first sub-pixel 21 includes a first electrode 211 (i.e., P electrode), a first semiconductor layer 212 (i.e., P-type semiconductor layer), a quantum well layer 213, a second semiconductor layer 214 (i.e., N-type semiconductor layer), and a second electrode 215 (i.e., N electrode) stacked together. The first electrode 211 is close to the driving backplate 1.

[0092] The display panel also includes a fourth insulating layer 6 located between the first electrode 211 and the first electrode pad 31. One end of the first lead 4 is electrically connected to the first electrode pad 31, and the other end of the first lead 4 is electrically connected to the first electrode 211 through a via penetrating the fourth insulating layer 6.

[0093] It should be noted that, Figure 6 and Figure 7 The first sub-pixel 21 is illustrated by the first electrode 211 in the subdivision. The first electrode pads 31 are arrayed on the first electrode 211 in the subdivision. A fourth insulating layer 6 is provided between the first electrode pads 31 and the first electrode 211.

[0094] It should be noted that, Figure 7 Taking the shape of the first electrode 211, which is a parallelogram, as an example, the shape of the first electrode 211 can also be a rectangle, such as... Figure 16 As shown, but not limited to this.

[0095] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 and Figure 12 As shown, the pixel island also includes a sapphire substrate 216 disposed on the side of the second electrode 215 opposite to the first electrode pad 31, and a buffer layer (not shown) located between the sapphire substrate 216 and the second electrode 215.

[0096] Optionally, the buffer layer can be made of gallium nitride (GaN), the first semiconductor layer 212 can be made of p-GaN, and the second semiconductor layer 214 can be made of n-GaN.

[0097] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 and Figure 12As shown, the first electrode pad 31 and the first lead 4 can be arranged in the same layer. In this way, only the original pattern needs to be changed when forming the first electrode pad 31, and the patterns of the first lead 4 and the first electrode pad 31 can be formed in one patterning process. There is no need to add a separate process for preparing the first lead 4, which can simplify the manufacturing process, save production costs, and improve production efficiency.

[0098] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 and Figure 12 As shown, the quantum well layer 213 of each first sub-pixel 21 within the same pixel island can be a single integrated structure, the second semiconductor layer 214 of each first sub-pixel 21 within the same pixel island can be a single integrated structure, and the second electrode 215 of each first sub-pixel 21 within the same pixel island can be a single integrated structure. That is, each first sub-pixel 21 within the same pixel island shares the quantum well layer 213, the second semiconductor layer 214, and the second electrode 215, and different first sub-pixels 21 are defined by separating the first semiconductor layer 212 and the first electrode 211.

[0099] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 , Figure 6 and Figure 12 As shown, it also includes a second electrode pad 31' disposed on the same layer as the first electrode pad 31. The second electrodes 215 within the same pixel island are electrically connected to the same second electrode pad 31', and the second electrodes 215 within different pixel islands are electrically connected to different second electrode pads 31'. That is, each first sub-pixel 21 within the same pixel island shares the second electrode pad 31'.

[0100] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 6 As shown, the second electrode pad 31' can be located in the area between two adjacent columns of the first electrode pad group 3.

[0101] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 , Figures 8-11 As shown, the drive backplane 1 also includes a negative electrode pad 13' disposed on the same layer as the positive electrode pad 13, and the negative electrode pad 13' is bonded to the second electrode pad 31'. That is, the position of the negative electrode pad 13' corresponds one-to-one with the position of the second electrode pad 31'.

[0102] Optionally, the positive electrode pad 13 and the negative electrode pad 13' can be made of bonding metals such as electroplated Cu. Figure 11 As shown, the thickness of the electroplated Cu can be greater than or equal to the sum of the thicknesses of the second insulating layer 16, the first planarization layer 18, and the third insulating layer 19, to ensure... Figure 12The bonding connection between the first electrode pad 31 and the second electrode pad 31' is shown.

[0103] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 and Figure 11 As shown, the drive backplane 1 further includes: a fifth insulating layer 110 located on the side of the positive electrode pad 13 facing away from the substrate 11, and a second planarization layer 111 located on the side of the fifth insulating layer 110 facing away from the substrate 11; the fifth insulating layer 110 and the second planarization layer 111 have a first exposed area exposing the positive electrode pad 13 and a second exposed area exposing the negative electrode pad 13'. Figure 12 The first electrode pad 31 shown is bonded to the positive electrode pad 13 through the first exposed area. Figure 12 The second electrode pad 31' shown is bonded to the negative electrode pad 13' through the second exposed area.

[0104] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 and Figure 11 As shown, the driving circuit 12 includes a first gate 121, a first gate insulating layer 122, an active layer 123, a second gate insulating layer 124, a second gate 125, an interlayer insulating layer 126, and source and drain electrodes (source electrode 127 and drain electrode 128) sequentially stacked between the substrate 11 and the first insulating layer 14. One end of the first sub-lead 51 is electrically connected to the drain electrode 128 of the driving circuit 12 through a via penetrating the first insulating layer 14. The drain electrode 128 is electrically connected to the active layer 123. The source electrode 127 of the driving circuit 12 is electrically connected to the first gate 121 and the second gate 125, respectively. The driving circuit 12 provided in this embodiment adopts a dual-gate structure, which can reduce leakage current.

[0105] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 5 and Figure 11 As shown, the driving backplane 1 also includes: a first conductive connection portion 112 and a second conductive connection portion 113 located on the first metal layer 14; a low-voltage power supply line VSS and a high-voltage power supply line VDD disposed on the same layer as the source and drain electrodes (source electrode 127 and drain electrode 128); a third conductive connection portion 114 and a fourth conductive connection portion 115 disposed on the same layer as the second gate 125; and a shielding electrode 116 disposed on the same layer as the first gate 121.

[0106] The negative electrode pad 13' is electrically connected to the first conductive connection portion 112 through a via penetrating the third insulating layer 19, the first planarization layer 18, and the second insulating layer 16. The first conductive connection portion 112 is electrically connected to the low-voltage power line VSS through a via penetrating the first insulating layer 14. The low-voltage power line VSS is electrically connected to the third conductive connection portion 114 through a via penetrating the interlayer insulating layer 126. The second conductive connection portion 113 is electrically connected to the high-voltage power line VDD through a via penetrating the first insulating layer 14. The high-voltage power line VDD is electrically connected to the fourth conductive connection portion 115 through a via penetrating the interlayer insulating layer 126. The high-voltage power line VDD is electrically connected to the shielding electrode 116 through a via penetrating the interlayer insulating layer 126, the second gate insulating layer 124, and the first gate insulating layer 122.

[0107] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 2 and Figure 9 As shown, multiple pixel islands 2 are arranged at intervals along the row direction X and the column direction Y. The negative electrode pads 13' of each pixel island 2 in the same column are electrically connected to the same low voltage power supply line VSS. The driving circuits 12 of each pixel island 2 in the same column are electrically connected to the same high voltage power supply line VDD. A high voltage power supply line VDD and a low voltage power supply line VSS are arranged in the gap between two adjacent columns of pixel islands 2.

[0108] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 2 As shown, multiple first sub-pixels 21 within each pixel island 2 are spaced apart along the row direction X and column direction Y. The first sub-pixels 21 in each row of each pixel island 2 are staggered sequentially along the row direction X, and the distance D1 between adjacent first sub-pixels 21 in the same row is less than the width W of the first sub-pixel 21 along the row direction X. In this way, more first sub-pixels 21 can be set within each pixel island 2, which can increase the number of viewpoints when the display panel is applied to 3D light field display.

[0109] In specific implementation, in the display panel provided in the embodiments of this disclosure, such as Figure 2 As shown, the distance D2 between any two adjacent first sub-pixels 21 along the center line of the column direction Y is equal.

[0110] In practical implementation, the display panel provided in this disclosure embodiment can be applied to a large-size, multi-viewpoint 3D light field display screen. This requires splicing multiple small-size screens to form a large-size display screen. Gaps between the spliced ​​screens will cause discontinuity in the 3D viewpoint display effect. To avoid gaps in the splicing, in the above-mentioned display panel provided in this disclosure embodiment, such as... Figure 17 As shown, Figure 17This is a plan view of the display panel. The display panel 1000 also includes a splicing area BB surrounding the display area AA. Figure 17 Each square blank area includes Figure 9 The driving backplane structure corresponding to the 9 pixel islands 2 shown includes a GOA driving circuit 100 (gate scan line driving circuit), an EOA driving circuit 200 (light emission scan line driving circuit), and a MUX circuit 300 (multiplexer). The GOA driving circuit 100 and EOA driving circuit 200 are respectively located between two adjacent columns of pixel units, and the MUX circuit 300 is located between two adjacent rows of pixel units. By setting the GOA driving circuit 100 and EOA driving circuit 200 between two adjacent columns of pixel units, this disclosure eliminates the need to fabricate the GOA driving circuit 100, EOA driving circuit 200, and MUX circuit 300 in the peripheral area of ​​the driving backplane 1. It also eliminates the need to reserve a border for the driving backplane to fabricate the driving circuits, solving the problems of framed display panels and image segmentation and discontinuity in large-size display screens after splicing, as seen in existing technologies. This disclosure can reserve splicing areas BB at the top, bottom, left, and right edges of small-size display screens for glass cutting, grinding, and other losses, enabling seamless splicing of individual display screens.

[0111] Specifically, such as Figure 17 As shown, assuming the position between two adjacent columns of pixel units where the driving circuit 100 is located is the first position, and the position between two adjacent columns of pixel units where the EOA driving circuit 200 is located is the second position, this embodiment of the disclosure... Figure 17 Taking the first position and the second position as an example, there is a gap of one column of pixel units between them. Of course, there can also be a gap of two columns of pixel units, three columns of pixel units, etc. between the first position and the second position.

[0112] Alternatively, the flexible printed circuit board (FPC) and driver chip (IC) within the driver backplane can be fabricated by bending them to the back of the driver backplane using side wiring and back bonding processes.

[0113] In specific implementations, the pixel islands in the display panels provided in the embodiments of this disclosure can be Mini LED pixel islands.

[0114] Based on the same inventive concept, this disclosure also provides a display device, including at least one of the display panels described above. Since the principle by which this display device solves the problem is similar to that of the aforementioned display panel, the implementation of this display device can refer to the implementation of the aforementioned display panel, and repeated details will not be elaborated further.

[0115] In specific implementation, in the display device provided in the embodiments of this disclosure, such as Figure 18 and Figure 19As shown, it also includes multiple lenses 400 located on the light-emitting side of the display panel 1000; the lenses 400 can be microlenses.

[0116] like Figure 18 As shown, multiple lenses 400 correspond one-to-one with multiple pixel islands 2, or, as... Figure 19 As shown, each lens 400 corresponds one-to-one with each first sub-pixel 21 in each pixel island 2;

[0117] The light emitted from each first sub-pixel 21 in each pixel island 2 is incident on the corresponding lens 400.

[0118] In specific implementation, in the display device provided in the embodiments of this disclosure, such as Figure 20 As shown, the display panel 1000 also includes a splicing area BB arranged around the display area AA, and the display device includes at least two display panels spliced ​​together (to splice four). Figure 17 Taking the display panel 1000 shown as an example, the splicing area BB of at least two spliced ​​display panels is provided with multiple second sub-pixels (not shown) arranged in the same way as the first sub-pixels 21. In this way, the arrangement of the second sub-pixels of the splicing area BB can be set to be the same as the arrangement of the first sub-pixels 21 in the display panel, and the splicing area BB can also achieve normal display, so that the spliced ​​display screen can display continuously.

[0119] This disclosure embodiment Figure 18 and Figure 19 The light field display device shown includes multiple first sub-pixels in each pixel island. Each pixel island can provide a sufficient number of subdivided viewpoints. The lens converges the light field information, which can form a continuous 3D light field display effect.

[0120] Specifically, the display device provided in the embodiments of this disclosure can be a large-size, multi-viewpoint 3D light field display screen, for example, used in cinemas / shopping mall advertising screens / multimedia conference rooms / outdoor advertising screens, providing a multi-viewpoint light field display effect with a large viewing angle and large main lobe that can be viewed by multiple people.

[0121] This disclosure provides a display panel and display device. By setting the number of rows of the first electrode pads in the first electrode pad group corresponding to each pixel island to be greater than the number of rows of the first sub-pixels in each pixel island, and setting the number of columns of the first electrode pads in the first electrode pad group corresponding to each pixel island to be less than the number of columns of the first sub-pixels in each pixel island, the multiple first electrode pads that originally needed to be vertically arranged one-to-one above each first sub-pixel of each pixel island are rearranged. For example, this disclosure takes 65 first sub-pixels per pixel island as an example, with the first row including 33 first sub-pixels and the second row including 32 first sub-pixels. By arranging the 65 first electrode pads corresponding to each pixel island into rows and columns, and each first electrode pad being electrically connected to the corresponding first sub-pixel through a first lead, the problem in the related art of not being able to create first electrode pads that correspond one-to-one with each first sub-pixel vertically above each first sub-pixel can be solved.

[0122] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0123] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, It has a display area, the display area including: A driving backplane includes a substrate, multiple driving circuits arrayed on the substrate, and multiple positive electrode pads located on the side of the driving circuits away from the substrate. Multiple pixel islands are located on the driving backplate, and each pixel island includes multiple first sub-pixels of the same color; Multiple first electrode pad groups are located between the multiple pixel islands and the driving backplane. Each first electrode pad group corresponds one-to-one with a pixel island, and the orthographic projection of the first electrode pad group onto the substrate lies within the orthographic projection range of the corresponding pixel island onto the substrate. Each first electrode pad group includes multiple first electrode pads, which are bonded to the positive electrode pad. The number of rows of the first electrode pads in each first electrode pad group is greater than the number of rows of the first sub-pixel in each pixel island, and the number of columns of the first electrode pads in each first electrode pad group is less than the number of columns of the first sub-pixel in each pixel island. The first electrode pad is electrically connected to the first sub-pixel via a first lead, and the positive electrode pad is electrically connected to the driving circuit via a second lead.

2. The display panel as described in claim 1, wherein the plurality of positive electrode pads are divided into a plurality of positive electrode pad groups, and the positive electrode pad groups correspond one-to-one with the first electrode pad groups; The plurality of driving circuits are divided into a plurality of driving circuit groups, and each driving circuit group corresponds one-to-one with the positive electrode pad group. The orthogonal projection area of ​​each positive electrode pad group on the substrate is smaller than the orthogonal projection area of ​​the driving circuit group on the substrate.

3. The display panel as described in claim 2, wherein, The orthographic projection of the second lead on the substrate is located within the orthographic projection range of the gap between two adjacent rows of the first sub-pixels on the substrate, and / or the orthographic projection of the second lead on the substrate is located within the orthographic projection range of the gap between two adjacent columns of the first sub-pixels on the substrate.

4. The display panel as claimed in claim 3, wherein, At least a portion of the second lead has an overlapping area with other second leads, and for two second leads with said overlapping area, one of the second leads is bridged in the overlapping area.

5. The display panel as claimed in claim 4, wherein, The drive backplane further includes a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer sequentially stacked between the drive circuit and the positive electrode pad, wherein the first insulating layer is close to the drive circuit; wherein... A portion of the second lead is located in the first metal layer; The other part of the second lead includes a first sub-lead, the bridging portion, and a second sub-lead. Both the first sub-lead and the second sub-lead are located in the first metal layer, and the bridging portion is located in the second metal layer. One end of the first sub-lead is electrically connected to the driving circuit through a via penetrating the first insulating layer, and the other end of the first sub-lead is electrically connected to one end of the bridging portion through a via penetrating the second insulating layer. One end of the second sub-lead is electrically connected to the other end of the bridging portion through a via penetrating the second insulating layer, and the other end of the second sub-lead is electrically connected to the positive electrode pad.

6. The display panel as claimed in claim 5, wherein, The drive backplane further includes: a first planarization layer located between the second metal layer and the positive electrode pad, and a third insulating layer located between the first planarization layer and the positive electrode pad; the other end of the second sub-lead is electrically connected to the positive electrode pad through a via that sequentially penetrates the second insulating layer, the first planarization layer and the third insulating layer.

7. The display panel as claimed in claim 6, wherein, Each of the first sub-pixels includes a first electrode, a first semiconductor layer, a quantum well layer, a second semiconductor layer, and a second electrode stacked together, with the first electrode close to the driving backplate; The display panel further includes a fourth insulating layer located between the first electrode and the first electrode pad, one end of the first lead is electrically connected to the first electrode pad, and the other end of the first lead is electrically connected to the first electrode through a via penetrating the fourth insulating layer.

8. The display panel as claimed in claim 7, wherein, The first electrode pad is disposed on the same layer as the first lead.

9. The display panel as claimed in claim 7, wherein, The quantum well layers of each first sub-pixel within the same pixel island are integral structures, the second semiconductor layers of each first sub-pixel within the same pixel island are integral structures, and the second electrodes of each first sub-pixel within the same pixel island are integral structures.

10. The display panel as claimed in claim 9, wherein, It also includes a second electrode pad disposed on the same layer as the first electrode pad, wherein the second electrode in the same pixel island is electrically connected to the same second electrode pad, and the second electrode in different pixel islands is electrically connected to different second electrode pads.

11. The display panel as claimed in claim 10, wherein, The second electrode pad is located in the area between two adjacent columns of the first electrode pad group.

12. The display panel as claimed in claim 11, wherein, The drive backplane also includes a negative electrode pad disposed on the same layer as the positive electrode pad, and the negative electrode pad is bonded to the second electrode pad.

13. The display panel as claimed in claim 12, wherein, The drive backplane further includes: a fifth insulating layer located on the side of the positive electrode pad facing away from the substrate, and a second planarization layer located on the side of the fifth insulating layer facing away from the substrate; the fifth insulating layer and the second planarization layer have a first exposed area exposing the positive electrode pad and a second exposed area exposing the negative electrode pad, the first electrode pad being bonded to the positive electrode pad through the first exposed area, and the second electrode pad being bonded to the negative electrode pad through the second exposed area.

14. The display panel as claimed in claim 13, wherein, The driving circuit includes a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, a second gate, an interlayer insulating layer, and source / drain electrodes stacked sequentially between the substrate and the first insulating layer; one end of the first sub-lead is electrically connected to the drain electrode of the driving circuit through a via penetrating the first insulating layer, the drain electrode is electrically connected to the active layer, and the source electrode of the driving circuit is electrically connected to the first gate and the second gate, respectively.

15. The display panel as claimed in claim 14, wherein, The driving backplane further includes: a first conductive connection portion and a second conductive connection portion located on the first metal layer, a low-voltage power supply line and a high-voltage power supply line disposed on the same layer as the source and drain electrodes, a third conductive connection portion and a fourth conductive connection portion disposed on the same layer as the second gate, and a shielding electrode disposed on the same layer as the first gate. The negative electrode pad is electrically connected to the first conductive connection portion through a via penetrating the third insulating layer, the first planarization layer, and the second insulating layer. The first conductive connection portion is electrically connected to the low-voltage power line through a via penetrating the first insulating layer. The low-voltage power line is electrically connected to the third conductive connection portion through a via penetrating the interlayer insulating layer. The second conductive connection portion is electrically connected to the high-voltage power line through a via penetrating the first insulating layer. The high-voltage power line is electrically connected to the fourth conductive connection portion through a via penetrating the interlayer insulating layer. The high-voltage power line is electrically connected to the shielding electrode through a via penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

16. The display panel as claimed in claim 15, wherein, The plurality of pixel islands are arranged at intervals along the row and column directions. The negative electrode pads of each pixel island in the same column are electrically connected to the same low-voltage power line. The driving circuits of each pixel island in the same column are electrically connected to the same high-voltage power line. A high-voltage power line and a low-voltage power line are arranged in the gap between two adjacent columns of pixel islands.

17. The display panel according to any one of claims 1-16, wherein, It includes pixel units with multiple rows and columns of different light-emitting colors. The pixel units located in the same row have the same light-emitting color, and the pixel units with different light-emitting colors located in the same column are arranged alternately. Each pixel unit includes at least two pixel islands spaced apart, the at least two pixel islands in each pixel unit are staggered along the row direction, and the outermost adjacent first sub-pixels of adjacent pixel islands in each pixel unit are staggered along the row direction.

18. The display panel as claimed in claim 17, wherein, Multiple first sub-pixels within each pixel island are spaced apart along the row and column directions. The first sub-pixels in each row of each pixel island are staggered sequentially along the row direction, and the distance between adjacent first sub-pixels in the same row is less than the width of the first sub-pixel along the row direction.

19. The display panel as claimed in claim 18, wherein, The distance between any two adjacent first sub-pixels along the center line of the column direction is equal.

20. The display panel as claimed in claim 19, wherein, It also includes a GOA driving circuit, an EOA driving circuit, and a MUX circuit. The GOA driving circuit and the EOA driving circuit are respectively disposed between two adjacent columns of the pixel units, and the MUX circuit is disposed between two adjacent rows of the pixel units.

21. The display panel according to any one of claims 1-16, wherein, The pixel island is a Mini LED pixel island.

22. A display device, wherein, It includes at least one display panel as described in any one of claims 1-21.

23. The display device as claimed in claim 22, wherein, It also includes multiple lenses located on the light-emitting side of the display panel; The plurality of lenses correspond one-to-one with the plurality of pixel islands, or each of the lenses corresponds one-to-one with each of the first sub-pixels in each of the pixel islands; The light emitted from each of the first sub-pixels in each of the pixel islands is incident on the corresponding lens.

24. The display device as claimed in claim 22 or 23, wherein, The display panel further includes a splicing area surrounding the display area, and the display device includes at least two display panels spliced ​​together, wherein the splicing area of ​​the at least two display panels is provided with a plurality of second sub-pixels arranged in the same manner as the first sub-pixels.

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