Shift register unit, drive control circuit, display device, and drive method

Abstract

Provided are a shift register unit (SRn), a driving control circuit, a display device, and a driving method, comprising: an input circuit (10) configured to provide a signal of an input signal terminal (IP) to a first node (N1) in response to a signal of a first clock signal terminal (CK); a control circuit (20) configured to control a signal of a second node (N2); a first output circuit (30) configured to provide a signal of a first reference voltage signal terminal (V1) to an output signal terminal (OT) in response to the signal of the first node (N1); a second output circuit (40) configured to provide a signal of a second reference voltage signal terminal (V2) to the output signal terminal (OT) in response to the signal of the second node (N2); and a noise reduction circuit (50) configured to provide a signal of a third reference voltage signal terminal (V3) to the second node (N2) in response to a signal of a noise reduction signal terminal (VEL), and control the second output circuit (40) to stop outputting a signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a shift register unit, a driving control circuit, a display device and a driving method. BACKGROUND

[0002] With the rapid development of display technology, display panels show a development trend of high integration and low cost. Among them, the array substrate row driving technology (Gate Driver on Array, GOA) integrates the driving control circuit on the array substrate of the display panel to form the scanning driving of the display panel. At present, the driving control circuit is usually composed of a plurality of cascaded shift register units. If the output of the shift register unit is unstable, it will cause display abnormalities. SUMMARY

[0003] Some embodiments of the present disclosure provide a shift register unit, comprising:

[0004] an input circuit configured to provide a signal of an input signal terminal to a first node in response to a signal of a first clock signal terminal;

[0005] a control circuit configured to control a signal of a second node;

[0006] a first output circuit configured to provide a signal of a first reference voltage signal terminal to an output signal terminal in response to a signal of the first node;

[0007] a second output circuit configured to provide a signal of a second reference voltage signal terminal to the output signal terminal in response to a signal of the second node;

[0008] a noise reduction circuit configured to provide a signal of a third reference voltage signal terminal to the second node in response to a signal of a noise reduction signal terminal, and to control the second output circuit to stop outputting a signal.

[0009] In some possible implementation modes provided by the present disclosure, the noise reduction circuit comprises a first transistor.

[0010] a gate of the first transistor is coupled with the noise reduction signal terminal, a first pole of the first transistor is coupled with the third reference voltage signal terminal, and a second pole of the first transistor is coupled with the second node.

[0011] In some possible implementation modes provided by the present disclosure, the first node comprises a first sub-node and a second sub-node.

[0012] The shift register unit further comprises a conducting circuit; the first sub-node is coupled with the second sub-node through the conducting circuit; the conducting circuit is configured to conduct the first sub-node and the second sub-node in response to a signal of a fourth reference voltage signal terminal;

[0013] The input circuit is further configured to provide the signal of the input signal terminal to the first sub-node in response to the signal of the first clock signal terminal;

[0014] The first output circuit is further configured to provide the signal of the first reference voltage signal terminal to the output signal terminal in response to the signal of the second sub-node.

[0015] In some possible implementation provided by the present disclosure, the control circuit comprises a first control circuit, a second control circuit and a third control circuit;

[0016] The first control circuit is configured to provide a fifth reference voltage signal terminal to a third node in response to the signal of the first clock signal terminal, and provide the signal of the first clock signal terminal to the third node in response to the signal of the first sub-node;

[0017] The second control circuit is configured to control the signal of the second sub-node and the signal of a fourth node;

[0018] The third control circuit is configured to provide the signal of a second clock signal terminal to the second node in response to the signals of the fourth node and the second clock signal terminal, and provide the signal of the second reference voltage signal terminal to the second node in response to the signal of the first sub-node.

[0019] In some possible implementation provided by the present disclosure, the first control circuit comprises a second transistor and a third transistor;

[0020] A gate of the second transistor is coupled with the first clock signal terminal, a first pole of the second transistor is coupled with the fifth reference voltage signal terminal, and a second pole of the second transistor is coupled with the third node;

[0021] A gate of the third transistor is coupled with the first sub-node, a first pole of the third transistor is coupled with the third node, and a second pole of the third transistor is coupled with the first clock signal terminal.

[0022] In some possible implementation provided by the present disclosure, the second control circuit is further configured to provide a signal of the third node to the fourth node in response to a signal of the fourth reference voltage signal end, and provide a signal of the second reference voltage signal end to a fifth node in response to a signal of the fourth node, and provide a signal of the second clock signal end to the fifth node in response to a signal of the second sub-node.

[0023] In some possible implementation provided by the present disclosure, the second control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor.

[0024] a gate of the fourth transistor is coupled with the fourth reference voltage signal end, a first electrode of the fourth transistor is coupled with the third node, and a second electrode of the fourth transistor is coupled with the fourth node;

[0025] a gate of the fifth transistor is coupled with the third node, a first electrode of the fifth transistor is coupled with the second reference voltage signal end, and a second electrode of the fifth transistor is coupled with the fifth node;

[0026] a gate of the sixth transistor is coupled with the second sub-node, a first electrode of the sixth transistor is coupled with the fifth node, and a second electrode of the sixth transistor is coupled with the second clock signal end;

[0027] a first electrode of the first capacitor is coupled with the fifth node, and a second electrode of the first capacitor is coupled with the second sub-node.

[0028] In some possible implementation provided by the present disclosure, the second control circuit is further configured to provide a signal of the third node to the fourth node in response to a signal of the fourth reference voltage signal end, and provide a signal of the second reference voltage signal end to a fifth node in response to a signal of the fourth node, and provide a signal of the second clock signal end to the fifth node in response to a signal of the second sub-node.

[0029] In some possible implementation provided by the present disclosure, the second control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor.

[0030] a gate of the fourth transistor is coupled with the fourth reference voltage signal end, a first electrode of the fourth transistor is coupled with the third node, and a second electrode of the fourth transistor is coupled with the fourth node;

[0031] A gate of the fifth transistor is coupled with the fourth node, a first electrode of the fifth transistor is coupled with the second reference voltage signal terminal, and a second electrode of the fifth transistor is coupled with the fifth node.

[0032] A gate of the sixth transistor is coupled with the second sub-node, a first electrode of the sixth transistor is coupled with the fifth node, and a second electrode of the sixth transistor is coupled with the second clock signal terminal.

[0033] A first electrode of the first capacitor is coupled with the fifth node, and a second electrode of the first capacitor is coupled with the second sub-node.

[0034] In some possible implementation provided by the present disclosure, the third control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, and a second capacitor.

[0035] A gate of the seventh transistor is coupled with the fourth node, a first electrode of the seventh transistor is coupled with the second clock signal terminal, and a second electrode of the seventh transistor is coupled with a first electrode of the eighth transistor.

[0036] A gate of the eighth transistor is coupled with the second clock signal terminal, and a second electrode of the eighth transistor is coupled with the second node.

[0037] A gate of the ninth transistor is coupled with the first sub-node, a first electrode of the ninth transistor is coupled with the second node, and a second electrode of the ninth transistor is coupled with the second reference signal terminal.

[0038] A first electrode of the second capacitor is coupled with the fourth node, and a second electrode of the second capacitor is coupled with the first electrode of the eighth transistor.

[0039] In some possible implementation provided by the present disclosure, the input circuit includes a tenth transistor.

[0040] A gate of the tenth transistor is coupled with the first clock signal terminal, a first electrode of the tenth transistor is coupled with the input signal terminal, and a second electrode of the tenth transistor is coupled with the first sub-node.

[0041] In some possible implementation provided by the present disclosure, the first output circuit includes an eleventh transistor.

[0042] A gate of the eleventh transistor is coupled with the second sub-node, a first electrode of the eleventh transistor is coupled with the output signal terminal, and a second electrode of the eleventh transistor is coupled with the first reference voltage signal terminal.

[0043] In some possible implementation provided by the present disclosure, the second output circuit includes a twelfth transistor and a third capacitor.

[0044] A gate of the twelfth transistor is coupled with the second node, a first pole of the twelfth transistor is coupled with the second reference voltage signal terminal, and a second pole of the twelfth transistor is coupled with the output signal terminal.

[0045] A first electrode of the third capacitor is coupled with the second node, and a second electrode of the third capacitor is coupled with the second reference voltage signal terminal.

[0046] In some possible implementation provided by the present disclosure, the turn-on circuit includes a thirteenth transistor.

[0047] A gate of the thirteenth transistor is coupled with the fourth reference voltage signal terminal, a first pole of the thirteenth transistor is coupled with the first sub-node, and a second pole of the thirteenth transistor is coupled with the second sub-node.

[0048] In some possible implementation provided by the present disclosure, the second reference voltage signal terminal and the third reference voltage signal terminal are the same signal terminal.

[0049] The present disclosure further provides a shift register unit, including:

[0050] An input circuit coupled with an input signal terminal and a first node, configured to provide a signal of the input signal terminal to the first node.

[0051] A control circuit coupled with a second node, configured to control the second node.

[0052] A first output transistor having a gate coupled with the second node, a first pole coupled with a second reference voltage signal terminal, and a second pole coupled with an output signal terminal, configured to provide a signal of the second reference voltage signal terminal to the output signal terminal in response to a signal of the second node.

[0053] A noise reduction transistor having a gate coupled with a noise reduction signal terminal, a first pole coupled with a third reference voltage signal terminal, and a second pole coupled with the second node, configured to provide a signal of the third reference voltage signal terminal to the second node in response to a signal of the noise reduction signal terminal.

[0054] In some possible implementation provided by the present disclosure, a third capacitor is further included, a first electrode of the third capacitor is coupled with the second reference voltage signal terminal, and a second electrode of the third capacitor is coupled with the second electrode of the noise reduction transistor.

[0055] In some possible implementation provided by the present disclosure, a second output transistor is further included, a gate of the second output transistor is coupled with the first node, a first electrode of the output transistor is coupled with the first reference voltage signal terminal, and a second electrode of the output transistor is coupled with the output signal terminal, and the output transistor is configured to provide the signal of the first reference voltage signal terminal to the output signal terminal in response to the signal of the first node.

[0056] In some possible implementation provided by the present disclosure, the second reference voltage signal terminal and the third reference voltage signal terminal are the same signal terminal.

[0057] The present disclosure further provides a driving control circuit including a plurality of the above-described shift register units connected in cascade.

[0058] The input signal terminal of the first-stage shift register unit is coupled with a frame trigger signal terminal.

[0059] In each of two adjacent shift register units, the input signal terminal of the next-stage shift register unit is coupled with the output signal terminal of the previous-stage shift register unit.

[0060] The present disclosure further provides a display device including the above-described driving control circuit.

[0061] The present disclosure further provides a driving method of the above-described shift register unit, including:

[0062] In the noise reduction stage, the first output circuit provides the signal of the first reference voltage signal terminal to the output signal terminal in response to the signal of the first node, the noise reduction circuit provides the signal of the third reference voltage signal terminal to the second node in response to the signal of the noise reduction signal terminal, and the second output circuit stops outputting a signal. BRIEF DESCRIPTION OF DRAWINGS

[0063] Figure 1 Some structural diagrams of the shift register unit provided by the present disclosure are shown.

[0064] Figure 2 A flowchart of the driving method of the shift register unit provided by the present disclosure is shown.

[0065] Figure 3 Some signal timing diagrams provided by the present disclosure are shown.

[0066] Figure 4 Another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure is shown in FIG. 13B.

[0067] Figure 5 Another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure is shown in FIG. 13B.

[0068] Figure 6 Another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure is shown in FIG. 13B.

[0069] Figure 7 Another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure is shown in FIG. 13B.

[0070] Figure 8 Another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure is shown in FIG. 13B.

[0071] Figure 9 Some structural schematic diagrams of a driving control circuit provided by an embodiment of the present disclosure are shown in FIG. 14. DETAILED DESCRIPTION

[0072] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0073] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as the common meaning thereof by those of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. The terms “include” or “contain” and similar words mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, without excluding other elements or objects. The terms “connect” or “connected” and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0074] It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, but only serve to illustrate the content of the present disclosure. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout.

[0075] The embodiment of the present disclosure provides a shift register unit, as shown in the accompanying drawings, comprising: Figure 1

[0076] The input circuit 10 is configured to provide a signal of an input signal terminal IP to a first node N1 in response to a signal of a first clock signal terminal CK.

[0077] The control circuit 20 is configured to control a signal of a second node N2.

[0078] The first output circuit 30 is configured to provide a signal of a first reference voltage signal terminal V1 to an output signal terminal OT in response to a signal of the first node N1.

[0079] The second output circuit 40 is configured to provide a signal of a second reference voltage signal terminal V2 to the output signal terminal OT in response to a signal of the second node N2.

[0080] The noise reduction circuit 50 is configured to provide a signal of a third reference voltage signal terminal V3 to the second node N2 in response to a signal of a noise reduction signal terminal VEL, and control the second output circuit 40 to stop outputting a signal.

[0081] In the embodiment of the present disclosure, through the cooperation of the input circuit, the control circuit, the first output circuit, the second output circuit and the noise reduction circuit, the output signal terminal can be coupled to a signal output driving signal, and the driving process of the coupled signal can be realized. In addition, by setting the noise reduction circuit, the noise reduction circuit can control the second output circuit to stop outputting a signal in the second stage, so as to prevent the first output circuit and the second output circuit from being turned on at the same time, avoid the short circuit of the first reference voltage signal terminal and the second reference voltage signal terminal, reduce the picture flicker, and improve the display effect. In addition, in the case of abnormal power failure or initialization, due to the effect of the noise reduction circuit, the short circuit of the first reference voltage signal terminal and the second reference voltage signal terminal can also be avoided, the picture flicker can be reduced, and the display effect can be improved.

[0082] In the embodiment of the present disclosure, as shown in the accompanying drawings, the noise reduction circuit 50 comprises a first transistor T1. Figure 1 The gate of the first transistor T1 is coupled to the noise reduction signal terminal VEL, the first pole of the first transistor T1 is coupled to the third reference voltage signal terminal V3, and the second pole of the first transistor T1 is coupled to the second node N2.

[0083] ​Exemplarily, the first transistor T1 can be turned on under control of an effective level of the noise reduction signal transmitted at the noise reduction signal end VEL, and can be turned off under control of an ineffective level of the noise reduction signal. Exemplarily, the first transistor T1 is set as a P-type transistor, and the effective level of the noise reduction signal is a low level, and the ineffective level of the noise reduction signal is a high level. Alternatively, the first transistor T1 is set as an N-type transistor, and the effective level of the noise reduction signal is a high level, and the ineffective level of the noise reduction signal is a low level.

[0084] In the embodiment of the present disclosure, as shown in Figure 1 The first node N1 includes a first sub-node N1-1 and a second sub-node N1-2. The shift register unit further includes a turn-on circuit 60; the first sub-node N1-1 is coupled with the second sub-node N1-2 through the turn-on circuit 60; the turn-on circuit 60 is configured to turn on the first sub-node N1-1 and the second sub-node N1-2 in response to a signal of the fourth reference voltage signal end V4;

[0085] The input circuit 10 is further configured to provide the signal of the input signal end IP to the first sub-node N1-1 in response to a signal of the first clock signal end CK;

[0086] The first output circuit 30 is further configured to provide the signal of the first reference voltage signal end V1 to the output signal end OT in response to a signal of the second sub-node N1-2.

[0087] In the embodiment of the present disclosure, as shown in Figure 1 The control circuit 20 includes a first control circuit 201, a second control circuit 202 and a third control circuit 203;

[0088] The first control circuit 201 is configured to provide the fifth reference voltage signal end V5 to the third node N3 in response to a signal of the first clock signal end CK, and provide the signal of the first clock signal end CK to the third node N3 in response to a signal of the first sub-node N1-1;

[0089] The second control circuit 202 is configured to control a signal of the second sub-node N1-2 and a signal of the fourth node N4;

[0090] The third control circuit 203 is configured to provide the signal of the second clock signal end CB to the second node N2 in response to a signal of the fourth node N4 and the second clock signal end CB, and provide the signal of the second reference voltage signal end V2 to the second node N2 in response to a signal of the first sub-node N1-1.

[0091] In the embodiment of the present disclosure, as shown in Figure 1 The first control circuit 201 includes a second transistor T2 and a third transistor T3;

[0092] The gate of the second transistor T2 is coupled with the first clock signal terminal CK, the first pole of the second transistor T2 is coupled with the fifth reference voltage signal terminal V5, and the second pole of the second transistor T2 is coupled with the third node N3;

[0093] The gate of the third transistor T3 is coupled with the first sub-node N1-1, the first pole of the third transistor T3 is coupled with the third node N3, and the second pole of the third transistor T3 is coupled with the first clock signal terminal CK.

[0094] Exemplarily, the second transistor T2 can be turned on under the control of the active level of the signal transmitted by the first clock signal terminal CK and can be turned off under the control of the inactive level of the signal. Exemplarily, the second transistor T2 is set as an N-type transistor, and the active level of the first clock signal is a high level and the inactive level of the first clock signal is a low level. Alternatively, the second transistor T2 is set as a P-type transistor, and the active level of the first clock signal is a low level and the inactive level of the first clock signal is a high level.

[0095] Exemplarily, the third transistor T3 can be turned on under the control of the active level of the signal transmitted by the first sub-node N1-1 and can be turned off under the control of the inactive level of the signal. Exemplarily, the third transistor T3 is set as an N-type transistor, and the active level of the signal is a high level and the inactive level of the signal is a low level. Alternatively, the third transistor T3 is set as a P-type transistor, and the active level of the signal is a low level and the inactive level of the signal is a high level.

[0096] In the embodiment of the present disclosure, as shown in Figure 1 The second control circuit 202 is further configured to provide the signal of the third node N3 to the fourth node N4 in response to the signal of the fourth reference voltage signal terminal V4, provide the signal of the second reference voltage signal terminal V2 to the fifth node N5 in response to the signal of the third node N3, and provide the signal of the second clock signal terminal CB to the fifth node N5 in response to the signal of the second sub-node N1-2.

[0097] In the embodiment of the present disclosure, as shown in Figure 1 The second control circuit 202 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a first capacitor C1.

[0098] The gate of the fourth transistor T4 is coupled with the fourth reference voltage signal terminal V4, the first pole of the fourth transistor T4 is coupled with the third node N3, and the second pole of the fourth transistor T4 is coupled with the fourth node N4;

[0099] The gate of the fifth transistor T5 is coupled with the third node N3, the first pole of the fifth transistor T5 is coupled with the second reference voltage signal end V2, and the second pole of the fifth transistor T5 is coupled with the fifth node N5;

[0100] The gate of the sixth transistor T6 is coupled with the second sub-node N1-2, the first pole of the sixth transistor T6 is coupled with the fifth node N5, and the second pole of the sixth transistor T6 is coupled with the second clock signal end CB;

[0101] The first electrode of the first capacitor C1 is coupled with the fifth node N5, and the second electrode of the first capacitor C1 is coupled with the second sub-node N1-2.

[0102] Exemplarily, the fourth transistor T4 can be turned on under the control of the effective level of the fourth reference voltage signal transmitted by the fourth reference voltage signal end V4, and can be turned off under the control of the invalid level of the fourth reference voltage signal. Exemplarily, the fourth transistor T4 is set as an N-type transistor, and the effective level of the fourth reference voltage signal is a high level, and the invalid level of the fourth reference voltage signal is a low level. Alternatively, the fourth transistor T4 is set as a P-type transistor, and the effective level of the fourth reference voltage signal is a low level, and the invalid level of the fourth reference voltage signal is a high level.

[0103] Exemplarily, the fifth transistor T5 can be turned on under the control of the effective level of the signal transmitted by the third node N3, and can be turned off under the control of the invalid level of the signal. Exemplarily, the fifth transistor T5 is set as an N-type transistor, and the effective level of the signal is a high level, and the invalid level of the signal is a low level. Alternatively, the fifth transistor T5 is set as a P-type transistor, and the effective level of the signal is a low level, and the invalid level of the signal is a high level.

[0104] Exemplarily, the sixth transistor T6 can be turned on under the control of the effective level of the signal transmitted by the second sub-node N1-2, and can be turned off under the control of the invalid level of the signal. Exemplarily, the sixth transistor T6 is set as an N-type transistor, and the effective level of the signal is a high level, and the invalid level of the signal is a low level. Alternatively, the sixth transistor T6 is set as a P-type transistor, and the effective level of the signal is a low level, and the invalid level of the signal is a high level.

[0105] In the embodiment of the present disclosure, as shown in Figure 1 The third control circuit 203 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2.

[0106] The gate of the seventh transistor T7 is coupled with the fourth node N4, the first pole of the seventh transistor T7 is coupled with the second clock signal end CB, and the second pole of the seventh transistor T7 is coupled with the first pole of the eighth transistor T8;

[0107] The gate of the eighth transistor T8 is coupled with the second clock signal end CB, and the second electrode of the eighth transistor T8 is coupled with the second node N2;

[0108] The gate of the ninth transistor T9 is coupled with the first sub-node N1-1, the first electrode of the ninth transistor T9 is coupled with the second node N2, and the second electrode of the ninth transistor T9 is coupled with the second reference signal end V2.

[0109] The first electrode of the second capacitor C2 is coupled with the fourth node N4, and the second electrode of the second capacitor C2 is coupled with the first electrode of the eighth transistor T8.

[0110] Exemplarily, the seventh transistor T7 can be turned on under the control of the active level of the signal transmitted by the fourth node N4, and can be turned off under the control of the inactive level of the signal. Exemplarily, the seventh transistor T7 is set as a P-type transistor, and the active level of the signal is a low level, and the inactive level of the signal is a high level. Alternatively, the seventh transistor T7 is set as an N-type transistor, and the active level of the signal is a high level, and the inactive level of the signal is a low level.

[0111] Exemplarily, the eighth transistor T8 can be turned on under the control of the active level of the second clock signal transmitted by the second clock signal end CB, and can be turned off under the control of the inactive level of the second clock signal. Exemplarily, the eighth transistor T8 is set as an N-type transistor, and the active level of the second clock signal is a high level, and the inactive level of the second clock signal is a low level. Alternatively, the eighth transistor T8 is set as a P-type transistor, and the active level of the second clock signal is a low level, and the inactive level of the second clock signal is a high level.

[0112] Exemplarily, the ninth transistor T9 can be turned on under the control of the active level of the signal transmitted by the first sub-node N1-1, and can be turned off under the control of the inactive level of the signal. Exemplarily, the ninth transistor T9 is set as an N-type transistor, and the active level of the signal is a high level, and the inactive level of the signal is a low level. Alternatively, the ninth transistor T9 is set as a P-type transistor, and the active level of the signal is a low level, and the inactive level of the signal is a high level.

[0113] In the embodiment of the present disclosure, as shown in Figure 1 The input circuit 10 includes a tenth transistor T10; the gate of the tenth transistor T10 is coupled with the first clock signal end CK, the first electrode of the tenth transistor T10 is coupled with the input signal end IP, and the second electrode of the tenth transistor T10 is coupled with the first sub-node N1-1.

[0114] The tenth transistor T10 can be turned on under control of an active level of a first clock signal transmitted by the first clock signal terminal CK, and can be turned off under control of an inactive level of the first clock signal. For example, when the tenth transistor T10 is an N-type transistor, the active level of the first clock signal is a high level, and the inactive level of the first clock signal is a low level. Alternatively, when the tenth transistor T10 is a P-type transistor, the active level of the first clock signal is a low level, and the inactive level of the first clock signal is a high level.

[0115] In the embodiment of the present disclosure, as shown in Figure 1 The first output circuit 30 includes an eleventh transistor T11.

[0116] The gate of the eleventh transistor T11 is coupled with the second sub-node N1-2, the first electrode of the eleventh transistor T11 is coupled with the output signal terminal OT, and the second electrode of the eleventh transistor T11 is coupled with the first reference voltage signal terminal V1.

[0117] The eleventh transistor T11 can be turned on under control of an active level of a signal transmitted by the second sub-node N1-2, and can be turned off under control of an inactive level of the signal. For example, when the eleventh transistor T11 is an N-type transistor, the active level of the signal is a high level, and the inactive level of the signal is a low level. Alternatively, when the eleventh transistor T11 is a P-type transistor, the active level of the signal is a low level, and the inactive level of the signal is a high level.

[0118] In the embodiment of the present disclosure, as shown in Figure 1 The second output circuit 40 includes a twelfth transistor T12 and a third capacitor C3.

[0119] The gate of the twelfth transistor T12 is coupled with the second node N2, the first electrode of the twelfth transistor T12 is coupled with the second reference voltage signal terminal V2, and the second electrode of the twelfth transistor T12 is coupled with the output signal terminal OT.

[0120] The first electrode of the third capacitor C3 is coupled with the second node N2, and the second electrode of the third capacitor C3 is coupled with the second reference voltage signal terminal V2.

[0121] The twelfth transistor T12 can be turned on under control of an active level of a signal transmitted by the second node N2, and can be turned off under control of an inactive level of the signal. For example, when the twelfth transistor T12 is an N-type transistor, the active level of the signal is a high level, and the inactive level of the signal is a low level. Alternatively, when the twelfth transistor T12 is a P-type transistor, the active level of the signal is a low level, and the inactive level of the signal is a high level.

[0122] In the embodiment of the present disclosure, asFigure 1 As shown, the conduction circuit 60 comprises a thirteenth transistor T13.

[0123] The gate of the thirteenth transistor T13 is coupled with the fourth reference voltage signal terminal V4, the first pole of the thirteenth transistor T13 is coupled with the first sub-node N1-1, and the second pole of the thirteenth transistor T13 is coupled with the second sub-node N1-2.

[0124] Exemplarily, the thirteenth transistor T13 can be turned on under the control of the effective level of the fourth reference voltage signal transmitted by the fourth reference voltage signal terminal V4, and can be turned off under the control of the ineffective level of the fourth reference voltage signal. Exemplarily, the thirteenth transistor T13 is set as an N-type transistor, then the effective level of the fourth reference voltage signal is high level, and the ineffective level of the fourth reference voltage signal is low level. Alternatively, the thirteenth transistor T13 is set as a P-type transistor, then the effective level of the fourth reference voltage signal is low level, and the ineffective level of the fourth reference voltage signal is high level.

[0125] In the embodiments of the present disclosure, the same signal is loaded on the second reference voltage signal terminal V2 and the third reference voltage signal terminal V3. Exemplarily, the second reference voltage signal terminal V2 and the third reference voltage signal terminal V3 can be the same signal terminal, which can reduce the number of signal lines and reduce the wiring difficulty.

[0126] In the specific implementation, according to the flow direction of the signal, the first pole of the above-mentioned transistor can be its source, and the second pole can be its drain; or the first pole can be its drain, and the second pole can be its source, which is not specifically distinguished here.

[0127] It should be noted that the transistor mentioned in the embodiments of the present disclosure can be a thin film transistor (TFT) or a metal oxide semiconductor (MOS), which is not limited here.

[0128] In the embodiments of the present disclosure, the above-mentioned transistors can all be set as P-type transistors, the first reference voltage signal terminal V1 can be configured to load a constant first reference voltage, and the first reference voltage is generally negative. In addition, the second reference voltage signal terminal V2 can load a constant second reference voltage, and the second reference voltage can generally be positive.

[0129] In this embodiment, the fourth reference voltage signal terminal V4 can be configured to apply a constant fourth reference voltage, which is generally negative. For example, the value of the first reference voltage can be less than the value of the fourth reference voltage, thus ensuring a more stable output signal while preventing screen flickering.

[0130] In this embodiment of the disclosure, the fifth reference voltage signal terminal V5 can be configured to apply a constant fifth reference voltage. For example, the value of the fifth reference voltage can be less than the value of the fourth reference voltage, thus enabling the shift register unit provided in this embodiment to prevent screen flickering while ensuring a more stable output signal.

[0131] In the embodiments of this disclosure, the value of the fifth reference voltage can be similar to or the same as the value of the first reference voltage. Of course, it can also be different.

[0132] In practical applications, the specific voltage values ​​mentioned above can be designed and determined according to the actual application environment, and are not limited here. Of course, all the transistors mentioned above can be set as N-type transistors, and are not limited here.

[0133] This disclosure provides a driving method for the above-described shift register unit, comprising:

[0134] During the noise reduction phase, the first output circuit responds to the signal of the first node by providing the signal of the first reference voltage signal terminal to the output signal terminal, and the noise reduction circuit responds to the signal of the noise reduction signal terminal by providing the signal of the third reference voltage signal terminal to the second node, thereby controlling the second output circuit to stop outputting signals.

[0135] like Figure 2 As shown, this disclosure provides a driving method for the above-mentioned shift register unit, including: S100, a first stage, loading a second level signal onto the input signal terminal; loading a second level signal onto the first clock signal terminal; loading a first level signal onto the second clock signal terminal; loading a first level signal onto the noise reduction signal terminal; and causing the output signal terminal to output a first level signal.

[0136] S200, Second stage: Apply a second level signal to the input signal terminal; apply a second level signal to the first clock signal terminal; apply a first level signal to the second clock signal terminal; apply a second level signal to the noise reduction signal terminal; so that the output signal terminal outputs a second level signal.

[0137] S300, Third stage: Apply a second level signal to the input signal terminal; apply a first level signal to the first clock signal terminal; apply a second level signal to the second clock signal terminal; apply a second level signal to the noise reduction signal terminal; so that the output signal terminal outputs a second level signal.

[0138] S400, the fourth stage, a first level signal is loaded to the input signal end; a second level signal is loaded to the first clock signal end, a first level signal is loaded to the second clock signal end, a second level signal is loaded to the noise reduction signal end, and a second level signal is outputted to the output signal end;

[0139] S500, the fifth stage, a first level signal is loaded to the input signal end; a first level signal is loaded to the first clock signal end, a second level signal is loaded to the second clock signal end, a first level signal is loaded to the noise reduction signal end, and a first level signal is outputted to the output signal end.

[0140] Exemplarily, when all the transistors in the shift register unit are P-type transistors, the first level signal is a low level signal, and the second level signal is a high level signal. Alternatively, when all the transistors in the shift register unit are N-type transistors, the first level signal is a high level signal, and the second level signal is a low level signal.

[0141] Exemplarily, the noise reduction stage can include the second stage, the third stage and the fourth stage.

[0142] Of course, in actual application, the implementation manner of the noise reduction stage can be determined according to the requirements of actual application, which is not limited herein.

[0143] Hereinafter, the working process of the pixel driving circuit provided by the embodiment of the present disclosure is described with the shift register unit shown in Figure 1 as an example, and in combination with the signal timing diagram shown in Figure 3 .

[0144] Wherein, ip represents the input signal of the input signal end IP, ck represents the first clock signal of the first clock signal end CK, cb represents the second clock signal of the second clock signal end CB, ot represents the output signal of the output signal end OT, and vel represents the noise reduction signal of the noise reduction signal end VEL.

[0145] Since the gates of the fourth transistor T4 and the thirteenth transistor T13 are both coupled with the fourth reference voltage signal end V4, the fourth reference voltage signal end V4 inputs a low level signal, and thus the fourth transistor T4 and the thirteenth transistor T13 are always in a conductive state. For the convenience of description, the state of the fourth transistor T4 and the thirteenth transistor T13 at any time will not be analyzed hereinafter.

[0146] In the first stage F1, the input signal ip provides a high level, the second clock signal cb provides a high level, the first clock signal ck provides a low level, and the noise reduction signal vel provides a low level. The tenth transistor T10 is turned on, the high level of the input signal ip is provided to the first sub-node N1-1 and the second sub-node N1-2, and the third transistor T3, the sixth transistor T6, the ninth transistor T9 and the eleventh transistor T11 are all turned off. Moreover, the second transistor T2 is turned on, the third node N3 and the fourth node N4 are both at a low level, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned off. The first transistor T1 is turned on, the second node N2 is at a high level, and the twelfth transistor T12 is also turned off. Thus, the signal output by the output terminal OT is maintained at a low level.

[0147] In the second stage F2, the input signal ip provides a high level, the second clock signal cb provides a low level, the first clock signal ck provides a high level, and the noise reduction signal vel provides a high level. The tenth transistor T10 is turned off, the first sub-node N1-1 and the second sub-node N1-2 are maintained at a high level, and the third transistor T3, the sixth transistor T6, the ninth transistor T9 and the eleventh transistor T11 are all turned off. Moreover, the first transistor T1 is turned off, the second transistor T2 is turned off, the third node N3 and the fourth node N4 are maintained at a low level, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned on. The second node N2 is at a low level, the twelfth transistor T12 is turned on, and thus the signal output by the output terminal OT is at a high level.

[0148] In the third stage F3, the input signal ip provides a high level, the second clock signal cb provides a high level, the first clock signal ck provides a low level, and the noise reduction signal vel provides a high level. The tenth transistor T10 is turned on, the high level of the input signal ip is provided to the first sub-node N1-1 and the second sub-node N1-2, and the third transistor T3, the sixth transistor T6, the ninth transistor T9 and the eleventh transistor T11 are all turned off. Moreover, the first transistor T1 is turned off, the second transistor T2 is turned on, the third node N3 and the fourth node N4 are both at a low level, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned off. The second node N2 is maintained at a low level, the twelfth transistor T12 is turned on, and thus the signal output by the output terminal OT is at a high level.

[0149] In the fourth stage F4, the input signal ip provides a low level, the second clock signal cb provides a low level, the first clock signal ck provides a high level, and the noise reduction signal vel provides a high level. The tenth transistor T10 is turned off, the first sub-node N1-1 and the second sub-node N1-2 remain at a high level, the third transistor T3, the sixth transistor T6, the ninth transistor T9 and the eleventh transistor T11 are all turned off. In addition, the first transistor T1 is turned off, the second transistor T2 is turned off, the third node N3 and the fourth node N4 remain at a low level, the seventh transistor T7 is turned on, the eighth transistor T8 is turned on, the second node N2 is at a low level, the twelfth transistor T12 is turned on, and the output signal end OT outputs a high level signal.

[0150] In the fifth stage F5, the input signal ip provides a low level, the second clock signal cb provides a high level, the first clock signal ck provides a low level, and the noise reduction signal vel provides a low level. The tenth transistor T10 is turned on, the low level of the input signal ip is provided to the first sub-node N1-1 and the second sub-node N1-2, the third transistor T3, the sixth transistor T6, the ninth transistor T9 and the eleventh transistor T11 are all turned on. In addition, the first transistor T1 is turned off, the second transistor T2 is turned on, the third node N3 and the fourth node N4 are both at a low level, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned off. The second node N2 is at a high level, the twelfth transistor T12 is turned off, and the output signal end OT outputs a low level signal.

[0151] The embodiment of the present disclosure further provides another structural schematic diagram of the shift register unit, as shown in Figure 4 The embodiment of the present disclosure further provides another structural schematic diagram of the shift register unit, as shown in

[0152] In the embodiment of the present disclosure, as shown in Figure 4 The second control circuit 202 is further configured to provide a signal of the third node N3 to the fourth node N4 in response to a fourth reference voltage signal end V4, provide a signal of the second reference voltage signal end V2 to the fifth node N5 in response to a signal of the fourth node N4, and provide a signal of the second clock signal end CB to the fifth node N5 in response to a signal of the second sub-node N1-2.

[0153] In the embodiment of the present disclosure, as shown in Figure 4 The second control circuit 202 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a first capacitor C1.

[0154] The gate of the fourth transistor T4 is coupled with a fourth reference voltage signal terminal V4, the first pole of the fourth transistor T4 is coupled with the third node N3, and the second pole of the fourth transistor T4 is coupled with the fourth node N4;

[0155] The gate of the fifth transistor T5 is coupled with the fourth node N4, the first pole of the fifth transistor T5 is coupled with a second reference voltage signal terminal V2, and the second pole of the fifth transistor T5 is coupled with a fifth node N5;

[0156] The gate of the sixth transistor T6 is coupled with the second sub-node N1-2, the first pole of the sixth transistor T6 is coupled with the fifth node N5, and the second pole of the sixth transistor T6 is coupled with a second clock signal terminal CB;

[0157] The first electrode of the first capacitor C1 is coupled with the fifth node N5, and the second electrode of the first capacitor C1 is coupled with the second sub-node N1-2.

[0158] Based on the above embodiment, the fifth transistor T5 is controlled by the signal of the fourth node N4 to realize conduction and cut-off. The remaining working processes can be referred to the description of the above embodiment, and will not be repeated here.

[0159] The present disclosure also provides another structure diagram of the shift register unit, as shown in Figure 5 The present embodiment is different from the above embodiment, and the same parts will not be repeated here.

[0160] In the present embodiment, the value of the first reference voltage can be the same as the value of the fourth reference voltage. For example, the first reference voltage signal terminal V1 and the fourth reference voltage signal terminal V4 can be the same signal terminal, which can reduce the number of signal lines and the wiring difficulty. For example, as shown in Figure 5 The gate of the eleventh transistor T11 is coupled with the second sub-node N1-2, the first pole of the eleventh transistor T11 is coupled with an output signal terminal OT, and the second pole of the eleventh transistor T11 is coupled with the fourth reference voltage signal terminal V4.

[0161] Based on the above embodiment, when the eleventh transistor T11 is turned on, the signal of the fourth reference voltage signal terminal V4 is provided to the output signal terminal OT. The remaining working processes can be referred to the description of the above embodiment, and will not be repeated here.

[0162] The present disclosure also provides another structure diagram of the shift register unit, as shown in Figure 6 The present embodiment is different from the above embodiment, and the same parts will not be repeated here.

[0163] In the embodiments of the present disclosure, the value of the fifth reference voltage can also be the same as that of the fourth reference voltage. For example, the fifth reference voltage signal terminal V5 can be the same as the fourth reference voltage signal terminal V4, so that the number of signal lines is reduced, and the wiring difficulty is reduced. Figure 6 As shown in FIG. 6, the gate of the second transistor T2 is coupled with the first clock signal terminal CK, the first electrode of the second transistor T2 is coupled with the fourth reference voltage signal terminal V4, and the second electrode of the second transistor T2 is coupled with the third node N3.

[0164] Based on the above-mentioned embodiments, when the second transistor T2 is turned on, the signal of the fourth reference voltage signal terminal V4 is provided to the third node N3. The remaining working processes can refer to the description of the above-mentioned embodiments, and will not be repeated here.

[0165] The embodiments of the present disclosure also provide another structure diagram of the shift register unit, as shown in FIG. 7, which is deformed for the implementation in the above-mentioned embodiments. Only the differences between the present embodiment and the above-mentioned embodiments will be described below, and the substantially same parts will not be repeated here. Figure 7 In the embodiments of the present disclosure, the value of the first reference voltage can also be the same as that of the fourth reference voltage. For example, the first reference voltage signal terminal V1 can be the same as the fourth reference voltage signal terminal V4, so that the number of signal lines is reduced, and the wiring difficulty is reduced. For example, as shown in FIG. 8, the gate of the eleventh transistor T11 is coupled with the second sub-node N1-2, the first electrode of the eleventh transistor T11 is coupled with the output signal terminal OT, and the second electrode of the eleventh transistor T11 is coupled with the fourth reference voltage signal terminal V4.

[0166] Figure 7 Based on the above-mentioned embodiments, when the eleventh transistor T11 is turned on, the signal of the fourth reference voltage signal terminal V4 is provided to the output signal terminal OT. The remaining working processes can refer to the description of the above-mentioned embodiments, and will not be repeated here.

[0167] The embodiments of the present disclosure also provide another structure diagram of the shift register unit, as shown in FIG. 9, which is deformed for the implementation in the above-mentioned embodiments. Only the differences between the present embodiment and the above-mentioned embodiments will be described below, and the substantially same parts will not be repeated here.

[0168] In the embodiments of the present disclosure, the value of the fifth reference voltage can also be the same as that of the fourth reference voltage. For example, the fifth reference voltage signal terminal V5 can be the same as the fourth reference voltage signal terminal V4, so that the number of signal lines is reduced, and the wiring difficulty is reduced. For example, as shown in FIG. 10, the gate of the twelfth transistor T12 is coupled with the third node N3, the first electrode of the twelfth transistor T12 is coupled with the output signal terminal OT, and the second electrode of the twelfth transistor T12 is coupled with the fourth reference voltage signal terminal V4. Figure 8 Based on the above-mentioned embodiments, when the twelfth transistor T12 is turned on, the signal of the fourth reference voltage signal terminal V4 is provided to the output signal terminal OT. The remaining working processes can refer to the description of the above-mentioned embodiments, and will not be repeated here.

[0169] Figure 8 ​​As shown, the gate of the second transistor T2 is coupled with the first clock signal terminal CK, the first electrode of the second transistor T2 is coupled with the fourth reference voltage signal terminal V4, and the second electrode of the second transistor T2 is coupled with the third node N3.

[0170] Based on the above embodiment, when the second transistor T2 is turned on, the signal of the fourth reference voltage signal terminal V4 is provided to the third node N3. The remaining working process can refer to the description of the above embodiment, which is not described here.

[0171] The embodiment of the present disclosure further provides a shift register unit, comprising:

[0172] An input circuit (for example, the input circuit 10 described above), the input circuit being coupled with an input signal terminal (for example, the input signal terminal IP described above) and a first node (for example, the first node N1 described above), and being configured to provide the signal of the input signal terminal to the first node;

[0173] A control circuit (for example, the control circuit 20 described above), the control circuit being coupled with a second node (for example, the N2 described above), and being configured to control the second node;

[0174] A first output transistor (for example, the twelfth transistor T12 described above), the gate of the first output transistor being coupled with the second node, the first electrode of the first output transistor being coupled with a second reference voltage signal terminal (for example, the second reference voltage signal terminal V2 described above), and the second electrode of the first output transistor being coupled with an output signal terminal (for example, the OUT described above), and being configured to provide the signal of the second reference voltage signal terminal to the output signal terminal in response to the signal of the second node;

[0175] A noise reduction transistor (for example, the first transistor T1 described above), the gate of the noise reduction transistor being coupled with a noise reduction signal terminal (for example, the VEL described above), the first electrode of the noise reduction transistor being coupled with a third reference voltage signal terminal (for example, the V3 described above), and the second electrode of the noise reduction transistor being coupled with the second node, and being configured to provide the signal of the third reference voltage signal terminal to the second node in response to the signal of the noise reduction signal terminal.

[0176] And the working process of the shift register unit in this embodiment can refer to the above description, which is not described here.

[0177] In the embodiment of the present disclosure, a third capacitor (for example, the third capacitor C3 described above) is further included, the first electrode of the third capacitor is coupled with the second reference voltage signal terminal, and the second electrode of the third capacitor is coupled with the second electrode of the noise reduction transistor.

[0178] In the embodiments of the present disclosure, a second output transistor (for example, the eleventh transistor T11 described above) is further included, a gate of the second output transistor is coupled with the first node, a first pole of the output transistor is coupled with a first reference voltage signal terminal (for example, the first reference voltage signal terminal V1 described above), a second pole of the output transistor is coupled with the output signal terminal, and the output transistor is configured to provide a signal of the first reference voltage signal terminal to the output signal terminal in response to a signal of the first node.

[0179] In the embodiments of the present disclosure, the second reference voltage signal terminal (for example, the second reference voltage signal terminal V2 described above) and the third reference voltage signal terminal (for example, the third reference voltage signal terminal V3 described above) are the same signal terminal.

[0180] The embodiments of the present disclosure provide a driving control circuit, including a plurality of cascaded shift register units; an input signal terminal of a first stage shift register unit is coupled with a frame trigger signal terminal; in each adjacent two stage shift register units, an input signal terminal of a next stage shift register unit is coupled with an output signal terminal of a previous stage shift register unit.

[0181] As shown in Figure 9 , the driving control circuit includes a plurality of cascaded shift register units SR1, SR2, SR3, …, SRn-2, SRn-1 and SRn; where n is a natural number. The value of n depends on the actual design needs. The shift register unit adopts, for example, Figure 1 or Figure 4 to Figure 8 The exemplary shift register unit includes an input signal terminal IP, an output signal terminal OT, a noise reduction signal terminal VEL, a first clock signal terminal CK and a second clock signal terminal CB. Wherein, each terminal accesses the signals marked in the timing diagram as shown in Figure 3 : the input signal terminal IP of the shift register unit SR1 is coupled with the frame trigger signal terminal stv, and in each of the remaining stage shift register units, the output signal terminal OT of the previous stage shift register unit is coupled with the input signal terminal IP of the next stage shift register unit, that is, the signal output by the output signal terminal of the shift register unit SR1 can be used as the signal of the input signal terminal of the shift register unit SR2, the signal output by the output signal terminal of the shift register unit SR2 can be used as the signal of the input signal terminal of the shift register unit SR3, …, the signal of the output signal terminal of the shift register unit SRn-1 can be used as the signal of the input signal terminal of the shift register unit SRn, until there is no next stage shift register unit. The noise reduction signal terminal VEL accesses the noise reduction signal vell, the first clock signal terminal CK accesses the first clock signal ckl, and the second clock signal terminal CB accesses the second clock signal cbl. Figure 9 The timing of the gate driving device as shown in Figure 3The timing shown is used to infer that, which will not be described here.

[0182] Based on the same disclosure concept, the present disclosure also provides a display device, which comprises a plurality of pixel units, a plurality of signal lines and the above-mentioned driving control circuit provided by the present disclosure. The output signal terminal of one shift register unit in the driving control circuit is coupled with at least one signal line in the plurality of signal lines. The principle of solving the problem of the display device is similar to that of the above-mentioned driving control circuit, and therefore the implementation of the display device can be referred to the implementation of the above-mentioned driving control circuit, and the repeated parts will not be described here.

[0183] In the implementation, the display device in the present disclosure can be any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. The other essential components of the display device are understood by those skilled in the art, which will not be described here and should not be regarded as a limitation of the present disclosure.

[0184] In the implementation, the display device can comprise a plurality of pixel units, a plurality of gate lines and data lines. Each pixel unit can comprise a plurality of sub-pixels, such as red sub-pixel, green sub-pixel and blue sub-pixel. The above-mentioned display device provided by the present disclosure can be organic light-emitting display device or liquid crystal display device, which is not limited here.

[0185] In the present disclosure, the plurality of gate lines are also provided with driving control circuit, and one gate line is coupled with the output signal terminal of one shift register unit in the driving control circuit. For example, when the above-mentioned display device provided by the present disclosure is liquid crystal display device, the TFT in the sub-pixel can be coupled with the gate line, and the above-mentioned driving control circuit can be used as gate driving circuit, which is coupled with the gate line and applied to provide gate scanning signal for the TFT in the sub-pixel. It should be noted that the TFT in the sub-pixel can be N-type transistor or P-type transistor, which is not limited here.

[0186] In some embodiments of the present disclosure, when the display device provided in the embodiments of the present disclosure is an organic light-emitting display device, the display device further comprises a plurality of light-emitting control signal lines; the plurality of light-emitting control signal lines are correspondingly provided with driving control circuits; one light-emitting control signal line is coupled with an output signal terminal of one shift register unit in the driving control circuit. In addition, the plurality of gate lines are also correspondingly provided with driving control circuits; one gate line is coupled with an output signal terminal of one shift register unit in the driving control circuit. For example, in an organic light-emitting display device, a plurality of organic light-emitting diodes and pixel circuits connected with the organic light-emitting diodes are generally provided. The light-emitting control transistor for controlling the light-emitting of the organic light-emitting diode and the scan control transistor for controlling the input of the data signal are generally provided in the pixel circuit.

[0187] In the specific implementation, the light-emitting control transistor can be coupled with the light-emitting control signal line, the scan control transistor can be coupled with the gate line, the organic light-emitting display device can comprise one driving control circuit provided in the embodiments of the present disclosure, the driving control circuit can be used as a light-emitting driving circuit and is coupled with the light-emitting control transistor to provide the light-emitting control signal of the light-emitting control transistor. Alternatively, the driving control circuit can also be used as a gate driving circuit and is coupled with the gate line to provide the gate scan signal of the scan control transistor.

[0188] Of course, the organic light-emitting display device can also comprise two driving control circuits provided in the embodiments of the present disclosure, one of which can be used as a light-emitting driving circuit and is coupled with the light-emitting control transistor to provide the light-emitting control signal of the light-emitting control transistor; the other driving control circuit can be used as a gate driving circuit and is coupled with the gate line to provide the gate scan signal of the scan control transistor, which is not limited herein.

[0189] Although the preferred embodiments of the present application have been described, those skilled in the art who have the benefit of the basic inventive concept can make further changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0190] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A shift register unit, wherein, The input circuit is configured to provide a signal of an input signal terminal to a first node in response to a signal of a first clock signal terminal; The control circuit is configured to control a signal of a second node; The first output circuit is configured to provide a signal of a first reference voltage signal terminal to an output signal terminal in response to a signal of the first node; The second output circuit is configured to provide a signal of a second reference voltage signal terminal to the output signal terminal in response to a signal of the second node; The noise reduction circuit is configured to provide a signal of a third reference voltage signal terminal to the second node in response to a signal of a noise reduction signal terminal, and to control the second output circuit to stop outputting a signal. The noise reduction circuit comprises a first transistor; 2. The shift register cell of claim 1, wherein, a gate of the first transistor is coupled with the noise reduction signal terminal, a first pole of the first transistor is coupled with the third reference voltage signal terminal, and a second pole of the first transistor is coupled with the second node. The first node comprises a first sub-node and a second sub-node; 3. The shift register cell of claim 1, wherein, The shift register unit further comprises a conduction circuit; the first sub-node is coupled with the second sub-node through the conduction circuit; the conduction circuit is configured to conduct the first sub-node and the second sub-node in response to a signal of a fourth reference voltage signal terminal; The input circuit is further configured to provide the signal of the input signal terminal to the first sub-node in response to the signal of the first clock signal terminal; The first output circuit is further configured to provide the signal of the first reference voltage signal terminal to the output signal terminal in response to a signal of the second sub-node. The control circuit comprises a first control circuit, a second control circuit, and a third control circuit; 4. The shift register cell of claim 3, wherein, The first control circuit is configured to provide a fifth reference voltage signal terminal to a third node in response to a signal of the first clock signal terminal, and to provide a signal of the first clock signal terminal to the third node in response to a signal of the first sub-node; The second control circuit is configured to control a signal of the second sub-node and a signal of a fourth node; The third control circuit is configured to provide a signal of a second clock signal terminal to the second node in response to signals of the fourth node and the second clock signal terminal, and to provide a signal of the second reference voltage signal terminal to the second node in response to a signal of the first sub-node. The first control circuit comprises a second transistor and a third transistor; 5. The shift register cell of claim 4, wherein, a gate of the second transistor is coupled with the first clock signal terminal, a first pole of the second transistor is coupled with the fifth reference voltage signal terminal, and a second pole of the second transistor is coupled with the third node; a gate of the third transistor is coupled with the first sub-node, a first pole of the third transistor is coupled with the third node, and a second pole of the third transistor is coupled with the first clock signal terminal. ​ 6. The shift register cell of claim 4, wherein, The second control circuit is further configured to provide a signal of the third node to the fourth node in response to a signal of the fourth reference voltage signal terminal, and provide a signal of the second reference voltage signal terminal to a fifth node in response to a signal of the fourth node, and provide a signal of the second clock signal terminal to the fifth node in response to a signal of the second sub-node.

7. The shift register cell of claim 6, wherein, The second control circuit comprises a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor; a gate of the fourth transistor is coupled with the fourth reference voltage signal terminal, a first electrode of the fourth transistor is coupled with the third node, and a second electrode of the fourth transistor is coupled with the fourth node; a gate of the fifth transistor is coupled with the fourth node, a first electrode of the fifth transistor is coupled with the second reference voltage signal terminal, and a second electrode of the fifth transistor is coupled with the fifth node; a gate of the sixth transistor is coupled with the second sub-node, a first electrode of the sixth transistor is coupled with the fifth node, and a second electrode of the sixth transistor is coupled with the second clock signal terminal; a first electrode of the first capacitor is coupled with the fifth node, and a second electrode of the first capacitor is coupled with the second sub-node.

8. The shift register cell of claim 4, wherein, The second control circuit is further configured to provide a signal of the third node to the fourth node in response to a signal of the fourth reference voltage signal terminal, and provide a signal of the second reference voltage signal terminal to a fifth node in response to a signal of the fourth node, and provide a signal of the second clock signal terminal to the fifth node in response to a signal of the second sub-node.

9. The shift register cell of claim 8, wherein, The second control circuit comprises a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor; a gate of the fourth transistor is coupled with the fourth reference voltage signal terminal, a first electrode of the fourth transistor is coupled with the third node, and a second electrode of the fourth transistor is coupled with the fourth node; a gate of the fifth transistor is coupled with the fourth node, a first electrode of the fifth transistor is coupled with the second reference voltage signal terminal, and a second electrode of the fifth transistor is coupled with the fifth node; a gate of the sixth transistor is coupled with the second sub-node, a first electrode of the sixth transistor is coupled with the fifth node, and a second electrode of the sixth transistor is coupled with the second clock signal terminal; a first electrode of the first capacitor is coupled with the fifth node, and a second electrode of the first capacitor is coupled with the second sub-node.

10. A shift register cell as claimed in any one of claims 4-9, wherein, The third control circuit comprises a seventh transistor, an eighth transistor, a ninth transistor and a second capacitor; a gate of the seventh transistor is coupled with the fourth node, a first electrode of the seventh transistor is coupled with the second clock signal terminal, and a second electrode of the seventh transistor is coupled with a first electrode of the eighth transistor; a gate of the eighth transistor is coupled with the second clock signal terminal, and a second electrode of the eighth transistor is coupled with the second node; A gate of the ninth transistor is coupled with the first sub-node, a first pole of the ninth transistor is coupled with the second node, and a second pole of the ninth transistor is coupled with the second reference signal terminal; A first electrode of the second capacitor is coupled with the fourth node, and a second electrode of the second capacitor is coupled with the first pole of the eighth transistor.

11. The shift register cell of any of claims 3-9, wherein, The input circuit includes a tenth transistor; A gate of the tenth transistor is coupled with the first clock signal terminal, a first pole of the tenth transistor is coupled with the input signal terminal, and a second pole of the tenth transistor is coupled with the first sub-node.

12. The shift register cell of any of claims 3-9, wherein, The first output circuit includes an eleventh transistor; A gate of the eleventh transistor is coupled with the second sub-node, a first pole of the eleventh transistor is coupled with the output signal terminal, and a second pole of the eleventh transistor is coupled with the first reference voltage signal terminal.

13. The shift register cell of any of claims 1-9, wherein, The second output circuit includes a twelfth transistor and a third capacitor; A gate of the twelfth transistor is coupled with the second node, a first pole of the twelfth transistor is coupled with the second reference voltage signal terminal, and a second pole of the twelfth transistor is coupled with the output signal terminal; A first electrode of the third capacitor is coupled with the second node, and a second electrode of the third capacitor is coupled with the second reference voltage signal terminal.

14. The shift register cell of any of claims 3-9, wherein, The conduction circuit includes a thirteenth transistor; A gate of the thirteenth transistor is coupled with the fourth reference voltage signal terminal, a first pole of the thirteenth transistor is coupled with the first sub-node, and a second pole of the thirteenth transistor is coupled with the second sub-node.

15. The shift register cell of any of claims 1-9, wherein, The second reference voltage signal terminal and the third reference voltage signal terminal are the same signal terminal.

16. A shift register unit, wherein, Comprise: An input circuit coupled with an input signal terminal and a first node, configured to provide a signal of the input signal terminal to the first node; A control circuit coupled with a second node, configured to control the second node; A first output transistor, a gate of the first output transistor is coupled with the second node, a first pole of the first output transistor is coupled with a second reference voltage signal terminal, and a second pole of the first output transistor is coupled with an output signal terminal, configured to provide a signal of the second reference voltage signal terminal to the output signal terminal in response to a signal of the second node; A noise reduction transistor, a gate of the noise reduction transistor is coupled with a noise reduction signal terminal, a first pole of the noise reduction transistor is coupled with a third reference voltage signal terminal, and a second pole of the noise reduction transistor is coupled with the second node, configured to provide a signal of the third reference voltage signal terminal to the second node in response to a signal of the noise reduction signal terminal.

17. The shift register cell of claim 16, wherein, Further comprising a third capacitor, a first electrode of the third capacitor is coupled with the second reference voltage signal terminal, and a second electrode of the third capacitor is coupled with the second pole of the noise reduction transistor.

18. The shift register cell of claim 17, wherein, The second output transistor is coupled with the first node at the gate, the first pole of the output transistor is coupled with the first reference voltage signal terminal, and the second pole of the output transistor is coupled with the output signal terminal, and is configured to provide the signal of the first reference voltage signal terminal to the output signal terminal in response to the signal of the first node.

19. The shift register cell of claim 16, wherein, The second reference voltage signal terminal and the third reference voltage signal terminal are the same signal terminal.

20. A drive control circuit, wherein, The driving control circuit comprises a plurality of shift register units connected in cascade, each of the shift register units being as claimed in any one of claims 1-19. The input signal terminal of the first stage shift register unit is coupled with a frame trigger signal terminal. In each of two adjacent stage shift register units, the input signal terminal of the next stage shift register unit is coupled with the output signal terminal of the previous stage shift register unit.

21. A display device, wherein, The driving control circuit comprises the driving control circuit as claimed in claim 20.

22. A driving method of a shift register unit as claimed in any one of claims 1 to 19, wherein, The driving control circuit comprises: In the noise reduction stage, the first output circuit provides the signal of the first reference voltage signal terminal to the output signal terminal in response to the signal of the first node, and the noise reduction circuit provides the signal of the third reference voltage signal terminal to the second node in response to the signal of the noise reduction signal terminal, and controls the second output circuit to stop outputting the signal.

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