Signal interconnection method, device, system and medium between radio frequency signal chain chips

Abstract

The present application discloses a signal interconnection method, device, system and medium between RF signal chain chips, which relates to the field of chip design technology and is used to reduce the number of IO ports to reduce the cost and difficulty of multi-chip interconnection while meeting the requirements of fast response configuration. In view of the problem that traditional solutions require a large number of IO ports, a signal interconnection method between RF signal chain chips is provided: the register write configuration words for register configuration writing are divided into several groups of register configuration values; a group of register configuration values ​​are written at one time within a clock cycle; the next group of register configuration values ​​are written in the next clock cycle; therefore, the cyclic distribution mechanism established in this way realizes the complete writing of register write configuration words, which can greatly compress the number of IO ports; and the writing time required by this method can be adjusted by adjusting the number of interfaces, thereby compressing the number of IO ports while meeting the fast configuration response time, so as to facilitate the interconnection between multiple chips.

Description

Technical Field

[0001] The present application relates to the field of chip design, and in particular to a method, device, system and medium for signal interconnection between radio frequency signal chain chips. Background Art

[0002] In wireless fields such as communications and radar, the RF signal chain is the basis for the implementation of various technologies. The RF signal chain is usually composed of multiple chips such as RF transceiver frequency conversion chips, analog-to-digital / digital-to-analog (AD / DA) chips and baseband chips (BB) chips to form a complete module. It can also be a system-in-a-package (SIP) of multiple chips to achieve the miniaturization of the RF signal chain system. By packaging multiple chips into an integrated circuit chip, the chip cost can be reduced, and the integrated circuit functions and indicators can be modified more flexibly. However, these chips need to be interconnected with control signals and data signals.

[0003] In related technologies, for slow control signals, such as filter parameters, register function power-down (PD) and other working mode selections, control signal configuration is generally performed through a standard serial peripheral interface (SPI). For configurations that require fast response, such as gain adjustment of RF transceiver frequency conversion chips, rapid changes in the local oscillator frequency of the frequency synthesizer (PLL), etc., due to the slow SPI configuration speed, additional parallel ports are required as configuration interfaces, which correspond one-to-one with the configuration registers. This will increase the area and cost of RF transceiver frequency conversion chips, as well as increase the cost and technical difficulty of packaging interconnection.

[0004] Therefore, technical personnel in this field now urgently need a signal interconnection method between RF signal chain chips to reduce the number of control interfaces to reduce the cost and difficulty of multi-chip interconnection while meeting the rapid response configuration between RF signal chain chips. Summary of the invention

[0005] The purpose of this application is to provide a signal interconnection method, device, system and medium between RF signal chain chips, which are used to reduce the number of control interfaces to reduce the cost and difficulty of multi-chip interconnection while meeting the rapid response configuration between RF signal chain chips.

[0006] In order to solve the above technical problems, the present application provides a signal interconnection method between RF signal chain chips, wherein the RF transceiver frequency conversion chip is connected with the AD / DA chip and the baseband chip through a clock interface and one or more register configuration IO interfaces;

[0007] Applied to the RF transceiver frequency conversion chip side, the method includes:

[0008] Receive a clock signal through the clock interface, and receive a register configuration value of the current clock cycle of the clock signal through the register configuration IO interface; wherein the register configuration value is one or more bits of data that need to be written into the register write configuration word of the RF transceiver frequency conversion chip, and the number of data bits contained in the register configuration value is equal to the number of the register configuration IO interface; and the register configuration values ​​corresponding to different clock cycles correspond to different bits of data in the register write configuration word;

[0009] According to the current clock cycle, writing the register configuration value into the corresponding register bit;

[0010] Repeat the above steps until the register write configuration word is completely written into the register.

[0011] In a possible embodiment, the radio frequency transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through multiple register configuration IO interfaces.

[0012] In a possible embodiment, the multiple register configuration IO interfaces multiplex the multiple FT test IO interfaces of the RF transceiver frequency conversion chip;

[0013] The clock interface is an FT test clock interface.

[0014] In a possible embodiment, the radio frequency transceiver frequency conversion chip is further connected to the AD / DA chip and the baseband chip via a function mode selection interface;

[0015] Accordingly, before receiving the clock signal through the clock interface, the method further includes:

[0016] According to the mode selection signal received by the functional mode selection interface, the functional mode is switched to the fast configuration mode;

[0017] The functional mode also includes other functional modes for implementing FT testing.

[0018] In order to solve the above technical problems, the present application also provides a signal interconnection method between RF signal chain chips, wherein the RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through a clock interface and one or more register configuration IO interfaces;

[0019] Applied to the AD / DA chip or the baseband chip, the method includes:

[0020] Write the configuration words to the registers of the radio frequency transceiver frequency conversion chip, and divide them into multiple groups of register configuration values ​​according to the number of the register configuration IO interfaces; wherein each group of register configuration values ​​corresponds to a different clock cycle of the clock signal;

[0021] According to the sequence of clock cycles, the corresponding groups of register configuration values ​​are sent to the radio frequency transceiver frequency conversion chip in sequence through the register configuration IO interface.

[0022] In a possible embodiment, the RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through multiple register configuration IO interfaces; the multiple register configuration IO interfaces are respectively multiple FT test IO interfaces of the RF transceiver frequency conversion chip, including at least: a scan in interface and a testdata out interface;

[0023] Then the register write configuration word that needs to be written into the RF transceiver frequency conversion chip is divided into multiple groups of register configuration values ​​according to the number of the register configuration IO interfaces, including:

[0024] In the register write configuration word, each continuous multiple bits of data are divided as a group to obtain multiple groups of register configuration values;

[0025] The multiplexed multiple FT test IO interfaces respectively correspond to one bit of data in each group of register configuration values.

[0026] In order to solve the above technical problems, the present application also provides a signal interconnection device between RF signal chain chips, wherein the RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through a clock interface and one or more register configuration IO interfaces;

[0027] Applied to the radio frequency transceiver frequency conversion chip side, the device includes:

[0028] A configuration receiving module is used to receive a clock signal through the clock interface, and receive a register configuration value of the current clock cycle of the clock signal through the register configuration IO interface; wherein the register configuration value is one or more bits of data that need to be written into the register write configuration word of the RF transceiver frequency conversion chip, and the number of data bits contained in the register configuration value is equal to the number of the register configuration IO interface; and the register configuration values ​​corresponding to different clock cycles correspond to different bits of data in the register write configuration word;

[0029] A configuration writing module, used for writing the register configuration value into the corresponding register bit according to the current clock cycle;

[0030] A cyclic writing module is used to repeatedly trigger the configuration receiving module and the configuration writing module until the register writing configuration word is completely written into the register.

[0031] In order to solve the above technical problems, the present application also provides a signal interconnection device between RF signal chain chips, wherein the RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through a clock interface and one or more register configuration IO interfaces;

[0032] Applied to the AD / DA chip or the baseband chip side, the device includes:

[0033] A configuration slicing module is used to write configuration words to the registers of the radio frequency transceiver frequency conversion chip, and divide the configuration words into multiple groups of register configuration values ​​according to the number of the register configuration IO interfaces; wherein each group of register configuration values ​​corresponds to a different clock cycle of the clock signal;

[0034] The cyclic distribution module is used to send the corresponding groups of register configuration values ​​to the radio frequency transceiver frequency conversion chip in sequence through the register configuration IO interface according to the sequence of clock cycles.

[0035] In order to solve the above technical problems, the present application also provides a signal interconnection system between RF signal chain chips, including: a RF transceiver frequency conversion chip, an AD / DA chip and a baseband chip;

[0036] The RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip via a clock interface and one or more register configuration IO interfaces;

[0037] The RF transceiver frequency conversion chip is used to implement the steps of the signal interconnection method between RF signal chain chips applied to the RF transceiver frequency conversion chip side as described above;

[0038] The AD / DA chip and the baseband chip are used to implement the steps of the signal interconnection method between RF signal chain chips applied to the AD / DA chip or baseband chip side as described above.

[0039] In order to solve the above technical problems, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the signal interconnection method between RF signal chain chips as described above are implemented.

[0040] The present application provides a signal interconnection method between RF signal chain chips. Through a cyclic distribution mechanism, the register write configuration word for register configuration writing is divided into multiple pieces, that is, multiple groups of register configuration values ​​are obtained; wherein the number of data bits included in each group of register configuration values ​​corresponds to the number of register configuration IO interfaces for realizing chip-to-chip interconnection, and the writing of each group of register configuration values ​​is realized by the register configuration IO interface; further, different groups of register configuration values ​​are written in different clock cycles using the clock signal provided by the clock interface, thereby realizing the writing of complete register write configuration words through a cyclic writing mechanism.

[0041] Based on the RF signal chain chip configuration response implemented by this solution, the IO port only needs to transmit the distributed register configuration data. The time for one configuration is determined by the time of one clock cycle and the number of groups of register configuration values, that is, the number of register configuration IO interfaces. Compared with the configuration write implemented by the SPI instruction of address bit + data bit when the configuration response is implemented through SPI, it has a faster configuration write speed when the clock cycle and the number of register write configuration word bits are the same, which can meet the requirements of fast response configuration between RF signal chain chips. In addition, with the configuration cycle distribution method implemented by this solution, the same IO port can transmit different register configuration values ​​in different clock cycles, thereby significantly reducing the number of IO ports required and reducing the cost and difficulty of multi-chip interconnection.

[0042] The signal interconnection device, system and computer-readable storage medium between RF signal chain chips provided in the present application correspond to the above method and have the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 This is a structural diagram of a common RF signal chain;

[0045] Figure 2 A schematic diagram of a fast response configuration interface for a 1T1R RF transceiver frequency conversion chip;

[0046] Figure 3 This is a quick response configuration interface connection diagram for a 1T1R RF transceiver frequency conversion chip;

[0047] Figure 4 A flow chart of a signal interconnection method between radio frequency signal chain chips applied to a radio frequency transceiver frequency conversion chip side provided by the present invention;

[0048] Figure 5 A flow chart of a signal interconnection method between radio frequency signal chain chips applied to an AD / DA chip or a baseband chip provided by the present invention;

[0049] Figure 6 A hardware architecture diagram of a signal interconnection method between radio frequency signal chain chips provided by the present invention;

[0050] Figure 7 A timing diagram of a signal interconnection method between radio frequency signal chain chips provided by the present invention;

[0051] Figure 8 A schematic diagram of the chip-to-chip interface connection of a signal interconnection method between radio frequency signal chain chips provided by the present invention. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] The core of this application is to provide a signal interconnection method, device, system and medium between RF signal chain chips.

[0054] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0055] RF signal chain is the basis of wireless fields such as communication and radar. Figure 1 As shown in the figure, the RF signal chain is usually composed of multiple chips such as frequency conversion chip, analog-to-digital / digital-to-analog (AD / DA) chip and baseband chip (BB) chip to form a complete module. It is also possible to use multiple chips in SIP packaging to achieve the miniaturization of the RF signal chain system, so that different chips (chiplets) can use the most suitable process, such as 65nm for RF transceiver frequency conversion chip, 28nm for AD / DA chip, and 14nm for baseband chip. By packaging multiple chips into an integrated circuit chip, the chip cost can be effectively reduced and the integrated circuit function and index modification can be more flexible, but the control signals and data signals need to be interconnected between these chips to ensure the normal operation of the RF signal chain.

[0056] In the related art, for slow control signals, such as filter parameters, register function power-down (PD) and other working mode selections, control signal configuration is generally performed through a standard serial peripheral interface (SPI).

[0057] For configurations that require fast response, such as gain adjustment of RF transceiver frequency conversion chips, fast changes in the local oscillator frequency of frequency synthesizers (PLL), etc., due to the slow SPI configuration speed, additional parallel ports need to be added as configuration interfaces, which correspond one-to-one with configuration registers. This will increase the area and cost of RF transceiver frequency conversion chips, as well as increase the cost and technical difficulty of packaging interconnection.

[0058] like Figure 2 As shown, for a 1-receive 1-transmit (1T1R) RF transceiver frequency conversion chip, its working mode is frequency division duplex (FDD); the gain control is 4 bits (bits) for each I / Q branch (I, In-Phase, in-phase; Q, Quadrature, orthogonal) mixer; the I / Q branch programmable gain amplifier (PGA) stage is 8 bits each; based on this, there are 48 bits of transceiver channel gain control registers. Each PLL frequency control bit is 8 bits; the 2-way PLL frequency control bit is 16 bits; in summary, in order to achieve fast response configuration of the 1T1R RF transceiver frequency conversion chip, at least 64 parallel control interfaces are required.

[0059] based on Figure 2 The 1T1R RF transceiver frequency conversion chip shown in the figure is a common fast response configuration scheme. Figure 3 As shown in the figure, the AD / DA chip and the BB chip are connected to the RF transceiver frequency conversion chip through 64 input / output (IO) ports. The 64 IO ports will increase the area and cost of the RF transceiver frequency conversion chip, thereby increasing the cost and technical difficulty of packaging interconnection, and cannot well meet the signal interconnection requirements between chips in the RF signal chain.

[0060] To solve the above problems, the present application provides a signal interconnection method between RF signal chain chips, which is applied to the RF transceiver frequency conversion chip and the AD / DA chip and the baseband chip, in an architecture connected by one clock interface and one or more register configuration IO interfaces, that is, in the rapid response configuration between RF signal chain chips implemented based on this method, the number of IO ports required is the sum of one clock interface and one or more register configuration IO interfaces.

[0061] Furthermore, the method provides corresponding solutions from both sides of the RF signal chain to achieve fast response configuration, namely, the RF transceiver frequency conversion chip side and the AD / DA chip or baseband chip side. The following embodiments will also illustrate the method from these two sides.

[0062] First, it is applied to the RF transceiver frequency conversion chip side, such as Figure 4 As shown, the method includes:

[0063] S11: receiving a clock signal through a clock interface, and receiving a register configuration value of a current clock cycle of the clock signal through a register configuration IO interface.

[0064] Among them, the register configuration value is one or more bits of data that need to be written into the register write configuration word of the RF transceiver frequency conversion chip, and the number of data bits contained in the register configuration value is equal to the number of register configuration IO interfaces; and the register configuration values ​​corresponding to different clock cycles correspond to different bits of data in the register write configuration word.

[0065] S12: According to the current clock cycle, write the register configuration value into the corresponding register bit.

[0066] S13: Repeat the above steps until the register write configuration word is completely written into the register.

[0067] That is, step S13 is to determine whether the register write configuration word is completely written into the register. If not, the method goes to step S11. If yes, the method ends.

[0068] Similarly, it is applied to the AD / DA chip or baseband chip side, such as Figure 5 As shown, the method includes:

[0069] S21: Write the configuration word to the register of the RF transceiver frequency conversion chip, and divide it into multiple groups of register configuration values ​​according to the number of register configuration IO interfaces.

[0070] Each group of register configuration values ​​corresponds to a different clock cycle of the clock signal.

[0071] S22: According to the sequence of the clock cycles, the corresponding groups of register configuration values ​​are sent to the RF transceiver frequency conversion chip in sequence through the register configuration IO interface.

[0072] It can be seen from the above steps that the purpose of this method is to write a complete register write configuration word by dividing the complete register write configuration word into several parts, that is, multiple groups of register configuration values, and writing each group of register configuration values ​​in sequence through the register configuration IO interface to achieve the writing of the complete register write configuration word. The clock interface is used to provide a clock signal, and the cyclic writing of the above register configuration value is realized based on the clock signal, and each group of register configuration values ​​is written into the register in sequence based on the clock cycle.

[0073] It is not difficult to understand that the cyclic writing method implemented by this method can greatly reduce the number of required IO ports. However, this embodiment does not limit the specific number of register configuration IO interfaces, which should be determined according to the fast configuration response time requirements in the actual scenario. For example, the number of required IO can be reduced by almost half with only 2 clock cycles (1 / 2 register configuration IO port + 1 clock interface).

[0074] Furthermore, based on the rapid response configuration requirements in general scenarios in actual applications, this embodiment also provides a possible solution for selecting the specific number of register configuration IO interfaces, such as Figure 6 As shown:

[0075] The number of register configuration IO interfaces is multiple, that is, the RF transceiver frequency conversion chip and the AD / DA chip and the baseband chip are connected through multiple register configuration IO interfaces.

[0076] And in Figure 6 In the example shown, the multi-channel can be 2 channels, that is, in this embodiment, only 2 register configuration IO interfaces + 1 clock interface, a total of 3 IO ports, are needed to implement the configuration response. Figure 2 The design of 64 parallel interfaces in the example can greatly reduce the number of required IO ports.

[0077] It should be noted that this embodiment does not limit the specific scheme of dividing the register writing configuration word into multiple groups of register configuration values, but provides a possible implementation scheme:

[0078] In the register write configuration word, each continuous certain number of bits of data is divided as a group to obtain multiple groups of register configuration values;

[0079] The number of data bits contained in each group of register configuration values ​​is equal to the number of register configuration IO interfaces; each register configuration IO interface transmits the same bit of data in each group of register configuration values.

[0080] For example, taking the two register configuration IO interfaces in the above embodiment as Reg_IO_1 and Reg_IO_2, each group of register configuration values ​​contains 2 bits of data, wherein Reg_IO_1 transmits the first bit of data, and Reg_IO_2 transmits the second bit of data.

[0081] Furthermore, combined with the above Figure 2 In the example of the 1T1R RF transceiver frequency conversion chip shown in the figure, the register write configuration word is 64 bits, including: 4-bit transmit I branch mixer gain, 4-bit transmit Q branch mixer gain, 8-bit transmit I branch PGA gain and other control words. The corresponding timing is as follows Figure 7 As shown, Reg_IO_1 outputs the 7 / 5-bit register configuration value corresponding to the transmit I branch mixer gain and the 3 / 1-bit register configuration value corresponding to the transmit Q branch mixer gain according to the clock cycle sequence; Reg_IO_2 outputs the 6 / 4-bit register configuration value corresponding to the transmit I branch mixer gain and the 2 / 0-bit register configuration value corresponding to the transmit Q branch mixer gain according to the clock cycle sequence; the transmission timing of other control words is the same.

[0082] It should also be noted that in Figure 6 In the architecture shown, the configuration word splitting and cyclic writing of register writing on the AD / DA chip and baseband chip side are mainly implemented by the configuration word interleaving module therein, that is, the configuration word interleaving module is the main execution subject of the above-mentioned AD / DA chip and baseband chip side methods. The RF transceiver frequency conversion chip side writes the received register configuration values ​​into the corresponding registers in sequence according to the clock cycle, which is implemented by the configuration word distribution module therein, that is, the configuration word distribution module is the main execution subject of the above-mentioned RF transceiver frequency conversion chip side method.

[0083] In addition, Figure 2 Taking the 1T1R RF transceiver frequency conversion chip shown in as an example, the register write configuration word is 64 bits, and the 2-way register configuration IO interface requires 64 / 2=32 clock cycles to complete. Assuming that one clock cycle is 20ns, the time to complete one configuration is 20*32=640ns. If the gain fast response time is less than 1us and the PLL frequency configuration time is 1us, this solution can meet the system configuration time requirements.

[0084] Similarly, if a faster response configuration is required, the number of register configuration IO interfaces can be increased. For example, a 4-way register configuration IO interface can reduce the time required to complete the above configuration by half, and an 8-way register configuration IO interface can reduce it to 1 / 4.

[0085] In addition, as a comparison, if the traditional SPI method is used to complete the configuration, since the SPI instruction is address bit + data bit, a total of 16 bits per time. Assuming that the SPI clock cycle is also 20ns, the time to complete the configuration of 64 bits, a total of 8 bytes, is 20*16*8=2.56us, which is greater than the above system fast configuration requirements and also affects other slow mode configuration responses.

[0086] It can be seen that the signal interconnection between RF signal chain chips implemented based on this method can improve the fast response configuration speed and reduce the number of IO ports, thereby reducing the chip interconnection cost and difficulty while meeting the needs of fast response configuration, and better meet the needs of actual chip production and design.

[0087] Furthermore, based on the above embodiment, this embodiment also provides a preferred implementation scheme for further reducing the number of required IO ports:

[0088] The above-mentioned multiple register configuration IO interfaces are respectively multiple FT test IO interfaces of the RF transceiver frequency conversion chip;

[0089] The clock interface is the FT test clock interface.

[0090] It should be noted that the FT test, i.e. Final Test, mentioned above in this embodiment is one of the many tests required for chip mass production. For this reason, some test pins are reserved during the design of the chip to implement the corresponding test functions. For example, in the RF transceiver frequency conversion chip, the reserved test pins include the FT test clock interface (scan clock interface) for FT test and another 2 IO interfaces (scan in interface, testdata out interface). Among them, the scanclock interface is the interface for providing clock signals during the FT test, which can be used to multiplex as the clock interface in the above method, and the other 2 FT interfaces can be multiplexed as the 2-way register configuration IO interface in the above method. However, it should be noted that the FT test IO interface includes not only the scan in interface and the testdata out interface; the scan in interface and the testdata out interface do not have only one interface each; when the test speed needs to be increased, more IO ports may be expanded during the design to complete the FT test. This embodiment only takes the 2-way register configuration IO interface in the above example as an example to provide a specific implementation description of multiplexed FT test IO interfaces with multiple register configuration IO interfaces.

[0091] Based on this, the two-way register configuration IO interfaces Reg_IO_1 and Reg_IO_2 in the above embodiment can correspond to the scan in interface and the testdata out interface respectively. The implementation scheme for Reg_IO_1 and Reg_IO_2 in the above embodiment can also be applied to the scan in interface and the testdata out interface, and this embodiment will not be repeated here.

[0092] It should also be noted that the testdata out interface in the above FT test interface is generally a unidirectional output. However, in the fast response configuration of the RF transceiver frequency conversion chip, multiplexing this interface requires this port to receive signals, that is, this interface needs to support input. Therefore, at the beginning of the design of the RF transceiver frequency conversion chip, it is required to design the testdata out interface as a bidirectional IO port to meet the multiplexing requirements of this embodiment. In addition, Figure 8 In the example, the scan clock interface is reused as the clock interface in the fast response configuration, so it is renamed to REG_CLK. Similarly, the scan in interface corresponds to Figure 8 The SCAN_IN interface in the above testdata out interface corresponds to Figure 8 The TESTDATA_OUT interface in the interface is used to distinguish it from the original interface function.

[0093] However, it should be noted that the premise of interface reuse is not to affect its original function. Therefore, based on this, this embodiment also provides a further implementation scheme based on the above embodiment. Figure 8 As shown:

[0094] The RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through a function mode selection interface;

[0095] Accordingly, before receiving the clock signal through the clock interface, the method further includes:

[0096] According to the mode selection signal received by the function mode selection interface, the function mode is switched to the fast configuration mode;

[0097] The functional mode also includes other functional modes for implementing FT test, such as scan mode and memory built-in self-test (memory bist) mode. Further, in this embodiment, the functional mode includes 3 modes, so the simplest one can select the FT test mode through the 2-way functional mode selection interface ( Figure 8The DFT_MODE interface and WORK_MODE interface in the chip can realize the selection of three functional modes. For example, taking the binary signal selection functional mode as an example, the mode selection signal can be set to "01" to select the fast configuration mode, that is, to realize the functional mode of the method provided by the present application; the mode selection signal can be set to "10" to select the scan mode; the mode selection signal can be set to "00" to select the memory bist mode; in this way, the chip can correctly judge the current working mode based on the mode selection signal to avoid the problems caused by the multiplexing interface.

[0098] In summary, based on the above embodiments, this embodiment will be further improved by reducing it to 1 clock interface and 2 register configuration IO interfaces. The above clock interface and register configuration IO interface functions are realized by multiplexing the test interface reserved for FT testing in the chip. Although in order to ensure that the multiplexing interface does not affect other functions, the interface involved also adds a functional mode selection interface, these interfaces are all existing test interfaces in the chip. That is, when the rapid response configuration between RF signal chain chips is realized by the method of this embodiment, there is no need to set up any additional interfaces, which facilitates the interconnection between multiple chips and minimizes the system complexity and cost.

[0099] In the above embodiment, a signal interconnection method between RF signal chain chips is described in detail, and the present application also provides an embodiment corresponding to a signal interconnection device between RF signal chain chips. Similar to the above, the present application also describes the embodiments of the device part from the RF transceiver frequency conversion chip side and the AD / DA chip or baseband chip side, and the device embodiment is also applied to the hardware architecture between the RF transceiver frequency conversion chip and the AD / DA chip and the baseband chip, which are connected through one clock interface and one or more register configuration IO interfaces.

[0100] Applied to the RF transceiver frequency conversion chip side, this embodiment provides a signal interconnection device between RF signal chain chips, including:

[0101] A configuration receiving module is used to receive a clock signal through a clock interface, and to receive a register configuration value of a current clock cycle of the clock signal through a register configuration IO interface; wherein the register configuration value is one or more bits of data in a register write configuration word that needs to be written into the RF transceiver frequency conversion chip, and the number of data bits included in the register configuration value is equal to the number of register configuration IO interfaces; and the register configuration values ​​corresponding to different clock cycles correspond to different bits of data in the register write configuration word;

[0102] The configuration writing module is used to write the register configuration value into the corresponding register bit according to the current clock cycle;

[0103] The cyclic writing module is used to repeatedly trigger the configuration receiving module and the configuration writing module until the register writing configuration word is completely written into the register.

[0104] Applied to the AD / DA chip or baseband chip side, this embodiment provides a signal interconnection device between radio frequency signal chain chips, including:

[0105] The configuration slicing module is used to write the configuration words to the registers of the RF transceiver frequency conversion chip, and divide them into multiple groups of register configuration values ​​according to the number of register configuration IO interfaces; wherein each group of register configuration values ​​corresponds to a different clock cycle of the clock signal;

[0106] The cyclic distribution module is used to send the corresponding groups of register configuration values ​​to the RF transceiver frequency conversion chip in sequence through the register configuration IO interface according to the sequence of clock cycles.

[0107] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0108] In addition to the embodiments of the signal interconnection method and device between RF signal chain chips provided in the above embodiments, the present application also provides an embodiment corresponding to a signal interconnection system between RF signal chain chips. A signal interconnection system between RF signal chain chips includes a RF transceiver frequency conversion chip, an AD / DA chip, and a baseband chip;

[0109] Among them, the RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through a clock interface and one or more register configuration IO interfaces;

[0110] The radio frequency transceiver frequency conversion chip is used to implement the steps of the signal interconnection method between radio frequency signal chain chips applied to the radio frequency transceiver frequency conversion chip side as in the above embodiment;

[0111] The AD / DA chip and the baseband chip are used to implement the steps of the signal interconnection method between RF signal chain chips applied to the AD / DA chip or the baseband chip side as in the above-mentioned embodiment.

[0112] Since the embodiments of the system part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the system part, which will not be repeated here.

[0113] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the steps recorded in the above method embodiment (which may be a method corresponding to the RF transceiver frequency conversion chip side, or a method corresponding to the AD / DA chip or baseband chip side, or a method corresponding to the RF transceiver frequency conversion chip side and the AD / DA chip or baseband chip side) are implemented.

[0114] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0115] The above is a detailed introduction to the signal interconnection method, device, system and medium between RF signal chain chips provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can refer to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of this application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of this application.

[0116] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A signal interconnection method between radio frequency signal chain chips, characterized in that: The RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through a clock interface and one or more register configuration IO interfaces; Applied to the RF transceiver frequency conversion chip side, the method includes: S11: receiving a clock signal through the clock interface, and receiving a register configuration value of the current clock cycle of the clock signal through the register configuration IO interface; wherein the register configuration value is one or more bits of data that need to be written into the register write configuration word of the RF transceiver frequency conversion chip, and the number of data bits included in the register configuration value is equal to the number of the register configuration IO interface; and the register configuration values ​​corresponding to different clock cycles correspond to different bits of data in the register write configuration word; S12: writing the register configuration value into the corresponding register bit according to the current clock cycle; S13: Repeat the above steps S11 and S12 until the register write configuration word is completely written into the register.

2. The signal interconnection method between radio frequency signal chain chips according to claim 1, characterized in that: The RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through multiple register configuration IO interfaces.

3. The signal interconnection method between radio frequency signal chain chips according to claim 2, characterized in that: The multiple register configuration IO interfaces multiplex the multiple FT test IO interfaces of the RF transceiver frequency conversion chip; The clock interface is an FT test clock interface.

4. The signal interconnection method between radio frequency signal chain chips according to claim 3, characterized in that: The RF transceiver frequency conversion chip is also connected to the AD / DA chip and the baseband chip via a function mode selection interface; Accordingly, before receiving the clock signal through the clock interface, the method further includes: According to the mode selection signal received by the functional mode selection interface, the functional mode is switched to the fast configuration mode; The functional mode also includes other functional modes for implementing FT testing.

5. A signal interconnection method between radio frequency signal chain chips, characterized in that: The RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through a clock interface and one or more register configuration IO interfaces; Applied to the AD / DA chip or the baseband chip, the method includes: Write the configuration words to the registers of the radio frequency transceiver frequency conversion chip, and divide them into multiple groups of register configuration values ​​according to the number of the register configuration IO interfaces; wherein each group of register configuration values ​​corresponds to a different clock cycle of the clock signal; According to the sequence of clock cycles, the corresponding groups of register configuration values ​​are sent to the radio frequency transceiver frequency conversion chip in sequence through the register configuration IO interface.

6. The signal interconnection method between radio frequency signal chain chips according to claim 5, characterized in that: The RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through multiple register configuration IO interfaces; The multiple register configuration IO interfaces multiplex the multiple FT test IO interfaces of the RF transceiver frequency conversion chip, including at least: a scan in interface and a testdata out interface; Then the register write configuration word that needs to be written into the RF transceiver frequency conversion chip is divided into multiple groups of register configuration values ​​according to the number of the register configuration IO interfaces, including: In the register write configuration word, each continuous multiple bits of data are divided as a group to obtain multiple groups of register configuration values; The multiplexed multiple FT test IO interfaces respectively correspond to one bit of data in each group of register configuration values.

7. A signal interconnection device between radio frequency signal chain chips, characterized in that: The RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through a clock interface and one or more register configuration IO interfaces; Applied to the radio frequency transceiver frequency conversion chip side, the device includes: A configuration receiving module is used to receive a clock signal through the clock interface, and receive a register configuration value of the current clock cycle of the clock signal through the register configuration IO interface; wherein the register configuration value is one or more bits of data that need to be written into the register write configuration word of the RF transceiver frequency conversion chip, and the number of data bits contained in the register configuration value is equal to the number of the register configuration IO interface; and the register configuration values ​​corresponding to different clock cycles correspond to different bits of data in the register write configuration word; A configuration writing module, used for writing the register configuration value into the corresponding register bit according to the current clock cycle; A cyclic writing module is used to repeatedly trigger the configuration receiving module and the configuration writing module until the register writing configuration word is completely written into the register.

8. A signal interconnection device between radio frequency signal chain chips, characterized in that: The RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip through a clock interface and one or more register configuration IO interfaces; Applied to the AD / DA chip or the baseband chip side, the device includes: A configuration slicing module is used to write configuration words to the registers of the radio frequency transceiver frequency conversion chip, and divide the configuration words into multiple groups of register configuration values ​​according to the number of the register configuration IO interfaces; wherein each group of register configuration values ​​corresponds to a different clock cycle of the clock signal; The cyclic distribution module is used to send the corresponding groups of register configuration values ​​to the radio frequency transceiver frequency conversion chip in sequence through the register configuration IO interface according to the sequence of clock cycles.

9. A signal interconnection system between radio frequency signal chain chips, characterized in that: include: RF transceiver frequency conversion chip, AD / DA chip and baseband chip; The RF transceiver frequency conversion chip is connected to the AD / DA chip and the baseband chip via a clock interface and one or more register configuration IO interfaces; The RF transceiver frequency conversion chip is used to implement the steps of the signal interconnection method between RF signal chain chips as described in any one of claims 1 to 4; The AD / DA chip and the baseband chip are used to implement the steps of the signal interconnection method between RF signal chain chips as described in claim 5 or 6.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the signal interconnection method between RF signal chain chips as described in any one of claims 1 to 6 are implemented.

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