Wearable devices and ECG sensors

Abstract

The present application provides a wearable device and an electrocardiogram sensor, wherein the wearable device has an ECG sensor, and the ECG sensor includes a first electrode, a second electrode, and a signal processing circuit, wherein the first electrode can be arranged on the rear shell of the watch body, and the second electrode can be arranged on the middle frame of the watch body. When the user wears the wearable device, the first electrode contacts the upper limb of the human body, and the other upper limb contacts the second electrode to collect the electrical signal of the human body. After the electrical signals collected by the two electrodes are transmitted to the signal processing circuit, the common-mode signal is extracted and suppressed to eliminate the common-mode signal to obtain the ECG signal. The ECG signal is amplified and converted from analog to digital to obtain a digital electrocardiogram signal and output. This solution extracts and offsets the common-mode signal through the common-mode suppression circuit, suppresses the common-mode signal in the output signal, thereby improving the common-mode suppression ratio of the dual-electrode ECG measurement, while avoiding the problem of micro-short circuit of the watch electrodes.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to wearable devices and electrocardiogram sensors. Background Art

[0002] With the development of electronic technology and people's increasing attention to health monitoring, wearable devices have become one of the main tools for personalized health management.

[0003] For example, wearable devices such as smart watches have realized the single-lead electrocardiogram (ECG) detection function. The current ECG detection module of smart watches adopts a three-electrode solution, including an ECG detection positive electrode (ECG-P), an ECG detection negative electrode (ECG-N) and a right leg drive electrode. Usually the ECG-P electrode and the right leg drive electrode are set at the bottom of the watch, and the ECG-N electrode is set at the middle frame of the watch. When users use smart watches, the ECG-P electrode and the right leg drive electrode at the bottom of the watch are easily affected by dirt or sweat and cause micro-short circuits, thereby affecting the accuracy of ECG electrocardiogram detection. Summary of the invention

[0004] In view of this, the present application provides a wearable device and an electrocardiogram sensor to solve at least part of the above problems, and the disclosed technical solutions are as follows:

[0005] In the first aspect, the present application provides a wearable device, including: a main body and an electrocardiogram sensor, the electrocardiogram sensor including a first electrode and a second electrode arranged on the main body, and an electrocardiogram signal processing circuit arranged inside the main body; the first electrode is arranged on the rear shell surface of the main body, and the second electrode is arranged on the side surface of the main body, the first electrode is used to collect a first original electrocardiogram signal of the human body, and the second electrode is used to collect a second original electrocardiogram signal of the human body; the electrocardiogram signal processing circuit is connected to the first electrode and the second electrode, and the electrocardiogram signal processing circuit includes a common mode suppression circuit, an amplification circuit and an analog-to-digital conversion circuit; the common mode suppression circuit is used to extract the common mode signal in the first original electrocardiogram signal and the second original electrocardiogram signal, and eliminate the common mode signal in the first original electrocardiogram signal and the second original electrocardiogram signal to obtain the first electrocardiogram signal and the second electrocardiogram signal; the amplification circuit amplifies the differential mode signal of the first electrocardiogram signal and the second electrocardiogram signal to obtain the electrocardiogram signal to be detected; the analog-to-digital conversion circuit converts the electrocardiogram signal to be detected into a digital electrocardiogram signal. This solution collects the original ECG signal of the human body through two electrodes. The original ECG signal is extracted and suppressed by the common-mode suppression circuit, which suppresses the common-mode signal in the output signal, thereby improving the common-mode rejection ratio of the dual-electrode ECG measurement and avoiding the problem of micro-short circuit of the watch electrode.

[0006] In a possible implementation of the first aspect, the common-mode suppression circuit includes a common-mode extraction circuit and a common-mode cancellation circuit; the common-mode extraction circuit superimposes the first original electrocardiogram signal and the second original electrocardiogram signal to obtain an extracted common-mode signal, and transmits the first original electrocardiogram signal, the second original electrocardiogram signal and the extracted common-mode signal to the common-mode cancellation circuit; the common-mode cancellation circuit subtracts the first original electrocardiogram signal from the extracted common-mode signal to obtain the first electrocardiogram signal, and subtracts the second original electrocardiogram signal from the extracted common-mode signal to obtain the second electrocardiogram signal. This solution extracts the common-mode signal from the original ECG signal through the common-mode extraction circuit, and further subtracts the original ECG signal from the common-mode signal through the common-mode cancellation circuit to eliminate the common-mode signal. The two-stage circuit structure of the common-mode extraction circuit and the common-mode cancellation circuit is used to realize common-mode suppression, and the circuit structure is simple and the cost is low.

[0007] In a possible implementation manner of the first aspect, the common-mode extraction circuit in the common-mode suppression circuit includes a first voltage buffer circuit (such as Figure 3 The operational amplifier A1 shown in FIG. Figure 3 The operational amplifier A2) and the impedance network (as shown Figure 3 Z1 and Z2 shown); the first voltage buffer circuit includes a first operational amplifier, the in-phase input terminal of the first operational amplifier is connected to the first electrode, the inverting input terminal is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is the first output terminal of the common mode extraction circuit; the second voltage buffer circuit includes a second operational amplifier, the in-phase input terminal of the second operational amplifier is connected to the second electrode, the inverting input terminal is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is the third output terminal of the common mode extraction circuit; the impedance network is connected between the output terminal of the first operational amplifier and the output terminal of the second operational amplifier, and the midpoint of the impedance network is the second output terminal of the common mode extraction circuit. It can be seen that the two original ECG signals are superimposed at the midpoint of the impedance network after passing through the two voltage buffer circuits. After the two signals are superimposed, the differential signal therein is offset and the common mode signal is retained, thereby realizing the extraction of the common mode signal. The common mode extraction circuit of this scheme uses a voltage buffer composed of two operational amplifiers and an impedance network connected to the rear stage of the voltage buffer. The circuit structure is simple and the cost is low.

[0008] In a possible implementation manner of the first aspect, the impedance network includes at least two impedances connected in series in sequence, and each impedance includes any one of a resistor, an inductor, and a capacitor, or any multiple of them connected in series and / or in parallel.

[0009] In a possible implementation of the first aspect, the common-mode cancellation circuit in the common-mode suppression circuit includes a first subtractor and a second subtractor; the in-phase input terminal of the first subtractor is connected to the first output terminal of the common-mode extraction circuit, the inverting input terminal is connected to the second output terminal of the common-mode extraction circuit, and the output terminal is the positive output terminal of the common-mode suppression circuit; the in-phase input terminal of the second subtractor is connected to the third output terminal of the common-mode extraction circuit, the inverting input terminal is connected to the second output terminal of the common-mode extraction circuit, and the output terminal is the negative output terminal of the common-mode suppression circuit. This solution uses a subtractor composed of an operational amplifier to subtract the original ECG signal from the common-mode signal, thereby eliminating the common-mode signal in the original ECG signal, and has a simple circuit structure and low cost.

[0010] In a possible implementation manner of the first aspect, the first subtractor includes a third operational amplifier; a non-inverting input terminal of the third operational amplifier is connected via a first impedance (such as Figure 5 Z3 in the figure is connected to the first output terminal of the common mode extraction circuit, and the in-phase input terminal is also connected to the first output terminal of the common mode extraction circuit through the second impedance (such as Figure 5 Z4 as shown is grounded, and the inverting input terminal of the third operational amplifier is connected through a third impedance (such as Figure 5 The Z5 shown in FIG. 1 is connected to the second output terminal of the common mode extraction circuit, and the inverting input terminal is also connected to the second output terminal of the common mode extraction circuit through a fourth impedance (such as Figure 5 The inverting input terminal of the fourth operational amplifier is connected to the output terminal of the third operational amplifier through the fifth impedance (such as Figure 5 The Z7 shown in FIG. 1 is connected to the second output terminal of the common mode extraction circuit, and the inverting input terminal is also connected to the second output terminal of the common mode extraction circuit through the sixth impedance (such as Figure 5 The Z8 shown in FIG. 1 is connected to the output terminal of the fourth operational amplifier, and the in-phase input terminal of the fourth operational amplifier is connected to the output terminal of the fourth operational amplifier through the seventh impedance (such as Figure 5 The Z9 shown in FIG. 1 is connected to the third output terminal of the common mode extraction circuit, and the in-phase input terminal is also connected to the third output terminal of the common mode extraction circuit through the eighth impedance (such as Figure 5 Z10 as shown is grounded.

[0011] In a possible implementation manner of the first aspect, the first impedance, the second impedance, the third impedance, the fourth impedance, the fifth impedance, the sixth impedance, the seventh impedance and the eighth impedance all include any one of resistance, inductance and capacitance, or any multiple of them connected in series and / or in parallel.

[0012] In a possible implementation manner of the first aspect, impedance values ​​of the first impedance, the second impedance, the third impedance, the fourth impedance, the fifth impedance, the sixth impedance, the seventh impedance, and the eighth impedance are equal.

[0013] In a second aspect, the present application further provides an electrocardiogram sensor, comprising: a first electrode, a second electrode, and an electrocardiogram signal processing circuit;

[0014] The first electrode is used to collect a first original electrocardiogram signal of the human body, and the second electrode is used to collect a second original electrocardiogram signal of the human body; the electrocardiogram signal processing circuit is connected to the first electrode and the second electrode, and the electrocardiogram signal processing circuit includes a common-mode suppression circuit, an amplification circuit and an analog-to-digital conversion circuit; the common-mode suppression circuit is used to extract the common-mode signal in the first original electrocardiogram signal and the second original electrocardiogram signal, and eliminate the common-mode signal in the first original electrocardiogram signal and the second original electrocardiogram signal to obtain the first electrocardiogram signal and the second electrocardiogram signal; the amplification circuit amplifies the differential-mode signal of the first electrocardiogram signal and the second electrocardiogram signal to obtain the electrocardiogram signal to be detected; the analog-to-digital conversion circuit converts the electrocardiogram signal to be detected into a digital electrocardiogram signal.

[0015] In a possible implementation of the second aspect, the common-mode suppression circuit includes a common-mode extraction circuit and a common-mode cancellation circuit; the common-mode extraction circuit superimposes the first original electrocardiogram signal and the second original electrocardiogram signal to obtain an extracted common-mode signal, and transmits the first original electrocardiogram signal, the second original electrocardiogram signal and the extracted common-mode signal to the common-mode cancellation circuit; the common-mode cancellation circuit subtracts the first original electrocardiogram signal from the extracted common-mode signal to obtain a first electrocardiogram signal, and subtracts the second original electrocardiogram signal from the extracted common-mode signal to obtain a second electrocardiogram signal.

[0016] In a possible implementation of the second aspect, the common-mode extraction circuit in the common-mode suppression circuit includes a first voltage buffer circuit, a second voltage buffer circuit and an impedance network; the first voltage buffer circuit includes a first operational amplifier, a non-inverting input terminal of the first operational amplifier is connected to the first electrode, an inverting input terminal is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is the first output terminal of the common-mode extraction circuit; the second voltage buffer circuit includes a second operational amplifier, a non-inverting input terminal of the second operational amplifier is connected to the second electrode, an inverting input terminal is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is the third output terminal of the common-mode extraction circuit; the impedance network is connected between the output terminal of the first operational amplifier and the output terminal of the second operational amplifier, and the midpoint of the impedance network is the second output terminal of the common-mode extraction circuit.

[0017] In a possible implementation manner of the second aspect, the common-mode cancellation circuit in the common-mode suppression circuit includes a first subtractor and a second subtractor; the non-inverting input terminal of the first subtractor is connected to the first output terminal of the common-mode extraction circuit, the inverting input terminal is connected to the second output terminal of the common-mode extraction circuit, and the output terminal is the positive output terminal of the common-mode suppression circuit; the non-inverting input terminal of the second subtractor is connected to the third output terminal of the common-mode extraction circuit, the inverting input terminal is connected to the second output terminal of the common-mode extraction circuit, and the output terminal is the negative output terminal of the common-mode suppression circuit.

[0018] In a possible implementation of the second aspect, the first subtractor includes a third operational amplifier; a non-inverting input terminal of the third operational amplifier is connected to the first output terminal of the common-mode extraction circuit through a first impedance, and the non-inverting input terminal is also grounded through a second impedance; an inverting input terminal of the third operational amplifier is connected to the second output terminal of the common-mode extraction circuit through a third impedance, and the inverting input terminal is also connected to the output terminal of the third operational amplifier through a fourth impedance; an inverting input terminal of the fourth operational amplifier is connected to the second output terminal of the common-mode extraction circuit through a fifth impedance, and the inverting input terminal is also connected to the output terminal of the fourth operational amplifier through a sixth impedance, and the non-inverting input terminal of the fourth operational amplifier is connected to the third output terminal of the common-mode extraction circuit through a seventh impedance, and the non-inverting input terminal is also grounded through an eighth impedance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a structural schematic diagram of a wearable device provided in an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of electrode distribution of a wearable device provided in an embodiment of the present application;

[0021] Figure 3 is a topological diagram of an electrocardiogram signal processing circuit provided in an embodiment of the present application;

[0022] Figure 4 is a topological diagram of another electrocardiogram signal processing circuit provided in an embodiment of the present application;

[0023] Figure 5 This is a topological diagram of another electrocardiogram signal processing circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The terms "first", "second", "third", etc. in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0025] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0026] The embodiment of the present application provides a wearable device (such as a smart watch, a smart bracelet, an armband, etc.), which has an electrocardiogram sensor (ECG sensor). The ECG sensor includes a first electrode, a second electrode and a signal processing circuit, wherein the first electrode can be arranged on the back shell of the watch body, and the second electrode can be arranged on the middle frame of the watch body. When the user wears the wearable device, the first electrode contacts the upper limb of the human body, and the other upper limb contacts the second electrode to collect the electrical signal of the human body. After the electrical signals collected by the two electrodes are transmitted to the signal processing circuit, the common-mode signal is extracted and suppressed to eliminate the common-mode signal to obtain the ECG signal. The ECG signal is amplified and converted from analog to digital to obtain a digital ECG signal and output. This solution extracts and offsets the common-mode signal by adding a common-mode suppression circuit in the signal processing circuit, thereby suppressing the common-mode signal in the output signal, thereby improving the common-mode rejection ratio of the dual-electrode ECG measurement, while avoiding the problem of micro-short circuit of the watch electrode.

[0027] Let's first combine Figure 1 The structure of the wearable device provided in the embodiment of the present application is introduced. The wearable device may be a wearable device including an ECG sensor, such as a smart watch, a smart bracelet, or an armband.

[0028] like Figure 1 As shown, the wearable device may include a processor, an input device, a sensor module, a memory, and a power supply module. It is understandable that Figure 1 The components shown do not constitute a specific limitation on the wearable device. The wearable device may also include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently.

[0029] The processor may include one or more processing units, for example, an application processor (AP), a controller, a memory, a digital signal processor (DSP), etc. Among them, different processing units may be independent devices or integrated in one or more processors. Among them, the controller may be the nerve center and command center of the wearable device. The controller may generate an operation control signal according to the instruction opcode and the timing signal to complete the control of fetching and executing instructions. In other embodiments, a memory may also be provided in the processor for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. The memory may store instructions or data that have just been used or recycled by the processor. If the processor needs to use the instruction or data again, it may be directly called from the memory, avoiding repeated access, reducing the waiting time of the processor, and thus improving the efficiency of the wearable device.

[0030] The input device is used to provide user input and can be a mechanical device. The user touches the input device to cause the input device to rotate, translate or tilt to implement user input, start the wearable device (for example, turn it on or off), determine or adjust the signal (for example, adjust the volume), and other functions or operations.

[0031] It can be understood that the user input in the embodiment of the present application can be the user rotating, translating, tilting, etc. the input device. The wearable device can include one or more input devices.

[0032] The sensor module may include one or more sensors, for example, an ECG sensor, a pressure sensor, an acceleration sensor, a touch sensor, etc. It should be understood that Figure 1 Only a few examples of sensors are listed. In actual applications, the wearable device may also include more or fewer sensors, or use other sensors with the same or similar functions to replace the above-listed sensors, etc., and the embodiments of the present application are not limited thereto.

[0033] The ECG sensor is used to measure ECG signals. In an embodiment of the present application, the ECG sensor may include two electrodes, a first electrode and a second electrode, and a signal processing circuit coupled to the two electrodes, the signal processing circuit including a common mode suppression circuit, an amplification circuit and an analog-to-digital converter (ADC) circuit. Among them, the two electrodes are used to contact the skin of the user at different positions, for example, taking the user wearing the wearable device on the left hand as an example, one electrode contacts the user's left wrist, and the other electrode contacts the user's right hand finger. In the ECG measurement mode, the user's voltage signal is collected by the above two electrodes, and then processed by the post-processing circuit to obtain the user's ECG data. The layout of the electrodes in the wearable device, the connection relationship between the various levels of the signal processing circuit, the measurement principle of ECG, etc. will be described in detail below.

[0034] In addition, the wearable device may also include a photoplethysmography (PPG) sensor, which can be used to detect heart rate, that is, the number of heartbeats per unit time.

[0035] The pressure sensor can be used to detect the pressure value between the human body and the wearable device. The pressure sensor is used to sense the pressure signal and can convert the pressure signal into an electrical signal. There are many types of pressure sensors, such as resistive pressure sensors, inductive pressure sensors, capacitive pressure sensors, etc., which are not limited in the embodiments of the present application.

[0036] Accelerometers can be used to detect the magnitude of acceleration of wearable devices in various directions (generally three axes). Wearable devices are wearable devices. When users wear them, they move under the influence of the users. Therefore, the magnitude of acceleration in various directions detected by the accelerometer can reflect the movement state of the human body.

[0037] A touch sensor may be provided on a display screen. The touch sensor and the display screen form a touch screen, also known as a "touch screen". The touch sensor is used to detect a touch operation applied thereto or thereabout. The touch sensor may transmit the detected touch operation to a processor to determine the type of touch event. A visual output related to the touch operation may be provided through the display screen. In other embodiments, the touch sensor may also be provided on the surface of the display screen, at a different location from the display screen.

[0038] The memory can be used to store computer executable program codes, and the executable program codes include instructions. The processor executes various functional applications and data processing of the wearable device by running the instructions stored in the memory. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc., which is not limited in the embodiments of the present application.

[0039] The power supply module can supply power to various components in the wearable device, such as a processor, a sensor module, etc. In some embodiments, the power supply module can be a battery or other portable power element. In other embodiments, the wearable device can also be connected to a charging device (for example, via a wireless or wired connection), and the power supply module can receive the power input by the charging device and store the power in the battery.

[0040] In some embodiments, continue to refer to Figure 1, the wearable device also includes a display screen. The display screen includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light-emitting diode or an active matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light emitting diode (QLED), etc. In some embodiments, a touch sensor can be provided in the display screen to form a touch screen, which is not limited in the embodiments of the present application. It can be understood that in some embodiments, the wearable device may include a display screen or may not include a display screen. For example, when the wearable device is a bracelet, it may include a display screen or may not include a display screen. When the wearable device is a watch, it may include a display screen.

[0041] In some other embodiments, continue to refer to Figure 1 The wearable device may also include an audio device, which may include a microphone, a speaker, or a receiver, etc., which may receive or output sound signals.

[0042] In addition, the wearable device may have a wireless communication function. Figure 1 The wearable device may further include a wireless communication module, a mobile communication module, one or more antennas 1, and one or more antennas 2. The wearable device may implement a wireless communication function through the antenna 1, the antenna 2, the wireless communication module, and the mobile communication module.

[0043] In some embodiments, the wearable device further includes an electrode group, which includes two electrodes. The electrode group can be arranged on one or more outer surfaces of the wearable device. One or more processors can monitor the voltage signal received by the electrode group. In some embodiments, the electrodes can be used to provide an ECG function for the wearable device. For example, when a user contacts a first electrode and a second electrode on the wearable device, the wearable device can provide a 2-lead ECG function, that is, the wearable device can obtain an ECG signal based on a first electrical signal detected by the first electrode and a second electrical signal detected by the second electrode. The following embodiments of the present application mainly take the example of a wearable device including two electrodes.

[0044] Combine the following Figure 2 The wearable device provided in this application is introduced by taking a smart watch as an example.

[0045] like Figure 2 As shown, the smart watch 100 may include a watch body 10 and a wristband 20 connected to the watch body 10, and the wristband 20 is used to wear the watch body 10 on the user's wrist. The wristband 20 can be implemented by a flexible strip.

[0046] The watch body 1 may include a display screen, a rear shell 101 and a middle frame 102. The display screen and the rear shell 101 are relatively arranged on both sides of the middle frame 102, and the middle frame 102 is used to connect the display screen and the rear shell 101. The smart watch 100 of this embodiment also includes an ECG sensor. The ECG sensor includes a first electrode 103, a second electrode 104, and a signal processing circuit coupled to the two electrodes.

[0047] The first electrode 103 may be disposed on the rear shell 101 , and the first electrode 103 is exposed on the surface of the rear shell 101 . When the user wears the watch, the first electrode 103 is in direct contact with the upper limb of the user wearing the watch.

[0048] The second electrode 104 may be disposed on the middle frame 102, and in the ECG measurement mode, the user's other upper limb contacts the second electrode 104. For example, taking the watch worn on the left hand as an example, in the ECG measurement mode, the user's right hand finger contacts the second electrode 104 to collect ECG signals.

[0049] The materials of the first electrode and the second electrode may be conductive materials such as copper, aluminum, silver, stainless steel, and graphite.

[0050] The two electrodes collect electrical signals from the surface of the limbs they touch and transmit them to the ECG sensor. The ECG sensor transmits the electrical signals collected by the two electrodes to the subsequent signal processing circuit for processing to generate corresponding electrocardiogram signals.

[0051] Combine the following Figure 3 to Figure 5 The signal processing process of ECG measurement of the wearable device provided in the embodiment of the present application is introduced.

[0052] See also Figure 3 , shows a circuit structure diagram of the signal processing circuit of the ECG sensor provided in an embodiment of the present application.

[0053] like Figure 3 As shown, the signal processing circuit includes a common mode suppression circuit 1, an amplifier circuit 2 and an ADC circuit 3.

[0054] The first input terminal of the common mode suppression circuit 1 Coupled to the first electrode (ECG-P electrode), the second input terminal The first output terminal is coupled to the non-inverting input terminal of the amplifier circuit 2 , and the second output terminal is coupled to the inverting input terminal of the amplifier circuit 2 .

[0055] The ECG-P electrode collects positive ECG signals, and the ECG-N electrode collects negative ECG signals. The positive and negative ECG signals are differential signals with the same amplitude and opposite directions. In addition, both positive and negative ECG signals include common mode signals. Therefore, the first input terminal The received electrical signal includes the positive ECG signal V ECGP and the common-mode signal V CM , the second input The received electrical signal includes a negative ECG signal V ECGN and the common-mode signal V CM .

[0056] The common-mode suppression circuit 1 is used to extract the common-mode signal from the original ECG signal (i.e., the differential ECG signal containing the common-mode signal) received at the two input ends, and further offset the common-mode signal in the original ECG signal, thereby retaining the differential ECG signal in the original ECG signal, i.e., the positive ECG signal and the negative ECG signal, and transmitting it to the amplification circuit 2.

[0057] The output end of the amplifier circuit 2 is connected to the input end of the ADC circuit. The amplifier circuit 2 is used to amplify the differential ECG signal after common mode cancellation, that is, the voltage difference between the positive ECG signal and the negative ECG signal, so as to obtain an analog ECG signal. The analog ECG signal is transmitted to the ADC circuit 3 and converted into a digital ECG signal.

[0058] like Figure 4 As shown, the common mode suppression circuit 1 includes a common mode extraction circuit 11 and a common mode cancellation circuit 14. The common mode extraction circuit 11 includes a voltage buffer circuit 12 and an impedance network 13. The impedance network 13 may include at least two impedances with adjustable impedance values. In addition, the impedance here may be any one of a resistor, a capacitor, an inductor, etc., such as multiple impedances of the same type connected in series and / or in parallel, or at least two types of impedances connected in series and / or in parallel, wherein the number of each type of impedance may be one or more.

[0059] The common mode extraction circuit 11 includes a first input terminal Second input a first output terminal, a second output terminal and a third output terminal.

[0060] In some embodiments, the voltage buffer circuit 12 includes two operational amplifiers, and the in-phase input terminal of the voltage buffer circuit 12 is the first input terminal of the common mode suppression circuit, and the inverting input terminal is the second input terminal. The output terminals of the two operational amplifiers are the first output terminal and the third output terminal of the common mode suppression circuit. Moreover, an impedance network 13 is connected between the output terminals of the two operational amplifiers, and the midpoint of the impedance network 13 is the second output terminal of the common mode suppression circuit. Among them, the midpoint of the impedance network refers to the position where the upper and lower groups of impedance values ​​of the point are equal, and the impedance values ​​on both sides of the midpoint can be matched by adjusting the impedance value of any impedance in the impedance network.

[0061] The voltage buffer circuit 12 provides a very large low frequency input impedance and achieves excellent low noise performance by isolating the ECG input electrodes from the impedance network 13 .

[0062] The original ECG signal input by the common mode extraction circuit is superimposed at the midpoint of the impedance network 13 after passing through the voltage buffer circuit 12. After the two original ECG signals are superimposed, the differential signal cancels out and retains the common mode signal, that is, V ECGP With V ECGN Offset, keep V CM And output through the midpoint of the impedance network 13.

[0063] The common mode cancellation circuit 14 includes a first input terminal, a second input terminal, and a third input terminal, as well as a first output terminal and a second output terminal. The first input terminal of the common mode cancellation circuit is coupled to the first output terminal of the common mode extraction circuit 11, the second input terminal is coupled to the second output terminal of the common mode extraction circuit, and the third input terminal is coupled to the third output terminal of the common mode extraction circuit. The first output terminal of the common mode cancellation circuit is coupled to the first input terminal of the amplifier circuit 3, and the second output terminal is coupled to the second input terminal of the amplifier circuit.

[0064] The common-mode cancellation circuit 14 mainly includes two subtractors, which respectively perform subtraction on the differential signal and the common-mode signal, and reasonably set the gain coefficient of the subtractor, so as to completely cancel the common-mode signal in the original differential signal and retain the differential-mode signal, thereby achieving the function of common-mode suppression.

[0065] Subsequently, the differential ECG signal after common-mode cancellation is amplified by the amplifier circuit 2 , and finally the ADC circuit 3 converts the analog ECG signal into a digital ECG signal.

[0066] See also Figure 5 , shows a circuit topology diagram of a common-mode suppression circuit provided in an embodiment of the present application.

[0067] like Figure 5 As shown, the common mode extraction circuit includes two voltage buffers and an impedance network, wherein the impedance network is connected between the output terminals of the two voltage buffers.

[0068] In some embodiments, the voltage buffer is a voltage follower formed by an operational amplifier, and its output voltage changes with the change of the input voltage. The impedance network may include impedances Z1 and Z2 connected in series, and the impedance values ​​of Z1 and Z2 are equal. In addition, the impedance network may include a larger number of impedances.

[0069] The non-inverting input terminal of the operational amplifier A1 is coupled to the ECG-P electrode, and the inverting input terminal is connected to the output terminal of A1 to form a first voltage buffer, so that the signal output by A1 changes with the change of the input signal at its non-inverting input terminal.

[0070] Similarly, the negative output terminal of operational amplifier A2 is connected to the output terminal of A2 to form a second voltage buffer, and its non-inverting input terminal is coupled to the ECG-N electrode. The signal output by A2 changes with the change of the input signal at its non-inverting input terminal.

[0071] The output end of A1 is the first output end of the common mode extraction circuit, and the output end of A2 is the third output end of the common mode extraction circuit. The midpoint of the impedance network is the second output end of the common mode extraction circuit. Taking the impedance network including Z1 and Z2 as an example, the midpoint is the common point of Z1 and Z2.

[0072] In some embodiments, the impedance value of each impedance may be adjusted so that the impedance values ​​on both sides of the midpoint match, thereby ensuring the common mode rejection characteristics of the circuit.

[0073] Continue to see Figure 5 The common mode cancellation circuit includes two subtractors, namely, a first subtractor formed by an operational amplifier A3 and a second subtractor formed by an operational amplifier A4.

[0074] The in-phase input terminal of the operational amplifier A3 is connected to the first output terminal of the common mode extraction circuit, that is, the output terminal of A1, through the resistor Z3. At the same time, the in-phase input terminal of A3 is also grounded to GND through the resistor Z4. The inverting input terminal of A3 is connected to the second input terminal of the common mode extraction circuit, that is, the midpoint of the impedance network, through the resistor Z5. At the same time, the inverting input terminal of A3 is connected to the output terminal of A3 through the resistor Z6. The output terminal of A3 is the positive output terminal of the common mode suppression circuit

[0075] Similarly, the in-phase input of operational amplifier A4 is connected to the third output of the common mode extraction circuit through Z9, and the in-phase input is grounded through Z10. The inverting input of A4 is connected to the second output of the common mode extraction circuit through Z7, and the negative output is connected to the output of A4 through Z8. The output of A4 is the negative output of the common mode suppression circuit.

[0076] It should be noted that the above Z3~Z10 can be any one of resistance, inductance, and capacitance, such as an impedance obtained by connecting multiple impedances of the same type in series and / or in parallel, or at least two types of impedances in series and / or in parallel, where the number of each type of impedance can be one or more.

[0077] Combine the following Figure 5 The circuit topology shown describes the operation of the common-mode rejection circuit:

[0078] As mentioned above, A1 constitutes a voltage buffer, so the output signal of A1 (i.e., the signal at point A) is the same as the signal at its in-phase input terminal, both of which are ECG signals collected by the ECG-P electrode, i.e., the positive ECG signal V ECGP and the common-mode signal V CM Similarly, A2 constitutes a voltage buffer, and its output signal (i.e., the signal at point B) is the same as its input signal, which is the ECG signal collected by the ECG-N electrode, i.e., the negative ECG signal V ECGN and the common-mode signal V CM .

[0079] V ECGP and V CM is transmitted to the midpoint of the impedance network (i.e., point C) through impedance Z1. At the same time, V ECGN and V CM The two signals (V ECGP and V CM , V ECGN and V CM ) are superimposed at point C. Among them, V ECGP With V ECGN are signals with the same amplitude and opposite phase, so the superposition of the above two sets of signals can make V ECGP and V ECGN cancel while preserving the common-mode signal V CM .

[0080] At the same time, the output V ECGP and V CM Transmitted to the non-inverting input of A3. The V output at point B ECGN and V CM The common-mode signal V CM Transmitted to the inverting inputs of A3 and A4.

[0081] For the subtractor formed by A3, the original positive ECG signal is input to the in-phase input terminal of A3. That is V ECGP +V CM , A3’s inverting input terminal inputs a common-mode signal V CMBy properly configuring the impedance values ​​of resistors Z3 to Z6 around A3, the output voltage of A3 is Equal to the non-inverting input With the inverting input V CM Subtract, that is, This can completely cancel the common-mode signal and preserve V ECGP .

[0082] Similarly, for the subtractor formed by A4, the original negative ECG signal is input to the in-phase input terminal of A4. The inverting input terminal inputs the common mode signal V CM By properly configuring the impedance values ​​of resistors Z7 to Z10 around A4, the output voltage of A4 is equal to the voltage difference between the two input terminals, that is, This can completely cancel the common-mode signal and preserve V ECGN .

[0083] In summary, the electrocardiogram signal processing circuit provided by the present application collects the original electrocardiogram signal of the human body through two electrodes and transmits it to the subsequent signal processing circuit. The two original electrocardiogram signals are superimposed at the midpoint of the impedance network after passing through the voltage buffer in the common mode extraction circuit. After superposition, the differential signal in the two original electrocardiogram signals is offset and the common mode signal, i.e., V ECGP With V ECGN Offset, keep V CM . And, the extracted common-mode signal is transmitted to the common-mode cancellation circuit. At the same time, the output ends of the two voltage buffers still output the original ECG signals respectively, and transmit them to the common-mode cancellation circuit of the subsequent stage. The common-mode cancellation circuit is composed of two subtractors. The in-phase input ends of the two subtractors input an original ECG signal, and the inverting input ends input the extracted common-mode signal. The subtractors are used to subtract the signals input from the two input ends to cancel out the common-mode signal in the original ECG signal, and obtain an ECG signal that does not contain a common-mode signal. Therefore, the electrocardiogram signal processing circuit can suppress the common-mode signal in the output signal, thereby improving the common-mode rejection ratio of the dual-electrode ECG measurement, and at the same time, avoiding the problem of micro-short circuit of the smart watch electrodes.

[0084] In addition, the common-mode suppression circuit provided in the embodiment of the present application can also be applied to processing circuits of other bioelectric signals, such as electroencephalogram (EEG) and electromyogram (EMG) signals. The working principle of the common-mode suppression circuit is the same as the common-mode suppression process of the above-mentioned ECG signal, which will not be repeated here.

[0085] The following will introduce the process of assigning values ​​of each resistor and impedance in the common-mode cancellation circuit and the common-mode extraction circuit:

[0086] First, the positive output and negative output of the common-mode cancellation circuit are analyzed separately:

[0087] Using one of the characteristics of the operational amplifier, that is, the input impedance is infinite, that is, the equivalent impedance between the non-inverting input terminal and the inverting input terminal is infinite, Z5 connected to the inverting input terminal of A3 and the negative feedback resistor Z6 are equivalent to being connected in series between point C and the output terminal of A3. Therefore, the currents flowing through Z5 and Z6 are equal, and the following formula can be obtained:

[0088]

[0089] In formula 1, V mid represents the extracted common mode voltage, that is, the voltage at point C; V N represents the voltage at the inverting input terminal of A3; Represents the output voltage at the positive output terminal of the common-mode cancellation circuit.

[0090] Similarly, Z3 and Z4 are equivalent to being connected in series between point A and ground (GND). Therefore, the currents flowing through Z3 and Z4 are also equal, and the following formula can be obtained:

[0091]

[0092] In formula 2, Represents the input voltage of the positive input terminal of the common-mode extraction circuit, that is, the voltage at point A; V P Represents the voltage at the non-inverting input of A3.

[0093] Using another characteristic of the operational amplifier, V N =V P , combining the above formulas (1) and (2) to obtain the following formula:

[0094]

[0095] Similarly, analyzing the negative output terminal of the common-mode cancellation circuit yields:

[0096]

[0097] From the above analysis, we can see that if Then Z3 = Z4 = Z5 = Z6 = Z7 = Z8 = Z9 = Z10. It can be seen that when the impedance values ​​of the resistors in the common mode cancellation circuit are the same, the output voltage of the two subtractors in the common mode cancellation circuit can be ensured to be the difference between the voltages input to the two input terminals of the subtractors.

[0098] Secondly, the circuit analysis of the second output terminal of the common mode extraction circuit is performed:

[0099] The second output terminal of the common mode extraction circuit, namely point C, is connected to the second input terminal of the common mode cancellation circuit, namely point D. Therefore, the currents at point C and point D are equal.

[0100] The current at point C is the sum of the current flowing through Z1 and the current flowing through Z2, that is, the total current I at point C. C The formula is as follows:

[0101]

[0102] Similarly, the current at point D is the sum of the current flowing through Z5 and Z6 and the current flowing through Z7 and Z8, that is, the total current at point D I D The formula is as follows:

[0103]

[0104] Because I C =I D , so we get the following formula:

[0105]

[0106] in, Moreover, V ECGP With V ECGN The amplitudes are the same and the directions are opposite. Substituting them into the above formula 7, formula 7 can be simplified as follows:

[0107]

[0108] According to formula 8, the smaller Z5 is and the larger Z1 is, the extracted common-mode signal V mid The closer it is to the true common-mode signal V CM Wherein, Z5 represents the impedance value of each resistor in the common mode cancellation circuit. Z1 represents the impedance value of each impedance in the impedance network in the common mode extraction circuit.

[0109] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A wearable device, characterized in that: include: A main body and an electrocardiogram sensor, wherein the electrocardiogram sensor comprises a first electrode and a second electrode arranged on the main body, and an electrocardiogram signal processing circuit arranged inside the main body; The first electrode is arranged on the rear shell surface of the main body, and the second electrode is arranged on the side surface of the main body, the first electrode is used to collect a first original electrocardiogram signal of a human body, and the second electrode is used to collect a second original electrocardiogram signal of a human body; The electrocardiogram signal processing circuit is connected to the first electrode and the second electrode, the electrocardiogram signal processing circuit includes a common mode suppression circuit, an amplification circuit and an analog-to-digital conversion circuit, and the common mode suppression circuit includes a common mode extraction circuit and a common mode cancellation circuit; The common mode extraction circuit is used to extract the common mode signal in the first original electrocardiogram signal and the second original electrocardiogram signal; The common mode cancellation circuit is used to directly eliminate the common mode signal in the first original electrocardiogram signal and the second original electrocardiogram signal to obtain the first electrocardiogram signal and the second electrocardiogram signal and transmit them to the amplification circuit; The amplifying circuit amplifies the differential signal of the first electrocardiogram signal and the second electrocardiogram signal to obtain the electrocardiogram signal to be detected; The analog-to-digital conversion circuit converts the electrocardiogram signal to be detected into a digital electrocardiogram signal; Wherein, the common mode cancellation circuit includes a first subtractor and a second subtractor formed by an operational amplifier; The non-inverting input terminal of the first subtractor is connected to the first output terminal of the common mode extraction circuit, the inverting input terminal is connected to the second output terminal of the common mode extraction circuit, and the output terminal is the positive output terminal of the common mode suppression circuit; The non-inverting input terminal of the second subtractor is connected to the third output terminal of the common mode extraction circuit, the inverting input terminal is connected to the second output terminal of the common mode extraction circuit, and the output terminal is the negative output terminal of the common mode suppression circuit.

2. The wearable device according to claim 1, characterized in that: The common mode extraction circuit in the common mode suppression circuit comprises a first voltage buffer circuit, a second voltage buffer circuit and an impedance network; The first voltage buffer circuit comprises a first operational amplifier, a non-inverting input terminal of the first operational amplifier is connected to the first electrode, an inverting input terminal is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is the first output terminal of the common mode extraction circuit; The second voltage buffer circuit comprises a second operational amplifier, a non-inverting input terminal of the second operational amplifier is connected to the second electrode, an inverting input terminal is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is the third output terminal of the common mode extraction circuit; The impedance network is connected between the output terminal of the first operational amplifier and the output terminal of the second operational amplifier, and the midpoint of the impedance network is the second output terminal of the common mode extraction circuit.

3. The wearable device according to claim 2, characterized in that: The impedance network includes at least two impedances connected in series, and each impedance includes any one of resistance, inductance and capacitance, or any multiple types connected in series and / or in parallel.

4. The wearable device according to claim 1, characterized in that: The first subtractor includes a third operational amplifier, and the second subtractor includes a fourth operational amplifier; The non-inverting input terminal of the third operational amplifier is connected to the first output terminal of the common mode extraction circuit through a first impedance, and the non-inverting input terminal is also grounded through a second impedance, the inverting input terminal of the third operational amplifier is connected to the second output terminal of the common mode extraction circuit through a third impedance, and the inverting input terminal is also connected to the output terminal of the third operational amplifier through a fourth impedance; The inverting input terminal of the fourth operational amplifier is connected to the second output terminal of the common-mode extraction circuit through a fifth impedance, and the inverting input terminal is also connected to the output terminal of the fourth operational amplifier through a sixth impedance. The non-inverting input terminal of the fourth operational amplifier is connected to the third output terminal of the common-mode extraction circuit through a seventh impedance, and the non-inverting input terminal is also grounded through an eighth impedance.

5. The wearable device according to claim 4, characterized in that: The first impedance, the second impedance, the third impedance, the fourth impedance, the fifth impedance, the sixth impedance, the seventh impedance and the eighth impedance all include any one of resistance, inductance and capacitance, or any multiple of them connected in series and / or in parallel.

6. The wearable device according to claim 4 or 5, characterized in that: The impedance values ​​of the first impedance, the second impedance, the third impedance, the fourth impedance, the fifth impedance, the sixth impedance, the seventh impedance and the eighth impedance are equal.

7. An electrocardiogram sensor, characterized in that: include: a first electrode, a second electrode and an electrocardiogram signal processing circuit; The first electrode is used to collect a first original electrocardiogram signal of a human body, and the second electrode is used to collect a second original electrocardiogram signal of a human body; The electrocardiogram signal processing circuit is connected to the first electrode and the second electrode, the electrocardiogram signal processing circuit includes a common mode suppression circuit, an amplification circuit and an analog-to-digital conversion circuit, and the common mode suppression circuit includes a common mode extraction circuit and a common mode cancellation circuit; The common mode extraction circuit is used to extract the common mode signal in the first original electrocardiogram signal and the second original electrocardiogram signal; The common mode cancellation circuit is used to eliminate the common mode signal in the first original electrocardiogram signal and the second original electrocardiogram signal to obtain a first electrocardiogram signal and a second electrocardiogram signal; The amplifying circuit amplifies the differential signal of the first electrocardiogram signal and the second electrocardiogram signal to obtain the electrocardiogram signal to be detected; The analog-to-digital conversion circuit converts the electrocardiogram signal to be detected into a digital electrocardiogram signal; Wherein, the common mode cancellation circuit includes a first subtractor and a second subtractor formed by an operational amplifier; The non-inverting input terminal of the first subtractor is connected to the first output terminal of the common mode extraction circuit, the inverting input terminal is connected to the second output terminal of the common mode extraction circuit, and the output terminal is the positive output terminal of the common mode suppression circuit; The non-inverting input terminal of the second subtractor is connected to the third output terminal of the common mode extraction circuit, the inverting input terminal is connected to the second output terminal of the common mode extraction circuit, and the output terminal is the negative output terminal of the common mode suppression circuit.

8. The electrocardiogram sensor according to claim 7, characterized in that: The common mode extraction circuit in the common mode suppression circuit comprises a first voltage buffer circuit, a second voltage buffer circuit and an impedance network; The first voltage buffer circuit comprises a first operational amplifier, a non-inverting input terminal of the first operational amplifier is connected to the first electrode, an inverting input terminal is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is the first output terminal of the common mode extraction circuit; The second voltage buffer circuit comprises a second operational amplifier, a non-inverting input terminal of the second operational amplifier is connected to the second electrode, an inverting input terminal is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is the third output terminal of the common mode extraction circuit; The impedance network is connected between the output terminal of the first operational amplifier and the output terminal of the second operational amplifier, and the midpoint of the impedance network is the second output terminal of the common mode extraction circuit.

9. The electrocardiogram sensor according to claim 7, characterized in that: The first subtractor includes a third operational amplifier, and the second subtractor includes a fourth operational amplifier; The non-inverting input terminal of the third operational amplifier is connected to the first output terminal of the common mode extraction circuit through a first impedance, and the non-inverting input terminal is also grounded through a second impedance, the inverting input terminal of the third operational amplifier is connected to the second output terminal of the common mode extraction circuit through a third impedance, and the inverting input terminal is also connected to the output terminal of the third operational amplifier through a fourth impedance; The inverting input terminal of the fourth operational amplifier is connected to the second output terminal of the common-mode extraction circuit through a fifth impedance, and the inverting input terminal is also connected to the output terminal of the fourth operational amplifier through a sixth impedance. The non-inverting input terminal of the fourth operational amplifier is connected to the third output terminal of the common-mode extraction circuit through a seventh impedance, and the non-inverting input terminal is also grounded through an eighth impedance.

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