Clock correction method and device

Abstract

The present application discloses a clock correction method and device, which relates to the field of integrated circuit technology and is used to reduce fractional spurious noise in a phase-locked loop (PLL) to improve the stability of the PLL. The method includes: a clock correction device can determine a first sequence based on an acquired analog signal and a target frequency division coefficient. The first sequence can be used to indicate the first frequency division coefficient and the second frequency division coefficient corresponding to the analog signal. The clock correction device can determine the number of times the frequency division coefficient is the first frequency division coefficient and the second frequency division coefficient in a phase detection period based on the first sequence, and obtain a corrected clock signal based on the number of times the first frequency division coefficient and the second frequency division coefficient are used. The phase detection period is M times the frequency division period.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a clock correction method and device. Background Art

[0002] A phase-locked loop (PLL) is a negative feedback control system that uses a voltage-tuned voltage-controlled oscillator (VCO) generated by phase synchronization to generate a target frequency. A fractional PLL can output a signal frequency that is a fractional multiple of a reference signal frequency. The fractional multiple of the frequency division ratio corresponding to the fractional PLL usually refers to the instantaneous frequency division ratio of the frequency divider with the average frequency division ratio over multiple cycles. In other words, the frequency division ratio of the fractional PLL refers to the average value of the integer frequency division ratio over multiple cycles. In the transient state, due to the phase error between the divider output signal and the reference signal, the VCO will generate spurious noise (i.e., fractional spurs), which will cause the fractional PLL to malfunction.

[0003] However, the existing technical solutions are not very effective in suppressing fractional spurious signals in fractional phase-locked loops and need to be improved. Summary of the Invention

[0004] The present invention provides a clock correction method and device to improve the effect of suppressing fractional spurious signals of a fractional phase-locked loop, thereby improving the stability of the fractional phase-locked loop.

[0005] In a first aspect, an embodiment of the present application provides a method for implementing a phase-locked loop, comprising: obtaining an analog signal, and determining a first sequence based on the analog signal and a target frequency division coefficient, the first sequence being used to indicate a first frequency division coefficient and a second frequency division coefficient corresponding to the analog signal. Based on the first sequence, determining the number of times the frequency division coefficient is the first frequency division coefficient and the number of times the frequency division coefficient is the second frequency division coefficient in a phase detection period, where the phase detection period is M times the frequency division period, where M is an integer greater than or equal to 2. Obtaining a correction clock signal based on the number of times the first frequency division coefficient and the number of times the second frequency division coefficient occur. Sending the correction clock signal.

[0006] Using this method, the correction clock signal in this application is obtained based on the number of first and second frequency division coefficients within a phase detection cycle, and the number of first and second frequency division coefficients is used to perform spectrum analysis on the analog signal. Therefore, using this correction clock signal to perform clock correction on the phase detector of a fractional phase-locked loop can avoid the fractional spurious problem of the fractional phase-locked loop, thereby improving the stability of the fractional phase-locked loop.

[0007] In one possible design, the analog signal is processed by a delta-sigma modulation circuit to obtain a binary stream corresponding to the analog signal. The first and second frequency division coefficients are determined based on the target frequency division coefficient. The first sequence is determined based on the binary stream, the first and second frequency division coefficients.

[0008] In one possible design, the target frequency division coefficient, the first frequency division coefficient, and the second frequency division coefficient satisfy:

[0009] NF=[a*N+b*(N+1)] / M.

[0010] M=a+b;

[0011] Among them, the NF represents the target frequency division coefficient, NF represents a decimal, the N represents the first frequency division coefficient, the N+1 represents the second frequency division coefficient, the a represents the number of times the frequency division coefficient is the first frequency division coefficient in the phase detection period, the b represents the number of times the frequency division coefficient is the second frequency division coefficient in the phase detection period, and the N, F, a, and b are all positive integers.

[0012] In one possible design, a correction voltage is determined based on the number of the first frequency division coefficient and the number of the second frequency division coefficient, and the correction voltage is input into a second oscillator to obtain the correction clock signal, and the second oscillator is used to output the correction clock signal.

[0013] In one possible design, a first voltage accumulation circuit performs p voltage accumulations according to the first frequency division coefficient a to obtain a first voltage. The first voltage accumulation circuit corresponds to the first frequency division coefficient. A second voltage accumulation circuit performs q voltage accumulations according to the second frequency division coefficient b to obtain a second voltage. The second voltage accumulation circuit corresponds to the second frequency division coefficient. The correction voltage is determined based on the first and second voltages.

[0014] In a second aspect, an embodiment of the present application further provides a clock correction device, comprising a communication module and a processing module.

[0015] A communication module is used to obtain analog signals.

[0016] The processing module is used to determine a first sequence according to the analog signal and the target frequency division coefficient, where the first sequence is used to indicate the first frequency division coefficient and the second frequency division coefficient corresponding to the analog signal.

[0017] The processing module is further configured to determine, based on the first sequence, the number of times the frequency division coefficient is the first frequency division coefficient and the number of times the frequency division coefficient is the second frequency division coefficient in a phase detection period, wherein the phase detection period is M times the frequency division period, where M is an integer greater than or equal to 2.

[0018] The processing module is further configured to obtain a correction clock signal according to the number of the first frequency division coefficient and the number of the second frequency division coefficient.

[0019] The communication module is also used to send the correction clock signal.

[0020] In one possible design, the processing module is specifically configured to: process the analog signal using a delta-sigma modulation circuit to obtain a binary stream corresponding to the analog signal; determine the first and second frequency division coefficients based on the target frequency division coefficient; and determine the first sequence based on the binary stream, the first and second frequency division coefficients.

[0021] In one possible design, the target frequency division coefficient, the first frequency division coefficient, and the second frequency division coefficient satisfy:

[0022] NF=[a*N+b*(N+1)] / M.

[0023] M=a+b;

[0024] Among them, the NF represents the target frequency division coefficient, NF represents a decimal, the N represents the first frequency division coefficient, the N+1 represents the second frequency division coefficient, the a represents the number of times the frequency division coefficient is the first frequency division coefficient in the phase detection period, the b represents the number of times the frequency division coefficient is the second frequency division coefficient in the phase detection period, and the N, F, a, and b are all positive integers.

[0025] In one possible design, the processing module is specifically configured to: determine a correction voltage based on the number of the first frequency division coefficient and the number of the second frequency division coefficient, input the correction voltage into a second oscillator to obtain the correction clock signal, and the second oscillator is configured to output the correction clock signal.

[0026] In one possible design, the processing module is specifically configured to: perform voltage accumulation p times using a first voltage accumulation circuit according to the number a of the first frequency division coefficient to obtain a first voltage, wherein the first voltage accumulation circuit corresponds to the first frequency division coefficient; perform voltage accumulation q times using a second voltage accumulation circuit according to the number b of the second frequency division coefficient to obtain a second voltage, wherein the second voltage accumulation circuit corresponds to the second frequency division coefficient; and determine the correction voltage based on the first voltage and the second voltage.

[0027] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a processor, and the processor is used to implement the method of the first aspect and any one of its designs when executing a computer program stored in a memory.

[0028] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium storing a computer program, which implements the method of the first aspect and any one of its designs when executed by a processor.

[0029] The technical effects brought about by the second to fourth aspects and any one of their designs can be referred to the technical effects brought about by the corresponding designs in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0031] Figure 1 A schematic diagram of the structure of a phase-locked loop device provided in an embodiment of the present application;

[0032] Figure 2 A flowchart of a clock correction method provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of the structure of another phase-locked loop device provided in an embodiment of the present application;

[0034] Figure 4a A schematic diagram of the structure of another phase-locked loop device provided in an embodiment of the present application;

[0035] Figure 4b A circuit diagram provided in an embodiment of the present application;

[0036] Figure 5 A schematic structural diagram of a clock correction device provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] To make the purpose, technical solutions, and advantages of this application more clear, the following optional detailed description of this application will be given in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0039] The following is a detailed introduction to the fractional phase-locked loop's small lock spurs in combination with the prior art.

[0040] The fractional division ratio of a fractional phase-locked loop is the average of the division ratios over multiple cycles of the frequency divider. For example, if the required division ratio is 100.25, three divisions with a factor of 100 and one with a factor of 101 are required in four division cycles, resulting in an average division ratio of (100*3+101*1) / 4=100.25.

[0041] This frequency division method offers high frequency resolution and a wide output frequency band, making it widely used in various frequency synthesizers. However, it cannot achieve a divided clock with the same duty cycle throughout each division cycle. This causes the phase-locked loop to periodically exhibit different phase-locked cycles, leading to periodic fractional pump current in the voltage-controlled oscillator's charge pump. This fractional pump current causes spurious noise at integer multiples of the phase-locked frequency, known as fractional spurs, to appear in the frequency spectrum. These spurs can significantly impact fractional phase-locked loops (PLLs), causing them to malfunction.

[0042] The existing technology solution is not very effective in suppressing the fractional spurious of the fractional phase-locked loop and needs to be improved.

[0043] In order to solve the above-mentioned defects, the present application provides a clock correction method and device to improve the effect of suppressing fractional spurious of a fractional phase-locked loop, thereby improving the stability of the fractional phase-locked loop.

[0044] In the present application, the method employed includes: a clock correction device can determine a first sequence based on an acquired analog signal and a target frequency division coefficient. The first sequence can be used to indicate the first and second frequency division coefficients corresponding to the analog signal. The clock correction device can determine, based on the first sequence, the number of times the frequency division coefficient is the first and second frequency division coefficients in a phase detection period, and obtain a corrected clock signal based on the number of times the first and second frequency division coefficients occur. The phase detection period is M times the frequency division period.

[0045] It is understood that the correction clock signal in this application is obtained based on the number of first and second frequency division coefficients within a phase detection cycle, and the number of first and second frequency division coefficients is used to perform spectrum analysis on the analog signal. Therefore, using this correction clock signal to perform clock correction on the phase detector of a fractional phase-locked loop can avoid the fractional spurious problem of the fractional phase-locked loop, thereby improving the stability of the fractional phase-locked loop.

[0046] In addition, the clock correction device may be included in a phase-locked loop system for executing the method shown in this application, or may be a processing device in the phase-locked loop system for executing the method shown in this application, such as a processor or processing module, etc., which is not specifically limited in this application.

[0047] For example, the clock correction device can be a device or apparatus in a phase-locked loop device. Alternatively, the clock correction device can be considered as a device independent of the phase-locked loop device, or an apparatus in an independent device. In this case, the clock correction device and the phase-locked loop device can be connected via a wired interface and / or a wireless interface. For example, Figure 1 A schematic diagram of the structure of a phase-locked loop device provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the clock correction device and the phase-locked loop device are independent devices, and are connected to each other via a communication module, wherein the communication module includes wired communication and wireless communication.

[0048] Figure 2 This is a flow chart of a clock correction method provided by an embodiment of the present invention. Taking a clock correction device as an example, the process may include the following steps:

[0049] S101: A clock correction device obtains an analog signal, where the analog signal may be an output signal of an oscillator.

[0050] As an example, the analog signal may be an analog signal output by a first oscillator, wherein the first oscillator may be an oscillator in a phase-locked loop device, and the first oscillator may be, for example, a voltage-controlled oscillator in the phase-locked loop device. Figure 3 A schematic diagram of the structure of a phase-locked loop device provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the voltage-controlled oscillator can be represented as a first oscillator. The clock correction device can be connected to the first oscillator via a wired interface and / or a wireless interface. Accordingly, the clock correction device can obtain the analog signal output by the first oscillator via the wired interface and / or the wireless interface.

[0051] As another example, the first oscillator may also be an oscillator connected to a phase-locked loop device, and the output signal of the first oscillator may be used to indicate the output signal of the oscillator of the phase-locked loop device. In this case, the first oscillator may be considered to be a device independent of the phase-locked loop device, or a device in an independent device. The first oscillator and the phase-locked loop device may be connected via a wired interface and / or a wireless interface. For example, the first oscillator may be a device in a clock correction device. In this case, the clock correction device may obtain an analog signal through the first oscillator. Alternatively, the first oscillator may be a device independent of the phase-locked loop device and the clock correction device, or a device in an independent device, and this application does not make any specific restrictions.

[0052] S102: The clock correction device determines a first sequence based on the analog signal and the target frequency division coefficient. The first sequence is used to indicate the first frequency division coefficient and the second frequency division coefficient corresponding to the analog signal.

[0053] As an example, the target frequency division coefficient can be set according to business needs. The target frequency division coefficient can be a decimal or an integer. In this application, the target frequency division coefficient is a decimal as an example, and the target frequency division coefficient can be expressed as NF. Wherein, N is the integer part of the decimal frequency division coefficient, F is the decimal part of the decimal frequency division coefficient, and both N and F are positive integers.

[0054] Optionally, the clock correction device can determine the first frequency division coefficient and the second frequency division coefficient based on the target frequency division coefficient. The first frequency division coefficient can be the maximum integer less than the target frequency division coefficient, and the second frequency division coefficient can be the minimum integer greater than the target frequency division coefficient. Exemplarily, the target frequency division coefficient can be expressed as NF, then the first frequency division coefficient can be expressed as N, and the second frequency division coefficient can be expressed as N+1. In a phase detection cycle, the number of times the frequency division coefficient of the phase-locked loop is the first frequency division coefficient can be expressed as a, and the number of times the frequency division coefficient of the phase-locked loop is the second frequency division coefficient can be expressed as b, then the target frequency division coefficient, the first frequency division coefficient and the second frequency division coefficient satisfy:

[0055] NF=[a*N+b*(N+1)] / M;

[0056] M=a+b;

[0057] Wherein, N, F, a, and b are all positive integers.

[0058] For example, the target frequency division coefficient is 100.25 (i.e., N=100, F=25), the first frequency division coefficient is 100, the second frequency division coefficient is 101, and the phase detection period is 4 times the frequency division period (i.e., M=4). Then, in one phase detection period, the frequency division coefficient of the phase-locked loop is the first frequency division coefficient 3 times, and the frequency division coefficient of the phase-locked loop is the second frequency division coefficient 1 time.

[0059] In one or more embodiments, after acquiring the analog signal, the clock correction device may process the analog signal through a delta-sigma modulation circuit to obtain a binary stream corresponding to the analog signal. The binary stream corresponding to the analog signal may be used to indicate that the analog signal includes two different signals. For example, the binary stream corresponding to the analog signal may be represented as "101010," where "1" may represent one signal in the analog signal and "0" may represent another signal in the analog signal. It is understandable that the order and number of occurrences of the two different signals in the analog signal may be determined based on the binary stream corresponding to the analog signal.

[0060] In one or more embodiments, the clock correction device can determine a first sequence based on the binary stream corresponding to the analog signal, the first frequency division coefficient, and the second frequency division coefficient. The first sequence can be used to indicate the first frequency division coefficient and the second frequency division coefficient corresponding to the analog signal. Taking the above case as an example, the first frequency division coefficient is 100, the second frequency division coefficient is 101, the target frequency division coefficient is 100.25, and the binary stream corresponding to the analog signal of the target frequency division coefficient is "0100". "0" can represent a signal whose frequency division coefficient in the analog signal is the first frequency division coefficient, and "1" can represent a signal whose frequency division coefficient in the analog signal is the second frequency division coefficient. The first sequence can be expressed as {100, 101, 100, 100}; or, the first sequence can be expressed as {A, B, A, A}, where A is used to indicate that the frequency division coefficient is 100, and B is used to indicate that the frequency division coefficient is 101. In addition, the first sequence can also be expressed as the binary stream of the analog signal, that is, the first sequence is the same as the binary stream corresponding to the analog signal.

[0061] S103: The clock correction device determines the number of times the frequency division coefficient is the first frequency division coefficient and the number of times the frequency division coefficient is the second frequency division coefficient in a phase detection period according to the first sequence, wherein the phase detection period is M times the frequency division period, and M is an integer greater than or equal to 2.

[0062] As an example, the clock correction device can determine the number of first frequency division coefficients and the number of second frequency division coefficients in a phase detection period based on the characters or character strings used to represent the first frequency division number in the first sequence and the characters or character strings used to represent the second frequency division coefficient. Taking the above embodiment as an example, the first sequence corresponding to the analog signal of multiple phase detection periods can be represented by {100, 101, 100, 100, ..., 100, 101, 100, 100}, where the phase detection period is 4 times the frequency division period. The clock correction device can obtain the frequency division coefficient of any phase detection period from the first sequence. For example, the frequency division coefficient of a phase detection period can be represented by {100, 101, 100, 100} or {101, 100, 100, 100}.

[0063] Furthermore, the clock correction device can determine the number of the first frequency division coefficient and the number of the second frequency division coefficient based on the frequency division coefficient of a phase detection cycle. For example, when the frequency division coefficient of a phase detection cycle in the first sequence is {100, 101, 100, 100}, where "100" represents the first frequency division coefficient and "101" represents the second frequency division coefficient, the number of the first frequency division coefficient is 3, and the number of the second frequency division coefficient is 1.

[0064] S104: The clock correction device obtains a correction clock signal according to the number of the first frequency division coefficient and the number of the second frequency division coefficient.

[0065] In one or more embodiments, the clock correction device can obtain a correction voltage based on the number of the first frequency division coefficient and the number of the second frequency division coefficient. Exemplarily, the voltage values ​​corresponding to the first frequency division coefficient and the second frequency division coefficient can be different. The clock correction device can obtain a correction voltage based on the number of the first frequency division coefficient and the number of the second frequency division coefficient, as well as the voltage value corresponding to the first frequency division coefficient and the voltage value corresponding to the second frequency division coefficient. For example, the correction voltage can be expressed as V, the voltage value corresponding to the first frequency division coefficient can be expressed as v1, the voltage value corresponding to the second frequency division coefficient can be expressed as v2, the number of the first frequency division coefficient can be expressed as a, and the number of the second frequency division coefficient can be expressed as b, then the correction voltage, the number of the first frequency division coefficient, and the number of the second frequency division coefficient satisfy:

[0066] V=a*v1+b*v2.

[0067] As an example, the clock correction device can perform p voltage accumulations through a first voltage accumulation circuit according to the number of the first frequency division coefficient to obtain a first voltage. The first voltage accumulation circuit corresponds to the first frequency division coefficient. Similarly, the clock correction device can perform q voltage accumulations through a second voltage accumulation circuit according to the number of the second frequency division coefficient to obtain a second voltage. The second voltage accumulation circuit corresponds to the second frequency division coefficient. Here, p is associated with the number of the first frequency division coefficient, and q is associated with the number of the second frequency division coefficient. For example, p is linearly associated with the number of the first frequency division coefficient, and q is linearly associated with the number of the second frequency division coefficient.

[0068] Figure 4a This is a schematic diagram of the structure of a clock correction device provided in an embodiment of the present application. Figure 4a As shown, circuit 1 can be represented as a first voltage accumulation circuit, and circuit 2 can be represented as a second voltage accumulation circuit.

[0069] Alternatively, the clock correction device may input the first sequence into a first voltage accumulation circuit and a second voltage accumulation circuit. Accordingly, the first voltage accumulation circuit may determine the first voltage based on the character or string indicating the first frequency division coefficient in the first sequence. Similarly, the second voltage accumulation circuit may determine the second voltage based on the character or string indicating the second frequency division coefficient in the first sequence.

[0070] For example, Figure 4b A circuit diagram provided in an embodiment of the present application. Figure 4b As shown, the clock correction device can input a first sequence into circuits 1 and 2. The voltage generation module of circuit 1 can generate a corresponding voltage based on the characters or strings of the first frequency division coefficient in the first sequence according to a preset rule. Similarly, circuit 2 can generate a corresponding voltage based on the characters or strings of the second frequency division coefficient in the first sequence.

[0071] It is understood that in this application, the first voltage accumulation circuit and the second voltage accumulation circuit can be the same circuit, or the first voltage accumulation circuit and the second voltage accumulation circuit can be different circuits. The first voltage accumulation circuit and / or the second voltage accumulation circuit can be devices in a clock correction device. Alternatively, the first voltage accumulation circuit and / or the second voltage accumulation circuit can also be considered to be devices independent of the clock correction device, or devices in independent devices, and this application does not make specific limitations.

[0072] As an example, the clock correction device may determine the correction voltage based on the first voltage and the second voltage. For example, the clock correction device may add the first voltage and the second voltage to determine the correction voltage. Alternatively, the clock correction device may use the first voltage and the second voltage as independent variables in a preset formula to obtain the correction voltage according to the preset formula.

[0073] In one or more embodiments, the clock correction device may input the correction voltage into the second oscillator to obtain the correction clock signal. The second oscillator may be used to output the correction clock signal. The second oscillator may be a device in the clock correction device. For example, Figure 4b As shown, the additional voltage-controlled oscillator can be represented as a second oscillator. Circuit 1 can input a corresponding voltage to the additional voltage-controlled oscillator through the charge-to-voltage module according to a preset period. Similarly, circuit 2 can also input a corresponding voltage to the additional voltage-controlled oscillator. The additional voltage-controlled oscillator can generate a correction clock signal based on the input voltage.

[0074] S105: The clock correction device sends a correction clock signal.

[0075] In one or more embodiments, after obtaining the corrected clock signal, the clock correction device may send the corrected clock signal to the target device (e.g., phase detector), thereby suppressing the fractional spurious effect of the fractional phase-locked loop and improving the stability of the fractional phase-locked loop. For example, Figure 4a As shown, an additional voltage-controlled oscillator can output a correction clock signal to the phase detector.

[0076] In one or more embodiments, the clock correction device may send the correction clock signal according to the phase detection period of the phase-locked loop device. That is, the clock correction device may send the correction clock signal to the phase detector after one or more phase detection periods.

[0077] It is understood that when the clock correction device is a device or apparatus in a phase-locked loop device, the clock correction device can send the corrected clock signal to the target device (e.g., a phase detector) via an internal connection line. When the clock correction device is a device independent of the phase-locked loop device, or an apparatus in an independent device, the clock correction device can send the corrected clock signal to the target device (e.g., a phase detector) via a wired interface and / or a wireless interface.

[0078] Based on the above content and the same concept, the present application provides a clock correction device. Figure 5 As shown, the device includes a communication module 501 and a processing module 502 .

[0079] The communication module 501 is used to obtain an analog signal.

[0080] The processing module 502 is configured to determine a first sequence according to the analog signal and a target frequency division coefficient, where the first sequence is used to indicate a first frequency division coefficient and a second frequency division coefficient corresponding to the analog signal.

[0081] The processing module 502 is further configured to determine, based on the first sequence, the number of times the frequency division coefficient is the first frequency division coefficient and the number of times the frequency division coefficient is the second frequency division coefficient in a phase detection period, wherein the phase detection period is M times the frequency division period, where M is an integer greater than or equal to 2.

[0082] The processing module 502 is further configured to obtain a correction clock signal according to the number of the first frequency division coefficient and the number of the second frequency division coefficient.

[0083] The communication module 501 is further configured to send the correction clock signal.

[0084] In one possible design, the processing module 502 is specifically configured to: process the analog signal using a delta-sigma modulation circuit to obtain a binary stream corresponding to the analog signal; determine the first and second frequency division coefficients based on the target frequency division coefficients; and determine the first sequence based on the binary stream, the first and second frequency division coefficients.

[0085] In one possible design, the target frequency division coefficient, the first frequency division coefficient, and the second frequency division coefficient satisfy:

[0086] NF=[a*N+b*(N+1)] / M.

[0087] M=a+b;

[0088] Among them, the NF represents the target frequency division coefficient, the N represents the first frequency division coefficient, the N+1 represents the second frequency division coefficient, the a represents the number of times the frequency division coefficient is the first frequency division coefficient in the phase detection period, and the b represents the number of times the frequency division coefficient is the second frequency division coefficient in the phase detection period. N, F, a, and b are all positive integers.

[0089] In one possible design, the processing module 502 is specifically configured to: determine a correction voltage based on the number of the first frequency division coefficient and the number of the second frequency division coefficient, input the correction voltage into a second oscillator to obtain the correction clock signal, and the second oscillator is configured to output the correction clock signal.

[0090] In one possible design, the processing module 502 is specifically configured to: perform p voltage accumulations using a first voltage accumulation circuit according to the number a of the first frequency division coefficient to obtain a first voltage, wherein the first voltage accumulation circuit corresponds to the first frequency division coefficient; perform q voltage accumulations using a second voltage accumulation circuit according to the number b of the second frequency division coefficient to obtain a second voltage, wherein the second voltage accumulation circuit corresponds to the second frequency division coefficient; and determine the correction voltage based on the first voltage and the second voltage.

[0091] Based on the same inventive concept, an embodiment of the present application provides an electronic device that can implement the functions of the device discussed above. Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown.

[0092] The electronic device in the embodiment of the present application may include a processor 601. The processor 601 is the control center of the device, and can use various interfaces and lines to connect the various parts of the device, by running or executing instructions stored in the memory 603 and calling data stored in the memory 603. Optionally, the processor 601 may include one or more processing units. The processor 601 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system and application programs, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 601. In some embodiments, the processor 601 and the memory 603 may be implemented on the same chip. In some embodiments, they may also be implemented separately on independent chips.

[0093] The processor 601 can be a general-purpose processor, such as a central processing unit (CPU), a digital phase-locked loop implementer, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or any conventional processor. The method steps disclosed in conjunction with the embodiments of the present application can be directly executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0094] In the embodiment of the present application, the memory 603 stores instructions that can be executed by at least one processor 601. The at least one processor 601 can be used to execute the method steps disclosed in the embodiment of the present application by executing the instructions stored in the memory 603.

[0095] Memory 603 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. Memory 603 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disc, etc. Memory 603 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 603 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0096] In the embodiment of the present application, the apparatus may further include a communication interface 602 , through which the electronic device may transmit data.

[0097] Optional, can be Figure 6 The processor 601 (or the processor 601 and the communication interface 602) shown implements Figure 5The processing module 502 and / or the communication module 501 shown, that is, the actions of the processing module 502 and / or the communication module 501 can be executed by the processor 601 (or the processor 601 and the communication interface 602).

[0098] Based on the same inventive concept, the embodiment of the present application further provides a computer-readable storage medium, which may store instructions, which, when executed on a computer, enable the computer to execute the operation steps provided in the above method embodiment. The computer-readable storage medium may be Figure 6 The memory 603 is shown.

[0099] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0100] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0101] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby executing the program on the computer or other programmable device.

Claims

1. A clock calibration method, characterized in that: The method comprises: Acquire an analog signal, where the analog signal is an analog signal output by the first oscillator; determining a first sequence according to the analog signal and a target frequency division coefficient, wherein the first sequence is used to indicate a first frequency division coefficient and a second frequency division coefficient corresponding to the analog signal; Determining, according to the first sequence, the number of times the frequency division coefficient is the first frequency division coefficient and the number of times the frequency division coefficient is the second frequency division coefficient in a phase detection period, wherein the phase detection period is M times the frequency division period, where M is an integer greater than or equal to 2; Obtaining a correction clock signal according to the number of the first frequency division coefficient and the number of the second frequency division coefficient; sending the correction clock signal; The obtaining of the correction clock signal according to the number of the first frequency division coefficient and the number of the second frequency division coefficient includes: performing voltage accumulation p times according to the number a of the first frequency division coefficient through a first voltage accumulation circuit to obtain a first voltage, wherein the first voltage accumulation circuit corresponds to the first frequency division coefficient; performing voltage accumulation q times by a second voltage accumulation circuit according to the number b of the second frequency division coefficient to obtain a second voltage, wherein the second voltage accumulation circuit corresponds to the second frequency division coefficient; determining a correction voltage according to the first voltage and the second voltage; The correction voltage is input into a second oscillator to obtain the correction clock signal, and the second oscillator is used to output the correction clock signal.

2. The method according to claim 1, wherein The determining of the first sequence according to the analog signal and the target frequency division coefficient includes: Processing the analog signal through a delta-sigma modulation circuit to obtain a binary stream corresponding to the analog signal; Determining the first frequency division coefficient and the second frequency division coefficient according to the target frequency division coefficient; The first sequence is determined according to the binary stream, the first frequency division coefficient, and the second frequency division coefficient.

3. The method according to claim 2, wherein The target frequency division coefficient, the first frequency division coefficient and the second frequency division coefficient satisfy: NF=[a*N+b*(N+1)] / M; M=a+b; Among them, the NF represents the target frequency division coefficient, the NF is represented as a decimal, the N represents the first frequency division coefficient, the N+1 represents the second frequency division coefficient, the a represents the number of times the frequency division coefficient is the first frequency division coefficient in the phase detection period, the b represents the number of times the frequency division coefficient is the second frequency division coefficient in the phase detection period, and the N, F, a, and b are all positive integers.

4. A clock correction device, characterized in that: The device comprises: A communication module, configured to obtain an analog signal, wherein the analog signal is an analog signal output by the first oscillator; a processing module, configured to determine a first sequence according to the analog signal and a target frequency division coefficient, wherein the first sequence is used to indicate a first frequency division coefficient and a second frequency division coefficient corresponding to the analog signal; The processing module is further configured to determine, based on the first sequence, the number of times the frequency division coefficient is the first frequency division coefficient and the number of times the frequency division coefficient is the second frequency division coefficient in a phase detection period, wherein the phase detection period is M times the frequency division period, where M is an integer greater than or equal to 2; The processing module is further configured to obtain a correction clock signal according to the number of the first frequency division coefficient and the number of the second frequency division coefficient; The communication module is further configured to send the correction clock signal; The correction clock signal is obtained according to the number of the first frequency division coefficient and the number of the second frequency division coefficient, and the processing module is specifically used to: performing voltage accumulation p times according to the number a of the first frequency division coefficient through a first voltage accumulation circuit to obtain a first voltage, wherein the first voltage accumulation circuit corresponds to the first frequency division coefficient; performing voltage accumulation q times by a second voltage accumulation circuit according to the number b of the second frequency division coefficient to obtain a second voltage, wherein the second voltage accumulation circuit corresponds to the second frequency division coefficient; determining a correction voltage according to the first voltage and the second voltage; The correction voltage is input into a second oscillator to obtain the correction clock signal, and the second oscillator is used to output the correction clock signal.

5. The device according to claim 4, characterized in that The first sequence is determined according to the analog signal and the target frequency division coefficient, and the processing module is specifically configured to: Processing the analog signal through a delta-sigma modulation circuit to obtain a binary stream corresponding to the analog signal; Determining the first frequency division coefficient and the second frequency division coefficient according to the target frequency division coefficient; The first sequence is determined according to the binary stream, the first frequency division coefficient, and the second frequency division coefficient.

6. The device according to claim 5, characterized in that The target frequency division coefficient, the first frequency division coefficient and the second frequency division coefficient satisfy: NF=[a*N+b*(N+1)] / M; M=a+b; Among them, the NF represents the target frequency division coefficient, the NF is represented as a decimal, the N represents the first frequency division coefficient, the N+1 represents the second frequency division coefficient, the a represents the number of times the frequency division coefficient is the first frequency division coefficient in the phase detection period, the b represents the number of times the frequency division coefficient is the second frequency division coefficient in the phase detection period, and the N, F, a, and b are all positive integers.

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