A method for branch predictor content isolation based on randomized indexing for fine-grained processor chip and electronic device

Abstract

The application relates to a fine-grained processor chip branch predictor content isolation method based on randomization index and an electronic device. It comprises a unit program block random key configuration method and a branch predictor content locking mechanism, unit program block random key configuration is realized through process key distribution and block key instruction generation, and branch predictor content locking is realized through entry locking of a branch jump target address table and a branch mode history table. Meanwhile, process key distribution is realized through random numbers of software or hardware, process keys are generated, block key instructions are generated through source code analysis and executable file analysis, and program blocks with security risks are identified; block keys are generated based on the calculation of a cryptography algorithm and program block context information through a code segment or an instruction for generating a block key. The application also has the advantages of more flexible key management, convenient content locking mechanism, more effective randomization index, great difficulty in attack training and safe and reliable branch prediction.

Description

Technical Field

[0001] This invention relates to the field of processor architecture, and in particular to a method and electronic device for content isolation of a fine-grained processor chip branch predictor based on randomized indexing. Background Technology

[0002] Chinese patent publication CN111638913A proposes a security enhancement method and electronic device for processor chip branch predictors based on randomized indexes. To increase the security of branch predictors in processor architectures, this method divides different programs into different security domains, assigns a key to each security domain, and applies the key to the original index of the branch predictor to generate a new index. This changes the fixed index mapping relationship of traditional branch predictors to randomized indexes. In this way, although it increases the difficulty for attackers to maliciously train across threads or privilege levels and avoids the risk of the system initiating erroneous branch predictions, attackers can still find the equivalent branch instruction set for malicious training through brute-force cracking. Summary of the Invention

[0003] The purpose of this invention is to provide a fine-grained processor chip branch predictor content isolation method based on randomized indexing, which can effectively isolate the branch predictor content and reliably prevent brute-force attacks and malicious training against the branch predictor.

[0004] Design a fine-grained processor chip branch predictor content isolation method based on randomized indexing, including a unit program block random key configuration method and a branch predictor content locking mechanism. The unit program block random key configuration method includes process key allocation and block key instruction generation; the branch predictor content locking mechanism includes locking entries of the branch jump target address table and the branch mode history table.

[0005] During process key allocation, when a new process is created, a key, known as the process key, is assigned to it. This key can be generated using various existing software or hardware random number generation methods. It can be managed by the operating system or virtual machine manager, similar to the ARM PA mechanism, or by a trusted execution environment such as TrustZone, or by the processor hardware. The processor hardware requires an additional register to store the process key. This register cannot be read by software; the process key is written to this register when the program runs. During block key instruction generation, source code and executable file analysis are used to identify program blocks with security risks. Upon entering a program block, a code snippet or instruction to generate the block key is inserted. The instruction for generating the block key can be similar to the PAC* / AUT* instructions of the ARM PA mechanism, or similar to the Intel AES-NI instructions. The difference is that the result of the block key generation instruction is stored in a software-unreadable register. When the security domain program block is executed, the code segment or instruction for generating the block key calculates and generates the block key based on the cryptographic algorithm and the context information of the program block. The context information of the program block includes, but is not limited to, the current process ID or thread ID, the virtual address of the program block, the program block number, and the current software stack position. The generated block key is stored in a software-unreadable hardware register for subsequent branch predictor index randomization. Multiple program blocks can share the same block key. Whether multiple program blocks share the same block key can be determined by analyzing the program execution characteristics.

[0006] When locking entries in the branch jump target address table and branch pattern history table, there are many types of branch predictors, and the core modules of various branch predictors are mainly the branch jump target address table and the branch pattern history table. The branch predictor content locking mechanism verifies the branch instructions to prevent attackers from maliciously training and modifying the entries in the branch jump target address table and branch pattern history table corresponding to the attacked branch instructions. In order to lock the contents of the aforementioned branch instructions in the branch jump target address table and branch pattern history table, this invention adds a branch entry status table and a locked entry record table. When the number of entries and the index of the branch jump target address table and the branch pattern history table are the same, or when the depth or number of entries of the branch jump target address table and the branch pattern history table are different, independent branch entry status tables and locked entry record tables can be assigned to them respectively; the branch entry status table is a 1-bit vector, and its index is the same as that of the branch jump target address table and the branch pattern history table. Each bit indicates whether the corresponding entry in the branch jump target address table and the branch pattern history table is locked.

[0007] When entries in the branch jump target address table and the branch mode history table are locked, the locked entry record table consists of three parts: the transient execution protected branch instruction label, the locked entry vector, and the entry status. The former is used to verify the branch instruction that can update or delete the locked entry content. The number of bits in the locked entry vector is equal to the number of entries in the branch jump target address table and the branch mode history table, and is used to indicate which entries correspond to the transient execution protected branch instruction. The entry status indicates whether the entry in the locked entry record table has been used.

[0008] When the entries in the branch jump target address table and the branch mode history table are locked, when a branch instruction requiring transient execution protection is executed for the first time, there is no corresponding entry in the branch jump target address table and the branch mode history table. The processor hardware calculates an information authorization code for the instruction based on the block key of the block it belongs to and its context information. The context information for the branch instruction requiring transient execution protection includes, but is not limited to, the process number, the code block number, and the branch instruction address.

[0009] When entries in the branch jump target address table and branch mode history table are locked, after the branch instruction is executed, its execution result needs to be updated in the branch jump target address table and branch mode history table. The original index of the branch jump target address table is usually generated from a portion of the branch instruction address, and the length of the selected bit depends on the size of the branch jump target address table. The original index of the branch mode history table is usually generated from a portion of the branch instruction address and global history information through a hash algorithm, and the length of the selected bit depends on the size of the branch mode history table. The code block key is XORed with the original index of the branch jump target address table and the original index of the branch mode history table to obtain a new index value, which is the position of the entry in the branch jump target address table and the branch mode history table corresponding to the aforementioned branch instruction that needs transient execution protection. The processor hardware updates the target address of the aforementioned branch instruction and whether the branch jump is performed in the branch jump target address table and the branch mode history table according to the new index value.

[0010] When entries in the branch jump target address table and branch mode history table are locked, after the branch instruction execution result is updated in the branch jump target address table and branch mode history table, the corresponding bit in the branch entry status table is set to 1 according to the new index value, indicating that the corresponding bit in the branch jump target address table and branch mode history table has been allocated to the branch instruction that needs transient execution protection and is in a locked state; at the same time, the processor hardware allocates an entry for this instruction in the locked entry record table, calculates an information check code for the instruction based on the branch instruction context information, stores it in the allocated entry branch instruction tag field, and sets the corresponding bit in the locked entry vector and the corresponding bit in the allocated entry status to 1 according to the new index value.

[0011] When the entries in the branch jump target address table and the branch mode history table are locked, when the branch instruction that needs transient execution protection is executed again, its corresponding code block key is XORed with the original index of the branch jump target address table and the original index of the branch mode history table respectively to obtain a new index value. Based on the new index, the branch jump target address table and the branch mode history table are searched to realize the prediction of the branch target address and the branch direction.

[0012] When entries in the branch jump target address table and branch mode history table are locked, when the branch instruction requiring transient execution protection is executed again, the processor hardware calculates an information check code based on the aforementioned branch instruction context information and compares it with the tag stored in the locked entry record table. If they match, the result can be updated to the locked entries in the branch jump target address table and branch mode history table. Because the original index of the branch jump target address table and the original index of the branch mode history table can also be generated by hashing a portion of the branch instruction address and global history information, the new index when the branch instruction is executed again may be different from the previous index. In this case, the execution result of the aforementioned branch instruction needs to be updated to other entries in the branch jump target address table and branch mode history table. At this time, based on the new index value, the corresponding bit in the branch entry status table needs to be set to 1, and the corresponding bit in the locking entry vector of the corresponding entry of the branch instruction in the locked entry record table needs to be set to 1.

[0013] When entries in the branch jump target address table and branch mode history table are locked, if the branch instruction requiring transient execution protection will not be executed subsequently, an unlocking instruction is executed. This instruction uses the virtual address of the transient execution protected branch instruction as a parameter and calculates an information checksum based on the context information of the branch instruction. When the information checksum matches the tag of an entry in the locked entry record table, the corresponding entry in the branch jump target address table and branch mode history table in the locked entry vector field of that entry is unlocked, i.e., the corresponding bit in the branch entry status table is set to 0. Finally, the status field of the above-mentioned locked entry record table entry is set to 0, so that the entry can be allocated to other branch instructions requiring transient execution protection.

[0014] An electronic device includes a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor being configured to run the computer program to perform the methods described above.

[0015] The beneficial technical effects of this invention are as follows: Since a key can be assigned to a process upon creation, this invention allows the key to be generated using random numbers from various existing software or hardware, and managed by the operating system or virtual machine manager, trusted execution environment, or processor hardware. Furthermore, through source code and executable file analysis, block key generation instructions for program blocks with security risks can be identified. Additionally, block keys can be generated through calculations based on cryptographic algorithms and program block context information using code snippets or instructions that generate block keys. This invention also offers advantages such as more flexible key management, convenient content locking mechanisms, more effective randomized indexing, greater difficulty in training against attacks, and secure and reliable branch prediction. Attached Figure Description

[0016] Figure 1 It is a hierarchical key management diagram; Figure 2 Branch entry status table structure diagram; Figure 3 Locked entry record table structure diagram. Implementation

[0017] A fine-grained processor chip branch predictor content isolation method based on randomized indexing includes a unit-block random key configuration method and a branch predictor content locking mechanism. The unit-block random key configuration method includes process key allocation and block key instruction generation. The branch predictor content locking mechanism includes locking entries in the branch jump target address table and the branch mode history table. The specific steps are as follows:

[0018] 1. During process key allocation, when a new process is created, a key is assigned to the process, i.e. Figure 1 The process key shown can be generated using various existing software or hardware random number generation methods. It can be managed by the operating system or virtual machine manager, like the ARM PA mechanism, or by a trusted execution environment such as TrustZone, or by the processor hardware. The processor hardware needs to add a register to store the process key. This register cannot be read by the software. When the program runs, the process key will be written into this register.

[0019] 2. During block key generation, source code and executable file analysis are used to identify program blocks with security risks. Upon entering a program block, a code snippet or instruction for generating the block key is inserted. The block key generation instruction can be similar to the PAC* / AUT* instructions of the ARM PA mechanism or similar to the Intel AES-NI instructions. The difference is that the result of the block key generation instruction in this invention is stored in a software-unreadable register. When a secure domain program block is executed, the code snippet or instruction for generating the block key calculates and generates the block key based on a cryptographic algorithm and the context information of the program block. The context information of the program block includes, but is not limited to, the current process ID or thread ID, the virtual address of the program block, the program block number, and the current software stack position. The generated block key is stored in a software-unreadable hardware register for subsequent branch predictor index randomization. In implementation, multiple program blocks can share the same block key. Whether multiple program blocks share a block key can be determined by analyzing program execution characteristics.

[0020] 3. The execution branch predictor content locking mechanism mainly involves locking entries in the branch jump target address table and the branch mode history table.

[0021] ① Branch Instruction Verification: The branch predictor content locking mechanism verifies branch instructions to prevent attackers from maliciously modifying the entries in the branch jump target address table and branch pattern history table corresponding to the attacked branch instructions. To lock the contents of the aforementioned branch instructions in the branch jump target address table and branch pattern history table, this invention adds a branch entry status table and a locked entry record table. Assuming that the branch jump target address table and branch pattern history table contain the same number of entries and have the same index, the branch entry status table is a 1-bit vector with the same index as the branch jump target address table and branch pattern history table. Each bit indicates whether the corresponding entry in the branch jump target address table and branch pattern history table is locked.

[0022] ② Locking of Branch Entry Status Table and Allocation of Entry Record Table: When the entries in the branch jump target address table and the branch mode history table are locked, the locked entry record table consists of three parts: transient execution protection branch instruction label, locked entry vector, and the entry status of the table. The former is used to verify the branch instruction that can update or delete the locked entry content. The number of bits in the locked entry vector is equal to the number of entries in the branch jump target address table and the branch mode history table, and is used to indicate which entries correspond to the transient execution protection branch instruction. The entry status indicates whether the entry in the locked entry record table has been used. The number of entries for the branch instruction in the actual implementation of the branch jump target address table and the branch mode history table may be different. Accordingly, independent branch entry status tables and locked entry record tables can be allocated to them respectively.

[0023] ③ Authorization of transient protection branch instructions: When a branch instruction that requires transient execution protection is executed for the first time, there is no corresponding entry in the branch jump target address table and the branch mode history table; the processor hardware calculates an information authorization code for the instruction based on the block key of the block in which it is located and its context information; the context information of the branch instruction that requires transient execution protection includes, but is not limited to, the process number, the code block number, and the branch instruction address.

[0024] ④ Generation of new index values: After the branch instruction is executed, its execution result needs to be updated in the branch jump target address table and the branch mode history table. The original index of the branch jump target address table is usually generated from a portion of the branch instruction address, and the length of the selected bit depends on the size of the branch jump target address table. The original index of the branch mode history table is usually generated from a portion of the branch instruction address and global history information through a hash algorithm, and the length of the selected bit depends on the size of the branch mode history table. The code block key is XORed with the original index of the branch jump target address table and the original index of the branch mode history table to obtain the new index value, which is the position of the entry in the branch jump target address table and the branch mode history table corresponding to the aforementioned branch instruction that needs transient execution protection. The processor hardware updates the target address of the aforementioned branch instruction and whether the branch jumps to the branch jump target address table and the branch mode history table according to the new index value.

[0025] ⑤ Entry Vector Position Locking and Status Position Allocation: After the branch instruction execution result is updated to the branch jump target address table and the branch mode history table, according to the new index value, the corresponding position in the branch entry status table is set to 1, indicating that the corresponding position in the branch jump target address table and the branch mode history table has been allocated to the branch instruction that needs transient execution protection and is in a locked state; at the same time, the processor hardware allocates an entry for this instruction in the locked entry record table, calculates an information check code for this instruction based on the branch instruction context information, and stores it in the allocated entry branch instruction tag field, and at the same time, based on the new index value, sets the corresponding position in the locked entry vector to 1, and sets the corresponding position in the allocated entry status to 1.

[0026] ⑥ Prediction of branch target address and branch direction: When the branch instruction that requires transient execution protection is executed again, its corresponding code block key is XORed with the original index of the branch jump target address table and the original index of the branch mode history table to obtain a new index value. Based on the new index, the branch jump target address table and the branch mode history table are searched to realize the prediction of branch target address and branch direction.

[0027] ⑦ Entry Locking Verification and Alignment: When the branch instruction requiring transient execution protection is executed again, the processor hardware calculates an information check code based on the branch instruction context information and compares it with the tag stored in the locked entry record table. If they match, the result can be updated to the locked entries in the branch jump target address table and the branch mode history table. Since the original index of the branch jump target address table and the original index of the branch mode history table can also be generated by hashing a portion of the branch instruction address and global history information, the new index when the branch instruction is executed again may be different from the previous index. In this case, the execution result of the aforementioned branch instruction needs to be updated to other entries in the branch jump target address table and the branch mode history table. At this time, based on the new index value, the corresponding position in the branch entry status table needs to be set to 1, and the corresponding position in the locked entry vector of the branch instruction in the locked entry record table needs to be set to 1.

[0028] ⑧ Execution of Transient Protection Instructions: When entries in the branch jump target address table and branch mode history table are locked, if the subsequent branch instructions requiring transient execution protection will not be executed, an unlock instruction is executed. This instruction uses the virtual address of the branch instruction requiring transient execution protection as a parameter and calculates an information checksum based on the context information of the branch instruction. When the information checksum matches the tag of an entry in the locked entry record table, the corresponding entry in the branch jump target address table and branch mode history table in the locked entry vector field of that entry is unlocked, i.e., the corresponding position in the branch entry status table is set to 0. Finally, the status field of the locked entry record table entry is set to 0, so that the entry can be allocated to other branch instructions requiring transient execution protection.

Claims

1. A fine-grained processor chip branch predictor content isolation method based on randomized indexing, comprising a unit program block random key configuration method and a branch predictor content locking mechanism, characterized in that: The unit program block random key configuration method includes: process key allocation and block key instruction generation; the branch predictor content locking mechanism includes: locking entries in the branch jump target address table and the branch mode history table; When a new process is created, a key is assigned to it. This key can be generated using various existing software or hardware random number generation methods. It can be managed by the operating system or virtual machine manager, like the ARM PA mechanism, or by a trusted execution environment, or by the processor hardware. The processor hardware needs to add a register to store the process key. This register cannot be read by the software. When the program runs, the process key will be written into the register. When generating block key instructions, source code analysis and executable file analysis are used to identify program blocks with security risks. When entering a program block, code snippets or instructions for generating block keys are inserted. The instructions for generating block keys can be similar to the PAC* / AUT* instructions of the ARMPA mechanism or similar to the Intel AES-NI instructions. The difference is that the result of the block key instructions is stored in a register that is not readable by software. When a secure domain program block is executed, the code fragment or instruction that generates the block key calculates and generates the block key based on a cryptographic algorithm and the context information of the program block. The context information of the program block includes the current process ID or thread ID, the virtual address of the program block, the program block number, and the current software stack position. After the block key is generated, it is stored in a hardware register that is not readable by the software for subsequent branch predictor index randomization. Multiple program blocks can share the same block key. Whether multiple program blocks share the same block key can be determined by analyzing the program execution characteristics. When entries in the branch jump target address table and the branch pattern history table are locked, if the number of entries and the index of the branch jump target address table and the branch pattern history table are the same, or if the depth or number of entries of the branch jump target address table and the branch pattern history table are different, then separate branch entry status tables and locked entry record tables are allocated to them respectively. The branch entry status table is a 1-bit vector, and its index is the same as that of the branch jump target address table and the branch pattern history table. Each bit indicates whether the corresponding entry in the branch jump target address table and the branch pattern history table is locked. When entries in the branch jump target address table and the branch mode history table are locked, the locked entry record table consists of three parts: transient execution protection branch instruction label, locked entry vector, and the status of the table entry. The former is used to verify the branch instruction that can update or delete the locked entry content. The number of bits in the locked entry vector is equal to the number of entries in the branch jump target address table and the branch mode history table, and is used to indicate which entries correspond to the transient execution protection branch instruction. The table entry status indicates whether the entry in the locked entry record table has been used. When the entries in the branch jump target address table and the branch mode history table are locked, when a branch instruction requiring transient execution protection is executed for the first time, there is no corresponding entry in the branch jump target address table and the branch mode history table; the processor hardware calculates an information authorization code for the instruction based on the block key of the block it belongs to and its context information. The context information for the branch instruction requiring transient execution protection includes the process number, code block number, and branch instruction address; When entries in the branch jump target address table and branch mode history table are locked, after the branch instruction is executed, its execution result needs to be updated in the branch jump target address table and branch mode history table. The original index of the branch jump target address table is usually generated from a portion of the branch instruction address, and the length of the selected bit depends on the size of the branch jump target address table. The original index of the branch mode history table is usually generated from a portion of the branch instruction address and global history information through a hash algorithm, and the length of the selected bit depends on the size of the branch mode history table. The code block key is XORed with the original index of the branch jump target address table and the original index of the branch mode history table to obtain a new index value, which is the position of the entry in the branch jump target address table and the branch mode history table corresponding to the aforementioned branch instruction that needs transient execution protection. The processor hardware updates the target address of the branch instruction and whether the branch jump is performed in the branch jump target address table and the branch mode history table according to the new index value. When entries in the branch jump target address table and the branch mode history table are locked, after the branch instruction execution result is updated to the branch jump target address table and the branch mode history table, the corresponding bit in the branch entry status table is set to 1 according to the new index value, indicating that the corresponding bit in the branch jump target address table and the branch mode history table has been allocated to the branch instruction that needs transient execution protection and is in a locked state; at the same time, the processor hardware allocates an entry for this instruction in the locked entry record table, calculates an information check code for this instruction based on the branch instruction context information, stores it in the allocated entry branch instruction tag field, and sets the corresponding bit in the locked entry vector and the corresponding bit in the allocated entry status to 1 according to the new index value; When the entries in the branch jump target address table and the branch mode history table are locked, when the branch instruction that needs transient execution protection is executed again, its corresponding code block key is XORed with the original index of the branch jump target address table and the original index of the branch mode history table respectively to obtain a new index value. Based on the new index, the branch jump target address table and the branch mode history table are searched to realize the prediction of the branch target address and the branch direction. When entries in the branch jump target address table and branch mode history table are locked, when a branch instruction requiring transient execution protection is executed again, the processor hardware calculates an information check code based on the aforementioned branch instruction context information and compares it with the tag stored in the locked entry record table. If they match, the result is updated in the locked entries in the branch jump target address table and branch mode history table. Because the original index of the branch jump target address table and the original index of the branch mode history table can also be generated by hashing a partial bit of the branch instruction address and global history information, the new index when the branch instruction is executed again may be different from the previous index. In this case, it is necessary to update the other entries in the branch jump target address table and branch mode history table with the aforementioned branch instruction execution result. Based on the new index value, it is necessary to set the corresponding bit in the branch entry status table to 1, and set the corresponding entry in the locked entry record table and the corresponding bit in the locked entry vector to 1. When entries in the branch jump target address table and branch mode history table are locked, if the branch instruction requiring transient execution protection will not be executed again, an unlocking instruction is executed. This instruction takes the virtual address of the branch instruction requiring transient execution protection as a parameter and calculates an information check code based on the context information of the branch instruction. When the information check code matches the tag of an entry in the locked entry record table, the corresponding entry in the branch jump target address table and branch mode history table in the locked entry vector field of that entry is unlocked, that is, the corresponding position in the branch entry status table is set to 0. Finally, the status field of the above-mentioned locked entry record table entry is set to 0, so that the entry can be allocated to other branch instructions that require transient execution protection.

2. An electronic device comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, characterized in that: The processor is configured to run the computer program to perform the method of claim 1 above.

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