Method, computer device and storage medium for optimizing a scan chain

Abstract

The present application provides a method, a computer device, and a storage medium for optimizing a scan chain. By obtaining first information of the scan register, the first information at least includes first position information of the scan register and the connection order of the plurality of scan registers. According to the first information, second information is determined, and the second information at least includes the distances between the plurality of scan registers. According to the second information, a wiring path of the scan register is determined, and the plurality of scan registers are connected according to the wiring path to optimize the scan chain. By the above method, the wiring path of the scan register is determined according to the distances between the scan registers, so that the scan chain can be optimized during wiring.

Description

Technical Field

[0001] This application relates to the technical field of digital logic circuits, and particularly to a method, a computer device, and a storage medium for optimizing a scan chain. Background Art

[0002] With the development of semiconductor technology, the logic inside chips has become increasingly complex. To improve chip quality, chips are generally tested when they leave the factory. In the field of chip testing, a scan chain can be used for testing. As an implementation technology of design for testability, this technology replaces ordinary registers in a chip with scan registers with scan functions, and connects the scan registers to form a scan chain.

[0003] However, the wire length connecting the scan registers is too long, thus occupying too much of the wiring resources of the entire chip. Therefore, how to optimize the wire length connecting the scan registers to optimize the scan chain is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose a method, a computer device, and a storage medium for optimizing a scan chain to solve or partially solve the above problems.

[0005] Based on the above purpose, in the first aspect of this application, a method for optimizing a scan chain is provided. The scan chain includes multiple scan registers, and the method includes:

[0006] Obtain first information of the scan registers. The first information at least includes the first position information of the scan registers and the connection order of the multiple scan registers;

[0007] Determine second information according to the first information. The second information at least includes the distances between multiple scan registers;

[0008] Determine the wiring path of the scan registers according to the second information; and

[0009] Connect the multiple scan registers according to the wiring path to optimize the scan chain.

[0010] In the second aspect of this application, a computer device is provided, including:

[0011] One or more processors, a memory; and

[0012] One or more programs;

[0013] The one or more programs are stored in the memory and executed by the one or more processors. The programs include instructions for executing the method described in the first aspect.

[0014] In a third aspect of the present application, there is provided a non-volatile computer-readable storage medium including a computer program, which, when executed by one or more processors, causes the processors to execute the method as described in the first aspect.

[0015] As can be seen from the above, a method, a computer device, and a storage medium for optimizing a scan chain provided by the present application obtain first information of the scan register, where the first information at least includes first position information of the scan register and the connection order of the plurality of scan registers. According to the first information, second information is determined, where the second information at least includes the distances between the plurality of scan registers. According to the second information, a wiring path of the scan register is determined, and the plurality of scan registers are connected according to the wiring path to optimize the scan chain. By the above method, the wiring path of the scan register is determined according to the distances between the scan registers, so that the scan chain can be optimized during wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present application or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings in the following description are only embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1A FIG. shows a schematic structural diagram of an exemplary general register 100 according to an embodiment of the present application.

[0018] Figure 1B FIG. shows a schematic structural diagram of an exemplary scan register 110 according to an embodiment of the present application.

[0019] Figure 1C FIG. shows a schematic structural diagram of an exemplary first scan chain 120 according to an embodiment of the present application.

[0020] Figure 2 FIG. shows a schematic structural diagram of an exemplary second scan chain 200 according to an embodiment of the present application.

[0021] Figure 3A FIG. shows a schematic diagram of an exemplary scan register according to an embodiment of the present application.

[0022] Figure 3B FIG. shows a schematic diagram of the connection of exemplary scan registers according to an embodiment of the present application.

[0023] Figure 3CShows a schematic diagram of the connection of another exemplary scan register according to an embodiment of the present application.

[0024] Figure 4A Shows a schematic structural diagram of an exemplary third scan chain 400 according to an embodiment of the present application.

[0025] Figure 4B Shows a schematic structural diagram of an exemplary fourth scan chain 410 according to an embodiment of the present application.

[0026] Figure 5A Shows a schematic diagram of an exemplary Hamiltonian circuit 500 according to an embodiment of the present application.

[0027] Figure 5B Shows a schematic structural diagram of an exemplary fifth scan chain 510 according to an embodiment of the present application.

[0028] Figure 6 Shows a schematic flowchart of an exemplary method 600 for optimizing a scan chain according to an embodiment of the present application.

[0029] Figure 7 Shows a schematic structural diagram of an exemplary computer device 700 according to an embodiment of the present application. Detailed implementation manners

[0030] To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0031] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the ordinary meanings understood by those of ordinary skill in the art to which the present application belongs. The "first", "second", and similar terms used in the embodiments of the present application do not indicate any order, quantity, or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0032] As described above, as an implementation technology of design for testability, the scan chain replaces the ordinary registers in the chip with scan registers with scan functions, enabling functional testing of the registers after the chip has completed the tape-out step, thereby determining whether the chip is functionally qualified.

[0033] Figure 1A Shows a schematic structural diagram of an exemplary general register 100 according to an embodiment of the present application.

[0034] As Figure 1A shown, the general register 100 may include a data input terminal D, a clock input terminal CLK, and a data output terminal Q. Among them, the clock active edge of the clock input terminal CLK may be a rising edge or a falling edge. Taking the clock active edge of the general register 100 as a rising edge as an example, when the clock input terminal CLK changes from a low level to a high level, the general register 100 samples the data input terminal D and sends the sampled value to the data output terminal Q. When the clock input terminal CLK is in other situations, the data output terminal Q maintains the original sampled value until the clock input terminal CLK changes from a low level to a high level for the second time.

[0035] Figure 1B Shows a schematic structural diagram of an exemplary scan register 110 according to an embodiment of the present application.

[0036] A scan register, that is, a shift register, is a sequential logic circuit that can store and transmit data. As Figure 1B shown, compared with the general register 100, a selector (Multiplexer, MUX) is added to the scan register 110. As Figure 1B shown, the scan register 110 may include a logical data input terminal D, a scan data input terminal (Scan In, SI), a scan enable terminal (Scan Enable, SE), a clock input terminal CLK, and a data output terminal Q. The selector MUX selects the input of the scan register 110 to be the logical data input terminal D or the scan data input terminal SI through the scan enable terminal SE. Therefore, when the clock active edge of the scan register 110 arrives, the output value of the scan register 110 is related to the value of the scan enable terminal SE.

[0037] For example, when the scan enable terminal SE is 0, the input of the scan register 110 may be the value of the logical data input terminal D, and when the scan enable terminal SE is 1, the input of the scan register 110 may be the value of the scan data input terminal SI. Or, when the scan enable terminal SE is 1, the input of the scan register 110 may be the value of the logical data input terminal D, and when the scan enable terminal SE is 0, the input of the scan register 110 may be the value of the scan data input terminal SI. The present application does not limit this.

[0038] In order to perform scan register testing (also known as scan testing), additional pins need to be added to the scan register to connect the scan registers. These connected scan registers are called a scan chain.

[0039] Figure 1C The structural schematic diagram of an exemplary first scan chain 120 according to an embodiment of the present application is shown.

[0040] As Figure 1C shown, the first scan chain 120 may include a plurality of cascaded scan registers (e.g., scan registers 122, 124, 126). The data output terminal Q of the previous scan register (e.g., scan register 122) in two adjacent scan registers is coupled to the scan data input terminal SI of the subsequent scan register (e.g., scan register 124). When the scan enable terminal SE of each scan register is 1, the plurality of scan registers can be connected end to end to form the first scan chain 120.

[0041] In the first scan chain 120, the scan data input terminal SI of the first scan register (e.g., scan register 122) is connected to a digital logic circuit (not shown in the figure), and the data output terminal Q of the last scan register (e.g., scan register 126) is connected to a digital logic circuit (not shown in the figure).

[0042] Functionally, the first scan chain 120 can be divided into a working path and a scan path. The working path is used to connect to the digital logic circuit through the logic data input terminal D when the chip is working normally, so as to ensure the normal operation of the chip. The scan path is used to serially input a plurality of initialization values to a plurality of scan registers through the start data input terminal when testing the chip, and output the output result of the scan test through the end data output terminal according to the test pattern input to the digital logic circuit, so as to detect the function and performance of the digital logic circuit.

[0043] For example, the scan data input terminal SI of the scan register 122 serves as the input terminal of the first scan chain 120. The data output terminal Q of the scan register 122 is connected to the scan data input terminal SI of the scan register 124, and the data output terminal Q of the scan register 124 is connected to the scan data input terminal SI of the next scan register. The data output terminal Q of the scan register 126 serves as the output terminal of the first scan chain 120. This connection path is the scan path of the first scan chain 120.

[0044] The scan test includes two processes: scan shift and scan capture. During the scan shift process, a plurality of initialization values of the test pattern can be serially input into a plurality of registers inside the chip through the scan path of the scan chain; during the scan capture process, the result (test result) of the chip combinational logic can be passed into each register through the working path of the scan chain, and then by comparing whether the serially output test result matches the expected result (initialization value), it can be determined whether there are defects inside the chip.

[0045] At the beginning of chip design, the connection order between scan registers is random. For example, it may be connected in alphabetical order according to the register names, which may result in the wire length connecting the scan registers not being the optimal solution, that is, the wire length connecting the scan registers may be too long, thus occupying too much of the overall chip routing resources.

[0046] Figure 2 The structural schematic diagram of an exemplary second scan chain 200 according to an embodiment of the present application is shown.

[0047] Taking the second scan chain 200 including 3 scan registers as an example, as Figure 2 shown, the second scan chain 200 may include a fifteenth scan register 202, a sixteenth scan register 204, a seventeenth scan register 206, an input end SI, and an output end SO. As described above, at the beginning of chip design, the connection order between scan registers is random. For example, it may be connected in alphabetical order according to the register names. In the second scan chain 200, taking the connection order of the fifteenth scan register 202, the sixteenth scan register 204, and the seventeenth scan register 206 being in alphabetical order (for example, the fifteenth scan register 202 → the sixteenth scan register 204 → the seventeenth scan register 206) as an example, in this way, the connection order of the fifteenth scan register 202, the sixteenth scan register 204, and the seventeenth scan register 206 is that the scan data input end of the fifteenth scan register 202 is connected to the input end SI of the second scan chain 200, the fifteenth scan register 202 and the sixteenth scan register 204 are connected end to end, the sixteenth scan register 204 and the seventeenth scan register 206 are connected end to end, and the data output end of the seventeenth scan register 206 is connected to the output end of the second scan chain 200.

[0048] It should be noted that due to the process reasons of chip routing, when routing to connect two registers, generally, the two registers will be connected along the directions of two coordinate axes on the plane (for example, coordinate axis X and coordinate axis Y).

[0049] It can be seen that the random connection order between scan registers will result in too long wire length for connecting scan registers. For a chip with increasingly complex internal logic, the random connection order between scan registers will not only result in too long wire length for connecting scan registers, but also cause the connection wires of scan registers to be in a mess, thus occupying too much of the overall chip routing resources. Therefore, how to optimize the wire length for connecting scan registers is an urgent problem to be solved.

[0050] In view of this, the present application provides a method, a computer device, and a storage medium for optimizing a scan chain. By obtaining first information of the scan register, the first information at least includes first position information of the scan register and the connection order of the multiple scan registers. According to the first information, second information is determined, the second information at least includes the distances between the multiple scan registers. According to the second information, a wiring path of the scan register is determined, and the multiple scan registers are connected according to the wiring path to optimize the scan chain. Through the above method, the wiring path of the scan register is determined according to the distances between the scan registers, so that the scan chain can be optimized during wiring.

[0051] The traveling salesman problem is a very classic NP-hard problem in combinatorial optimization. It describes such a problem that a merchant knows the distances between a series of cities. He starts from a starting city and goes to other cities, requiring that each city be visited only once and the distance of the loop back to the starting city is the shortest. This loop is called a Hamiltonian loop. NP-hard problem: An NP problem refers to a problem that can be solved within polynomial time using a certain amount of computation. An NP-hard problem refers to a problem that can be reduced to an NP problem, but the problem itself is not necessarily an NP problem. Such problems can only find approximate solutions. A Hamiltonian loop refers to a loop in an undirected graph or a directed graph that starts from a point, visits all points in the graph exactly once, and then returns to the starting point.

[0052] In order to reduce the wire length of connecting the scan registers, it is necessary to find an optimal solution with the shortest wire length after connecting the scan registers. In some embodiments, the problem of reducing the wire length of the scan chain can be converted into a model of the traveling salesman problem for solution.

[0053] In the traveling salesman problem, a city is a point, the straight-line distance between the points is calculated and this value is used as the distance between the cities, and then the loop with the shortest distance is solved. For the scan registers in the scan chain, in some embodiments, the graphics of the scan registers in the chip can be regarded as rectangles, so that the distances between the calculated rectangles can reflect to a certain extent the wire length between the scan registers after wiring.

[0054] Figure 3A The schematic diagram of an exemplary scan register according to an embodiment of the present application is shown.

[0055] Taking the scan chain including 3 scan registers as an example, as Figure 3AAs shown, in some embodiments, the first scan register 302, the third scan register 304, and the second scan register 306 can be regarded as rectangles, and each scan register is converted into a city in the traveling salesman problem. Since in the traveling salesman problem, a city is a point, the straight-line distance between points is calculated and this value is used as the distance between cities, and then the shortest-distance circuit is solved. Therefore, for scan registers, in some embodiments, a layout file of the digital logic circuit can be obtained, and the layout file can include first information of multiple scan registers. The first information can at least include the position information of the scan registers (for example, the first position information) and the connection order of the multiple scan registers. In a digital logic circuit, the position information of a scan register is usually the corner coordinates of the register. To make the calculated distance between rectangles reflect to some extent the wire length between scan registers after wiring, in some embodiments, the corner coordinates of the scan registers can be converted into center coordinates.

[0056] As Figure 3A shown, taking the conversion of the corner coordinates 3022 of the first scan register 302 into center coordinates as an example, in some embodiments, the size of the scan register can be obtained, and the center coordinates of the scan register can be calculated according to the size of the scan register and the corner coordinates 3022.

[0057] For example, the width of the scan register is W, the height is H, and the corner coordinates 3022 are , then the center coordinates of the scan register can be calculated in the following way:

[0058]

[0059]

[0060] After converting the corner coordinates into center coordinates, the distance between scan registers (for example, the second information) can be calculated according to the center coordinates to reflect to some extent the wire length between scan registers after wiring. As Figure 3A shown, in the wiring of a digital logic circuit, since when connecting two registers, the two scan registers are connected along the directions of two coordinate axes (for example, the coordinate axis X and the coordinate axis Y) on the plane, in some embodiments, the Manhattan distance between the coordinates of each scan register can be calculated, and the Manhattan distance is used as the distance between scan registers. The Manhattan distance is the sum of the absolute axial distances of two points in the standard coordinate system.

[0061] It can be understood that the embodiments of the present application are only described by taking the Manhattan distance between scan registers as an example. For a chip wiring process that does not require connecting scan registers along the directions of two coordinate axes on a plane, the distance between two scan registers can be calculated as the straight-line distance between the central coordinate points, and this solution also falls within the protection scope of the present application.

[0062] By abstracting the scan registers into central coordinate points and calculating the Manhattan distance between the points, the scan registers are thus converted into cities in the traveling salesman problem, and the scan chain reorganization is converted into the traveling salesman problem. Furthermore, the problem of reducing the scan chain wire length can be converted into finding the optimal solution in the traveling salesman problem.

[0063] In the process of finding the optimal solution to the traveling salesman problem, in some embodiments, algorithms (such as the greedy algorithm and the LKH algorithm (Lin-Kernighan Heuristic)) can be used for solving.

[0064] As Figure 3A shown, for the first scan register 302, the third scan register 304, and the second scan register 306, in some embodiments, if the Manhattan distance between the first scan register 302 and the second scan register 306 (for example, the first distance) is less than the Manhattan distance between the first scan register 302 and the third scan register 304 (for example, the second distance), then the path between the first scan register 302 and the second scan register 306 can be determined as the wiring path of the first scan register 302, that is, the first scan register 302 is connected to the second scan register 306 during the wiring process. If the Manhattan distance between the second scan register 306 and the third scan register 304 is less than the Manhattan distance between the second scan register 306 and other scan registers, then the path between the second scan register 306 and the third scan register 304 can be determined as the wiring path of the second scan register 306, that is, the second scan register 306 is connected to the third scan register 304 during the wiring process.

[0065] Figure 3B shows a schematic diagram of the connection of exemplary scan registers according to an embodiment of the present application.

[0066] After connecting the first scan register 302, the third scan register 304, and the second scan register 306 according to the method of the embodiment of the present application, in combination with Figure 2 and Figure 3B, since the connections of the first scan register 302, the third scan register 304, and the second scan register 306 are not made in a certain order, but rather a path with a short Manhattan distance between the scan registers is selected for connection. Therefore, compared with the wire lengths of the connections between the fifteenth scan register 202, the sixteenth scan register 204, and the seventeenth scan register 206 in the second scan chain 200, the wire lengths of the connections between the first scan register 302, the third scan register 304, and the second scan register 306 are shorter and more orderly.

[0067] To further optimize the wire lengths of the connections of the scan registers, in some embodiments, the wiring paths of the scan registers can be determined according to the path lengths between the scan registers.

[0068] Figure 3C FIG. shows a schematic diagram of the connection of another exemplary scan register according to an embodiment of the present application.

[0069] As Figure 3C shown, the connections between the fourth scan register 312, the third scan register 314, and the fifth scan register 316 can be the initial connections of the scan registers. Based on the initial connections of the scan registers, the wire lengths of the connections of the scan registers can be further optimized. In some embodiments, the path set of the fourth scan register 312, the third scan register 314, and the fifth scan register 316 can be determined according to the Manhattan distance between the scan registers. For the fourth scan register 312, the fifth scan register 316, and the sixth scan register 318, if the length of the path between the fourth scan register 312 and the fifth scan register 316 (e.g., the first path) is less than the length of the path between the fourth scan register 312 and the sixth scan register 318 (e.g., the second path), then the path between the fourth scan register 312 and the fifth scan register 316 can be determined as the wiring path of the fourth scan register 312. On the basis of calculating the initial connections of the scan registers, shorter wire lengths are further screened according to the path lengths of the scan registers.

[0070] Due to the reasons of the chip functions, the connection order of some scan registers (e.g., the target scan registers) in the scan chain cannot be changed, while the implementation algorithm of the traveling salesman problem assumes that the order in which the traveling salesman arrives at each city can be changed arbitrarily. Therefore, when implementing the algorithm for solving the traveling salesman problem, this particularity of the scan chain needs to be taken into account.

[0071] Figure 4A FIG. shows a schematic structural diagram of an exemplary third scan chain 400 according to an embodiment of the present application.

[0072] The third scan chain 400 may include an input terminal SI, an output terminal SO, an eleventh scan register 402, a twelfth scan register 404, a thirteenth scan register 406, and a fourteenth scan register 408. When dealing with the order-immutable restriction of partial scan registers, in some embodiments, the information of this part of scan registers may be recorded according to the first information. For example, the names of the scan registers and the order they need to follow (e.g., the target connection order), and the information of this part of scan registers is determined as the second information. For example, as Figure 4A shown, in the third scan chain 400, the thirteenth scan register 406 and the fourteenth scan register 408 need to maintain the order of accessing the thirteenth scan register 406 first and then the fourteenth scan register 408 unchanged. Then, when using the greedy algorithm to optimize the wire length, in some embodiments, the algorithm can be restricted from accessing the fourteenth scan register 408 before accessing the thirteenth scan register 406, so as to ensure the connection order of the thirteenth scan register 406 and the fourteenth scan register 408.

[0073] In the process of obtaining the initial wiring using the greedy algorithm and further optimizing the wire length using the LKH algorithm, in some embodiments, the path formed by the thirteenth scan register 406 and the fourteenth scan register 408 cannot be selected as the path to be deleted. For example, the path of the thirteenth scan register 406 and the fourteenth scan register 408 (e.g., the target path) is determined as the wiring path of the thirteenth scan register 406 (e.g., the current scan register), so as to ensure the connection order of the thirteenth scan register 406 and the fourteenth scan register 408.

[0074] Figure 4B shows a schematic structural diagram of an exemplary fourth scan chain 410 according to an embodiment of the present application.

[0075] As Figure 4B shown, in the optimized fourth scan chain 410, the thirteenth scan register 406 and the fourteenth scan register 408 remain unchanged. After the signal is output from the eleventh scan register 402, the thirteenth scan register 406 is accessed first, and then the fourteenth scan register 408 is accessed.

[0076] The optimal solution to the traveling salesman problem is a Hamiltonian cycle, and a scan chain is composed of a fixed initial pin, connecting a series of scan registers, and then connecting a fixed termination pin, where the initial pin and the termination pin cannot change. Pins are the input and output ports of the basic structural units of the chip. The above-mentioned initial pin can be the input terminal of the scan chain, and the termination pin can be the output terminal of the scan chain. Therefore, when forming a Hamiltonian cycle, it is necessary to consider how to connect the input terminal and the output terminal of the scan chain.

[0077] Figure 5A FIG. shows a schematic diagram of an exemplary Hamiltonian circuit 500 according to an embodiment of the present application.

[0078] As Figure 5A shown, after converting the problem of reducing the length of the scan chain into a model of the traveling salesman problem for solution, a circuit (e.g., the routing result) composed of the seventh scan register 502, the ninth scan register 504, the eighth scan register 506, and the first routing path 516, the second routing path 512, and the third routing path 514 can be obtained. When connecting the input end and the output end of the scan chain, in some embodiments, the distances from two adjacent scan registers to the input end and the output end can be calculated for determination. The path with the shortest sum of the distances from two adjacent scan registers to the input end and the output end respectively is used as the routing path for the input end and the output end.

[0079] For example, in the Hamiltonian circuit 500, for the seventh scan register 502 and the eighth scan register 506 which are adjacent scan registers, the ninth scan register 504 and the tenth scan register are adjacent scan registers. If the sum of the distance (e.g., the third distance) between the input end and the seventh scan register 502 and the distance (e.g., the fourth distance) between the output end and the eighth scan register 506 is less than the sum of the distance (e.g., the fifth distance) between the input end and the ninth scan register 504 and the distance (e.g., the sixth distance) between the output end and the tenth scan register, it can be determined that the sum of the wire lengths between the input end and the seventh scan register 502 and between the output end and the eighth scan register 506 is the shortest. Then, the input end can be connected to the seventh scan register 502, and the output end can be connected to the eighth scan register 506.

[0080] For the routing path (e.g., the target routing path) between the seventh scan register 502 and the eighth scan register 506, the routing path between the seventh scan register 502 and the eighth scan register 506 can be disconnected to form a scan chain.

[0081] Figure 5B FIG. shows a schematic diagram of the structure of an exemplary fifth scan chain 510 according to an embodiment of the present application.

[0082] As Figure 5B shown, compared with Figure 2 the second scan chain 200 connected in sequence shown in, the wire length of the fifth scan chain 510 is relatively shorter and more orderly. In this way, the scan chain in the digital logic circuit is optimized, and the overall routability of the digital logic circuit and the routing success rate of the subsequent routing process can also be optimized.

[0083] It should be noted that the above algorithms for optimizing the length of the scan chain (e.g., the greedy algorithm and the LKH algorithm) are only exemplary. For other algorithms that can calculate the shortest path, such as the Dijkstra algorithm and the Floyd algorithm (Floyd-Warshall algorithm), etc., they also fall within the protection scope of this application.

[0084] Figure 6 FIG. shows a schematic flow chart of an exemplary method 600 for optimizing a scan chain according to an embodiment of the present application. The scan chain includes a plurality of scan registers (e.g., Figure 3A the first scan register 302, the third scan register 304, and the second scan register 306 in Figure 6 ), as shown, method 600 may include the following steps.

[0085] In step 602, obtain first information of the scan register, where the first information at least includes first position information of the scan register and the connection order of the plurality of scan registers.

[0086] In step 604, determine second information according to the first information, where the second information at least includes the distances between the plurality of scan registers.

[0087] In some embodiments, the first position information is the corner coordinates of the scan register (e.g., Figure 3A the corner coordinates 3022 in

[0088] ), and the determining the second information according to the first information further includes: obtaining the size of the scan register (e.g., the width of the scan register is W and the height is H); calculating the center coordinates of the scan register according to the size of the scan register and the corner coordinates; calculating the distance (e.g., Manhattan distance) according to the center coordinates. By abstracting the scan register into a center coordinate point and calculating the Manhattan distance between the points, the scan register is thus converted into a city in the traveling salesman problem, and the scan chain reorganization is converted into the traveling salesman problem. Furthermore, the problem of reducing the scan chain length can be converted into finding the optimal solution in the traveling salesman problem. Figure 4A and Figure 4B ), and the connection order of the at least two target scan registers is the target connection order; determining the information of the at least two target scan registers as the second information. Thus, when implementing the algorithm for solving the traveling salesman problem, this particularity of the scan chain can be taken into account.

[0089] In step 606, according to the second information, determine the wiring path of the scan register.

[0090] In some embodiments, the plurality of scan registers at least includes a first scan register (e.g., Figure 3A the first scan register 302 in Figure 3A ), a second scan register (e.g., Figure 3A the scan register 306 in

[0091] ), and a third scan register (e.g., Figure 3C the scan register 304 in Figure 3C ). The distance includes a first distance between the first scan register and the second scan register and a second distance between the first scan register and the third scan register. The determining the wiring path of the scan register according to the second information further includes: in response to the first distance being less than the second distance, determining the path between the first scan register and the second scan register as the wiring path of the first scan register. In this way, since the path with a short Manhattan distance between the plurality of scan registers is selected for connection, the wire length for connecting the plurality of scan registers is shorter and more orderly. Figure 3C ), the determining the wiring path of the scan register according to the second information further includes: according to the distance, determining a set of paths of the plurality of scan registers, the set of paths including a first path between the fourth scan register and the fifth scan register and a second path between the fourth scan register and the sixth scan register; in response to the length of the first path being less than the length of the second path, determining the first path as the wiring path of the fourth scan register. On the basis of calculating the initial connection of the scan register, further screen the shorter wire lengths according to the path lengths of the scan registers.

[0092] In some embodiments, the determining the wiring path of the scan register according to the second information further includes: according to the second information, determining whether the current scan register is the at least two target scan registers; in response to the current scan register being the at least two target scan registers, determining the wiring path of the current scan register according to the target connection order. In this way, in the process of optimizing the wire length for connecting the scan registers, the particularity that the connection order cannot be changed in some scan registers is also taken into account.

[0093] In some embodiments, determining the wiring path of the scan register according to the second information further includes: determining whether the current scan register is one of the at least two target scan registers according to the second information; in response to the current scan register being one of the at least two target scan registers, determining a target path between the at least two target scan registers; and determining the target path as the wiring path of the current scan register. In this way, in the process of optimizing the wire length of the connection between scan registers, the particularity that the connection order cannot be changed in some scan registers is also taken into account.

[0094] In step 608, connect the multiple scan registers according to the wiring path to optimize the scan chain.

[0095] In some embodiments, connecting the multiple scan registers according to the wiring path to optimize the scan chain further includes: determining an input end (e.g., the input end SI in Figure 5B and an output end (e.g., the output end SO in Figure 5B of the scan chain; and connecting the multiple scan registers, the input end, and the output end according to the wiring path to optimize the scan chain. In this way, the scan chain in the digital logic circuit is optimized, and the overall wiring performance of the digital logic circuit and the wiring success rate of the subsequent wiring process can also be optimized.

[0096] In some embodiments, the multiple scan registers include a seventh scan register (e.g., the seventh scan register 502 in Figure 5A ), an eighth scan register (e.g., the eighth scan register 506 in Figure 5A ), a ninth scan register (e.g., the scan register 504 in Figure 5A ), and a tenth scan register. The seventh scan register and the eighth scan register are adjacent scan registers, and the ninth scan register and the tenth scan register are adjacent scan registers. Connecting the multiple scan registers, the input end, and the output end according to the wiring path further includes: connecting the multiple scan registers according to the wiring path to obtain a wiring result of the multiple scan registers (e.g., Figure 5Athe Hamiltonian circuit therein 500); determining a third distance between the input terminal and the seventh scan register and a fourth distance between the output terminal and the eighth scan register; determining a fifth distance between the input terminal and the ninth scan register and a sixth distance between the output terminal and the tenth scan register; in response to the sum of the third distance and the fourth distance being less than the sum of the fifth distance and the sixth distance, determining a target routing path between the seventh scan register and the eighth scan register according to the routing result (for example, Figure 5A the routing path between the seventh scan register 502 and the eighth scan register 506 therein); disconnecting the target routing path, and connecting the input terminal and the seventh scan register and connecting the output terminal and the eighth scan register. In this way, the scan chain in the digital logic circuit is optimized, and the overall routability of the digital logic circuit and the routing success rate of the subsequent routing process can also be optimized.

[0097] A method, a computer device, and a storage medium for optimizing a scan chain provided by the present application. By obtaining first information of the scan register, the first information at least includes first position information of the scan register and the connection order of the multiple scan registers. According to the first information, second information is determined, the second information at least includes distances between the multiple scan registers. According to the second information, a routing path of the scan register is determined, and the multiple scan registers are connected according to the routing path to optimize the scan chain. By the above method, the routing path of the scan register is determined according to the distance between the scan registers, so that the scan chain can be optimized during routing.

[0098] It should be noted that the method of the embodiments of the present application can be executed by a single device, such as a computer or a server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In this case of the distributed scenario, one of the multiple devices can only execute one or more steps of the method of the embodiments of the present application, and these multiple devices will interact with each other to complete the described method.

[0099] It should be noted that some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be executed in a different order from that in the above embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0100] Figure 7FIG. 0 shows a schematic structural diagram of an exemplary computer device 700 according to an embodiment of the present application. The computer device 700 may include: a first processor 702, a memory 704, a network interface 706, a peripheral interface 708, and a bus 710. Among them, the first processor 702, the memory 704, the network interface 706, and the peripheral interface 708 are communicatively connected to each other inside the device through the bus 710.

[0101] The first processor 702 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. The first processor 702 may be used to execute functions related to the technology described in the present application. In some embodiments, the first processor 702 may further include multiple processors integrated as a single logic component. As Figure 7 shown, the first processor 702 may include multiple processors, for example, a second processor 702a, a third processor 702b, and a fourth processor 702c.

[0102] The memory 704 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as Figure 7 shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solution of the present application) and data to be processed. The first processor 702 may also access the stored program instructions and data, and execute the program instructions to operate on the data to be processed. The memory 704 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 704 may include a random access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard disk, a solid state drive (SSD), a flash memory, a memory stick, etc.

[0103] The network interface 706 may be configured to provide communication with other external devices to the computer device 700 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination of the above. It can be understood that the type of the network is not limited to the above specific examples. In some embodiments, the network interface 706 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0104] The peripheral interface 708 can be configured to connect the computer device 700 to one or more peripheral devices to enable information input and output. For example, the peripheral devices can include input devices such as keyboards, mice, touchpads, touchscreens, microphones, various sensors, etc., and output devices such as displays, speakers, vibrators, indicator lights, etc.

[0105] The bus 710 can be configured to transfer information between various components of the computer device 700 (such as the first processor 702, the memory 704, the network interface 706, and the peripheral interface 708), such as internal buses (e.g., processor - memory bus), external buses (USB ports, PCI - E buses), etc.

[0106] It should be noted that although the above - mentioned devices only show the first processor 702, the memory 704, the network interface 706, the peripheral interface 708, and the bus 710, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above - mentioned devices may also only include the components necessary to implement the solution of the embodiments of the present application, and do not necessarily include all the components shown in the figure.

[0107] The computer device of the above - mentioned embodiment is used to implement the corresponding method 600 in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be elaborated herein.

[0108] Based on the same technical concept, corresponding to the method of any of the above - mentioned embodiments, the present application also provides a non - transitory computer - readable storage medium. The non - transitory computer - readable storage medium stores computer instructions, and the computer instructions are used to cause the computer to execute the method 600 as described in any of the foregoing embodiments.

[0109] The computer - readable medium of this embodiment includes permanent and non - permanent, removable and non - removable media, and information storage can be implemented by any method or technology. The information can be computer - readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase - change memory (PRAM), static random - access memory (SRAM), dynamic random - access memory (DRAM), other types of random - access memory (RAM), read - only memory (ROM), electrically erasable programmable read - only memory (EEPROM), flash memory or other memory technologies, compact disc read - only memory (CD - ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic disk storage or other magnetic storage devices, or any other non - transmission medium that can be used to store information that can be accessed by a computing device.

[0110] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the method 600 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be elaborated here.

[0111] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary, and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

[0112] In addition, for the sake of simplicity of description and discussion, and in order not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. In addition, the devices may be shown in block diagram form in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In the case where specific details (such as circuits) are set forth to describe the exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with variations of these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0113] Although the present application has been described in connection with specific embodiments of the present application, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (such as dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0114] The embodiments of the present application are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A method for optimizing a scan chain, characterized in that, The scan chain includes a plurality of scan registers, and the method includes: Obtaining first information of the scan registers, where the first information at least includes first position information of the scan registers and the connection order of the plurality of scan registers; Determining second information according to the first information, where the second information at least includes the distances between the plurality of scan registers; Determining a wiring path of the scan registers according to the second information; and Connecting the plurality of scan registers according to the wiring path to optimize the scan chain; Wherein, the plurality of scan registers at least includes a first scan register, a second scan register, and a third scan register, and the determining the wiring path of the scan registers according to the second information further includes: In response to a first distance between the first scan register and the second scan register being less than a second distance between the first scan register and the third scan register, determining a path between the first scan register and the second scan register as the wiring path of the first scan register.

2. The method according to claim 1, characterized in that The first position information is the corner coordinates of the scan register, and the determining the second information according to the first information further includes: Obtaining the size of the scan register; Calculating the center coordinates of the scan register according to the size of the scan register and the corner coordinates; Calculating the distance according to the center coordinates.

3. The method according to claim 2, wherein The plurality of scan registers at least includes a fourth scan register, a fifth scan register, and a sixth scan register, and the determining the wiring path of the scan registers according to the second information further includes: Determining a set of paths of the plurality of scan registers according to the distances, where the set of paths includes a first path between the fourth scan register and the fifth scan register and a second path between the fourth scan register and the sixth scan register; In response to the length of the first path being less than the length of the second path, determining the first path as the wiring path of the fourth scan register.

4. The method according to claim 1, characterized in that, The determining the second information according to the first information further includes: Determining at least two target scan registers among the plurality of scan registers according to the connection order of the plurality of scan registers, where the connection order of the at least two target scan registers is a target connection order; Determining the information of the at least two target scan registers as the second information.

5. The method according to claim 4, characterized in that The determining the wiring path of the scan registers according to the second information further includes: Determining whether the current scan register is the at least two target scan registers according to the second information; In response to the current scan register being the at least two target scan registers, determining the wiring path of the current scan register according to the target connection order.

6. The method according to claim 4, characterized in that, The determining the wiring path of the scan registers according to the second information further includes: Determining whether the current scan register is the at least two target scan registers according to the second information; In response to the current scan register being the at least two target scan registers, determine a target path between the at least two target scan registers; Determine the target path as the wiring path of the current scan register.

7. The method according to claim 1, characterized in that The connecting the plurality of scan registers according to the wiring path to optimize the scan chain further includes: Determine an input end and an output end of the scan chain; Connect the plurality of scan registers, the input end and the output end according to the wiring path to optimize the scan chain.

8. The method according to claim 7, wherein The plurality of scan registers include a seventh scan register, an eighth scan register, a ninth scan register, and a tenth scan register. The seventh scan register and the eighth scan register are adjacent scan registers, and the ninth scan register and the tenth scan register are adjacent scan registers. The connecting the plurality of scan registers, the input end and the output end according to the wiring path further includes: Connect the plurality of scan registers according to the wiring path to obtain a wiring result of the plurality of scan registers; Determine a third distance between the input end and the seventh scan register and a fourth distance between the output end and the eighth scan register; Determine a fifth distance between the input end and the ninth scan register and a sixth distance between the output end and the tenth scan register; In response to the sum of the third distance and the fourth distance being less than the sum of the fifth distance and the sixth distance, determine a target wiring path between the seventh scan register and the eighth scan register according to the wiring result; Disconnect the target wiring path, and connect the input end and the seventh scan register and connect the output end and the eighth scan register.

9. A computer device, characterized in that, Comprising: One or more processors, memories; And One or more programs; Wherein, the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1-8.

10. A non-volatile computer-readable storage medium containing a computer program, characterized in that, When the computer program is executed by one or more processors, the processors are caused to execute the method according to any one of claims 1-8.

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