Drive module and display device

Abstract

The present application belongs to the field of display, and specifically relates to a driving module and a display device, wherein the driving module includes a system-level chip and a relay circuit timing controller, wherein the timing controller is communicatively connected to the system-level chip, the relay circuit is connected between the system-level chip and the timing controller, and the relay circuit includes a communication monitoring unit and a backlight control unit, wherein the communication monitoring unit is used to monitor the communication connection between the system-level chip and the timing controller, and when the communication connection between the timing controller and the system-level chip continues, the backlight control unit controls the backlight module to turn on. When the image signal of the system-level chip fails to be given in time or the given image signal is distorted, and the timing controller fails to receive the valid signal output by the front-end system-level chip, the backlight module remains in a closed state, and the display device does not display the picture regardless of whether the display panel is working, thereby improving or eliminating display abnormalities.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to a driving module and a display device. Background Art

[0002] In line with current mainstream market demand, more and more display devices will be equipped with manufacturers' own system-on-chips (SOCs) to achieve purposes such as decoding video signals, running systems, image quality processing, and expanding interfaces.

[0003] When the device is powered on, if the SoC's image signal isn't delivered in a timely manner, and the control board (CB) fails to receive valid signals from the SoC, it will briefly enter built-in self-test (BIST) mode, causing the display panel to flicker (display a few frames of white images) and display anomalies. Furthermore, as display devices grow larger, the data transmission lines are also growing longer, causing transmission losses. This can distort the signals received by the timing controller, leading to the control board failing to receive valid signals and display anomalies. Summary of the Invention

[0004] The purpose of this application is to provide a driving module and a display device to improve or eliminate display abnormalities.

[0005] To achieve the above objectives, the present application provides a driver module, including a system-level chip, and the driver module further includes:

[0006] A timing controller, the timing controller being communicatively connected to the system-on-chip;

[0007] A relay circuit is connected between the system-level chip and the timing controller. The relay circuit includes a communication monitoring unit and a backlight control unit. The communication monitoring unit is used to monitor the communication connection between the system-level chip and the timing controller. When the communication connection between the timing controller and the system-level chip continues, the backlight control unit controls the backlight module to turn on.

[0008] Optionally, the relay circuit includes a relay chip, the relay chip includes an enable pin and a backlight power pin, the backlight power pin is connected to the backlight power supply of the backlight module, the relay chip controls the backlight power supply to be turned on or off through the enable pin, and the backlight control unit includes the enable pin and the backlight power pin.

[0009] Optionally, the relay chip includes a first pin, a second pin, a third pin and a fourth pin, the first pin is connected to the hot plug detection signal pin at one end of the system-level chip, the second pin is connected to the clock lock pin at one end of the system-level chip, the third pin is connected to the hot plug detection signal pin at one end of the timing controller, the fourth pin is connected to the clock lock pin at one end of the timing controller, and the communication monitoring unit includes the first pin, the second pin, the third pin and the fourth pin.

[0010] Optionally, the relay chip includes a data input pin and a data output pin, and the data input pin and the data output pin are connected to a data transmission channel between the system-level chip and the timing controller.

[0011] Optionally, the relay chip includes a first pin, a second pin, a third pin and a fourth pin, the first pin is connected to the auxiliary channel pin at one end of the system-level chip, the second pin is connected to the hot plug detection channel pin at one end of the system-level chip, the third pin is connected to the auxiliary channel pin at one end of the timing controller, and the fourth pin is connected to the hot plug detection channel pin at one end of the timing controller, and the communication monitoring unit includes the first pin, the second pin, the third pin and the fourth pin.

[0012] Optionally, the relay chip includes a data input pin and a data output pin, and the data input pin and the data output pin are connected to a main channel between the system-level chip and the timing controller, and the main channel is used to transmit image signals and audio data.

[0013] Optionally, the system-level chip and the timing controller are connected through a hot plug detection signal pin and a clock lock pin, and the communication monitoring unit includes an AND gate circuit, a first NOT gate circuit and a second NOT gate circuit, the first input end of the AND gate circuit is connected to the hot plug detection signal pin through the first NOT gate circuit, the second input end of the AND gate circuit is connected to the clock lock pin through the second NOT gate circuit, and the output end of the AND gate circuit is connected to the backlight control unit.

[0014] Optionally, the system-level chip and the timing controller are connected through a hot plug detection channel and an auxiliary channel, and the communication monitoring unit includes an AND gate circuit, a first NOT gate circuit and a second NOT gate circuit, the first input end of the AND gate circuit is connected to the hot plug detection channel through the first NOT gate circuit, the second input end of the AND gate circuit is connected to the auxiliary channel through the second NOT gate circuit, and the output end of the AND gate circuit is connected to the backlight control unit.

[0015] Optionally, the backlight control unit includes a switching circuit, the switching circuit includes a field effect transistor, the output end of the AND gate circuit is connected to the control end of the switching circuit, the first end of the switching circuit is connected to the backlight module, and the second end of the switching circuit is connected to the backlight power supply of the backlight module.

[0016] The present application also provides a display device, comprising:

[0017] The driving module;

[0018] The display panel is connected to the timing controller of the driving module.

[0019] The driving module and display device disclosed in this application have the following beneficial effects:

[0020] In the present application, the driving module includes a system-on-chip (SoC), a relay circuit, and a timing controller. The timing controller is in communication with the SoC, the relay circuit is connected between the SoC and the timing controller, and the relay circuit includes a communication monitoring unit and a backlight control unit. While the communication connection between the timing controller and the SoC persists, the backlight control unit controls the backlight module to turn on. If the image signal from the SoC is not provided in a timely manner or is distorted, and the timing controller fails to receive a valid signal output by the front-end SoC, the backlight module remains in an off state. Regardless of whether the display panel is working, the display device does not display any image, thereby improving or eliminating display anomalies.

[0021] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0024] Figure 1 It is a structural diagram of the driving module in Example 1 of the present application.

[0025] Figure 2 This is a schematic diagram of the VBO interface receiving and sending signals in Example 1 of the present application.

[0026] Figure 3This is a schematic diagram of the normal operation of the drive module in Example 1 of the present application.

[0027] Figure 4 This is a schematic diagram of the operation of the driving module when the signal is distorted in Example 1 of the present application.

[0028] Figure 5 It is a structural diagram of the driving module in Example 2 of the present application.

[0029] Figure 6 This is a schematic diagram of the principle of sending and receiving signals of the eDP interface in the second embodiment of the present application.

[0030] Figure 7 This is a structural diagram of the logic gate circuit in Example 3 of the present application.

[0031] Figure 8 It is a structural diagram of the display device in Example 4 of the present application.

[0032] Description of reference numerals:

[0033] 100. Driver module; 110. System-on-chip;

[0034] 121, relay chip; 1211, enable pin; 1212, backlight power pin; 1213, first pin; 1214, second pin; 1215, third pin; 1216, fourth pin; 1217, data input pin; 1218, data output pin; 122, logic gate circuit; 1221, AND gate circuit; 1222, first NOT gate circuit; 1223, second NOT gate circuit; 1224, switch circuit; 130, timing controller;

[0035] 200. Display panel; 300. Backlight module. DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0037] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0038] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0039] Example 1

[0040] See also Figure 1 As shown, in this embodiment, the driver module 100 includes a system-on-chip 110, a relay circuit, and a timing controller 130 (TCON). The timing controller 130 is in communication with the system-on-chip 110. The system-on-chip 110 outputs image signals, and the timing controller 130 is connected to the display panel to control the display panel to display images.

[0041] The relay circuit is connected between the SoC 110 and the timing controller 130. The relay circuit includes a communication monitoring unit and a backlight control unit. The communication monitoring unit is used to monitor the communication connection between the SoC 110 and the timing controller 130. When the communication connection between the timing controller 130 and the SoC 110 is maintained, the backlight control unit controls the backlight module to turn on. Conversely, when the communication connection between the timing controller 130 and the SoC 110 is interrupted or the communication is abnormal, the backlight control unit controls the backlight module to turn off. The relay circuit may include a relay chip 121 (IC) or a logic gate circuit 122.

[0042] In some display devices, the image signal of the system-level chip 110 is not given in time after power-on, and the timing controller 130 fails to receive the valid signal output by the front-end system-level chip 110. The display device will briefly enter the built-in self-test mode, causing the display panel image to flicker and cause display abnormality.

[0043] In this embodiment, the driver module 100 includes a system-on-chip (SoC) 110, a relay circuit, and a timing controller 130. The timing controller 130 is in communication with the SoC 110. The relay circuit is connected between the SoC 110 and the timing controller 130. The relay circuit includes a communication monitoring unit and a backlight control unit. While the communication connection between the timing controller 130 and the SoC 110 is maintained, the backlight control unit controls the backlight module to turn on. If the image signal from the SoC 110 is not provided in a timely manner, and if the timing controller 130 fails to receive a valid signal output by the front-end SoC 110, the backlight module remains in the off state. Regardless of whether the display panel is working, the display device does not display any image, thereby improving or eliminating display anomalies.

[0044] The addition of a relay circuit to the driver module 100 allows for rapid location of the problem when the display device displays an abnormality. Since the backlight control unit controls the backlight module to turn on when the communication connection between the timing controller 130 and the SoC 110 is maintained, and when the backlight module is turned off, it can be determined that the input signal problem occurs between the SoC 110 and the timing controller 130. When the backlight module is turned off, it can be determined that the input signal problem occurs between the timing controller 130 and the display panel.

[0045] Furthermore, as display devices become larger, the lines used to transmit data are also becoming longer, resulting in losses during the transmission process. This can cause distortion of the signal received by the timing controller 130, which in turn can lead to the timing controller 130 failing to receive a valid signal, resulting in display anomalies. By using a communication monitoring unit to monitor the communication connection between the SoC 110 and the timing controller 130, if the image signal provided by the SoC 110 is distorted and the timing controller 130 fails to receive a valid signal from the front-end SoC 110, the backlight module remains off. Regardless of whether the display panel is operating, the display device will not display an image, thereby improving display anomalies caused by signal distortion.

[0046] For example, see Figure 1 As shown, the relay circuit includes a relay chip 121, and the relay chip 121 includes an enable pin 1211 (EN) and a backlight power pin 1212 (Vbgl). The backlight power pin 1212 is connected to the backlight power of the backlight module. The relay chip 121 can control the backlight power on or off through the enable pin 1211, thereby controlling the backlight module to be on or off. In other words, when the communication connection between the timing controller 130 and the system-level chip 110 is continuous, the enable pin 1211 turns on the backlight power. When the communication connection between the timing controller 130 and the system-level chip 110 is interrupted or the communication is abnormal, the enable pin 1211 turns off the backlight power. The backlight control unit includes an enable pin 1211 and a backlight power pin 1212.

[0047] The communication monitoring unit and the backlight control unit are integrated in the relay chip 121, the driving module has a higher degree of integration and a simpler structure, and it is also convenient to control the backlight module to be turned on or off through the backlight power supply.

[0048] See also Figure 1 and Figure 2 As shown, the V-By-One (VBO) interface is a digital interface for image information transmission. The system-level chip 110 and the relay chip 121 can be connected using the VBO interface, and the relay chip 121 and the timing controller 130 can also be connected using the VBO interface.

[0049] The relay chip 121 includes a first pin 1213, a second pin 1214, a third pin 1215, and a fourth pin 1216. The first pin 1213 is connected to the hot plug detection signal (HTPDN) pin at one end of the system-on-chip 110, and the second pin 1214 is connected to the clock lock (LOCKN) pin at one end of the system-on-chip 110. The third pin 1215 is connected to the hot plug detection signal pin at one end of the timing controller 130, and the fourth pin 1216 is connected to the clock lock pin at one end of the timing controller 130. The communication monitoring unit includes a first pin 1213, a second pin 1214, a third pin 1215, and a fourth pin 1216.

[0050] The VBO interface uses the hot-plug detect signal pin and the clock lock pin for signal transmission. Both pins are pulled high by pull-up resistors. When no receiving device is connected or the receiving device is inactive, the hot-plug detect signal pin is high. The VBO interface requires a handshake before transmitting or receiving signals. This means that when the receiving end is connected to a receiving device and activated, the hot-plug detect signal is set low to begin clock and data recovery (CDR training). The transmitting end starts and locks the clock frequency. After clock recovery is complete, the receiving end sets the clock lock signal low to begin data format calibration (ALN training). After the handshake is completed, the VBO interface begins transmitting valid signals. If the transmitting end changes the clock frequency or interrupts transmission, or if the receiving end loses the clock, the clock lock signal is set high to restart clock and data recovery. If the hot-plug detect signal and the clock lock signal (high or low) are not in the correct state, valid signal transmission will not occur.

[0051] In this embodiment, the SoC 110 and relay chip 121 are connected using a VBO interface, with the SoC 110 acting as the transmitter and the relay chip 121 as the receiver. The relay chip 121 and timing controller 130 are also connected using a VBO interface, with the relay chip 121 acting as the transmitter and the timing controller 130 acting as the receiver. The valid signal transmitted by the VBO interface is the image signal. The relay chip 121 performs a handshake with both the SoC 110 and the timing controller 130. While the communication connection between the timing controller 130 and the SoC 110 remains established, the enable pin 1211 turns on the backlight power supply, thereby controlling the backlight module.

[0052] The VBO interface supports 4.0Gbps high-speed signal transmission, and its unique encoding method avoids the time lag problem between the data and clock at the receiving end, and is widely used in the field of ultra-high-definition LCD TVs.

[0053] In some embodiments, the relay chip 121 includes a plurality of data input pins 1217 and a plurality of data output pins 1218 . The data input pins 1217 and the data output pins 1218 are connected to a data transmission channel (data channel) between the system-on-chip 110 and the timing controller 130 .

[0054] The data transmission channel between the system-on-chip 110 and the timing controller 130 is also connected through the relay chip 121, which can prevent the image signal, hot plug detection signal and clock lock signal from being out of synchronization and affecting the display.

[0055] The relay chip 121 may also be provided with a signal conditioning unit to improve signal distortion caused by transmission losses and to improve or eliminate display anomalies caused by signal distortion. The signal conditioning unit may include multiple gears corresponding to signal gain. For example, the signal conditioning unit may have 15 gears, with the signal gain gradually increasing from gear 1 to gear 15, and the default gain corresponding to gear 8.

[0056] When the signal loss during transmission is relatively moderate and the signal received by the timing controller 130 does not have the problem of signal distortion: Figure 3 As shown, the receiving end is connected to the receiving device and activated, the hot plug detection signal is set low, and clock data recovery begins. The transmitting end starts and locks the clock frequency. After the receiving end completes clock recovery, the clock lock signal is set low to start data format calibration. After the handshake is completed, the VBO interface begins to transmit valid signals. The enable pin 1211 turns on the backlight power supply, and the backlight power pin 1212 is connected to the backlight power supply of the backlight module. When the driver module 100 is in operation, the signal conditioning unit is not in operation.

[0057] When the signal loss during transmission is relatively large or small, and the signal received by the timing controller 130 is distorted: Figure 4 As shown, the receiving end is connected to the receiving device and activated, the hot plug detection signal is set low, and clock data recovery begins. The sending end starts and locks the clock frequency. The receiving end fails to complete clock data recovery (CDR training NG), and the signal conditioning unit calculates the compensation gain. According to the calculation result, when the signal loss during transmission is relatively large, the gear is increased. When the signal loss during transmission is relatively small, the gear is reduced, and clock data recovery is performed again. When the clock data recovery is successful (CDR training OK), the clock lock signal is set low and data format calibration begins. After the handshake is completed, the VBO interface begins to transmit valid signals. The enable pin 1211 turns on the backlight power supply, and the backlight power pin 1212 is connected to the backlight power supply of the backlight module.

[0058] Example 2

[0059] The difference between the second embodiment and the first embodiment is that the communication interface between the system-on-chip 110 and the relay chip 121 is different, and the communication interface between the relay chip 121 and the timing controller 130 is also different.

[0060] See also Figure 5 As shown, the system-on-chip 110 and the relay chip 121 are connected using an eDP (Embedded DisplayPort) interface, and the relay chip 121 and the timing controller 130 are also connected using an eDP interface.

[0061] The relay chip 121 includes a first pin 1213, a second pin 1214, a third pin 1215, and a fourth pin 1216. The first pin 1213 is connected to the auxiliary channel (AUX CH) pin at one end of the system-on-chip 110, and the second pin 1214 is connected to the hot plug detection channel (HPD) pin at one end of the system-on-chip 110. The third pin 1215 is connected to the auxiliary channel pin at one end of the timing controller 130, and the fourth pin 1216 is connected to the hot plug detection channel pin at one end of the timing controller 130. The communication monitoring unit includes a first pin 1213, a second pin 1214, a third pin 1215, and a fourth pin 1216.

[0062] The eDP interface uses hot plug detection channel pins and auxiliary channel pins to transmit signals. Figure 6 As shown, after the transmitter and receiver are connected to the power supply and powered, the hot plug detection channel detects the connection between the receiver and the transmitter, the receiver parameters are read through the auxiliary channel, and finally the effective signal is transmitted through the main channel (Main Link).

[0063] In this embodiment, the SoC 110 and relay chip 121 are connected using an eDP interface, with the SoC 110 acting as the transmitter and the relay chip 121 as the receiver. The relay chip 121 and timing controller 130 are also connected using an eDP interface, with the relay chip 121 acting as the transmitter and the timing controller 130 acting as the receiver. The valid signal transmitted by the eDP interface is the image signal. The relay chip 121 is in communication with both the SoC 110 and the timing controller 130, and its enable pin 1211 turns on the backlight power supply, thereby controlling the backlight module.

[0064] In some embodiments, the relay chip 121 includes a data input pin 1217 and a data output pin 1218 , which are connected to a main channel between the system-on-chip 110 and the timing controller 130 , and the main channel is used to transmit image signals and audio data.

[0065] The data transmission channel between the SoC 110 and the timing controller 130 is also connected via a relay chip 121, preventing asynchrony among the main, auxiliary, and hot-plug detection channel signals, which could affect the display. Furthermore, relay chip 121 also includes a signal conditioning unit to mitigate signal distortion caused by transmission losses and improve or eliminate display anomalies caused by signal distortion.

[0066] Example 3

[0067] The difference between the third embodiment and the first and second embodiments is that the structure of the relay circuit is different. In the third embodiment, the relay circuit is a logic gate circuit 122 .

[0068] See also Figure 7 As shown, the system-on-chip 110 and the timing controller 130 are connected via a hot plug detection signal pin and a clock lock pin. The communication monitoring unit includes an AND gate circuit 1221, a first NOT gate circuit 1222, and a second NOT gate circuit 1223. A first input of AND gate circuit 1221 is connected to the hot plug detection signal pin via the first NOT gate circuit 1222, a second input of AND gate circuit 1221 is connected to the clock lock pin via the second NOT gate circuit 1223, and an output of AND gate circuit 1221 is connected to the backlight control unit.

[0069] The system-level chip 110 and the timing controller 130 are connected through the VBO interface. When the handshake is completed and the signals are sent and received, the hot plug detection signal and the clock lock signal are both low levels. After passing through the NOT gate, the hot plug detection signal and the clock lock signal are both high levels. If the two input ends of the AND gate circuit 1221 are both high-level signals, the output end of the AND gate circuit 1221 also outputs a high-level signal. The high-level signal output by the AND gate circuit 1221 can control the backlight control unit to turn on.

[0070] The relay circuit is a logic gate circuit 122. It monitors the communication connection between the SoC 110 and the timing controller 130. When the communication connection between the timing controller 130 and the SoC 110 is maintained, the backlight control unit controls the backlight module 300 to turn on. When the communication connection between the timing controller 130 and the SoC 110 is interrupted or abnormal, the backlight control unit controls the backlight module 300 to turn off. Compared to the relay chip 121, the logic gate circuit 122 has a simpler structure, which helps reduce the manufacturing cost of the display device.

[0071] It should be noted that the SoC 110 and the timing controller 130 may be connected via a VBO interface, but are not limited thereto. The SoC 110 and the timing controller 130 may also be connected via an eDP interface, depending on the specific situation.

[0072] When the SoC 110 and the timing controller 130 are connected via the eDP interface, the eDP interface utilizes a hot plug detection channel and an auxiliary channel. The communication monitoring unit includes an AND gate 1221, a first NOT gate 1222, and a second NOT gate 1223. The first input of AND gate 1221 is connected to the hot plug detection channel via the first NOT gate 1222. The second input of AND gate 1221 is connected to the auxiliary channel via the second NOT gate 1223. The output of AND gate 1221 is connected to the backlight control unit.

[0073] See also Figure 7 As shown, the backlight control unit includes a switch circuit 1224, which includes a field-effect transistor. The output end of the AND gate circuit 1221 is connected to the control end of the field-effect transistor. The first end of the field-effect transistor is connected to the backlight module 300, and the second end of the field-effect transistor is connected to the backlight power supply of the backlight module 300. The control end, first end, and second end of the field-effect transistor can be its gate, drain, and source, respectively.

[0074] The switch circuit 1224 is a field effect transistor, which controls the backlight module 300 and the backlight power supply to be turned on or off. The structure is simple, which helps to reduce the manufacturing cost of the display device.

[0075] Example 4

[0076] This application also provides a display device, see Figure 8 As shown, the display device includes a driving module 100 and a display panel 200, and the display panel 200 is connected to the timing controller 130 of the driving module 100. The driving module 100 includes the driving module 100 disclosed in the first to third embodiments.

[0077] In this embodiment, the display device includes a driver module 100, which includes a system-on-chip (SoC) 110, a relay circuit, and a timing controller 130. The timing controller 130 is in communication with the SoC 110. The relay circuit is connected between the SoC 110 and the timing controller 130. The relay circuit includes a communication monitoring unit and a backlight control unit. While the communication connection between the timing controller 130 and the SoC 110 is maintained, the backlight control unit controls the backlight module 300 to turn on. If the timing controller 130 fails to receive a valid signal output by the front-end SoC 110, the backlight module 300 remains in the off state. Regardless of whether the display panel 200 is operating, the display device does not display any image, thereby improving or eliminating display anomalies.

[0078] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0079] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0080] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0081] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, all changes or modifications made in accordance with the claims and description of the present application are within the scope of the patent of this application.

Claims

1. A driving module, comprising a system-on-chip, characterized in that: The driving module further includes: A timing controller, the timing controller being communicatively connected to the system-on-chip; a relay circuit connected between the system-on-chip and the timing controller, the relay circuit including a communication monitoring unit and a backlight control unit, the communication monitoring unit being configured to monitor the communication connection between the system-on-chip and the timing controller, and the backlight control unit controlling the backlight module to turn on when the communication connection between the timing controller and the system-on-chip is maintained; The relay circuit includes a relay chip, the relay chip includes an enable pin and a backlight power pin, the backlight power pin is connected to the backlight power supply of the backlight module, the relay chip controls the backlight power supply to be turned on or off through the enable pin, and the backlight control unit includes the enable pin and the backlight power pin; The relay chip includes a first pin, a second pin, a third pin and a fourth pin, the first pin is connected to the hot plug detection signal pin at one end of the system-level chip, the second pin is connected to the clock lock pin at one end of the system-level chip, the third pin is connected to the hot plug detection signal pin at one end of the timing controller, and the fourth pin is connected to the clock lock pin at one end of the timing controller, and the communication monitoring unit includes the first pin, the second pin, the third pin and the fourth pin; or The relay chip includes a first pin, a second pin, a third pin and a fourth pin, the first pin is connected to the auxiliary channel pin at one end of the system-level chip, the second pin is connected to the hot plug detection channel pin at one end of the system-level chip, the third pin is connected to the auxiliary channel pin at one end of the timing controller, and the fourth pin is connected to the hot plug detection channel pin at one end of the timing controller. The communication monitoring unit includes the first pin, the second pin, the third pin and the fourth pin.

2. The driving module according to claim 1, characterized in that: When the first pin is connected to the hot plug detection signal pin at one end of the system-level chip, the relay chip includes a data input pin and a data output pin, and the data input pin and the data output pin are connected to the data transmission channel between the system-level chip and the timing controller.

3. The driving module according to claim 1, wherein: When the first pin is connected to the auxiliary channel pin at one end of the system-level chip, the relay chip includes a data input pin and a data output pin, and the data input pin and the data output pin are connected to the main channel between the system-level chip and the timing controller, and the main channel is used to transmit image signals and audio data.

4. The driving module according to claim 1, characterized in that: The system-level chip and the timing controller are connected via a hot plug detection signal pin and a clock lock pin. The communication monitoring unit includes an AND gate circuit, a first NOT gate circuit, and a second NOT gate circuit. The first input end of the AND gate circuit is connected to the hot plug detection signal pin via the first NOT gate circuit, the second input end of the AND gate circuit is connected to the clock lock pin via the second NOT gate circuit, and the output end of the AND gate circuit is connected to the backlight control unit.

5. The driving module according to claim 1, characterized in that: The system-level chip and the timing controller are connected via a hot plug detection channel and an auxiliary channel. The communication monitoring unit includes an AND gate circuit, a first NOT gate circuit, and a second NOT gate circuit. A first input end of the AND gate circuit is connected to the hot plug detection channel via the first NOT gate circuit, a second input end of the AND gate circuit is connected to the auxiliary channel via the second NOT gate circuit, and an output end of the AND gate circuit is connected to the backlight control unit.

6. The driving module according to claim 4 or 5, characterized in that: The backlight control unit includes a switching circuit, which includes a field effect transistor. The output end of the AND gate circuit is connected to the control end of the switching circuit, the first end of the switching circuit is connected to the backlight module, and the second end of the switching circuit is connected to the backlight power supply of the backlight module.

7. A display device, characterized in that: include: The drive module according to any one of claims 1 to 6; The display panel is connected to the timing controller of the driving module.

Images