Display panel, display device, and display panel driving method

Abstract

The present disclosure provides a display panel, a display device, and a display panel driving method, which relate to the field of display technology and are used to reduce the hopping frequency between gamma voltages of different colors. The display panel includes a plurality of sub-pixels arranged in an array, at least one data line group, at least one data bus group, and at least one control switch group, wherein the plurality of sub-pixels include first-color sub-pixels, and the first-color sub-pixels include first-type first-color sub-pixels and second-type first-color sub-pixels; the at least one data line group includes a plurality of data lines connected to a display unit, wherein a column of sub-pixels is connected to two data lines, and a data line is connected to pixels of the same type in a column of sub-pixels; the data bus group is connected to the display unit; a first data bus of the data bus group is connected to a first-type first-color sub-pixel, and a second data bus is connected to a second-type first-color sub-pixel; and the at least one control switch group includes a plurality of control switches connected to the data bus group.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a method for driving the display panel. Background Art

[0002] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby achieving display. Summary of the Invention

[0003] The embodiments of the present disclosure aim to provide a display panel, a display device, and a display panel driving method for reducing the switching frequency between gamma voltages of different colors, thereby reducing power consumption and improving the lifespan and quality of the display panel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a display panel is provided. The display panel includes a plurality of subpixels arranged in an array, at least one data line group, at least one data bus group, and at least one control switch group. The plurality of subpixels include first-color subpixels, the first-color subpixels including first-type first-color subpixels and second-type first-color subpixels. The plurality of subpixels also includes at least one display unit, the display unit including at least four adjacent columns of subpixels, at least two of the at least four columns of subpixels being first-subpixel columns, a column of other subpixels being disposed between every two first-subpixel columns, and at least two columns of first-subpixel columns including first-type first-subpixel columns and second-type first-subpixel columns arranged sequentially, wherein the first-type first-subpixel columns include first-type first-color subpixels and second-type first-color subpixels arranged sequentially along the column direction, and the second-type first-subpixel columns include second-type first-color subpixels and first-type first-color subpixels arranged sequentially along the column direction. At least one data line group includes a plurality of data lines connected to the display unit, with one column of subpixels connected to two data lines, and one data line connected to pixels of the same type within the column of subpixels.

[0006] At least one data bus group, comprising a plurality of data buses, connected to the display unit; the data bus group comprises a first data bus and a second data bus, the first data bus being connected to the first-type first-color sub-pixels in the at least two first sub-pixel columns via at least two data lines, and the second data bus being connected to the second-type first-color sub-pixels in the at least two first sub-pixel columns via at least two data lines. At least one control switch group, comprising a plurality of control switches, connected to the data bus group; the control switch group comprises a first control switch and a second control switch, the first data bus being connected to each data line connected thereto, and the second data bus being connected to each data line connected thereto.

[0007] In the above-described circuit connection and arrangement of the display panel, on the one hand, a first data bus is connected to a first type of first-color sub-pixels via corresponding data lines, and a second data bus is connected to a second type of first-color sub-pixels via corresponding data lines. For example, the first type of first-color sub-pixels and the second type of first-color sub-pixels are both green sub-pixels, meaning that the first data bus and the second data bus each control the gamma voltage range of the same color. This arrangement eliminates the need for the voltages transmitted by the first data bus and the second data bus to jump between gamma voltages of different colors, reducing the number of jumps between gamma voltages of different colors, thereby reducing power consumption and improving the quality and service life of the display panel. Furthermore, within the display unit of the display panel, multiple sub-pixels are arranged in an array, with each column of sub-pixels connected to two data lines, each of which is connected to a different data bus. The connection between the data lines and the corresponding sub-pixels ensures a more uniform circuit arrangement and consistent circuit connections in the first sub-pixel column and other sub-pixel columns, facilitating uniformity of data signals received by each sub-pixel column, ensuring consistent brightness across the display unit, and improving display uniformity.

[0008] In some embodiments, the multiple sub-pixels also include second color sub-pixels and third color sub-pixels; the display unit also includes at least one second sub-pixel column and at least one third sub-pixel column arranged in sequence along the row direction, and the first sub-pixel column is located between the second sub-pixel column and the third sub-pixel column; the second sub-pixel column includes second color sub-pixels and third color sub-pixels arranged in sequence along the column direction, and the third sub-pixel column includes third color sub-pixels and second color sub-pixels arranged in sequence along the column direction; the data bus group also includes a third data bus and a fourth data bus, the third data bus is connected to the second color sub-pixels of the at least one second sub-pixel column and at least one third sub-pixel column through at least two data lines, and the fourth data bus is connected to the third color sub-pixels of the at least one second sub-pixel column and at least one third sub-pixel column through at least two data lines; the multiple control switches also include a third control switch and a fourth control switch, the third data bus is connected to each data line connected to it with a third control switch, and the fourth data bus is connected to each data line connected to it with a fourth control switch.

[0009] In some embodiments, the data bus includes a fan-out line, a transfer line, and at least two connecting lines; the fan-out line is connected to the transfer line, the at least two connecting lines are connected to the transfer line, and the connecting line is connected to the control switch.

[0010] In some embodiments, the first data bus includes a first fan-out line, a first transfer line and at least two first connection lines; the first fan-out line is connected to the first transfer line, the at least two first connection lines are connected to the first transfer line, and the first connection line is connected to the first control switch; the second data bus includes a second fan-out line, a second transfer line and at least two second connection lines; the second fan-out line is connected to the second transfer line, the at least two second connection lines are connected to the second transfer line, and the second connection line is connected to the second control switch; the third data bus includes a third fan-out line, a third transfer line and at least two third connection lines; the third fan-out line is connected to the third transfer line, the at least two third connection lines are connected to the third transfer line, and the third connection line is connected to the third control switch; the fourth data bus includes a fourth fan-out line, a fourth transfer line and at least two fourth connection lines; the fourth fan-out line is connected to the fourth transfer line, the at least two fourth connection lines are connected to the fourth transfer line, and the fourth connection line is connected to the fourth control switch.

[0011] In some embodiments, the first transfer line, the second transfer line, the third transfer line and the fourth transfer line all extend in the row direction and are arranged in the column direction; the first fan-out line, the second fan-out line, the third fan-out line and the fourth fan-out line are all arranged on the side of the first transfer line, the second transfer line, the third transfer line and the fourth transfer line away from the multiple sub-pixels; the first connection line, the second connection line, the third connection line and the fourth connection line all extend in the column direction and are arranged on the side of the first transfer line, the second transfer line, the third transfer line and the fourth transfer line close to the multiple sub-pixels.

[0012] In some embodiments, the display unit includes at least four sub-pixels located in a first row and at least four sub-pixels located in a second row; the display panel also includes multiple control lines for controlling the control switches; at least two control switches corresponding to at least two adjacent sub-pixels located in the same row are connected to the same control line.

[0013] In some embodiments, the display unit includes eight adjacent columns of sub-pixels, and the display unit includes four columns of first sub-pixels, two columns of second sub-pixel columns, and two columns of third sub-pixel columns; the display unit includes at least eight sub-pixels located in the first row and eight sub-pixels located in the second row, the eight sub-pixels in the first row are divided into a first group of sub-pixels and a second group of sub-pixels, and the eight sub-pixels in the second row are divided into a third group of sub-pixels and a fourth group of sub-pixels, and each group of sub-pixels includes four adjacent sub-pixels; the four control switches corresponding to the first group of sub-pixels are all connected to the first control line, and the four control switches corresponding to the second group of sub-pixels are all connected to the second control line; the four control switches corresponding to the third group of sub-pixels are all connected to the third control line; and the four control switches corresponding to the fourth group of sub-pixels are all connected to the fourth control line.

[0014] In some embodiments, the first control line, the second control line, the third control line and the fourth control line all extend in the row direction and are arranged in the column direction. The multiple control switches are arranged between the multiple control lines and the multiple sub-pixels. The control switches include an active layer pattern, a gate pattern, a first pole pattern and a second pole pattern. The gate pattern overlaps with the active layer pattern, and one end of the gate pattern is connected to the corresponding control line. The first pole pattern is connected to the active layer pattern and to the corresponding data bus. The second pole pattern is connected to the active layer pattern and to the corresponding data line. When the data bus includes a fan-out line, a transfer line and at least two connecting lines, the first pole pattern is connected to a connecting line of the corresponding data bus.

[0015] In some embodiments, the display unit includes four adjacent columns of sub-pixels; the first data bus and the second data bus are the same data bus, serving as a first common data bus, and the third data bus and the fourth data bus are the same data bus, serving as a second common data bus; the first common data bus is connected to the first type of first color sub-pixels and the second type of first color sub-pixels in the two first sub-pixel columns through at least two data lines; the second common data bus is connected to the second color sub-pixels and the third color sub-pixels in the second sub-pixel column and the third sub-pixel column through at least two data lines.

[0016] In some embodiments, the first shared data bus includes a shared first fan-out line, a shared first transfer line, and at least two shared first connection lines; the shared first fan-out line is connected to the shared first transfer line, the at least two shared first connection lines are connected to the shared first transfer line, and one shared first connection line is connected to the first control switch and the second control switch corresponding to a column of sub-pixels; the second shared data bus includes a shared second fan-out line, a shared second transfer line, and at least two shared second connection lines; the shared second fan-out line is connected to the shared second transfer line, the at least two shared second connection lines are connected to the shared second transfer line, and one shared second connection line is connected to the third control switch and the fourth control switch corresponding to a column of sub-pixels.

[0017] In some embodiments, the first common transfer line and the second common transfer line both extend in the row direction and are arranged in the column direction; the common first fan-out line and the common second fan-out line are arranged on the side of the common first transfer line and the common second transfer line away from the multiple sub-pixels; the common first connection line and the common second connection line are arranged on the side of the common first transfer line and the common second transfer line close to the multiple sub-pixels.

[0018] In some embodiments, the display unit includes at least a first pixel group and a second pixel group located in a first row, and a second pixel group and a first pixel group located in a second row; the first pixel group includes a first sub-pixel and a second sub-pixel of a first type, and the second pixel group includes a first sub-pixel and a third sub-pixel of a second type, and the display panel also includes a plurality of control lines for controlling the control switches; wherein the first control switch and the third control switch corresponding to the first pixel group in the first row are both connected to the first control line, and the second control switch and the fourth control switch corresponding to the second pixel group in the first row are both connected to the second control line; the second control switch and the fourth control switch corresponding to the second pixel group in the second row are both connected to the third control line, and the first control switch and the third control switch corresponding to the first pixel group in the second row are both connected to the fourth control line.

[0019] In some embodiments, the first control line, the second control line, the third control line and the fourth control line all extend in the row direction and are arranged in the column direction. The two control switches corresponding to a column of sub-pixels constitute a common control switch. The common control switch is arranged between the multiple control lines and the multiple sub-pixels. The common control switch includes a common active layer pattern, two gate patterns, a common first pole pattern, and two second pole patterns. The two gate patterns overlap with the common active layer pattern. The two gate patterns are respectively located on both sides of the common first pole pattern, and one end of each of the gate patterns is connected to the corresponding control line. The common first pole pattern is connected to the common active layer pattern and to the corresponding data bus. The two second pole patterns are connected to the active layer pattern, and the two second pole patterns are respectively connected to the corresponding data lines. When the common data bus includes a common fan-out line, a common transfer line and at least two common connecting lines, the common first pole pattern is connected to a common connecting line of the corresponding common data bus.

[0020] In some embodiments, when the display unit includes at least four adjacent columns of sub-pixels, each of the four adjacent columns of sub-pixels includes a second sub-pixel column, a first-category first sub-pixel column, a third sub-pixel column, and a second-category first sub-pixel column arranged in sequence, wherein the second sub-pixel column, the first-category first sub-pixel column and the third sub-pixel column, the second-category first sub-pixel column are mirror-symmetrically arranged, and the data line connecting the second sub-pixel column and the first-category first sub-pixel column and the data line connecting the third sub-pixel column and the second-category first sub-pixel column are mirror-symmetrically arranged.

[0021] In another aspect, a display device is provided, comprising the display panel as described in any one of the above aspects and a driver chip connected to the data bus group.

[0022] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here.

[0023] On the other hand, a driving method for the display panel described in any embodiment of the first aspect is provided, wherein the driving method includes: in the first time period t1 of the first scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to output display signals respectively, and controlling the first control switch connected to the first sub-pixel column of the first type and the third control switch connected to the second sub-pixel column in the display unit to be in an open state; in the first time period t3 of the second scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to output display signals respectively, and controlling the second control switch connected to the first sub-pixel column of the first type and the fourth control switch connected to the second sub-pixel column in the display unit to be in an open state.

[0024] The above driving method has the same structure and beneficial technical effects as the display panels provided in some of the above embodiments, and will not be described in detail here.

[0025] In some embodiments, the display unit includes eight adjacent columns of sub-pixels, and the display unit includes a first sub-display unit and a second sub-display unit arranged along a row direction; the first sub-display unit includes four adjacent columns of sub-pixels, and the second sub-display unit includes four adjacent columns of sub-pixels; the driving method further includes: in a first period of the first scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to output display signals respectively, and controlling the second control switch connected to the second type of first sub-pixel column in the first sub-display unit, the fourth control switch connected to the third sub-pixel column, the first control switch connected to the first type of first sub-pixel column, and the third control switch connected to the second sub-pixel column to be in an open state; in a second period of the first scanning time, controlling the first data bus, the second data bus, the third data bus and the fourth data bus to output display signals respectively, and controlling the first control switch connected to the first type of first sub-pixel column, the fourth control switch connected to the second type of first sub-pixel column in the second sub-display unit, The second control switch connected to the second sub-pixel column, the third control switch connected to the second sub-pixel column, and the fourth control switch connected to the third sub-pixel column are in an open state; in a first period of the second scanning time, the first data bus, the second data bus, the third data bus, and the fourth data bus are controlled to output display signals respectively, and the first control switch connected to the second type of first sub-pixel column, the third control switch connected to the third sub-pixel column, the second control switch connected to the first type of first sub-pixel column, and the fourth control switch connected to the second sub-pixel column in the first sub-display unit are controlled to be in an open state; in a second period of the second scanning time, the first data bus, the second data bus, the third data bus, and the fourth data bus are controlled to output display signals respectively, and the second control switch connected to the first type of first sub-pixel column, the first control switch connected to the second type of first sub-pixel column, the fourth control switch connected to the second sub-pixel column, and the third control switch connected to the third sub-pixel column in the second sub-display unit are controlled to be in an open state.

[0026] In some embodiments, during a second period of the first scanning time, the first data bus, the second data bus, the third data bus, and the fourth data bus are controlled to output display signals respectively, and the second control switch connected to the second type first sub-pixel column and the fourth control switch connected to the third sub-pixel column in the display unit are controlled to be in an open state;

[0027] During the second period of the second scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the first control switch connected to the second type of first sub-pixel column and the third control switch connected to the third sub-pixel column in the display unit are controlled to be in an open state. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0029] Figure 1 is a planar structural diagram of a display panel according to some embodiments of the present disclosure;

[0030] Figure 2 is a driving timing diagram of a display panel according to some embodiments of the present disclosure;

[0031] Figure 3A A planar structural diagram of a display panel provided in some embodiments of the present disclosure;

[0032] Figure 3B A driving timing diagram of a display panel provided in some embodiments of the present disclosure;

[0033] Figure 4 Another planar structural diagram of a display panel provided in some embodiments of the present disclosure;

[0034] Figure 5A A planar structural diagram of a display panel provided in some embodiments of the present disclosure;

[0035] Figure 5B A driving timing diagram of a display panel provided in some embodiments of the present disclosure;

[0036] Figure 6 Another planar structural diagram of a display panel provided in some embodiments of the present disclosure;

[0037] Figure 7A A planar structural diagram of a display panel provided in some embodiments of the present disclosure;

[0038] Figure 7B A driving timing diagram of a display panel provided in some embodiments of the present disclosure;

[0039] Figure 8 Another planar structural diagram of a display panel provided in some embodiments of the present disclosure;

[0040] Figure 9 A planar structural diagram of a display panel provided in some embodiments of the present disclosure;

[0041] Figure 10 A structural diagram of a pixel driving circuit of a display panel provided in some embodiments of the present disclosure;

[0042] Figure 11 This is a planar structural diagram of a display device provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0046] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0047] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0048] “A and / or B, including the following three combinations: A only, B only, and a combination of A and B.

[0049] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining that" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0050] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0051] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0052] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0053] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5 brackets; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5 brackets. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range for approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0054] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0055] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0056] At present, a demultiplexing driving scheme has been developed for display driving of display devices. Each source channel of the driver chip drives two or more sub-pixel columns in a time-division manner, so as to reduce the number of source channel settings while improving the display resolution, thereby achieving the effect of improving resolution and reducing manufacturing costs.

[0057] like Figure 1 and Figure 2As shown, in some embodiments, a display panel includes a plurality of sub-pixels P arranged in an array and a plurality of data lines DT (DT1-DT4, DT1'-DT4') arranged in a vertical direction. It also includes a plurality of gate lines GT (GT1, GT2) extending in a horizontal direction. Each data line DT is connected to a plurality of sub-pixels in the same sub-pixel column and is used to input data signals to the corresponding connected sub-pixels. A column of sub-pixels includes multiple color sub-pixels, such as red sub-pixels and blue sub-pixels. Each gate line is connected to a plurality of sub-pixels in the same row of sub-pixels and is used to control the sub-pixels to turn on, so that data signals are written when turned on. The plurality of data lines are divided into a plurality of groups, each group of data lines is connected to a data channel D of a driver chip Q via a fan-out line FT. A control switch K is provided on the line connecting each data line to the data channel. The control switch may be a demultiplexer. The control switch controls the control switches connected to the plurality of data lines to turn on in sequence in a time-division driving manner, thereby inputting data signals to the sub-pixels connected to the corresponding data lines. Multiple gate lines scan row by row, controlling the sequential opening of multiple rows of sub-pixels so that the data signals transmitted by the data lines are input to the corresponding sub-pixels. For example, each data line group includes four data lines (DT1, DT1', DT2, DT2'), which are connected to a fan-out line. A control switch is provided between the fan-out line and each data line. The four control switches are controlled by control lines MUX1 to MUX4 and sequentially open to input data signals to their corresponding data lines. When a sub-pixel is turned on, the data line inputs the corresponding data signal to the sub-pixel.

[0058] Since the gamma voltages corresponding to sub-pixels of different colors are different, and one fan-out line FT is connected to multiple data lines DT, and multiple data lines are connected to sub-pixels of different colors, the initial data signal in the fan-out line jumps between gamma voltages of different colors, generating additional power consumption. Figure 2 As shown, the fan-out line FT1 is responsible for driving the sub-pixels connected to the data lines DT1, DT1', DT2, and DT2'. The gamma voltage of the initial data signal it transmits jumps between the red gamma voltage, green gamma voltage, blue gamma voltage, green gamma voltage, and red gamma voltage in sequence, and the number of jumps is frequent. Since each fan-out line needs to transmit the gamma voltages of the sub-pixels of multiple colors connected to it, the gamma voltage output by the data channel of the corresponding connected driver chip jumps frequently. Frequent voltage jumps will lead to the problem of high power consumption of the driver chip.

[0059] Based on this, some embodiments of the present disclosure provide a display panel, a display device, and a driving method for a display panel. By adjusting the circuit arrangement, different fan-out lines respectively control the gamma voltage ranges of different colors, thereby reducing the number of jumps of the initial data signal between different color gamma voltages, thereby reducing power consumption and improving the reliability of the display panel.

[0060] The display panel, display device, and display panel driving method provided by the present disclosure are respectively introduced below.

[0061] like Figure 3A and Figure 7A As shown, some embodiments of the present disclosure provide a display panel 100 , which includes a plurality of sub-pixels 10 arranged in an array, at least one data line group 30 , at least one data bus group 40 and at least one control switch group 50 .

[0062] The plurality of sub-pixels 10 include first-color sub-pixels 11, which include first-type first-color sub-pixels 111 and second-type first-color sub-pixels 112. The plurality of sub-pixels 10 include at least one display unit 20, which includes at least four adjacent columns of sub-pixels 10. At least two of the at least four columns of sub-pixels 10 are first sub-pixel columns 210, with a column of other sub-pixels disposed between every two first sub-pixel columns 210. The at least two first sub-pixel columns 210 include sequentially arranged first-type first sub-pixel columns 2101 and second-type first sub-pixel columns 2102. The first-type first sub-pixel columns 2101 include first-type first-color sub-pixels 111 and second-type first-color sub-pixels 112 sequentially disposed along a column direction Y, and the second-type first sub-pixel columns 2102 include second-type first-color sub-pixels 112 and first-type first-color sub-pixels 111 disposed sequentially along a column direction Y.

[0063] like Figure 3A and Figure 7A As shown, multiple sub-pixels are arranged in an array, arranged into multiple rows along the row direction and multiple columns along the column direction. Taking the display unit 20 including four adjacent columns of sub-pixels as an example, two of the four columns of sub-pixels 10 are first sub-pixel columns 210, and the two first sub-pixel columns 210 are not adjacent. As shown in the figure, the first sub-pixel columns 210 are located in the second column and the fourth column, respectively. The sub-pixels in the second column are the first-category first sub-pixel column 2101, the sub-pixels in the fourth column are the second-category first sub-pixel column 2102, and the sub-pixels in the first column and the third column are other sub-pixels. It should be noted that the first sub-pixel columns 210 in FIG. 3 are merely an example, and the two first sub-pixel columns 210 can also be located in the first column and the third column, that is, the sub-pixel column in the first column is the first-category first sub-pixel column 2101, and the sub-pixel column in the third column is the second-category first sub-pixel column 2102.

[0064] For example, the first color sub-pixel 11 is a green sub-pixel. The first-type first color sub-pixel 111 can be considered a light green sub-pixel, and the second-type first color sub-pixel 112 can be considered a dark green sub-pixel. The light green sub-pixel and the dark green sub-pixel are simply used to distinguish the two types of first color sub-pixels and do not represent the actual shades of green displayed. The alternating arrangement order of the first-type first color sub-pixels 111 and the second-type first color sub-pixels 112 in the first-type first sub-pixel column 2101 and the second-type first pixel column 2102 is opposite.

[0065] At least one data line group 30 includes a plurality of data lines DT connected to the display unit 20 . Two data lines DT are connected to a column of sub-pixels 10 , and one data line DT is connected to the same type of pixels in a column of sub-pixels 10 .

[0066] like Figure 3A and Figure 7A As shown, one data line group 30 corresponds to one display unit 20. When the display unit 20 includes four adjacent columns of sub-pixels, the data line group 30 includes eight data lines DT. One column of sub-pixels 10 is connected to two data lines DT, for example, the first column of sub-pixels is connected to two data lines DT (DT1, DT1'), and the third column of sub-pixels is connected to two data lines DT (DT3, DT3'); the first-type first sub-pixel column 2101 (the second column of sub-pixels) is connected to two data lines DT (DT2, DT2'), and the first-type first color sub-pixel 111 is connected to the data line DT2, and the second-type first color sub-pixel 112 is connected to the data line DT2'; the second-type first sub-pixel column 2102 (the fourth column of sub-pixels) is connected to two data lines DT (DT4, DT4'), and the first-type first color sub-pixel 111 is connected to the data line DT4, and the second-type first color sub-pixel 112 is connected to the data line DT4'.

[0067] At least one data bus group 40 includes multiple data buses 41, and the data bus group 40 is connected to the display unit 20; the data bus group 40 includes a first data bus 411 and a second data bus 412, the first data bus 411 is connected to the first type of first color sub-pixels 111 in at least two first sub-pixel columns 210 through at least two data lines DT, and the second data bus 412 is connected to the second type of first color sub-pixels 112 in at least two first sub-pixel columns 210 through at least two data lines DT.

[0068] like Figure 3A and Figure 7AAs shown, one data bus group 40 corresponds to one display unit. Data bus 41 is connected to the driver chip and to the data lines DT. Data bus 41 is configured to transmit initial data signals provided by the driver chip to each data line it is connected to. The data lines then transmit the data signals to the corresponding sub-pixels, thereby enabling the sub-pixels to display. Data bus group 40 includes a first data bus 411 and a second data bus 412. For example, first data bus 411 and second data bus 412 transmit initial data signals required for green sub-pixels. First data bus 411 is connected to first-category, first-color sub-pixels 111 in two first sub-pixel columns 210 via two data lines DT2 and DT4. Second data bus 412 is connected to second-category, first-color sub-pixels 112 in two first sub-pixel columns 210 via two data lines DT2' and DT4'. A black dot in the figure represents a data line connected to a sub-pixel.

[0069] At least one control switch group 50, including multiple control switches 51, is connected to the data bus group 40; the control switch group 50 includes a first control switch K1 and a second control switch K2, the first control switch K1 is connected between the first data bus 411 and each connected data line DT, and the second control switch K2 is connected between the first data bus 411 and each connected data line DT.

[0070] like Figure 3A and Figure 7A As shown, one control switch group 50 corresponds to one data bus group 40, that is, one control switch group 50 corresponds to one display unit. A control switch 51 is provided between each data bus group 40 and each of the data lines connected thereto. The control switch group 50 includes a first control switch K1 and a second control switch K2. The first control switch K1 is connected between the first data bus 411 and the two data lines DT2 and DT4 connected thereto, and the second control switch K2 is connected between the first data bus 411 and the two data lines DT2' and DT4' connected thereto.

[0071] Combine Figure 5BThe first data bus 411 transmits the initial data signal required for the display of the first color sub-pixel (green sub-pixel), and the second data bus 412 transmits the initial data signal required for the display of the first color sub-pixel (green sub-pixel). The first control switch K1 and the second control switch K2 are turned on or off in response to the control signal. When the first control switch K1 is turned on, the first data bus 411 transmits the initial data signal to at least two data lines (data lines DT2 and DT4) through the first control switch K1, thereby controlling the display of the first type of first color sub-pixels 111 in the at least two first sub-pixel columns 210 connected to the data lines; when the second control switch K2 is turned on, the second data bus 412 transmits the initial data signal to at least two data lines (data lines DT2' and DT4') through the second control switch K2, thereby controlling the display of the second type of first color sub-pixels 112 in the at least two first sub-pixel columns 210 connected to the data lines.

[0072] The line connection and arrangement method in the above-mentioned display panel are adopted. On the one hand, the first data bus 411 is connected to the first type of first color sub-pixel 111 through the corresponding data line DT, and the second data bus 412 is connected to the second type of first color sub-pixel 112 through the corresponding data line DT. For example, the first type of first color sub-pixel 111 and the second type of first color sub-pixel 112 are both green sub-pixels, that is, the first data bus 411 and the second data bus 412 respectively control the gamma voltage range of the same color. In this way, the initial data signal transmitted by the first data bus and the second data bus does not need to jump between different color gamma voltages, which reduces the number of times the first data bus 411 and the second data bus 412 jump between different color gamma voltages, thereby reducing power consumption and improving the quality and service life of the display panel. On the other hand, multiple sub-pixels are arranged in an array within the display unit 20 in the display panel 100, and each column of sub-pixels is connected to two data lines, and the two data lines are connected to different data buses. The connection between the above data lines and the corresponding sub-pixels can ensure that the line arrangement is more orderly, and the consistency of the line connection in the first sub-pixel column and other sub-pixel columns is ensured, which is beneficial to the uniformity of the data signals received by each sub-pixel column, ensures the consistent brightness of the display unit 20, and can improve the uniformity of the display.

[0073] In some embodiments, continue to refer to Figure 3A and Figure 7AThe plurality of sub-pixels 10 further include second-color sub-pixels 12 and third-color sub-pixels 13. The display unit 20 further includes at least one second sub-pixel column 220 and at least one third sub-pixel column 230 sequentially arranged along the row direction X, with the first sub-pixel column 210 located between the second sub-pixel column 220 and the third sub-pixel column 230. The second sub-pixel column 220 includes the second-color sub-pixels 12 and the third-color sub-pixels 13 sequentially arranged along the column direction Y, and the third sub-pixel column 230 includes the third-color sub-pixels 13 and the second-color sub-pixels 12 sequentially arranged along the column direction Y. A column of other sub-pixels is disposed between every two of the first sub-pixel columns, and the column of other sub-pixels is either the second sub-pixel column 220 or the third sub-pixel column 230.

[0074] For example, the second color sub-pixel 12 is a red sub-pixel, the third color sub-pixel 13 is a color sub-pixel, and the display unit 20 includes four columns of sub-pixels, which are respectively a second sub-pixel column 220, a first-type first sub-pixel column 2101, a third sub-pixel column 230, and a second-type first sub-pixel column 2102 arranged in sequence. The alternating arrangement order of the second color sub-pixels 12 and the third color sub-pixels 13 in the second sub-pixel column 220 and the third sub-pixel column 230 is opposite.

[0075] The data bus group 40 further includes a third data bus 413 and a fourth data bus 414. The third data bus 413 is connected to the second color subpixels 12 of at least one second subpixel column 220 and at least one third subpixel column 230 via at least two data lines DT. The fourth data bus 414 is connected to the third color subpixels 13 of at least one second subpixel column 220 and at least one third subpixel column 230 via at least two data lines DT. The plurality of control switches K further include a third control switch K3 and a fourth control switch K4. The third control switch K3 is connected between the third data bus 413 and each connected data line DT. The fourth data bus 414 is connected to each connected data line DT via a fourth control switch K4.

[0076] Exemplarily, the third data bus 413 is connected to the second color sub-pixel 12 of the second sub-pixel column 220 and the third sub-pixel column 230 through two data lines DT (data lines DT1 and DT3), and a third control switch K3 is connected between the third data bus 413 and the two data lines DT; the fourth data bus 414 is connected to the third color sub-pixel 13 of the second sub-pixel column 220 and the third sub-pixel column 230 through two data lines DT (data lines DT1' and DT3'), and a fourth control switch K4 is connected between the fourth data bus 414 and the two data lines DT.

[0077] Combine Figure 3BThe first data bus 411 transmits the initial data signal required for the display of the first color sub-pixel (green sub-pixel), the second data bus 412 transmits the initial data signal required for the display of the first color sub-pixel (green sub-pixel), the third data bus 413 transmits the initial data signal required for the display of the second color sub-pixel (red sub-pixel), and the fourth data bus 414 transmits the initial data signal required for the display of the third color sub-pixel (blue sub-pixel). The first control switch K1, the second control switch K2, the third control switch K3, and the fourth control switch K4 are turned on or off in response to the control signal. When the first control switch K1 is turned on, the first data bus 411 transmits the initial data signal to at least two data lines (data lines DT2 and DT4) through the first control switch K1, thereby controlling the display of the first type of first color sub-pixels 111 in the at least two first sub-pixel columns 210 connected to the data lines; when the second control switch K1 is turned on, the first data bus 411 transmits the initial data signal to the at least two data lines (data lines DT2 and DT4) through the first control switch K1, thereby controlling the display of the first type of first color sub-pixels 111 in the at least two first sub-pixel columns 210 connected to the data lines; When K2 is turned on, the second data bus 412 transmits the initial data signal to at least two data lines (data lines DT2' and DT4') through the second control switch K2, thereby controlling the display of the second-category first-color sub-pixels 112 in the at least two first sub-pixel columns 210 connected to the data lines; when the third control switch K3 is turned on, the third data bus 413 transmits the initial data signal to at least two data lines (data lines DT1 and DT3) through the third control switch K3, thereby controlling the display of the second-color sub-pixels 12 in the at least two second sub-pixel columns 220 connected to the data lines; when the fourth control switch K4 is turned on, the fourth data bus 414 transmits the initial data signal to at least two data lines (data lines DT1' and DT3') through the fourth control switch K4, thereby controlling the display of the third-color sub-pixels 13 in the at least two third sub-pixel columns 230 connected to the data lines.

[0078] For example, the control lines 61, 62, 63, and 64 input working levels in sequence, control the corresponding control switches to be turned on in sequence, and the data signals are sequentially fed into the data lines connected to the control switches, for example, Figure 3B As shown, the data signal is simultaneously fed into DT1 and DT2, then simultaneously fed into DT3' and DT4', then simultaneously fed into DT1' and DT2', and finally simultaneously fed into DT3 and DT4. When the gate lines GT1\GT2 control the corresponding row of sub-pixels to turn on, the sub-pixels realize display under the control of the data signal. Thus, Figure 3A The display order of the two rows and four columns of sub-pixels is: from top to bottom and from left to right, first the red sub-pixel (12) and the green sub-pixel (111) are displayed, then the blue sub-pixel (13) and the green sub-pixel (112) are displayed, then the blue sub-pixel (13) and the green sub-pixel (112) are displayed, and then the red sub-pixel (12) and the green sub-pixel (111) are displayed.

[0079] It should be noted that the third data bus 413 is connected to the second color sub-pixel 12 through the corresponding data line DT, and the fourth data bus 414 is connected to the third color sub-pixel 13 through the corresponding data line DT. For example, the second color sub-pixel 12 is a red sub-pixel, and the third color sub-pixel 13 is a blue sub-pixel. The third data bus 413 and the fourth data bus 414 respectively control the gamma voltage range of the second color sub-pixel 12 and the third color sub-pixel 13. This setting enables the third data bus 413 and the fourth data bus 414 to respectively control the threshold voltage compensation time and voltage range of the sub-pixel corresponding to a color, thereby avoiding additional power consumption due to frequent jumps between the voltages of the red and blue sub-pixels. At the same time, combined with the aforementioned content, it can be obtained that the first data bus 411 is connected to the first type of first color sub-pixel 111 through the corresponding data line DT, and the second data bus 412 is connected to the second type of first color sub-pixel 112 through the corresponding data line DT, that is, the first data bus 411 and the second data bus 412 control the gamma voltage range of the green sub-pixel, that is, the number of times the data voltage transmitted by the data bus 41 jumps between the red, green and blue sub-pixels is reduced, thereby reducing the power consumption of the display panel, improving the quality and service life of the display panel, and enhancing the picture display. Furthermore, since each column of sub-pixels is connected to two data lines, and each data line controls the same type of sub-pixels in a column of sub-pixels, the arrangement of each data line and the connection to the data bus are consistent. As can be seen from FIG5 , the hopping frequency of the gamma voltage of the data signal transmitted by each data line is consistent. For example, the hopping frequency of the red gamma voltage transmitted by the data line DT1 is consistent with the hopping frequency of the green gamma voltage transmitted by the data line DT1′. At least two adjacent sub-pixels in the row direction can be displayed simultaneously, which is beneficial to further improve the uniformity of the data signals received by each sub-pixel column, reduce the difference between each data line, ensure the uniformity of the brightness of the display unit 20, and improve the uniformity of the display.

[0080] In some embodiments, continue to refer to Figure 3A and Figure 4 The data bus 41 includes a fan-out line 410, a transfer line 420 and at least two connecting lines 430; the fan-out line 410 is connected to the transfer line 420, at least two connecting lines 430 are connected to the transfer line 420, and the connecting line 430 is connected to the control switch K.

[0081] It can be understood that the fan-out line is connected to the data channel of the driver chip, and a transfer line 420 is provided. The transfer line 420 is connected to at least two connecting lines 430, and the connecting line is connected to the corresponding data line DT. The initial data signal output by the driver chip can be transmitted to multiple connecting lines 430 through the fan-out line 410 and the transfer line, and then transmitted to the corresponding data line. A control switch is provided between the transfer line and the data line. By turning the control switch on or off, the data signal corresponding to the data line in the initial data signal transmitted by the data bus is transmitted to the data line. This arrangement can realize the connection of one data bus to multiple data lines and simplify the circuit of the fan-out line 410 part of the data bus 41, thereby reducing the number of fan-out lines 410 in the data bus group 40 in the display panel 100, further simplifying the circuit arrangement of the data bus group 40, and reducing the signal interference between different data buses 41.

[0082] In some embodiments, as Figure 3A As shown, the first data bus 411 includes a first fan-out line 411a, a first patch line 411b, and at least two first connection lines 411c. The first fan-out line 411a is connected to the first patch line 411b, at least two first connection lines 411c are connected to the first patch line 411b, and the first connection line 411c is connected to the first control switch K1. The second data bus 412 includes a second fan-out line 412a, a second patch line 412b, and at least two second connection lines 412c. The second fan-out line 412a is connected to the second patch line 412b, at least two second connection lines 412c are connected to the second patch line 412b, and the second connection line 412c is connected to the second control switch K2. The third data bus 413 includes a third fan-out line 413a, a third patch line 413b, and at least two third connection lines 413c. The third fan-out line 413a is connected to the third patch line 413b, at least two third connection lines 413c are connected to the third patch line 413b, and the third connection line 413c is connected to the third control switch K3. The fourth data bus 414 includes a fourth fan-out line 414a, a fourth patch line 414b, and at least two fourth connection lines 414c. The fourth fan-out line 414a is connected to the fourth patch line 414b, at least two fourth connection lines 414c are connected to the fourth patch line 414b, and the fourth connection line 414b is connected to the fourth control switch K4.

[0083] For example, Figure 3AAs shown, the first data bus 411 includes a first fan-out line 411a, a first transfer line 411b, and two first connection lines 411c. The first fan-out line 411a is connected to the first transfer line 411b, and the two first connection lines 411c are connected to the first transfer line 411b. Each first connection line 411c is connected to a first control switch K1. One first control switch K1 is connected to the data line DT2 and is connected to the first-category first-color sub-pixel 111 via the data line DT2. The other first control switch K1 is connected to the data line DT4 and is connected to the first-category first-color sub-pixel 111 via the data line DT4. Similarly, the second data bus 412, the third data bus 413, and the fourth data bus 414 are connected to the second-category first-color sub-pixel 112, the second-color sub-pixel 12, and the third-color sub-pixel 13, respectively, via corresponding data lines.

[0084] For example, Figure 5A As shown, the first data bus 411 includes a first fan-out line 411a, a first transfer line 411b, and four first connection lines 411c. The first fan-out line 411a is connected to the first transfer line 411b, and the four first connection lines 411c are connected to the first transfer line 411b. Each first connection line 411c is connected to a first control switch K1. The four first control switches K1 are respectively connected to the data lines DT2, DT4, DT6, and DT8, and are respectively connected to the corresponding first-category first-color sub-pixels 111 through the data lines DT2, DT4, DT6, and DT8. Similarly, the second data bus 412, the third data bus 413, and the fourth data bus 414 are respectively connected to the second-category first-color sub-pixels 112, the second-color sub-pixels 12, and the third-color sub-pixels 13 through the corresponding data lines.

[0085] In some embodiments, the following describes the film layer wiring design of the data bus and data lines in the display panel.

[0086] like Figure 4 As shown, the first transfer line 411b, the second transfer line 412b, the third transfer line 413b and the fourth transfer line 414b all extend along the row direction X and are arranged along the column direction Y; the first fan-out line 411a, the second fan-out line 412a, the third fan-out line 413a and the fourth fan-out line 414a are all arranged on the side of the first transfer line 411b, the second transfer line 412b, the third transfer line 413b and the fourth transfer line 414b away from the multiple sub-pixels 10; the first connection line 411c, the second connection line 412c, the third connection line 413c and the fourth connection line 414c all extend along the column direction Y and are arranged on the side of the first transfer line 411b, the second transfer line 412b, the third transfer line 413b and the fourth transfer line 414b close to the multiple sub-pixels 10.

[0087] It should be noted that the display panel 100 includes a display area AA and a frame area BB. The frame area BB is arranged on at least one side of the display area AA. Multiple sub-pixels and multiple data lines are arranged in the display area AA. The data bus group and the control switch group are located in the peripheral area BB.

[0088] The first fan-out line 411a, the second fan-out line 412a, the third fan-out line 413a and the fourth fan-out line 414a are used to transmit the initial data signal from the frame area BB to the display area AA, and are respectively transferred to at least two first connecting lines 411c, at least two second connecting lines 412c, at least two third connecting lines 413c and at least two fourth connecting lines 414c through the first connecting line 411b, the second connecting line 412b, the third connecting line 413b and the fourth connecting line 414b. The data voltage signal is respectively transmitted to the corresponding sub-pixel 10 by the first connecting line 411c, the second connecting line 412c, the third connecting line 413c and the fourth connecting line 414c. Figure 4 It can be seen that the first adapter line 411b, the second adapter line 412b, the third adapter line 413b and the fourth adapter line 414b are close to the display area AA relative to the first fan-out line 411a, the second fan-out line 412a, the third fan-out line 413a and the fourth fan-out line 414a, the first connection line 411c, the second connection line 412c, the third connection line 413c and the fourth connection line 414c are close to the display area AA relative to the first adapter line 411b, the second adapter line 412b, the third adapter line 413b and the fourth adapter line 414b, and the first fan-out line 411a, the second fan-out line 412a, the third fan-out line 413a and the fourth fan-out line 414a are far away from the display area AA, which is convenient for connection with the driver chip. The above-mentioned line arrangement is regular, which can reduce signal interference between different data buses 41.

[0089] For example, see Figure 4 The display panel includes a substrate, and a first gate layer 102, a second gate layer 103, a first source-drain metal layer 104, and a second source-drain metal layer 105 stacked on the substrate. Multiple fan-out lines can be located in the first gate layer 102 or the second gate layer 103. For example, two adjacent fan-out lines are located in different gate layers to share wiring pressure, improve space utilization, and increase the spacing between adjacent fan-out lines located in the same layer, thereby reducing the probability of short circuits. For example, the first fan-out line 411a and the third fan-out line 413a are located in the second gate layer 103, and the second fan-out line 412a and the fourth fan-out line 414a are located in the first gate layer 102. Alternatively, the first fan-out line 411a and the third fan-out line 413a are located in the first gate layer 102, and the second fan-out line 412a and the fourth fan-out line 414a are located in the second gate layer 103.

[0090] The first transfer line 411b, the second transfer line 412b, the third transfer line 413b, and the fourth transfer line 414b are located on the first source-drain metal layer 104, and the first connecting line 411c, the second connecting line 412c, the third connecting line 413c, and the fourth connecting line 414c are located on the second gate layer 103. Furthermore, the first fan-out line 411a and the second fan-out line 412a located on the first gate layer 102 are alternately arranged with the third fan-out line 413a and the fourth fan-out line 414a located on the second gate layer 103. This layered wiring method increases wiring space and increases the spacing between adjacent lines, making short circuits less likely to occur and improving the reliability of the display panel.

[0091] In some embodiments, as Figure 3A As shown, the display unit 20 includes at least four sub-pixels 10 located in the first row H1 and at least four sub-pixels 10 located in the second row H2; the display panel 100 also includes a plurality of control lines 60 for controlling the control switch K; the at least two control switches K1 corresponding to at least two adjacent sub-pixels 10 located in the same row are both connected to the same control line 60.

[0092] In some examples, reference Figure 3A The display unit 20 includes four adjacent columns of sub-pixels, including four sub-pixels 10 located in the first row H1, which are red sub-pixels, green sub-pixels, blue sub-pixels, and green sub-pixels, respectively; and four sub-pixels 10 located in the second row H2, which are blue sub-pixels, green sub-pixels, red sub-pixels, and green sub-pixels, respectively; wherein the four sub-pixels 10 in the first row H1 are connected to the third control switch K3, the first control switch K1, the fourth control switch K4, and the second control switch K2 in sequence. Figure 3A As shown, the third control switch K3 and the first control switch K1 are connected to the same control line 61, and the fourth control switch K4 and the second control switch K2 are connected to the same control line 62. Similarly, the fourth control switch K4 and the second control switch K2 correspondingly connected in sequence in the four sub-pixels 10 of the second row H2 are connected to the same control line 63, and the third control switch K3 and the first control switch K1 are connected to the same control line 64.

[0093] In other examples, refer to Figure 5A and Figure 6The display unit 20 includes eight adjacent columns of sub-pixels 10, and the display unit 20 includes four columns of first sub-pixel columns 210, two columns of second sub-pixel columns 220, and two columns of third sub-pixel columns 230; the display unit 20 includes at least eight sub-pixels 10 located in the first row H1 and eight sub-pixels 10 located in the second row H1, the eight sub-pixels 10 in the first row are divided into a first group of sub-pixels 10a and a second group of sub-pixels 10b, and the eight sub-pixels 10 in the second row are divided into a third group of sub-pixels 10c and a fourth group of sub-pixels 10d, and each group of sub-pixels 10 includes four adjacent sub-pixels 10.

[0094] The first group of sub-pixels 10a and the second group of sub-pixels 10b are red sub-pixels, green sub-pixels, blue sub-pixels and green sub-pixels respectively. The third group of sub-pixels 10c and the fourth group of sub-pixels 10d are blue sub-pixels, green sub-pixels, red sub-pixels and green sub-pixels respectively.

[0095] The four control switches K corresponding to the first group of sub-pixels 10a are all connected to the first control line 61, the four control switches K corresponding to the second group of sub-pixels 10b are all connected to the second control line 62; the four control switches corresponding to the third group of sub-pixels 10c are all connected to the third control line 63; the four control switches K corresponding to the fourth group of sub-pixels 10d are all connected to the fourth control line 64.

[0096] Exemplarily, the first control switch K1, the second control switch K2, the third control switch K3 and the fourth control switch K4 corresponding to the first group of sub-pixels 10a are all connected to the first control line 61, the first control switch K1, the second control switch K2, the third control switch K3 and the fourth control switch K4 corresponding to the second group of sub-pixels 10b are all connected to the second control line 62; the first control switch K1, the second control switch K2, the third control switch K3 and the fourth control switch K4 corresponding to the third group of sub-pixels 10c are all connected to the third control line 63; the first control switch K1, the second control switch K2, the third control switch K3 and the fourth control switch K4 corresponding to the fourth group of sub-pixels 10d are all connected to the fourth control line 64.

[0097] For example, the first control line 61 controls the first control switch K1, the second control switch K2, the third control switch K3, and the fourth control switch K4 connected to the first group of sub-pixels 10a to turn on, so that the sub-pixels in the first group of sub-pixels 10a are in a display state. The first control line 61, the second control line 62, the third control line 63, and the fourth control line 64 sequentially output control signals to control the control switches connected thereto to turn on in sequence, so that the sub-pixels in the first group of sub-pixels 10a, the sub-pixels in the second group of sub-pixels 10a, the sub-pixels in the third group of sub-pixels 10c, and the sub-pixels in the fourth group of sub-pixels 10d are displayed in sequence.

[0098] For example, referring to Figure 5A and Figure 6 The first data bus 411 is connected to the first type of first color sub-pixels 111 in the four columns of first sub-pixel columns 210 through four data lines DT2, DT4, DT6, and DT8, and the second data bus 412 is connected to the second type of first color sub-pixels 112 in the four columns of first sub-pixel columns 210 through four data lines DT2', DT4', DT6', and DT8'; the third data bus 413 is connected to the second color sub-pixels 12 in the two columns of second sub-pixel columns 220 and the two columns of third sub-pixel columns 230 through four data lines DT1, DT3, DT5, and DT7, and the fourth data bus 414 is connected to the third color sub-pixels 13 in the two columns of second sub-pixel columns 220 and the two columns of third sub-pixel columns 230 through four data lines DT1', DT3', DT5', and DT7'.

[0099] It should be noted that each of the above-mentioned data buses 41 is connected to four data lines DT in a display unit 20, and the four data lines are all connected to sub-pixels of the same color. This arrangement can, on the one hand, reduce the number of fan-out lines in the data bus 41 and simplify the line arrangement; on the other hand, each data bus 41 controls the gamma voltage of a color, and further controls the threshold voltage compensation time and voltage range of the sub-pixel corresponding to a color, thereby eliminating the additional power consumption caused by jumping between different colors, and improving the quality and service life of the display panel 100.

[0100] In some embodiments, the following describes the film layer wiring design of the control lines and control switches in the display panel.

[0101] Reference Figure 4 The first control line 61, the second control line 62, the third control line 63 and the fourth control line 64 all extend along the row direction X and are arranged along the column direction Y. A plurality of control switches K are arranged between the plurality of control lines 60 and the plurality of sub-pixels 10. The control switch K includes an active layer pattern 50a, a gate pattern 50b, a first pole pattern 50c and a second pole pattern 50d. The gate pattern 50b overlaps with the active layer pattern 50a, and one end of the gate pattern 50b is connected to the corresponding control line 60. The first pole pattern 50c is connected to the active layer pattern 50a and to the corresponding data bus 41. The second pole pattern 50d is connected to the active layer pattern 50a and to the corresponding data line DT. When the data bus 41 includes a fan-out line 410, a transfer line 420 and at least two connecting lines 430, the first pole pattern 50c is connected to one connecting line 430 of the corresponding data bus 41.

[0102] A first control line 61, a second control line 62, a third control line 63, and a fourth control line 64, and a plurality of control switches are arranged in the peripheral area BB. The plurality of control switches are arranged along the row direction X, and two control switches correspond to a column of sub-pixels. The two control switches are arranged on one side of a column of sub-pixels, in a direction Z pointing from the peripheral area to the display area. A plurality of fan-out lines, adapter lines, control lines, control switches, and a plurality of sub-pixels are sequentially arranged. A connecting line crosses the plurality of control lines, connecting the adapter lines and the control switches.

[0103] Exemplarily, the display panel also includes an active layer 101 arranged between the substrate and the first gate layer, wherein the first control line 61, the second control line 62, the third control line 63 and the fourth control line 64 are arranged in the first source-drain metal layer 104, the active layer pattern 50a of the multiple control switches K is arranged in the active layer 101, the first pole pattern 50c and the second pole pattern 50d are arranged in the first source-drain metal layer 104, and the gate pattern 50b is arranged in the first gate layer 102.

[0104] In some embodiments, reference Figure 7A The display unit 20 includes four adjacent columns of sub-pixels 10; the first data bus 411 and the second data bus 412 are the same data bus, serving as the first common data bus 401, and the third data bus 413 and the fourth data bus 414 are the same data bus, serving as the second common data bus 402; the first common data bus 401 is connected to the first type of first color sub-pixels 111 and the second type of first color sub-pixels 112 in the two first sub-pixel columns 210 through at least two data lines DT; the second common data bus 402 is connected to the second color sub-pixels 12 and the third color sub-pixels 13 in the second sub-pixel column 220 and the third sub-pixel column 230 through at least two data lines DT.

[0105] For example, referring to Figure 7A The display unit 20 includes four adjacent columns of sub-pixels 10, namely the second sub-pixel column 220, the first-category first sub-pixel column 2101, the third sub-pixel column 230, and the second-category first sub-pixel column 2102. The first shared data bus 401 is connected to the first-category first-color sub-pixel 111 and the second-category first-color sub-pixel 112 through corresponding data lines DT, and the second shared data bus 402 is connected to the second-color sub-pixel 12 and the third-color sub-pixel 13 through corresponding data lines DT. For example, the first-category first-color sub-pixel 111 and the second-category first-color sub-pixel 112 are both green sub-pixels, that is, the first shared data bus 401 controls the gamma voltage range of the same color, and the second shared data bus 402 controls the gamma voltage range of the other two colors. This configuration can reduce the number of times the first shared data bus 401 and the second shared data bus 402 jump between gamma voltages of different colors. For example, referring to Figure 7BIn the initial data signal transmitted by the second common data bus 402, two red gamma voltages are adjacent, and two blue gamma voltages are adjacent. Compared with some technologies (such as Figure 1 and Figure 2 ) The data voltage transmitted by the data bus frequently jumps between the gamma voltages of different colors in sequence. The number of gamma voltage jumps of the initial data signal transmitted by the second common data bus 402 is halved, and the gamma voltage jump range is reduced. The first common data bus 401 does not perform gamma voltage jumps, which can reduce power consumption and improve the quality and service life of the display panel.

[0106] In some embodiments, as Figure 7A As shown, the first shared data bus 401 includes a shared first fan-out line 401a, a shared first transfer line 401b and at least two shared first connection lines 401c; the shared first fan-out line 401a is connected to the shared first transfer line 401b, at least two shared first connection lines 401c are connected to the shared first transfer line 401b, and one shared first connection line 401c is connected to the first control switch K1 and the second control switch K2 corresponding to a column of sub-pixels 10; the second shared data bus 402 includes a shared second fan-out line 402a, a shared second transfer line 402b and at least two shared second connection lines 402c; the shared second fan-out line 402a is connected to the shared second transfer line 402b, at least two shared second connection lines 402c are connected to the shared second transfer line 402b, and one shared second connection line 402c is connected to the third control switch K3 and the fourth control switch K4 corresponding to a column of sub-pixels 10.

[0107] For example, referring to Figure 7A The first shared data bus 401 includes a shared first fan-out line 401a, a shared first transfer line 401b, and two shared first connection lines 401c. The shared first fan-out line 401a is connected to the shared first transfer line 401b, and the two shared first connection lines 401c are connected to the shared first transfer line 401b. One shared first connection line 401c is connected to a first control switch K1 and a second control switch K2 corresponding to a column of sub-pixels 10. The first control switch K1 corresponding to one column of sub-pixels is connected to the corresponding first-category first-color sub-pixel 111 through the data line DT2, and the second control switch K2 is connected to the corresponding second-category first-color sub-pixel 112 through the data line DT2'. The first control switch K1 corresponding to another column of sub-pixels is connected to the corresponding first-category first-color sub-pixel 111 through the data line DT4, and the second control switch K2 is connected to the corresponding second-category first-color sub-pixel 112 through the data line DT4'. Similarly, the second common data bus 402 is respectively connected to the second type of first color sub-pixel 112 , second color sub-pixel 12 , and third color sub-pixel 13 through corresponding data lines.

[0108] In some embodiments, the following describes a film layer wiring design for sharing data buses and data lines in a display panel.

[0109] Reference Figure 8 The shared first transfer line 401b and the second shared transfer line 402b both extend along the row direction X and are arranged along the column direction Y; the shared first fan-out line 401a and the shared second fan-out line 402a are arranged on the side of the shared first transfer line 401b and the shared second transfer line 402b away from the multiple sub-pixels 10; the shared first connection line 401c and the shared second connection line 402c are arranged on the side of the shared first transfer line 401b and the shared second transfer line 402b close to the multiple sub-pixels 10.

[0110] Exemplarily, it should be noted that the display panel 100 includes a display area AA and a border area BB, the border area BB is arranged on at least one side of the display area AA, multiple sub-pixels and multiple data lines are arranged in the display area AA, and the data bus group and the control switch group are located in the peripheral area BB.

[0111] The shared first fan-out line 401a and the shared second fan-out line 402a are used to transmit data voltage signals from the frame area BB to the display area AA, and are respectively transferred to at least two shared first connecting lines 401c and at least two shared second connecting lines 402c through the shared first connecting line 401b and the shared second connecting line 402b. The shared first connecting line 401c and the shared second connecting line 402c transmit the data voltage signals to the corresponding sub-pixels 10. Therefore, according to the signal transmission method combined with Figure 8 It can be seen that the shared first adapter line 401b and the shared second adapter line 402b are closer to the display area AA relative to the shared first fan-out line 401a and the shared second fan-out line 402a, the shared first connecting line 401c and the shared second connecting line 402c are closer to the display area AA relative to the shared first adapter line 401b and the shared second adapter line 402b, and the shared first fan-out line 401a and the shared second fan-out line 402a are away from the display area AA, which is convenient for connection with the driver chip. The above-mentioned line arrangement is regular, which can reduce signal interference between different data buses 41.

[0112] Exemplarily, the display panel includes a substrate, and a first gate layer 102, a second gate layer 103, a first source-drain metal layer 104, and a second source-drain metal layer 105 stacked on the substrate. Multiple shared fan-out lines may be located in the first gate layer 102 or the second gate layer 103. For example, a shared first fan-out line 401a may be located in the second gate layer 103, and a shared second fan-out line 402a may be located in the first gate layer 102. Alternatively, a shared second fan-out line 402a may be located in the first gate layer 102, and the shared first fan-out line 401a and the shared second fan-out line 402c may be located in the second gate layer 103. A shared first transfer line 401b and a shared second transfer line 402b may be located in the first source-drain metal layer 104, and a shared first connection line 401c and a shared second connection line 402c may be located in the second gate layer 102. The shared second fan-out line 402a located in the first gate layer 102 and the shared first fan-out line 401a located in the second gate layer 103 are alternately arranged. The above-mentioned layered wiring method can increase the wiring space, and the interval between two adjacent lines is larger, which is less likely to cause short circuits, thereby improving the reliability of the display panel.

[0113] In some embodiments, as Figure 7A As shown, the display unit 20 includes at least a first pixel group 21 and a second pixel group 22 located in a first row H1, and a second pixel group 22 and a first pixel group 21 located in a second row H2; the first pixel group 21 includes a first sub-pixel 111 of a first type and a second color sub-pixel 12, and the second pixel group 22 includes a first sub-pixel 112 of a second type and a third color sub-pixel 13. The display panel 100 further includes a plurality of control lines 60 for controlling the control switch K.

[0114] Among them, the first control switch K1 and the third control switch K3 corresponding to the first pixel group 21 of the first row H1 are both connected to the first control line 61, and the second control switch K2 and the fourth control switch K4 corresponding to the second pixel group 22 of the first row H1 are both connected to the second control line 62; the second control switch K2 and the fourth control switch K4 corresponding to the second pixel group 22 of the second row H2 are both connected to the third control line 63, and the first control switch K1 and the third control switch K3 corresponding to the first pixel group 21 of the second row H2 are both connected to the fourth control line 64.

[0115] For example, referring to Figure 7AThe display unit 20 includes a first pixel group 21 and a second pixel group 22 located in a first row H1, and a second pixel group 22 and a first pixel group 21 located in a second row H2. The first pixel group 21 includes red sub-pixels and green sub-pixels in sequence, and the second pixel group 22 includes blue sub-pixels and green sub-pixels in sequence. The first pixel group 21 in the first row H1 is connected to the third control switch K3, the first control switch K1 and the first control line 61 in sequence, and the second pixel group 22 in the first row H1 is connected to the fourth control switch K4 and the second control switch K2 and the second control line 62 in sequence. Figure 7A As shown, the third control switch K3 and the first control switch K1 are connected to the same control line 61, and the fourth control switch K4 and the second control switch K2 are connected to the same control line 62. Similarly, the fourth control switch K4 and the second control switch K2 correspondingly connected in sequence in the second pixel group 22 of the second row H2 are connected to the third control line 63, and the third control switch K3 and the first control switch K1 correspondingly connected in sequence in the first pixel group 21 of the second row H2 are connected to the fourth control line 64.

[0116] For example, the first control line 61 controls the first control switch K1 and the third control switch K3 connected to the first pixel group 21 in the first row H1 to turn on, causing the sub-pixels in the first pixel group 21 to be in a display state. The second control line 62 controls the second control switch K2 and the fourth control switch K4 connected to the second pixel group 22 in the first row H1 to turn on, causing the sub-pixels in the second pixel group 22 to be in a display state. The first control line 61, the second control line 62, the third control line 63, and the fourth control line 64 sequentially output control signals to control the control switches connected thereto to turn on in sequence, so that the sub-pixels in the first pixel group 21 and the second pixel group 22 in the first row H1, and the sub-pixels in the first pixel group 21 and the second pixel group 22 in the second row H2 are displayed in sequence.

[0117] In some embodiments, as Figure 8As shown, the first control line 61, the second control line 62, the third control line 63 and the fourth control line 64 all extend along the row direction X and are arranged along the column direction Y. The two control switches K corresponding to a column of sub-pixels constitute a common control switch K1. The common control switch K1 is arranged between the multiple control lines 60 and the multiple sub-pixels 10. The common control switch K1 includes a common active layer pattern 501a, two gate patterns 501b, a common first electrode pattern 501c, and two second electrode patterns 501d. The two gate patterns 501b overlap with the common active layer pattern 501a. The two gate patterns 501b are respectively located at the common first electrode pattern 501c and the second electrode pattern 501d. On both sides of the pole pattern 501c, one end of each gate pattern 501b is connected to the corresponding control line 60, the common first pole pattern 501c is connected to the common active layer pattern 501a, and is connected to the corresponding data bus 41, the two second pole patterns 501d are connected to the active layer pattern 501a, and the two second pole patterns 501b are respectively connected to the corresponding data lines DT; when the common data bus 42 includes a common fan-out line 42a, a common transfer line 42b and at least two common connecting lines 42c, the common first pole pattern 501c is connected to a common connecting line 42c of the corresponding common data bus 42.

[0118] A first control line 61, a second control line 62, a third control line 63, and a fourth control line 64, and a plurality of common control switches GK are arranged in the peripheral area BB. The plurality of common control switches GK are arranged along the row direction X, and one common control switch (two control switches) corresponds to a column of sub-pixels. The common control switches are arranged on one side of a column of sub-pixels, in the direction Z from the peripheral area to the display area. A plurality of common fan-out lines, a common transfer line, a control line, a control switch, and a plurality of sub-pixels are sequentially arranged. A connecting line crosses the plurality of control lines, connecting the transfer line and the control switch.

[0119] Exemplarily, the display panel also includes an active layer 101 arranged between the substrate and the first gate layer, wherein the first control line 61, the second control line 62, the third control line 63 and the fourth control line 64 are arranged in the first source-drain metal layer 104, the common active layer pattern 501a of multiple common control switches GK is arranged in the active layer, the common first pole pattern 501c and the second pole pattern 501d are arranged in the first source-drain metal layer 104, and the common gate pattern 501b is arranged in the first gate layer 102.

[0120] In some embodiments, as Figure 3A 、 Figure 5A 、 Figure 7A and Figure 9As shown, in the case where the display unit 20 includes at least four adjacent columns of sub-pixels 10, each adjacent four columns of sub-pixels include a second sub-pixel column 220, a first-category first sub-pixel column 2101, a third sub-pixel column 230, and a second-category first sub-pixel column 2102 arranged in sequence, wherein the second sub-pixel column 220, the first-category first sub-pixel column 2101 and the third sub-pixel column 230, the second-category first sub-pixel column 2102 are arranged in mirror symmetry, and the data line DT connecting the second sub-pixel column 220 and the first-category first sub-pixel column 2101 and the data line DT connecting the third sub-pixel column 230 and the second-category first sub-pixel column 2102 are arranged in mirror symmetry.

[0121] like Figure 3A 、 Figure 7A and Figure 9 As shown, the display unit includes four adjacent columns of sub-pixels, which are respectively a second sub-pixel column 220, a first-category first sub-pixel column 2101, a third sub-pixel column 230, and a second-category first sub-pixel column 2102 arranged in sequence. The boundary line between the first-category first sub-pixel column 2101 and the third sub-pixel column 230 is used as the symmetry axis O. The second sub-pixel column 220 and the second-category first sub-pixel column 2102 are mirror-symmetrical about the symmetry axis O, and the first-category first sub-pixel column 2101 and the third sub-pixel column 230 are mirror-symmetrical about the symmetry axis O. The mirror symmetry of the two sub-pixel columns refers to the mirror symmetry of the patterns set in each film layer in the sub-pixel. The data lines DT1, DT1', DT2, and DT2' connecting the second sub-pixel column 220 and the first-category first sub-pixel column 2101 are mirror-symmetrical to the data lines DT3, DT3', DT4, and DT4' connecting the third sub-pixel column 230 and the second-category first sub-pixel column 2104 about the symmetry axis O. For example, the connection position between the data line DT1 and the second-color sub-pixel 12 is located in the left half area of ​​the sub-pixel, and the connection position between the data line DT4' and the second-category first-color sub-pixel 112 is located in the right half area of ​​the sub-pixel, and the two connection positions are mirror-symmetrical.

[0122] like Figure 5A As shown, in the case where the display unit 20 includes eight adjacent columns of sub-pixels 10, the eight columns of sub-pixels are divided into two groups, with each adjacent four columns of sub-pixels as a group, and each adjacent four columns of sub-pixels include a second sub-pixel column 220, a first-type first sub-pixel column 2101, a third sub-pixel column 230 and a second-type first sub-pixel column 2102 arranged in sequence. The film layer settings and the corresponding mirror image alignment of the data lines in each adjacent four columns of sub-pixels can refer to the above description.

[0123] For example, referring to Figure 9The arrangement of the sub-pixels and data lines described above makes the circuit arrangement within the display unit 20 more orderly, and is not affected by alignment offset during the manufacturing process, so that the pixel parasitism at different positions is consistent, ensuring consistent brightness within the display unit 20, avoiding uneven brightness caused by parasitic differences, and further improving the uniformity of the display panel.

[0124] Exemplarily, each sub-pixel 10 includes a pixel driving circuit 80, which can be a 7T1C, 8T1C or 9T1C circuit, wherein T represents a transistor, and the number before T represents the number of transistors, C represents a capacitor, and the number before C represents the number of capacitors. Exemplarily, 7T1C represents 7 transistors and 1 capacitor.

[0125] In some embodiments, the introduction is based on Figure 10 The structure of the pixel driving circuit 80 shown is a 7T1C pixel driving circuit. The pixel driving circuit 80 includes: a second reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a first reset transistor T7.

[0126] For example, Figure 10 As shown, the second reset transistor T1 includes a gate, a first electrode, and a second electrode. The gate of the second reset transistor T1 is electrically connected to the third scan signal line Gate3, the first electrode of the second reset transistor T1 is electrically connected to the first initialization signal line Vinit1, and the second electrode of the second reset transistor T1 is electrically connected to the first node N1. The second reset transistor T1 is configured to reset the gate (first node N1) of the driving transistor T3 in response to a reset signal received at the third scan signal line Gate3.

[0127] For example, Figure 10 As shown, the compensation transistor T2 includes a gate, a first electrode, and a second electrode. The gate of the compensation transistor T2 is electrically connected to the first scan signal line Gate1, the first electrode of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode of the compensation transistor T2 is electrically connected to the third node N3. The compensation transistor T2 is configured to reset or threshold-compensate the driving transistor T3 in response to a scan signal received at the first scan signal line Gate1.

[0128] For example, Figure 10As shown, the driving transistor T3 includes a gate, a first electrode, and a second electrode. The gate of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode of the driving transistor T3 is electrically connected to the third node N3. The driving transistor T3 is configured to generate a driving current signal.

[0129] For example, Figure 10 As shown, the data write transistor T4 includes a gate, a first electrode, and a second electrode. The gate of the data write transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the data write transistor T4 is electrically connected to the data signal line Data, and the second electrode of the data write transistor T4 is electrically connected to the second node N2. The data write transistor T4 is configured to transmit a data signal received on the data signal line Data to the driving transistor T3 in response to a scan signal received on the first scan signal line Gate1.

[0130] For example, Figure 10 As shown, the first emission control transistor T5 includes a gate, a first electrode, and a second electrode. The gate of the first emission control transistor T5 is electrically connected to the emission control signal line EM, the first electrode of the first emission control transistor T5 is electrically connected to the power signal line ELVDD, and the second electrode of the first emission control transistor T5 is electrically connected to the second node N2. The first emission control transistor T5 is configured to transmit a power signal received on the power signal line ELVDD to the driving transistor T3 in response to the emission control signal received on the emission control signal line EM.

[0131] For example, Figure 10 As shown, the second light-emission control transistor T6 includes a gate, a first electrode, and a second electrode. The gate of the second light-emission control transistor T6 is electrically connected to the light-emission control signal line EM, the first electrode of the second light-emission control transistor T6 is electrically connected to the third node N3, and the second electrode of the second light-emission control transistor T6 is electrically connected to the fourth node N4. The second light-emission control transistor T6 is configured to transmit a driving current signal to the light-emitting device L in response to a light-emission control signal received on the light-emission control signal line EM, thereby driving the light-emitting device L to emit light.

[0132] For example, Figure 10As shown, the first reset transistor T7 includes a gate, a first electrode, and a second electrode. The gate of the first reset transistor T7 is electrically connected to the second scan signal line Gate2, the first electrode of the first reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second electrode of the first reset transistor T7 is electrically connected to the fourth node N4. The first reset transistor T7 is configured to: in response to a reset signal received at the second scan signal line Gate2, transmit the initialization signal received at the second initialization signal line Vinit2 to the light-emitting device L to reset the light-emitting device L.

[0133] Exemplarily, the anode of the light emitting device L is electrically connected to the fourth node N4, and the cathode of the light emitting device L is electrically connected to the reference voltage line ELVSS.

[0134] It should be noted that the first electrode of the transistor disclosed herein is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0135] In the circuit provided by the embodiments of the present disclosure, nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0136] For example, Figure 10 As shown, the pixel driving circuit 80 also includes: a capacitor Cst, the capacitor Cst includes: a first plate Cst1 and a second plate Cst2, the first plate Cst1 of the capacitor Cst is electrically connected to the first node N1, and the second plate Cst2 of the capacitor Cst is electrically connected to the power signal line ELVDD.

[0137] Combine Figure 9 In the film layer setting of the display panel, a sub-pixel 10 includes multiple patterns located in each film layer, and the multiple patterns include the active layer pattern, gate pattern, source pattern and drain pattern of the transistor in the pixel driving circuit of the sub-pixel, the first plate pattern and the second substrate pattern of the capacitor. The display panel also includes multiple signal line patterns connected to the pixel driving circuit, such as data line patterns, power signal line patterns, etc.

[0138] The embodiment of the present disclosure further provides a display device 1000, which includes the display panel 100 provided by any of the above embodiments. Therefore, the display device 1000 provided by the present invention has all the beneficial effects of the display panel 100 provided by any of the above embodiments, which will not be described in detail here.

[0139] For example, referring to Figure 3A The display device 1000 further includes a driver chip 70. The driver chip 70 is electrically connected to the data bus group 40. The driver chip 70 is configured to provide a driving signal to the display panel 100 to control the display of the display panel 100.

[0140] The display device 1000 can be any device that displays either moving (e.g., video) or stationary (e.g., still images), and whether textual or graphical. More specifically, it is contemplated that the embodiments described herein can be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, augmented reality (AR) devices, virtual reality (VR) devices, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of jewelry), and any other product or component having a display function.

[0141] For example, Figure 11 As shown, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a car display, an aircraft display, a wearable device, a virtual reality (VR) device, etc.

[0142] The display device 1000 may be any one of a flat display device, a curved display device, a foldable display device, and a rollable display device.

[0143] The display device 1000 includes a display panel 100. The display panel 100 may be an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a micro light emitting diode display panel, etc., which is not specifically limited in the embodiment of the present disclosure.

[0144] like Figure 5B and Figure 7B As shown, some embodiments of the present disclosure also provide a driving method applied to the display panel 100 provided by any of the above embodiments. The driving method is based on the display panel 100 provided by the above embodiments. Therefore, the driving method provided by the present disclosure has all the beneficial effects of the display panel 100 provided by any of the above embodiments, which will not be repeated here.

[0145] In some embodiments, reference Figure 3A 、 Figure 5B and Figure 7B , in the first period t1 of the first scanning time T10, controlling the first data bus 411, the second data bus 412, the third data bus 413, and the fourth data bus 414 to output display signals respectively, and controlling the first control switch K1 connected to the first sub-pixel column 2101 of the first type and the third control switch K3 connected to the second sub-pixel column 220 in the display unit 20 to be in an open state;

[0146] In the first time period t3 of the second scanning time T20, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the second control switch K2 connected to the first sub-pixel column 2101 of the first type and the fourth control switch K4 connected to the second sub-pixel column 220 in the display unit 20 are controlled to be in the open state.

[0147] For example, referring to Figure 3A 、 Figure 5B and Figure 7A The display unit includes at least four adjacent columns of sub-pixels, wherein, when the first control switch K1 connected to the first-category first sub-pixel column 2101 and the third control switch K3 connected to the second sub-pixel column 220 are in an open state, the first control switch K1 controls the first-category first-color sub-pixel 111 located in the first-category first sub-pixel column 2101 to be displayed, and the third control switch K3 controls the second-color sub-pixel 12 located in the second sub-pixel column 220 to be displayed; when the second control switch K2 connected to the first-category first sub-pixel column 2101 and the fourth control switch K4 connected to the second sub-pixel column 220 are in an open state, the second control switch K2 controls the second-category first-color sub-pixel 112 located in the first-category first sub-pixel column 2101 to be displayed, and the fourth control switch K4 controls the third-color sub-pixel 13 located in the second sub-pixel column 220 to be displayed.

[0148] In some embodiments, reference Figure 5A and Figure 5B The display unit 20 includes eight adjacent columns of sub-pixels 10, and the display unit 20 includes a first sub-display unit 201 and a second sub-display unit 202 arranged along the row direction X; the first sub-display unit 201 includes four adjacent columns of sub-pixels, and the second sub-display unit 202 includes four adjacent columns of sub-pixels.

[0149] In the first time period t1 of the first scanning time T10, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the second control switch K2 connected to the second type first sub-pixel column 2102, the fourth control switch K4 connected to the third sub-pixel column 230, the first control switch K1 connected to the first type first sub-pixel column 2101, and the third control switch K3 connected to the second sub-pixel column 220 in the first sub-display unit 201 are controlled to be in the open state.

[0150] In the second time period t2 of the first scanning time T10, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the first control switch K1 connected to the first type first sub-pixel column 2101, the second control switch K2 connected to the second type first sub-pixel column 2102, the third control switch K3 connected to the second sub-pixel column 220, and the fourth control switch K4 connected to the third sub-pixel column 230 in the second sub-display unit 202 are controlled to be in an open state.

[0151] In the first time period t3 of the second scanning time T20, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the first control switch K1 connected to the second type first sub-pixel column 2102, the third control switch K3 connected to the third sub-pixel column 230, the second control switch K2 connected to the first type first sub-pixel column 2101, and the fourth control switch K4 connected to the second sub-pixel column 220 in the first sub-display unit 201 are controlled to be in an open state.

[0152] In the second time period t4 of the second scanning time T20, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the second control switch K2 connected to the first type first sub-pixel column 2101, the first control switch K1 connected to the second type first sub-pixel column 2102, the fourth control switch 514 connected to the second sub-pixel column 220, and the third control switch K3 connected to the third sub-pixel column 230 in the second sub-display unit 202 are controlled to be in an open state.

[0153] For example, referring to Figure 5A and Figure 5B In the case where the display unit 20 includes eight adjacent columns of sub-pixels 10, the display unit 20 includes at least eight sub-pixels 10 located in the first row H1 and eight sub-pixels 10 located in the second row H1. The eight sub-pixels 10 in the first row are divided into a first group of sub-pixels 10a and a second group of sub-pixels 10b. The eight sub-pixels 10 in the second row are divided into a third group of sub-pixels 10c and a fourth group of sub-pixels 10d. Each group of sub-pixels 10 includes four adjacent sub-pixels 10.

[0154] Among them, in the first time period t1 of the first scanning time T10, the sub-pixels in the first group of sub-pixels 10a are displayed, in the second time period t2 of the first scanning time T10, the sub-pixels in the second group of sub-pixels 10b are displayed, in the first time period t3 of the second scanning time T20, the sub-pixels in the third group of sub-pixels 10c are displayed, and in the second time period t4 of the second scanning time T20, the sub-pixels in the fourth group of sub-pixels 10d are displayed.

[0155] In some embodiments, reference Figure 3A 、 Figure 3B 、 Figure 7A and Figure 7B In the second period t2 of the first scanning time T10, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the second control switch K2 connected to the second type first sub-pixel column 2102 and the fourth control switch K4 connected to the third sub-pixel column 230 in the display unit are controlled to be in an open state; in the second period t4 of the second scanning time T20, the first data bus 411, the second data bus 412, the third data bus 413 and the fourth data bus 414 are controlled to output display signals respectively, and the first control switch K1 connected to the second type first sub-pixel column 2102 and the third control switch K3 connected to the third sub-pixel column 230 in the display unit 20 are controlled to be in an open state.

[0156] For example, referring to Figure 3A 、 Figure 3B 、 Figure 7A and Figure 7BThe display unit includes at least four adjacent columns of sub-pixels, wherein, when the second control switch K2 connected to the second-category first sub-pixel column 2102 and the fourth control switch K4 connected to the third sub-pixel column 230 are in an open state, the second control switch K2 controls the second-category first-color sub-pixel 112 located in the second-category first sub-pixel column 2102 to be displayed, and the fourth control switch K4 controls the third-color sub-pixel 13 located in the third sub-pixel column 230 to be displayed; when the first control switch K1 connected to the second-category first sub-pixel column 2102 and the third control switch K3 connected to the third sub-pixel column 230 are in an open state, the first control switch K1 controls the first-category first-color sub-pixel 111 located in the second-category first sub-pixel column 2102 to be displayed, and the third control switch K3 controls the second-color sub-pixel 12 located in the third sub-pixel column 230 to be displayed.

[0157] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0158] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: include: A plurality of sub-pixels are arranged in an array, the plurality of sub-pixels include first color sub-pixels, second color sub-pixels, and third color sub-pixels, the first color sub-pixels include first-type first color sub-pixels and second-type first color sub-pixels; the plurality of sub-pixels include at least one display unit, the display unit includes at least four adjacent columns of sub-pixels, at least two columns of sub-pixels in the at least four columns of sub-pixels are first sub-pixel columns, a column of other sub-pixels is arranged between every two first sub-pixel columns, and at least two columns of first sub-pixel columns include first-type first sub-pixel columns and second-type first sub-pixel columns arranged in sequence, wherein the first-type first sub-pixel columns are arranged in a sequential manner. The pixel column includes a first type of first color sub-pixels and a second type of first color sub-pixels sequentially arranged along the column direction, and the second type of first sub-pixel column includes a second type of first color sub-pixels and a first type of first color sub-pixels sequentially arranged along the column direction; the display unit further includes at least one second sub-pixel column and at least one third sub-pixel column sequentially arranged along the row direction, and the first sub-pixel column is located between the second sub-pixel column and the third sub-pixel column; the second sub-pixel column includes a second color sub-pixel and a third color sub-pixel sequentially arranged along the column direction, and the third sub-pixel column includes a third color sub-pixel and a second color sub-pixel sequentially arranged along the column direction; At least one data line group, comprising a plurality of data lines, connected to the display unit, wherein a column of sub-pixels is connected to two data lines, and one data line is connected to pixels of the same type in the column of sub-pixels; at least one data bus group, comprising a plurality of data buses, the data bus group being connected to the display unit; the data bus group comprising a first data bus, a second data bus, a third data bus, and a fourth data bus, the first data bus being connected to the first-color sub-pixels of the first type in the at least two first sub-pixel columns via at least two data lines, the second data bus being connected to the first-color sub-pixels of the second type in the at least two first sub-pixel columns via at least two data lines, the third data bus being connected to the second-color sub-pixels of the at least one second sub-pixel column and at least one third sub-pixel column via at least two data lines, and the fourth data bus being connected to the third-color sub-pixels of the at least one second sub-pixel column and at least one third sub-pixel column via at least two data lines; at least one control switch group, comprising a plurality of control switches, connected to the data bus group; the control switch group comprising a first control switch, a second control switch, a third control switch, and a fourth control switch, wherein the first data bus is connected to each data line connected thereto via the first control switch, the first data bus is connected to each data line connected thereto via the second control switch, the third data bus is connected to each data line connected thereto via the third control switch, and the fourth data bus is connected to each data line connected thereto via the fourth control switch; The display panel is configured to, during a first period of a first scanning time, control the first data bus, the second data bus, the third data bus, and the fourth data bus to respectively output display signals, and control the first control switch connected to the first sub-pixel column of the first type and the third control switch connected to the second sub-pixel column in the display unit to be in an open state; During the first period of the second scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the second control switch connected to the first sub-pixel column of the first type and the fourth control switch connected to the second sub-pixel column in the display unit are controlled to be in an open state.

2. The display panel according to claim 1, wherein: The data bus includes a fan-out line, a transfer line and at least two connecting lines; The fan-out line is connected to the adapter line, the at least two connecting lines are connected to the adapter line, and the connecting line is connected to the control switch.

3. The display panel according to claim 2, wherein: The first data bus includes a first fan-out line, a first transfer line and at least two first connection lines; The first fan-out line is connected to the first adapter line, the at least two first connection lines are connected to the first adapter line, and the first connection line is connected to the first control switch; The second data bus includes a second fan-out line, a second transfer line and at least two second connection lines; The second fan-out line is connected to the second patch line, the at least two second connection lines are connected to the second patch line, and the second connection line is connected to the second control switch; The third data bus includes a third fan-out line, a third transfer line and at least two third connection lines; The third fan-out line is connected to the third transfer line, the at least two third connection lines are connected to the third transfer line, and the third connection line is connected to the third control switch; The fourth data bus includes a fourth fan-out line, a fourth transfer line and at least two fourth connection lines; The fourth fan-out line is connected to the fourth transition line, the at least two fourth connection lines are connected to the fourth transition line, and the fourth connection line is connected to the fourth control switch.

4. The display panel according to claim 3, wherein: The first patch cord, the second patch cord, the third patch cord, and the fourth patch cord all extend in a row direction and are arranged in a column direction; The first fan-out line, the second fan-out line, the third fan-out line, and the fourth fan-out line are all arranged on a side of the first transfer line, the second transfer line, the third transfer line, and the fourth transfer line away from the plurality of sub-pixels; The first connection line, the second connection line, the third connection line and the fourth connection line all extend along the column direction and are arranged on a side of the first transfer line, the second transfer line, the third transfer line and the fourth transfer line close to the plurality of sub-pixels.

5. The display panel according to claim 1, wherein: The display unit includes at least four sub-pixels located in a first row and at least four sub-pixels located in a second row; the display panel further includes a plurality of control lines for controlling the control switches; The at least two control switches corresponding to at least two adjacent sub-pixels in the same row are both connected to the same control line.

6. The display panel according to claim 5, wherein: The display unit includes eight adjacent columns of sub-pixels, wherein the display unit includes four first sub-pixel columns, two second sub-pixel columns, and two third sub-pixel columns; The display unit includes at least eight sub-pixels located in a first row and eight sub-pixels located in a second row, the eight sub-pixels in the first row are divided into a first group of sub-pixels and a second group of sub-pixels, the eight sub-pixels in the second row are divided into a third group of sub-pixels and a fourth group of sub-pixels, and each group of sub-pixels includes four adjacent sub-pixels; The four control switches corresponding to the first group of sub-pixels are all connected to the first control line, the four control switches corresponding to the second group of sub-pixels are all connected to the second control line; the four control switches corresponding to the third group of sub-pixels are all connected to the third control line; the four control switches corresponding to the fourth group of sub-pixels are all connected to the fourth control line.

7. The display panel according to claim 6, wherein: The first control line, the second control line, the third control line and the fourth control line all extend in the row direction and are arranged in the column direction. The plurality of control switches are arranged between the plurality of control lines and the plurality of sub-pixels, and the control switches include an active layer pattern, a gate pattern, a first electrode pattern, and a second electrode pattern, wherein the gate pattern overlaps with the active layer pattern, and one end of the gate pattern is connected to the corresponding control line, the first electrode pattern is connected to the active layer pattern and to the corresponding data bus, and the second electrode pattern is connected to the active layer pattern and to the corresponding data line; In a case where the data bus includes a fan-out line, a transfer line, and at least two connection lines, the first pole pattern is connected to a corresponding connection line of the data bus.

8. The display panel according to claim 1, wherein: The display unit includes four adjacent columns of sub-pixels; The first data bus and the second data bus are the same data bus, serving as a first common data bus; the third data bus and the fourth data bus are the same data bus, serving as a second common data bus; The first shared data bus is connected to the first type of first color sub-pixels and the second type of first color sub-pixels in the two first sub-pixel columns through at least two data lines; the second shared data bus is connected to the second color sub-pixels and the third color sub-pixels in the second sub-pixel column and the third sub-pixel column through at least two data lines.

9. The display panel according to claim 8, wherein: The first shared data bus includes a shared first fan-out line, a shared first transfer line, and at least two shared first connection lines; The common first fan-out line is connected to the common first transfer line, the at least two common first connection lines are connected to the common first transfer line, and one common first connection line is connected to the first control switch and the second control switch corresponding to a column of sub-pixels; The second shared data bus includes a shared second fan-out line, a shared second transfer line, and at least two shared second connection lines; The common second fan-out line is connected to the common second transfer line, the at least two common second connection lines are connected to the common second transfer line, and one common second connection line is connected to the third control switch and the fourth control switch corresponding to a column of sub-pixels.

10. The display panel according to claim 9, wherein: The common first adapter wire and the common second adapter wire both extend in a row direction and are arranged in a column direction; The common first fan-out line and the common second fan-out line are arranged on a side of the common first transfer line and the common second transfer line away from the plurality of sub-pixels; The common first connecting line and the common second connecting line are arranged on a side of the common first transfer line and the common second transfer line close to the plurality of sub-pixels.

11. The display panel according to claim 9, wherein The display unit includes at least a first pixel group and a second pixel group located in a first row, and a second pixel group and a first pixel group located in a second row; the first pixel group includes a first sub-pixel of a first type and a second color sub-pixel, and the second pixel group includes a first sub-pixel of a second type and a third color sub-pixel, and the display panel further includes a plurality of control lines for controlling the control switches; Among them, the first control switch and the third control switch corresponding to the first pixel group in the first row are both connected to the first control line, and the second control switch and the fourth control switch corresponding to the second pixel group in the first row are both connected to the second control line; the second control switch and the fourth control switch corresponding to the second pixel group in the second row are both connected to the third control line, and the first control switch and the third control switch corresponding to the first pixel group in the second row are both connected to the fourth control line.

12. The display panel according to claim 11, wherein: The first control line, the second control line, the third control line and the fourth control line all extend in the row direction and are arranged in the column direction. Two control switches corresponding to a column of sub-pixels constitute a common control switch, the common control switch is arranged between the multiple control lines and the multiple sub-pixels, the common control switch includes a common active layer pattern, two gate patterns, a common first electrode pattern, and two second electrode patterns, the two gate patterns overlap with the common active layer pattern, the two gate patterns are respectively located on both sides of the common first electrode pattern, and one end of each of the gate patterns is connected to the corresponding control line, the common first electrode pattern is connected to the common active layer pattern and to the corresponding data bus, the two second electrode patterns are connected to the active layer pattern, and the two second electrode patterns are respectively connected to the corresponding data lines; In the case where the common data bus includes a common fan-out line, a common transfer line, and at least two common connection lines, the common first pole pattern is connected to a corresponding common connection line of the common data bus.

13. The display panel according to claim 1, wherein: In the case where the display unit includes at least four adjacent columns of sub-pixels, each of the four adjacent columns of sub-pixels includes a second sub-pixel column, a first-category first sub-pixel column, a third sub-pixel column, and a second-category first sub-pixel column arranged in sequence, wherein the second sub-pixel column, the first-category first sub-pixel column and the third sub-pixel column, the second-category first sub-pixel column are mirror-symmetrically arranged, and the data line connecting the second sub-pixel column and the first-category first sub-pixel column and the data line connecting the third sub-pixel column and the second-category first sub-pixel column are mirror-symmetrically arranged.

14. A display device, characterized in that: The device comprises the display panel according to any one of claims 1 to 13, and a driving chip connected to the data bus group.

15. A driving method for the display panel according to any one of claims 1 to 13, characterized in that: The driving method includes: The display unit includes eight adjacent columns of sub-pixels, and the display unit includes a first sub-display unit and a second sub-display unit arranged along a row direction; the first sub-display unit includes four adjacent columns of sub-pixels, and the second sub-display unit includes four adjacent columns of sub-pixels; During a first period of a first scanning time, controlling the first data bus, the second data bus, the third data bus, and the fourth data bus to output display signals respectively, and controlling the second control switch connected to the second type of first sub-pixel column, the fourth control switch connected to the third sub-pixel column, the first control switch connected to the first type of first sub-pixel column, and the third control switch connected to the second sub-pixel column in the first sub-display unit to be in an open state; During a second period of the first scanning time, the first data bus, the second data bus, the third data bus, and the fourth data bus are controlled to output display signals respectively, and the first control switch connected to the first sub-pixel column of the first type, the second control switch connected to the second sub-pixel column of the second type, the third control switch connected to the second sub-pixel column, and the fourth control switch connected to the third sub-pixel column in the second sub-display unit are controlled to be in an open state; During a first period of a second scanning time, controlling the first data bus, the second data bus, the third data bus, and the fourth data bus to output display signals respectively, and controlling the first control switch connected to the second type of first sub-pixel column, the third control switch connected to the third sub-pixel column, the second control switch connected to the first type of first sub-pixel column, and the fourth control switch connected to the second sub-pixel column in the first sub-display unit to be in an open state; During the second period of the second scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the second control switch connected to the first type of first sub-pixel column, the first control switch connected to the second type of first sub-pixel column, the fourth control switch connected to the second sub-pixel column, and the third control switch connected to the third sub-pixel column in the second sub-display unit are controlled to be in an open state.

16. The driving method according to claim 15, wherein: Also includes: During a second period of the first scanning time, the first data bus, the second data bus, the third data bus, and the fourth data bus are controlled to output display signals respectively, and the second control switch connected to the second sub-pixel column and the fourth control switch connected to the third sub-pixel column in the display unit are controlled to be in an open state; During the second period of the second scanning time, the first data bus, the second data bus, the third data bus and the fourth data bus are controlled to output display signals respectively, and the first control switch connected to the second type of first sub-pixel column and the third control switch connected to the third sub-pixel column in the display unit are controlled to be in an open state.

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