Code word synchronization method, receiver, network device and network system

Abstract

A codeword synchronization method, a receiver and a network device. The method determines a candidate bit from a plurality of bits of a data sequence received at a receiving end, determines a synchronization position based on the candidate bit, and the synchronization position is used to indicate the starting position of a codeword in the data sequence. The method is a self-synchronization method, and can achieve the technical effect of high-precision codeword synchronization of a data stream at a receiving end without inserting additional data into the data stream at a transmitting end, and its synchronization performance achieves high reliability.

Description

[0001] This application is a divisional application. The application number of the original application is 202010424884.9, and the original application date is May 19, 2020. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of communications, and in particular to a codeword synchronization method, a receiver, a network device, and a network system. Background Art

[0003] With the improvement of production technology, channel loss and noise have become key factors limiting data transmission rate and distance. The emergence of forward error correction provides error correction protection for data in transmission, thereby improving the data transmission rate and transmission distance of the channel. FEC can be divided into block code and convolutional code according to the different ways of processing information sequences. For block codes, they can be further divided into linear block codes and non-linear block codes. Linear block codes are widely used in the physical layer of the Open System Interconnection Model (OSI) of Ethernet and the media access control sublayer of the data link layer due to their simple coding implementation.

[0004] The error detection and correction functions of linear block codes must be implemented based on complete codewords. Therefore, it is necessary to determine the codeword boundaries in the data stream, that is, to find the beginning and end of a complete codeword. This process is called codeword synchronization or frame synchronization.

[0005] At present, the industry already has synchronization schemes suitable for linear block codes. Take the alignment marker (AM) synchronization scheme used in 200 / 400GE in the 802.3 standard as an example. In this scheme, a fixed AM sequence must be inserted into each codeword of a certain length. The receiving end can perform codeword synchronization by recognizing the AM sequence. However, the existence of the AM sequence is equivalent to inserting additional data into the data stream at the sending end, adding redundant information. Summary of the invention

[0006] The present application provides a self-synchronizing codeword synchronization method, a receiver and a network device, which are used to solve the technical problem of adding additional data in an AM synchronization solution.

[0007] In a first aspect, the present application provides a codeword synchronization method. The method comprises: step 1, receiving a data sequence, wherein the data sequence comprises a plurality of bits; step 2, determining a candidate bit in the data sequence, wherein the candidate bit is included in the plurality of bits; step 3, determining a synchronization position according to the candidate bit, wherein the synchronization position is used to indicate a starting position of a codeword in the data sequence.

[0008] The method is executed by a receiving device in the network. The method can achieve the technical effect of high-precision codeword synchronization of the data stream at the receiving end without inserting additional data into the data stream at the sending end, and the synchronization performance achieves high reliability.

[0009] In a possible implementation, the step three includes: verifying the candidate bit, and when the verification succeeds, determining the position of the candidate bit as the synchronization position.

[0010] In one possible implementation, at least one second test data block is divided in the data sequence according to the alternative bit, and the position of the alternative bit is the starting position of the at least one second test data block; the characteristic value of the at least one second test data block is verified, and when the verification is successful, the position of the alternative bit is determined to be the synchronization position.

[0011] In a possible implementation, verifying the characteristic value of the at least one second test data block includes: sequentially accumulating the characteristic value of each second test data block in the at least one second test data block to obtain a cumulative value, and the verification is successful when the cumulative value meets the synchronization condition.

[0012] In a possible implementation, the characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of test data blocks whose recheck bits are the same as the original check bits, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; wherein the length of the test data block is n bits, the first k bits of the test data block are information bits, the last nk bits of the test data block are the original check bits, the recheck bits are obtained based on the information bits, the length of the recheck bits is nk bits, and n and k are integers.

[0013] In one possible implementation, verifying the characteristic value of the at least one second test data block includes: adding the characteristic values ​​of all second test data blocks in the at least one second test data block to obtain a total value, and when the total value meets a synchronization condition, the verification is successful.

[0014] In a possible implementation, the characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of non-all-zero sequences in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of non-zero elements in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value is the number of correctable test data blocks, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is uncorrectable The number of test data blocks, the synchronization condition is that the total value is less than or equal to the synchronization threshold; or the characteristic value is the number of test data blocks whose recheck bits are the same as the original check bits, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or the characteristic value is the number of test data blocks whose recheck bits are different from the original check bits, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; wherein the length of the test data block is n bits, the first k bits of the test data block are information bits, the last nk bits of the test data block are the original check bits, the recheck bits are obtained based on the information bits, the length of the recheck bits is nk bits, and n and k are integers.

[0015] In a possible implementation manner, the position of the candidate bit is used as the synchronization position.

[0016] In a possible implementation manner, a plurality of observation bits are selected from the data sequence; and the candidate bit is selected from the plurality of observation bits.

[0017] In a possible implementation, the selecting the candidate bit from the multiple observation bits includes: determining multiple groups of first test data blocks from the data sequence based on the multiple observation bits, wherein each group of first test data blocks in the multiple groups of first test data blocks includes at least one first test data block, and the position of each observation bit in the multiple observation bits is the starting position of each group of first test data blocks in the multiple groups of first test data blocks; and selecting an observation bit from the multiple observation bits as the candidate bit based on characteristic values ​​of the multiple groups of first test data blocks.

[0018] In a possible implementation, the selecting an observation bit from the multiple observation bits as the alternative bit based on the characteristic values ​​of the multiple groups of first test data blocks includes: judging in turn whether the characteristic values ​​of each group of first test data blocks in the multiple groups of first test data blocks meet the alternative condition until it is determined that the characteristic values ​​of a group of first test data blocks meet the alternative condition; and using the observation bit corresponding to the group of first test data blocks that meet the alternative condition as the alternative bit.

[0019] In a possible implementation, the characteristic value of the group of first test data blocks is the total value of the number of all-zero sequences in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of non-all-zero sequences in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of zero elements in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or , the characteristic value of the group of first test data blocks is the total value of the number of non-zero elements in the check sequences of all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of correctable test data blocks in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of uncorrectable test data blocks in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or The characteristic value is the total value of the number of test data blocks whose recheck bits are the same as the original check bits in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the total value of the number of test data blocks whose recheck bits are different from the original check bits in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the cumulative value of the number of all-zero sequences in the check sequences of the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; or The characteristic value of the group of first test data blocks is the cumulative value of the number of zero elements in the check sequences of the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the cumulative value of the number of error-correctable test data blocks in the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value of the group of first test data blocks is the cumulative value of the number of test data blocks whose recheck bits are the same as the original check bits in the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold;The length of the test data block is n bits, the first k bits of the test data block are information bits, the last nk bits of the test data block are the original check bits, the recheck bits are obtained according to the information bits, the length of the recheck bits is nk bits, and n, k and X are integers. ;

[0020] In one possible implementation, selecting an observation bit from the multiple observation bits as the candidate bit based on the characteristic values ​​of the multiple groups of first test data blocks includes: comparing the characteristic values ​​of each group of first test data blocks in the multiple groups of first test data blocks, and selecting the observation bit corresponding to a group of first test data blocks with extreme characteristic values ​​as the candidate bit.

[0021] In a possible implementation, the characteristic value is the number of all-zero sequences in the check sequence, and the extreme value is the maximum value; or the characteristic value is the number of non-all-zero sequences in the check sequence, and the extreme value is the minimum value; or the characteristic value is the number of zero elements in the check sequence, and the extreme value is the maximum value; or the characteristic value is the number of non-zero elements in the check sequence, and the extreme value is the minimum value; or the characteristic value is the number of correctable test data blocks, and the extreme value is the maximum value; or the characteristic value is the number of uncorrectable test data blocks, and the extreme value is the minimum value; or the characteristic value is the number of test data blocks whose recheck bits are the same as the original check bits, and the extreme value is the maximum value; or the characteristic value is the number of test data blocks whose recheck bits are different from the original check bits, and the extreme value is the minimum value; wherein the length of the test data block is n bits, the first k bits of the test data block are information bits, the last nk bits of the test data block are the original check bits, the recheck bits are obtained based on the information bits, the length of the recheck bits is nk bits, and n and k are integers.

[0022] In a possible implementation, the selecting multiple observation bits from the data sequence includes: selecting one bit from the data sequence at every T bit interval as the observation bit, where T is an integer greater than zero; or selecting one bit from the data sequence at every L*n+T bit interval as the observation bit, where L is the number of interval test data blocks, the length of the test data block is the n bits, and L and T are integers greater than zero.

[0023] In a possible implementation, the data sequence is a modulated signal, and the data sequence includes multiple modulation code elements, wherein the selecting multiple observation bits from the first data includes: selecting the starting bit of the modulation code element at every interval of T modulation code elements in the data sequence as the observation bit, and T is an integer greater than zero; or selecting the starting bit of the modulation code element at every interval of L*m+T modulation code elements in the data sequence as the observation bit, and L is the number of interval test data blocks, the length of the test data block is the m modulation code elements, and L and T are integers greater than zero.

[0024] In a possible implementation, the number of observation bits is P, P is a positive integer, and the length of the codeword is the P bits.

[0025] In a possible implementation, in the step 2, determining the alternative bits in the data sequence includes determining the alternative bits in the first subsequence, and in the step 3, dividing at least one second test data block in the data sequence according to the alternative bits includes dividing at least one second test data block in the second subsequence according to the alternative bits, the first subsequence and the second subsequence are included in the data sequence, and the second subsequence is the same as, partially the same as, or different from the first subsequence.

[0026] In a possible implementation, after step 3, the method further includes: step 4, in response to the data sequence being in an unlocked state, determining an update synchronization position of the data sequence.

[0027] In a possible implementation, the determining the updated synchronization position of the data sequence includes: re-executing the step 2 and the step 3, and using the synchronization position determined by the re-executed step 3 as the updated synchronization position.

[0028] In a possible implementation, after step three and before step four, the method further includes: dividing a plurality of synchronization codewords from the data sequence according to the synchronization position, wherein the synchronization position is a starting position of the plurality of synchronization codewords; verifying characteristic values ​​of the plurality of synchronization codewords, and when the verification fails, determining that the data sequence is in the unlocked state.

[0029] In a possible implementation, verifying the characteristic values ​​of the multiple synchronization codewords includes: accumulating the characteristic values ​​of each of the multiple synchronization codewords in sequence to obtain an accumulated value, and the verification fails when the accumulated value meets the unlocking condition.

[0030] In a possible implementation, the characteristic value is the number of non-all-zero sequences in the check sequence, and the lock-loss condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of non-zero elements in the check sequence, and the lock-loss condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of uncorrectable codewords, and the lock-loss condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of codewords whose recheck bits are different from the original check bits, and the lock-loss condition is that the cumulative value is greater than or equal to the synchronization threshold; wherein the length of the codeword is n bits, the first k bits of the codeword are information bits, the last nk bits of the codeword are the original check bits, the recheck bits are obtained based on the information bits, the length of the recheck bits is nk bits, and n and k are integers.

[0031] In a possible implementation, verifying the characteristic values ​​of the multiple synchronization codewords includes: adding the characteristic values ​​of all synchronization codewords in the multiple synchronization codewords to obtain a total value, and when the total value meets the loss of lock condition, the verification fails.

[0032] In a possible implementation, the characteristic value is the number of all-zero sequences in the check sequence, and the lock-loss condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value is the number of non-all-zero sequences in the check sequence, and the lock-loss condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, and the lock-loss condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value is the number of non-zero elements in the check sequence, and the lock-loss condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of error-correctable codewords, and the lock-loss condition is that the total value is less than or equal to the synchronization threshold; or The characteristic value is the number of uncorrectable codewords, and the lock-loss condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of codewords whose recheck bits are the same as the original check bits, and the lock-loss condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value is the number of codewords whose recheck bits are different from the original check bits, and the lock-loss condition is that the total value is greater than or equal to the synchronization threshold; wherein the length of the codeword is n bits, the first k bits of the codeword are information bits, the last nk bits of the codeword are the original check bits, the recheck bits are obtained based on the information bits, the length of the recheck bits is nk bits, and n and k are integers.

[0033] In a possible implementation manner, the data sequence is a linear block code.

[0034] In a second aspect, the present application provides a communication device that executes the method in the first aspect or any possible implementation of the first aspect. Specifically, the network device includes a unit for executing the method in the first aspect or any possible implementation of the first aspect.

[0035] In a third aspect, the present application provides a communication device, the communication device comprising: a processor, a communication interface and a memory. The communication interface may be a transceiver. The memory may be used to store program code, and the processor is used to call the program code in the memory to execute the method in the aforementioned first aspect or any possible implementation of the first aspect, which will not be repeated here.

[0036] In a fourth aspect, the present application provides a network system, which includes a sending device and a receiving device, wherein the receiving device is the communication device provided in the second or third aspect, and the receiving device is used to receive a data sequence sent by the sending device.

[0037] In a fifth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the methods described in the above aspects.

[0038] In a sixth aspect, the present application provides a computer program product comprising computer program instructions, which, when executed on a network device, enables the network device to execute the method provided in the first aspect or any possible implementation of the first aspect.

[0039] In a seventh aspect, the present application provides a chip comprising a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory to execute the method in the above-mentioned first aspect and any possible implementation of the first aspect.

[0040] Optionally, the above chip only includes a processor, and the processor is used to read and execute a computer program stored in the memory. When the computer program is executed, the processor executes the method in the first aspect or any possible implementation of the first aspect.

[0041] In an eighth aspect, the present application provides a network node, the network node comprising: a main control board and an interface board. The main control board comprises: a first processor and a first memory. The interface board comprises: a second processor, a second memory and an interface card. The main control board and the interface board are coupled.

[0042] The first memory can be used to store program code, and the first processor is used to call the program code in the first memory to perform the following operations: determine an alternative bit in the data sequence, and the alternative bit is included in the multiple bits; determine a synchronization position based on the alternative bit, and the synchronization position is used to indicate the starting position of a codeword in the data sequence.

[0043] The second memory may be used to store program codes, and the second processor is used to call the program codes in the second memory to trigger the interface card to perform the following operations: receiving a data sequence, wherein the data sequence includes a plurality of bits.

[0044] In a possible implementation, an inter-process communication (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate through the IPC channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings used in the embodiments. Obviously, the following drawings are only drawings of some embodiments of the present application. For ordinary technicians in this field, other technical solutions and drawings that can also implement the present application can be obtained based on these drawings without creative labor.

[0046] Figure 1 A synchronization position of a codeword provided in an embodiment of the present application;

[0047] Figure 2 A synchronization flow chart provided for an embodiment of the present application;

[0048] Figure 3 A synchronization flow chart provided for an embodiment of the present application;

[0049] Figure 4 A method for selecting an observation bit provided in an embodiment of the present application;

[0050] Figure 5 A method for selecting an observation bit provided in an embodiment of the present application;

[0051] Figure 6 A method for selecting an observation bit provided in an embodiment of the present application;

[0052] Figure 7 A method for selecting an observation bit provided in an embodiment of the present application;

[0053] Figure 8 A first stage of synchronization lock determination provided by an embodiment of the present application;

[0054] Fig. 9 A second stage of synchronization lock determination provided by an embodiment of the present application;

[0055] Fig.10 A synchronization loss lock judgment provided in an embodiment of the present application;

[0056] Fig.11 A synchronization flow chart provided for an embodiment of the present application;

[0057] Fig.12 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0058] Fig.13 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0059] Fig.14 A schematic diagram of the structure of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] The embodiments of the present application are described below in conjunction with the accompanying drawings.

[0061] Due to the influence of channel loss and noise, errors may occur when the signal is transmitted in the channel, affecting the reliability of the communication system. When the signal is represented in the form of a data sequence composed of multiple bits, the transmission error is specifically manifested as the change in the value of some bits in the data sequence, that is, the occurrence of error bits. FEC is a technology for controlling transmission errors in communication systems. In FEC technology, redundant information is sent together with the original data sequence to recover errors during transmission and reduce the bit error rate. FEC can be divided into block codes and convolutional codes according to the different ways of processing information sequences. For block codes, they can be further divided into linear block codes and nonlinear block codes. Taking the systematic code in linear block codes as an example, the transmitter groups the original data sequence, and the length of each group is k bits. Then, in each group, according to specific coding rules, nk bits of redundant information, also called parity, are added, and finally a codeword with a length of n bits is obtained. Therefore, in a codeword with a length of n bits, the first k bits are original data, also called information bits, and the last nk bits are parity bits. The entire codeword consists of information bits and parity bits. After the codeword reaches the receiving end through the channel, if the number of error bits in the codeword is within the correctable range, the receiving end can check and correct the error through the decoding process, and restore the received codeword to the original data sent by the sender, thereby resisting the interference caused by the channel and improving the reliability of the communication system. The error detection and correction functions of linear block codes must be implemented based on complete codewords. Therefore, before decoding the data sequence received by the receiving end, it is necessary to determine the codeword boundary in the data sequence, that is, to find the starting position and ending position of a complete codeword. This process is called codeword synchronization or frame synchronization. If the codeword synchronization is incorrect, that is, the true codeword boundary cannot be determined, the error detection or correction effect cannot be achieved in the subsequent decoding process, and it may even increase bit errors, causing the performance of the communication system to deteriorate.

[0062] The starting position of each codeword can also be called the synchronization position. Figure 1 shows the synchronization position in the codeword. Figure 1 As shown, the length of the entire codeword is n bits, of which the first k bits are original data (information bits), the last nk bits are additional check bits (parity bits) added by the encoding rule, and the synchronization position is the starting position of the codeword, that is, the position of the first bit in the codeword. Wherein, n and k are both integers. It can be seen that in the data sequence, the number of synchronization positions is multiple, and the multiple synchronization positions are related to each other, wherein the interval between each synchronization position is fixed, and the interval is the length of the codeword.

[0063] In the embodiments of the present application, although the systematic code is used for illustration, the present application is not limited to the systematic code, but is also applicable to non-systematic code (non-systematic code), and the present application can be applicable to all communication systems of linear block codes. The linear block codes include but are not limited to Reed-Solomon code (RS code), Bose-Chaudhuri-Hocquenghem code (BCH code), Low-Density Parity-Check code (LDPC code), Hamming code, Golay code, and Reed-Muller code, etc.

[0064] The embodiment of the present application provides a codeword synchronization method and a device and system based on the method. These methods, devices and systems are based on the same inventive concept. The method may include two stages. In the first stage, multiple groups of first test data blocks are divided according to multiple observation bits, and an observation bit that is most likely to be located at the synchronization position is selected from multiple observation bits according to the multiple groups of first test data blocks. In the second stage, a group of second test data blocks are divided according to the observation bit that is most likely to be located at the synchronization position, and whether the observation bit that is most likely to be located at the synchronization position is the synchronization position is determined according to the group of second test data blocks. The method can also only include the first stage. After determining to select the observation bit that is most likely to be located at the synchronization position, the observation bit that is most likely to be located at the synchronization position is directly used as the synchronization position. In this method, the technical effect of high-precision codeword synchronization of the receiving end data stream can be achieved without inserting additional data in the data stream of the sending end, and its synchronization performance achieves high reliability.

[0065] Figure 2 The method flow chart of the embodiment of the present application is shown. The method is applied to a receiving device in a communication network. The receiving device can be various devices that perform FEC, including but not limited to routers, switches and servers. The steps of the method include:

[0066] S210, receiving a data sequence.

[0067] Specifically, the receiving end receives a data sequence from the transmitting end, and the data sequence includes a plurality of bits, each bit being binary data. That is, the data sequence is a sequence composed of a plurality of bits, which may also be referred to as a bit sequence. In some embodiments, the data sequence is a linear block code. The data sequence may have bit errors when transmitted through a channel, and operations such as error detection and error correction are required.

[0068] S220, in the first stage, determining a candidate bit in the data sequence, the candidate bit being included in the multiple bits. The candidate bit is the observation bit that is most likely to be located at a synchronization position among the multiple observation bits, or in other words, the position of the candidate bit is the most likely synchronization position.

[0069] like Figure 3 As shown, in the first stage, two steps S221 and S222 may be included:

[0070] S221, the receiving end selects a plurality of observation bits from the received data sequence. The positions of these observation bits include the synchronization position, that is, the position of a certain observation bit among these observation bits may be the synchronization position, or in other words, the positions of these observation bits can cover the synchronization position.

[0071] Optionally, in the first stage, the method uses only a portion of the data sequence, such as a first subsequence in the data sequence, when determining the candidate bits in the data sequence, that is, determining the candidate bits in the first subsequence. The first subsequence includes a plurality of bits, and the first subsequence may be any portion of the data sequence. The receiving end selects the plurality of observation bits from the first subsequence, and the positions of the observation bits may be synchronization positions. For example, the number of the observation bits is P, and P is an integer greater than 1.

[0072] Optionally, when selecting multiple observation bits from the received data sequence, the interval between every two adjacent observation bits in the multiple observation bits is the same, and the position of each observation bit in the multiple observation bits moves backward in sequence.

[0073] In the codeword synchronization process, the concept of test data block is introduced. The test data block is a part of the data sequence. The test data block consists of a number of consecutive bits. The length of the test data block is the same as the length of the codeword. It can be said that the test data block is used to simulate a codeword.

[0074] Optionally, the multiple observation bits may be located in the same test data block, and the position of each observation bit in the multiple observation bits in the same test data block is moved backward in sequence. Specifically, one bit is selected as the observation bit every T bits, where T is an integer greater than zero. Figure 4 The method of selecting observation bits is shown, where b1, b2, and b3 are three adjacent observation bits, corresponding to the three bits x(0), x(1), and x(2) in the data sequence. The interval between each observation bit is 1 bit, that is, T is 1. The three observation bits are located in the same test data block, for example Figure 4In the test data block divided by x(0) as the starting position. In the test data block, b1 is located at the first position in the test data block, and b2 and b3 are located at the second and third positions in the test data block respectively, that is, the position of each of the three observation bits in the same test data block moves backward in sequence. Figure 4 Only three observation bits are shown, but the selection method of more observation bits can be inferred from this, which will not be described in detail here.

[0075] Optionally, the multiple observation bits may be located in multiple test data blocks respectively, and the position of each observation bit in the multiple observation bits in each test data block is moved backward in sequence. Specifically, one bit is selected as the observation bit every L*n+T bits, where L is the number of interval test data blocks, the length of the test data block is n bits, and L and T are integers greater than zero. Figure 5 The method of selecting observation bits is shown, where b1 and b2 are two adjacent observation bits, corresponding to the two bits x(0) and x(L*n+1) in the data sequence. The two observation bits are located in two different test data blocks, for example Figure 5 In the test data block divided by x(0) as the starting position and in the test data block divided by x(L*n) as the starting position. The interval between the two test data blocks is L test data blocks, and the interval between the two observation bits is L*n+1 bits, that is, T is 1. In the test data block divided by x(0) as the starting position, the position of b1 is the first position in the test data block, and in the test data block divided by x(L*n) as the starting position, the position of b2 is the second position in the test data block, that is, the position of each of the two observation bits in each test data block moves backwards in sequence. Although Figure 5 Only two observation bits are shown, but the selection method of more observation bits can be deduced by analogy, which will not be repeated here. In this case, the interval between adjacent observation bits is farther, and the correlation between observation bits is lower, thereby reducing the impact of burst errors and improving the accuracy of codeword synchronization.

[0076] Optionally, when selecting the multiple observation bits, the positions of the multiple observation bits may be made to traverse all positions in the test data block.

[0077] For example, when the multiple observation bits are located in the same test data block, the positions of the multiple observation bits can be made to traverse all positions in the same test data block, that is, the positions of the multiple observation bits can traverse all positions in the same codeword. Figure 4In the selection method of observation bits shown, the length of the codeword is n bits, the number of observation bits is P, and when P is equal to n, the positions of the multiple observation bits can traverse all positions in the same test data block.

[0078] For example, when the multiple observation bits are respectively located in multiple test data blocks, the same position in each of the multiple test data blocks is regarded as an equivalent position. For example, the first position in each of the multiple test data blocks is regarded as an equivalent position, so that the positions of the multiple observation bits traverse all equivalent positions, that is, the positions of the multiple observation bits traverse all positions in the multiple test data blocks. Figure 5 In the method for selecting observation bits shown, the length of the codeword is n bits, the number of equivalent positions is n, and the number of observation bits is P. When P is equal to n, the positions of the multiple observation bits can traverse all equivalent positions, that is, the positions of the multiple observation bits can traverse all positions in multiple test data blocks.

[0079] Optionally, when selecting the multiple observation bits, the positions of the multiple observation bits may not traverse all positions in the codeword. That is, the value of P may be smaller than n.

[0080] If the positions of the multiple observation bits traverse all positions in the test data block, the accuracy of the code word synchronization result will be higher. However, as the number of observation bits increases, the system resources consumed by the code word synchronization process will also increase.

[0081] The signal can be modulated at the transmitting end to obtain a modulated signal. Common modulation methods include pulse amplitude modulation (Pulse-Amplitude Modulation, PAM), quadrature amplitude modulation (Quadrature Amplitude Modulation, QAM), phase-shift keying (Phase-Shift Keying, PSK), etc. The pulse amplitude of the modulated signal can include multiple orders, and the number of the multiple orders can be called the order of modulation. Taking PAM as an example, when the pulse amplitude of the modulated signal has 2 orders, the modulation order is 2, and the modulation method can be called PAM2; when the pulse amplitude of the modulated signal has 4 orders, the modulation order is 4, and the modulation method can be called PAM4, and so on. The modulated signal can be represented as a modulated data sequence. Compared with the unmodulated data sequence, the basic unit of the modulated data sequence is changed from a bit to a codeword, that is, in the modulated data sequence, the codeword is composed of a number of codewords, and the codeword is composed of a number of bits. The number of bits included in the codeword is related to the order of modulation. When the modulation order is M, the number of bits included in the codeword is log2 M, where M is an integer multiple of 2. For example, when the modulation order is 2, the codeword includes 1 bit, and when the modulation order is 4, the codeword includes 2 bits. It can be seen that the starting position of the codeword must also be the starting position of a certain codeword, and not other positions of the codeword. Therefore, for the modulated signal, when selecting the multiple observation bits, only the starting bit of the codeword can be considered, without considering other bits of the codeword.

[0082] Optionally, the multiple observation bits are respectively the starting bits of multiple code elements, the multiple code elements are in the same test data block, and the positions of the multiple code elements in the same test data block are moved backward in sequence. Specifically, every T modulation code elements, the starting bit of the modulation code element is selected as the observation bit, and T is an integer greater than zero. That is to say, every T·log2M bits, the starting bit of the modulation code element is selected as the observation bit. Figure 6The method of selecting observation bits is shown, where the data sequence is a modulated signal and the modulation order is 4. The data sequence includes multiple modulation code elements, each code element includes 2 bits, such as a code element composed of x(0) and x(1), a code element composed of x(2) and x(3), and a code element composed of x(4) and x(5), and so on. Among them, b1, b2, and b3 are three adjacent observation bits, corresponding to the three bits x(0), x(2), and x(4) in the data sequence respectively. The three observation bits are the starting bits of the three code elements, which are the code elements composed of x(0) and x(1), the code elements composed of x(2) and x(3), and the code elements composed of x(4) and x(5). There is one code element between every two adjacent code elements in the three code elements, that is, T is 1. Moreover, the positions of the three code elements in the same test data block are moved backwards in sequence. Although Figure 6 Only three observation bits are shown, but the selection method of more observation bits can be inferred from this, which will not be described in detail here.

[0083] Optionally, the multiple observation bits are respectively the starting bits of multiple code elements, the multiple code elements are respectively located in multiple test data blocks, and the position of each code element in the multiple code elements in each test data block is moved backward in sequence. Specifically, for every interval of L*m+T modulation code elements, the starting bit of the modulation code element is selected as the observation bit, where L is the number of interval test data blocks, the length of the test data block is the m modulation code elements, and L and T are integers greater than zero. In other words, for every interval of (L·m+T)·log2M bits, the starting bit of the modulation code element is selected as the observation bit. Figure 7 The method for selecting observation bits is shown, where the data sequence is a modulated signal and the modulation order is 4. The data sequence includes multiple modulation symbols, each symbol includes 2 bits, such as a symbol composed of x(0) and x(1), a symbol composed of x(L*n) and x(L*n+1), and a symbol composed of x(L*n+2) and x(L*n+3), and so on. Wherein b1 and b2 are two adjacent observation bits, corresponding to the two bits x(0) and x(L*n+2) in the data sequence respectively. The two observation bits are the starting bits of the two symbols, which are the symbol composed of x(0) and x(1), and the symbol composed of x(L*n+2) and x(L*n+3). Moreover, the two observation bits are respectively located in two different test data blocks, for example Figure 7In the test data block divided with x(0) as the starting position and in the test data block divided with x(L*n) as the starting position. The interval between the two test data blocks is L test data blocks, and the interval between two observation bits is L*m+1 code elements, that is, T is 1. In the test data block divided with x(0) as the starting position, the code element where b1 is located is the first code element in the test data block, and in the test data block divided with x(L*n) as the starting position, the code element where b2 is located is the second code element in the test data block, that is, the position of each of the two code elements in each test data block moves backward in sequence. Although Figure 7 Only two observation bits are shown, but the selection method of more observation bits can be deduced by analogy, which will not be repeated here. In this case, the interval between adjacent observation bits is farther, and the correlation between observation bits is lower, thereby reducing the impact of burst errors and improving the accuracy of codeword synchronization.

[0084] S222, selecting a candidate bit from the multiple observation bits. The candidate bit is an observation bit among the multiple observation bits, and the candidate bit is the observation bit most likely to be located at the synchronization position. Specifically, S222 may include two steps, S2221 and S2222.

[0085] S2221: divide a plurality of groups of first test data blocks from the data sequence according to the plurality of observation bits, wherein the plurality of groups of first test data blocks correspond to the plurality of observation bits one by one. Specifically, each group of first test data blocks in the plurality of groups of first test data blocks includes at least one first test data block, and the position of each observation bit in the plurality of observation bits is the starting position of each group of first test data blocks in the plurality of groups of first test data blocks.

[0086] Optionally, each observation bit in the multiple observation bits is used as a starting position, and the subsequent N test data blocks are selected, where N is an integer greater than or equal to 1. The position of each observation bit in the multiple observation bits is the starting position of each group of first test data blocks in the multiple groups of first test data blocks. The N test data blocks selected with each observation bit as the starting position are a group of first test data blocks, and the multiple groups of N test data blocks selected with each observation bit in the multiple observation bits as the starting position are the multiple groups of first test data blocks. Each group of first test data blocks in the multiple groups of first test data blocks corresponds to an observation bit as the starting position of the group of first test data blocks, that is, the multiple groups of first test data blocks correspond one-to-one to the multiple observation bits.

[0087] Optionally, the N test data blocks may be continuous, that is, each group of first test data blocks includes N continuous data blocks. When the length of each test data block is n bits, the N*n continuous bits thereafter are selected to obtain the N test data blocks.

[0088] Optionally, the N test data blocks may also be discontinuous, and the starting position of each test data block in the N test data blocks is associated with the observation bit corresponding to the group of test data blocks. Specifically, the interval between the starting position of each test data block and the observation bit corresponding to the group of test data blocks is an integer multiple of the length of the codeword, that is, the interval between every two test data blocks in the N test data blocks is an integer multiple of the length of the codeword. In addition, the interval between every two test data blocks in the N test data blocks may be the same or different.

[0089] like Figure 4 As shown, the observation bit b1 is taken as the starting position, and a group of first test data blocks thereafter is selected. The group of first test data blocks includes N test data blocks, namely B1, B2, ..., B N , each test data block has a length of n bits. Similarly, taking the observed bit b2 or b3 as the starting position, a group of first test data blocks thereafter can also be selected. Taking the observed bit b1, b2 or b3 as the starting position respectively, the plurality of groups of first test data blocks are selected. Figure 5 , Figure 6 and Figure 7 In the method of the plurality of groups of first test data blocks, Figure 4 Similar, no further elaboration is required here.

[0090] S2222: According to the characteristic values ​​of the multiple groups of first test data blocks, select one observation bit from the multiple observation bits as the candidate bit, that is, the observation bit most likely to be located at the synchronization position.

[0091] Optionally, when selecting an observation bit from the multiple observation bits as the observation bit most likely to be located at the synchronization position according to the characteristic values ​​of the multiple groups of first test data blocks, the selection method may be an early termination selection method. Specifically, it is determined in turn whether the characteristic values ​​of each group of first test data blocks in the multiple groups of first test data blocks meet the alternative condition, until it is determined that the characteristic value of a group of first test data blocks meets the alternative condition, and the observation bit corresponding to the group of first test data blocks that meets the alternative condition is used as the alternative bit.

[0092] Optionally, when selecting an observation bit from the plurality of observation bits as the observation bit most likely to be located at the synchronization position according to the characteristic values ​​of the plurality of groups of first test data blocks, the selection method may be a traversal selection method. Specifically, the characteristic values ​​of each group of first test data blocks in the plurality of groups of first test data blocks are compared, and the observation bit corresponding to the group of first test data blocks with the characteristic value being an extreme value is selected as the candidate bit.

[0093] Under the selection method of early termination and the selection method of traversal, the calculation of characteristic values ​​can be performed in parallel, that is, multiple calculation units are used to simultaneously calculate the characteristic values ​​of multiple test data blocks. For example, 10 calculation units are used to simultaneously calculate the characteristic values ​​of 10 test data blocks. The parallel calculation method can save calculation time and reduce latency.

[0094] Optionally, the characteristic value may be a characteristic value of a verification sequence.

[0095] A parity-check matrix can be generated for each linear block code, which describes the linear relationship between the data in the codeword of the linear block code, and the parity-check matrix can be applied to the decoding process. When the data sequence is a linear block code, the parity-check matrix also exists for the data sequence, which can be called the parity-check matrix of the data sequence. Specifically, the following relationship is satisfied between the data sequence and the parity-check matrix of the data sequence:

[0096]

[0097] Wherein, C is a codeword in the data sequence, S is the check sequence of the codeword, and H is the check matrix of the data sequence. It can be seen from the above relationship (1) that the check sequence of the codeword in the data sequence is obtained by multiplying the codeword by the transposed matrix of the check matrix of the data sequence, and the check sequence is a zero vector, that is, an all-zero matrix.

[0098] As described above, when the data sequence is the data sequence received by the receiving end, it is necessary to determine the starting position of the codeword in the data sequence. If the codeword is not divided from the data sequence at the correct starting position, the obtained codeword will no longer satisfy the above relationship (1). At this time, the check sequence of the codeword in the data sequence can be expressed by the following relationship:

[0099] SR=R·HT(2)

[0100] Where R is a codeword in the data sequence received by the receiving end, S Ris the check sequence of the codeword, and H is the check matrix of the original data sequence sent by the transmitter. In the above equation (2), the check sequence of the codeword in the data sequence received by the receiver is the product of the codeword and the transposed matrix of the check matrix of the original data sequence sent by the transmitter. From the above analysis, it can be seen that when there is an error bit in the codeword, S R It is no longer an all-zero matrix. Therefore, the codeword synchronization can be achieved by using the check sequence of the test data block in the data sequence received by the receiving end. Specifically, the check sequence of the test data block in the data sequence received by the receiving end can be used to select an observation bit from the multiple observation bits as the observation bit most likely to be located at the synchronization position.

[0101] Optionally, the check sequence of each group of first test data blocks in the multiple groups of first test data blocks is calculated respectively.

[0102] like Figure 4 As shown, the check sequence of a group of first test data blocks starting with the observation bit b1 is calculated, that is, Figure 4 The S shown (1) , including S1 (1) ,S2 (1) ,…,S N (1) , corresponding to the test data blocks B1, B2, ..., B N Similarly, the check sequences of a group of first test data blocks starting with observation bits b2 and b3 are calculated respectively, that is, Figure 4 The S shown (2) ,S (3) .Although Figure 4 Only the calculation method of the check sequence of a group of first test data blocks with three observation bits as starting bits is shown, but the calculation methods of more check sequences can be deduced by analogy, which will not be described in detail here. Figure 5 , Figure 6 and Figure 7 The calculation method of the check sequence of the plurality of groups of first test data blocks is the same as Figure 4 Similar, no further elaboration is required here.

[0103] For example, the characteristic value may be the number of all-zero sequences in the check sequence. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of a group of first test data blocks is greater than or equal to the synchronization threshold. Specifically, the relationship between the number of all-zero sequences in the check sequence of each group of first test data blocks and the synchronization threshold is judged in turn until it is determined that the number of all-zero sequences in the check sequence of a group of first test data blocks is greater than or equal to the synchronization threshold, and the observation bit corresponding to the group of first test data blocks that meets the alternative condition is used as the alternative bit. The observation bit corresponding to a group of first test data blocks is, that is, the observation bit that serves as the starting bit of the group of first test data blocks.

[0104] The value of the synchronization threshold can be obtained through simulation analysis. For example, a data sequence is used as the data sequence received by the receiving end, and the bit error rate of the data sequence is designed to be within an acceptable range. The number of all-zero sequences in the check sequence of a group of test data blocks divided based on the synchronization position and the number of all-zero sequences in the check sequence of a group of test data blocks divided based on the asynchronous position are counted respectively, and the synchronization threshold is determined according to the difference between the two, so that the synchronization threshold can be used to distinguish the synchronization position from the asynchronous position.

[0105] When the characteristic value is the number of all-zero sequences in the check sequence, and the above-mentioned early termination selection method is adopted, the selection process of the observation bit most likely to be located at the synchronization position can be referred to as Figure 4 The synchronization threshold can be 2. Figure 4 As shown, the check sequence S is judged in turn (1) ,S (2) ,S (3) For example, if the number of all-zero sequences in the check sequence of the first group of first test data blocks is Q1=0, which is less than the synchronization threshold, and the number of all-zero sequences in the check sequence of the second group of first test data blocks is Q2=2, which is equal to the synchronization threshold, then b2 is selected as the observation bit most likely to be located at the synchronization position. Furthermore, when b2 is determined to meet the alternative condition, the relationship between the number of all-zero sequences in the check sequence corresponding to the subsequent observation bits and the synchronization threshold is no longer determined, that is, S is no longer determined. (3) The relationship between the number of all-zero sequences in and the synchronization threshold.

[0106] Optionally, in the above-mentioned early termination selection method, for the characteristic value of each group of first test data blocks, a statistical method of early termination can also be adopted. That is, the characteristic value of the group of first test data blocks can be the total value of the number of all-zero sequences in the check sequence of all first test data blocks in the group of first test data blocks, and accordingly, the alternative condition can be that the total value is greater than or equal to the synchronization threshold. Figure 4 In the selection process shown in the figure, each group of check sequences S is judged in turn. (1) ,S (2) ,S (3) When the relationship between the number of all-zero sequences and the synchronization threshold is considered, for each group of first test data blocks, the check sequence of each test data block is calculated in turn. When the check sequence is an all-zero sequence, the number of all-zero sequences is increased by 1. When the cumulative value of the number of all-zero sequences meets the alternative condition, that is, the cumulative value of the number of all-zero sequences is greater than or equal to the synchronization threshold, it is considered that the group of first test data blocks has met the alternative condition, and the subsequent test data blocks in the group for which the check sequence is not calculated will no longer be calculated. For example, for the second group of first test data blocks, if S1 (2) ,S2 (2) If all of them are all zero sequences, it is considered that the number of all-zero sequences Q2 in the check sequence of the second group of first test data blocks has accumulated to 2, reaching the synchronization threshold, and the group of first test data blocks has met the alternative condition, then b2 is selected as the observation bit most likely to be located at the synchronization position, and the subsequent S3 is no longer calculated. (2) To S N (2) check sequence. Optionally, in the above-mentioned early termination selection method, a traversal statistical method can also be adopted for the characteristic value of each group of first test data blocks. That is to say, the characteristic value of the group of first test data blocks can be the cumulative value of the number of all-zero sequences in the check sequence of the first X first test data blocks in the group of first test data blocks. Accordingly, the alternative condition can be that the cumulative value is greater than or equal to the synchronization threshold. In the specific selection process, the check sequence of each first test data block in the group is calculated to determine whether the total value of the number of all-zero sequences in the group of check sequences meets the alternative condition, that is, whether the total value of the number of all-zero sequences in the group of check sequences is greater than or equal to the synchronization threshold. The specific operation process will not be repeated here.

[0107] For example, the characteristic value may be the number of all-zero sequences in the check sequence. When the above traversal selection method is adopted, the extreme value is associated with the characteristic value. The extreme value may be a maximum value. Specifically, the number of all-zero sequences in the check sequence of each group of first test data blocks may be counted, and a group of first test data blocks with the largest number of all-zero sequences may be determined, and the observation bits corresponding to the group of first test data blocks may be used as the observation bits most likely to be located at the synchronization position.

[0108] When the characteristic value is the number of all-zero sequences in the check sequence, the selection process of the observation bit most likely to be located at the synchronization position can also be referred to as Figure 4 .like Figure 4 As shown, the statistical check sequence S (1) ,S (2) ,S (3) The number of all-zero sequences in are recorded as Q1, Q2, and Q3 respectively, and the maximum value thereof is determined. For example, Q1=0, Q2=0, and Q3=2, that is, the maximum value is Q3=2, then b3 is selected as the observation bit most likely to be located at the synchronization position, and the position where b3 is located is the most likely synchronization position.

[0109] For example, the characteristic value may be the number of non-all-zero sequences in the check sequence. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of a group of first test data blocks is less than or equal to the synchronization threshold. Specifically, the relationship between the number of non-all-zero sequences in the check sequence of each group of first test data blocks and the synchronization threshold is judged in turn, until it is determined that the number of non-all-zero sequences in the check sequence of a group of first test data blocks is less than or equal to the synchronization threshold, then the observation bit corresponding to the group of first test data blocks that meets the alternative condition is used as the alternative bit. The value of the synchronization threshold can also be obtained through simulation analysis, and the specific process is similar to the synchronization threshold corresponding to the all-zero sequence, which will not be repeated here.

[0110] For example, the characteristic value may be the number of non-all-zero sequences in the check sequence. When the above traversal selection method is adopted, the extreme value is associated with the characteristic value. The extreme value may be a minimum value. Specifically, the number of non-all-zero sequences in the check sequence of each group of first test data blocks may be counted, and a group of first test data blocks with the least number of non-all-zero sequences may be determined, and the observation bits corresponding to the group of first test data blocks may be used as the observation bits most likely to be located at the synchronization position.

[0111] For example, the characteristic value may be the number of zero elements in a check sequence. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of a group of first test data blocks is greater than or equal to the synchronization threshold. Specifically, the relationship between the number of zero elements in the check sequence of each group of first test data blocks and the synchronization threshold is judged in turn until it is determined that the number of zero elements in the check sequence of a group of first test data blocks is greater than or equal to the synchronization threshold, and the observation bit corresponding to the group of first test data blocks that meets the alternative condition is used as the alternative bit. The value of the synchronization threshold can also be obtained through simulation analysis.

[0112] For example, the characteristic value may be the number of zero elements in the check sequence. When the above traversal selection method is adopted, the extreme value is associated with the characteristic value. The extreme value may be a maximum value. Specifically, the number of zero elements in the check sequence of each group of first test data blocks may be counted, and a group of first test data blocks with the largest number of zero elements may be determined, and the observation bits corresponding to the group of first test data blocks may be used as the observation bits most likely to be located at the synchronization position.

[0113] For example, the characteristic value may be the number of non-zero elements in a check sequence. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of a group of first test data blocks is less than or equal to the synchronization threshold. Specifically, the relationship between the number of non-zero elements in the check sequence of each group of first test data blocks and the synchronization threshold is judged in turn until it is determined that the number of non-zero elements in the check sequence of a group of first test data blocks is less than or equal to the synchronization threshold, and the observation bit corresponding to the group of first test data blocks that meets the alternative condition is used as the alternative bit. The value of the synchronization threshold can also be obtained through simulation analysis.

[0114] For example, the characteristic value may be the number of non-zero elements in the check sequence. When the above traversal selection method is adopted, the extreme value is associated with the characteristic value. The extreme value may be a minimum value. Specifically, the number of non-zero elements in the check sequence of each group of first test data blocks may be counted, and a group of first test data blocks with the least number of non-zero elements may be determined, and the observation bits corresponding to the group of first test data blocks may be used as the observation bits most likely to be located at the synchronization position.

[0115] When the characteristic value is a non-all-zero sequence, a zero element or a non-zero element in the check sequence, combined with Figure 4 The specific implementation process of the data sequence shown can refer to the introduction when the characteristic value is an all-zero sequence in the check sequence, which will not be repeated here.

[0116] Optionally, the characteristic value may be a correctable characteristic value. After the receiving end divides the codewords in the data sequence, the state of the codewords can be determined, and the state includes a correctable state and an uncorrectable state. When the codeword is in a correctable state, the codeword is also called a correctable codeword; when the codeword is in an uncorrectable state, the codeword is also called an uncorrectable codeword. The correctable characteristic value of a group of codewords can be associated with the state of the codewords in the group of codewords. Similarly, for the test data blocks divided out from the data sequence received by the receiving end, the state of the test data blocks can also be determined, and the state includes a correctable state and an uncorrectable state. When the test data block is in a correctable state, the test data block is also called a correctable test data block; when the test data block is in an uncorrectable state, the test data block is also called an uncorrectable test data block. The correctable characteristic value of a group of test data blocks can be associated with the state of the test data blocks in the group of test data blocks.

[0117] For example, the error-correctable characteristic value may be the number of error-correctable test data blocks. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of a group of first test data blocks is greater than or equal to the synchronization threshold. Specifically, the relationship between the number of error-correctable test data blocks and the synchronization threshold in each group of first test data blocks is judged in turn until it is determined that the number of error-correctable test data blocks in a group of first test data blocks is greater than or equal to the synchronization threshold, and then the observation bit corresponding to the group of first test data blocks that meets the alternative condition is used as the alternative bit. The value of the synchronization threshold can also be determined by simulation analysis.

[0118] When the error-correctable characteristic value is the number of error-correctable test data blocks, the selection process of the observation bit most likely to be located at the synchronization position can be referred to as follows: Figure 4 The synchronization threshold can be 2. Figure 4 As shown, the relationship between the number of correctable test data blocks in each group of first test data blocks and the synchronization threshold is determined in sequence. For example, the number of correctable test data blocks in the first group of first test data blocks Q1=0, which is less than the synchronization threshold, and the number of correctable test data blocks in the second group of first test data blocks Q2=2, which is equal to the synchronization threshold, then b2 is selected as the observation bit most likely to be located at the synchronization position. Moreover, when b2 is determined to meet the alternative condition, the relationship between the number of correctable test data blocks corresponding to the subsequent observation bits and the synchronization threshold is no longer determined, that is, the relationship between Q3 and the synchronization threshold is no longer determined.

[0119] For example, the error-correctable characteristic value may be the number of error-correctable test data blocks. When the above traversal selection method is adopted, the extreme value is associated with the characteristic value. The extreme value may be a maximum value. Specifically, the number of error-correctable test data blocks in each group of first test data blocks may be counted, and a group of first test data blocks with the largest number of error-correctable test data blocks may be determined, and the observation bits corresponding to the group of first test data blocks may be used as the observation bits most likely to be located at the synchronization position.

[0120] When the error-correctable characteristic value is the number of error-correctable test data blocks, the selection process of the observation bit most likely to be located at the synchronization position can also be referred to as Figure 4 .like Figure 4 As shown, the number of correctable test data blocks in each group of first test data blocks with observation bits b1, b2, and b3 as starting bits is counted respectively, and recorded as Q1, Q2, and Q3 respectively, and the maximum value therein is determined. For example, Q1=0, Q2=0, and Q3=2, that is, the maximum value is Q3=2, then b3 is selected as the observation bit most likely to be located at the synchronization position, and the position where b3 is located is the most likely synchronization position.

[0121] For example, the correctable characteristic value may be the number of uncorrectable test data blocks. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of a group of first test data blocks is less than or equal to the synchronization threshold. Specifically, the relationship between the number of uncorrectable test data blocks and the synchronization threshold in each group of first test data blocks is judged in turn until it is determined that the number of uncorrectable test data blocks in a group of first test data blocks is less than or equal to the synchronization threshold, and the observation bit corresponding to the group of first test data blocks that meets the alternative condition is used as the alternative bit. The value of the synchronization threshold can also be obtained through simulation analysis.

[0122] For example, the correctable error characteristic value may be the number of uncorrectable test data blocks. When the above traversal selection method is adopted, the extreme value is associated with the characteristic value. The extreme value may be a minimum value. Specifically, the number of uncorrectable test data blocks in each group of first test data blocks may be counted, and a group of first test data blocks with the least number of uncorrectable test data blocks may be determined, and the observation bits corresponding to the group of first test data blocks may be used as the observation bits most likely to be located at the synchronization position.

[0123] Optionally, the characteristic value may be a recheck characteristic value. The recheck characteristic value is associated with the relationship between the recheck bit and the original check bit. In combination with the above description, in a codeword of n bits in length, the first k bits are information bits, and the last nk bits are check bits. The check bits of the last nk bits are calculated based on the first k bits of information bits and in accordance with a specific coding rule. For a data sequence received by the receiving end, if the starting position of the codeword in the data sequence is not found, the relationship between the information bit and the check bit is no longer satisfied in the divided codeword. That is to say, even if the same characteristic coding rule is followed, based on the first k bits, it will not be possible to obtain the same content as the last nk bits in each test data block. In each test data block in the data sequence received by the receiving end, the last nk bits and the first k bits may no longer satisfy the above specific coding rule. Therefore, when the last nk bits recalculated based on the first k bits in each test data block in the data sequence received by the receiving end and in accordance with the specific coding rule, there may be differences compared with the last nk bits in each test data block in the data sequence received by the receiving end. The last nk bits in each test data block in the data sequence received by the receiving end can be called original check bits, and the last nk bits recalculated based on the first k bits in each test data block in the data sequence received by the receiving end and according to the specific encoding rule can be called re-check bits.

[0124] From the above analysis, it can be known that when there is an error bit in the test data block, the recheck bit is different from the original check bit. Therefore, the recheck bit in each test data block in the data sequence received by the receiving end can be compared with the original check bit to achieve codeword synchronization. Specifically, the recheck bit in each test data block in the data sequence received by the receiving end can be compared with the original check bit, and one observation bit is selected from the multiple observation bits as the observation bit most likely to be located at the synchronization position.

[0125] For example, the re-check characteristic value may be the number of test data blocks whose re-check bits are identical to the original check bits. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be greater than or equal to the synchronization threshold. Specifically, the relationship between the number of test data blocks whose re-check bits are identical to the original check bits in each group of first test data blocks and the synchronization threshold is judged in turn, until it is determined that the number of test data blocks whose re-check bits are identical to the original check bits in a group of first test data blocks is greater than or equal to the synchronization threshold, then the observation bits corresponding to the group of first test data blocks that meet the alternative condition are used as the alternative bits. The value of the synchronization threshold can also be obtained through simulation analysis.

[0126] When the recheck characteristic value is the number of test data blocks whose recheck bits are the same as the original check bits, the selection process of the observation bit most likely to be located at the synchronization position can be referred to as Figure 4 The synchronization threshold can be 2. Figure 4 As shown, the relationship between the number of test data blocks with the same recheck bit and the original check bit in each group of first test data blocks and the synchronization threshold is determined in sequence. For example, the number of test data blocks with the same recheck bit and the original check bit in the first group of first test data blocks Q1=0, which is less than the synchronization threshold, and the number of test data blocks with the same recheck bit and the original check bit in the second group of first test data blocks Q2=2, which is equal to the synchronization threshold, then b2 is selected as the observation bit most likely to be located at the synchronization position. And, when b2 is determined to meet the alternative condition, the relationship between the number of test data blocks with the same recheck bit and the original check bit corresponding to the subsequent observation bit and the synchronization threshold is no longer determined, that is, the relationship between Q3 and the synchronization threshold is no longer determined.

[0127] For example, the recheck characteristic value may be the number of test data blocks whose recheck bits are identical to the original check bits. When the above traversal selection method is adopted, the extreme value is associated with the characteristic value. The extreme value may be a maximum value. Specifically, the number of test data blocks whose recheck bits are identical to the original check bits in each group of first test data blocks may be counted, and a group of first test data blocks having the largest number of test data blocks whose recheck bits are identical to the original check bits may be determined, and the observation bits corresponding to the group of first test data blocks may be used as the observation bits most likely to be located at the synchronization position.

[0128] When the recheck characteristic value is the number of test data blocks whose recheck bits are the same as the original check bits, the selection process of the observation bit most likely to be located at the synchronization position can also be referred to as Figure 4 .like Figure 4 As shown, the number of test data blocks whose re-check bits are the same as the original check bits in each group of first test data blocks with observation bits b1, b2, and b3 as starting bits is counted respectively, and recorded as Q1, Q2, and Q3 respectively, and the maximum value therein is determined. For example, Q1=0, Q2=0, and Q3=2, that is, the maximum value is Q3=2, then b3 is selected as the observation bit most likely to be located at the synchronization position, and the position where b3 is located is the most likely synchronization position.

[0129] For example, the re-check characteristic value may be the number of test data blocks whose re-check bits are different from the original check bits. When the above-mentioned early termination selection method is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be less than or equal to the synchronization threshold. Specifically, the relationship between the number of test data blocks whose re-check bits are different from the original check bits and the synchronization threshold in each group of first test data blocks is judged in turn, until it is determined that the number of test data blocks whose re-check bits are different from the original check bits in a group of first test data blocks is less than or equal to the synchronization threshold, then the observation bits corresponding to the group of first test data blocks that meet the alternative condition are used as the alternative bits. The value of the synchronization threshold can also be obtained through simulation analysis.

[0130] For example, the recheck characteristic value may be the number of test data blocks whose recheck bits are different from the original check bits. When the above-mentioned traversal selection method is adopted, the extreme value is associated with the characteristic value. The extreme value may be a minimum value. Specifically, the number of test data blocks whose recheck bits are different from the original check bits in each group of first test data blocks may be counted, and a group of first test data blocks having the least number of test data blocks whose recheck bits are different from the original check bits may be determined, and the observation bits corresponding to the group of first test data blocks may be used as the observation bits most likely to be located at the synchronization position.

[0131] Optionally, according to the characteristic values ​​of the multiple groups of first test data blocks, the synchronization possibility indexes of the multiple observation bits are respectively determined, and the larger the value of the synchronization possibility index is, the greater the possibility that the position of the observation bit is the synchronization position is. For example, when the characteristic value of the multiple groups of first test data blocks is the number of all-zero sequences in the check sequence of each group of first test data blocks in the multiple groups of first test data blocks, the synchronization possibility index can be positively correlated with the number of all-zero sequences, that is, the more the number of all-zero sequences is, the larger the value of the synchronization possibility index is, indicating that the possibility that the position of the observation bit is the synchronization position is greater. For example, when the characteristic value of the multiple groups of first test data blocks is the number of non-all-zero sequences in the check sequence of each group of first test data blocks in the multiple groups of first test data blocks, the synchronization possibility index can be negatively correlated with the number of non-all-zero sequences, that is, the smaller the number of non-all-zero sequences is, the larger the value of the synchronization possibility index is, indicating that the possibility that the position of the observation bit is the synchronization position is greater. Similarly, when the characteristic value of the multiple groups of first test data blocks is the number of zero elements in the check sequence of each group of first test data blocks in the multiple groups of first test data blocks, or the characteristic value of the multiple groups of first test data blocks is the number of correctable test data blocks in each group of first test data blocks in the multiple groups of first test data blocks, or the characteristic value of the multiple groups of first test data blocks is the number of test data blocks whose re-check bits are the same as the original check bits in each group of first test data blocks in the multiple groups of first test data blocks, the synchronization possibility indicator may be positively correlated with the number of zero elements or the number of correctable test data blocks or the number of test data blocks whose re-check bits are the same as the original check bits; when the multiple groups When the characteristic value of the first test data block is the number of non-zero elements in the check sequence of each group of first test data blocks in the multiple groups of first test data blocks, or the characteristic value of the multiple groups of first test data blocks is the number of uncorrectable test data blocks in each group of first test data blocks in the multiple groups of first test data blocks, or the characteristic value of the multiple groups of first test data blocks is the number of test data blocks whose re-check bits are different from the original check bits in each group of first test data blocks in the multiple groups of first test data blocks, the synchronization possibility indicator may be negatively correlated with the number of non-zero elements or the number of uncorrectable test data blocks or the number of test data blocks whose re-check bits are different from the original check bits; details will not be repeated here.

[0132] Optionally, when the number of observation bits with the largest value of the synchronization possibility index in the multiple groups of first test data blocks is greater than one, one of the observation bits can be selected as the observation bit most likely to be located at the synchronization position according to other conditions. For example, from the observation bits with the largest value of the synchronization possibility index, one observation bit is randomly selected as the observation bit most likely to be located at the synchronization position. For example, from the observation bits with the largest value of the synchronization possibility index, the observation bit that is ranked first in the data sequence is selected as the observation bit most likely to be located at the synchronization position.

[0133] S230, in the second stage, the candidate bit is verified, and when the verification is successful, the position of the candidate bit is determined to be the synchronization position. Specifically, S230 may include two steps, S231 and S232.

[0134] S231: divide a group of second test data blocks in the data sequence according to the candidate bit, the group of second test data blocks including at least one second test data block. The candidate bit is the observation bit most likely to be located at the synchronization position.

[0135] Optionally, in the second stage, when the method divides at least one second test data block in the data sequence according to the candidate bits, only a portion of the data sequence, such as a second subsequence in the data sequence, can be used. A group of second test data blocks is divided in the data sequence according to the candidate bits, that is, a group of second test data blocks is divided in the second subsequence according to the candidate bits.

[0136] Optionally, the second subsequence may be identical to the first subsequence in the first stage, that is, all bits of the second subsequence and the first subsequence are identical, and the two subsequences completely overlap. Optionally, the second subsequence may be partially identical to the first subsequence in the first stage, that is, some bits of the second subsequence and the first subsequence are identical, and the two subsequences partially overlap. Optionally, the second subsequence may be different from the first subsequence in the first stage, that is, all bits of the second subsequence and the first subsequence are different, and the two subsequences have no intersection.

[0137] When the intersection between the data used in the first stage and the second stage is less, the independence between the data used in the first stage and the second stage is stronger, and the accuracy of the code word synchronization result is higher. Therefore, when the first subsequence is different from the second subsequence, the accuracy of the code word synchronization result is higher.

[0138] In the second stage, a group of second test data blocks is divided in the second subsequence according to the candidate bits, ie, the observed bits most likely to be located at the synchronization position, and the group of second test data blocks includes at least one second test data block.

[0139] Partitioning a group of second test data blocks in the second subsequence according to the candidate bits may be performed by using the candidate bits as the starting bits of the at least one second test data block, thereby partitioning the at least one second test data block.

[0140] According to the observation bit that is most likely to be located at the synchronization position, a group of second test data blocks are divided in the second subsequence, or the observation bit that is most likely to be located at the synchronization position is used as the starting bit of the test data block to divide the second subsequence into multiple test data blocks, and at least one test data block is selected from the multiple test data blocks as the at least one second test data block. In this case, a number of test data blocks are spaced between the at least one second test data block and the observation bit that is most likely to be located at the synchronization position, and the at least one second test data block can be located before the observation bit that is most likely to be located at the synchronization position, or can be located after the observation bit that is most likely to be located at the synchronization position.

[0141] Optionally, the at least one second test data block may be continuous, that is, the at least one second test data block includes N continuous data blocks. When the length of each test data block is n bits, the at least one second test data block is obtained by selecting the subsequent N*n continuous bits.

[0142] Optionally, the at least one second test data block may also be discontinuous, and the starting position of each test data block in the at least one second test data block is associated with the candidate bit. Specifically, the interval between the starting position of each test data block and the candidate bit is an integer multiple of the length of the codeword, that is, the interval between every two test data blocks in the at least one second test data block is an integer multiple of the length of the codeword. Furthermore, the interval between every two test data blocks in the at least one second test data block may be the same or different.

[0143] S232: Verify the characteristic value of the at least one second test data block, and when the verification is successful, determine the position of the candidate bit as the synchronization position.

[0144] Optionally, the characteristic value of the at least one second test data block is verified, and the verification method may be an early termination verification method. Specifically, the characteristic values ​​of each second test data block in the at least one second test data block are accumulated in sequence to obtain a cumulative value, until the cumulative value meets the synchronization condition, the verification is successful, and the position of the candidate bit is determined to be the synchronization position.

[0145] The synchronization condition is associated with the characteristic value. Specifically,

[0146] The characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or,

[0147] The characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or,

[0148] The characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the cumulative value is greater than or equal to a synchronization threshold; or,

[0149] The characteristic value is the number of test data blocks with the same recheck bit and original check bit, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold;

[0150] The value of the synchronization threshold may also be obtained through simulation analysis. Furthermore, the synchronization threshold in step 230 and the synchronization threshold in step 2222 may be the same value or different values.

[0151] Optionally, the characteristic value of the at least one second test data block is verified, and the verification method may be a traversal verification method. Specifically, the characteristic values ​​of all second test data blocks in the at least one second test data block are added together to obtain a total value. When the total value satisfies a synchronization condition, the verification is successful, and the position of the candidate bit is determined to be the synchronization position.

[0152] The synchronization condition is associated with the characteristic value. Specifically,

[0153] The characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or,

[0154] The characteristic value is the number of non-all-zero sequences in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; or,

[0155] The characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or,

[0156] The characteristic value is the number of non-zero elements in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; or,

[0157] The characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or,

[0158] The characteristic value is the number of uncorrectable test data blocks, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; or,

[0159] The characteristic value is the number of test data blocks with the same recheck bit and original check bit, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or

[0160] The characteristic value is the number of test data blocks where the recheck bits are different from the original check bits, and the synchronization condition is that the total value is less than or equal to the synchronization threshold.

[0161] The value of the synchronization threshold may also be obtained through simulation analysis. Furthermore, the synchronization threshold in step 230 and the synchronization threshold in step 2222 may be the same value or different values.

[0162] In both the early termination verification method and the traversal verification method, the calculation of the characteristic values ​​can be performed in parallel, that is, multiple calculation units are used to simultaneously calculate the characteristic values ​​of multiple test data blocks. For example, 10 calculation units are used to simultaneously calculate the characteristic values ​​of 10 test data blocks. The parallel calculation method can save calculation time and reduce latency.

[0163] Figures 8 to 9 An exemplary process of determining the observation bit in the data sequence that is most likely to be located at the synchronization position, and verifying whether the position of the observation bit that is most likely to be located at the synchronization position is the synchronization position is shown. Figure 8 The linear block code shown is a BCH (360, 340) code, that is, each codeword is 360 bits long, and the length of the information data in each codeword is 340 bits. The modulation mode of the BCH (360, 340) code is Non-Return-to-Zero (NRZ), and the modulation order M is 2, so each codeword includes 1 bit. The check matrix for the BCH (360, 340) code is as follows:

[0164]

[0165] Where α is the Galois Field GF(2 10 )'s primitive element.

[0166] Figure 8 FIG. 1 shows a part of the data sequence received by the receiving end. It is necessary to confirm the starting position of the codeword in the data sequence, that is, the synchronization position. In combination with the above description, in the first stage, the observation bit that is most likely to be located at the synchronization position in the data sequence is determined. Figure 8As shown, in the first stage, the starting bit of the modulation symbol is selected as the observation bit every T·log2M bits, and T is 1, that is, the starting bit of the modulation symbol is selected as the observation bit every 1 bit. Therefore, 360 consecutive bits are selected as the observation bits, that is, the number of observation bits P is 360, as shown in Figure 8 b1, b2, b3, …, b shown 359 ,b 360 According to these observation bits, multiple groups of first test data blocks are divided from the data sequence, and the number of test data blocks N in each group of first test data blocks is 2, that is, each group of first test data blocks includes 2 test data blocks, such as Figure 8 Multiple groups B1, B2 are shown.

[0167] Combined with the above description, Figure 8 Among the multiple observation bit positions in the data sequence shown, only one observation bit position is the real synchronization position of the data sequence. The number of all-zero sequences in the check sequence of each group of first test data blocks is used as the basis for selecting the observation bit that is most likely to be located at the synchronization position. Figure 8 As shown, the check sequence S is a row vector with a length of 4. For example, the check sequence set of a group of first test data blocks starting with the observation bit b1 is S (1) , including S1 (1) ,S2 (1) , corresponding to test data blocks B1, B2, and similarly, to observe bits b2, b3, ..., b 359 ,b 360 A set of check sequences for a first test data block with a starting bit, S (2) ,S (3) ,…,S (359) ,S (360) . Count the number of all-zero sequences in the check sequence of the first test data block of each group, and record them as Q1, Q2, Q3, ..., Q 359 ,Q 360 .like Figure 8 As shown, Q1=0, that is, there is no all-zero sequence in the check sequence of a group of first test data blocks starting with the observation bit b1. Similarly, Q2=0, Q3=1, ..., Q 359 =2,Q 360 = 0. Assume that in all 360 Q values, Q 359 The value of is the largest, then the bit b will be observed 359 As the observation bit most likely to be located at the synchronization position. 359 It is the starting bit of a test data block, and every 360 bits thereafter are the starting bits of subsequent test data blocks.

[0168] When the observation bit most likely to be located at the synchronization position is selected as b 359 Afterwards, after the portion of the data sequence used in the first stage, that is, after the first subsequence, according to the b 359 A group of second test data blocks is divided out. That is, a group of second test data blocks is divided out in the second subsequence, and the second subsequence is different from the first subsequence. Fig. 9 As shown, the group of second test data blocks includes 4 test data blocks. The characteristic value of the at least one second test data block is verified, and the characteristic value is the number of all-zero sequences in the check sequence of the at least one second test data block. The above-mentioned traversal verification method is adopted, that is, the number of all-zero sequences in the check sequence of all second test data blocks in the at least one second test data block is added to obtain a total value. When the total value is greater than or equal to the synchronization threshold, the verification is successful. The synchronization threshold is 2. Fig. 9 As shown in the figure, in the check sequence of the 4 test data blocks, the number of all-zero sequences is 3, which is greater than 2, so b is determined. 359 The current location is the synchronization location.

[0169] Optionally, when the verification is unsuccessful, the above step S220 is re-executed, that is, the first stage is re-executed, and the observation bit that is most likely to be located at the synchronization position is re-selected.

[0170] Step S230 is an optional step, that is, the method may only include the first stage. In this case, step S240 is directly entered after step S220. In this case, in the method, after determining the candidate bit, the position of the candidate bit is directly determined as the synchronization position. That is, the most likely synchronization position is directly used as the synchronization position.

[0171] S240: Determine whether the data sequence is in a synchronization locked state.

[0172] After the receiving end determines the synchronization position, the received data sequence can be divided into multiple synchronization code words according to the synchronization position. When the data sequence is divided into multiple synchronization code words according to the synchronization position, it can be considered that the data sequence is in a synchronization lock position. That is, after determining the synchronization position, the receiving end determines that the data sequence is in a synchronization lock state. When the data sequence is in a synchronization lock state, the receiving end can perform operations such as error detection and error correction on the data sequence.

[0173] S250, lock loss judgment.

[0174] After the receiving end starts to perform error detection and correction operations on the data sequence, it is still necessary to continue to observe whether the codeword division in the data sequence is accurate, that is, whether the synchronization position is accurate. When the synchronization position is inaccurate, the content of each test data block divided according to the synchronization position no longer corresponds to the real codeword. At this time, it can also be said that the synchronization lock state of the data sequence is lost. Therefore, the process of judging whether the synchronization position of the data sequence is accurate can also be called the loss of lock judgment process.

[0175] In the unlocking judgment process, multiple synchronization code words are divided from the data sequence according to the synchronization position, and the synchronization position is the starting position of the multiple synchronization code words; the characteristic values ​​of the multiple synchronization code words are verified, and when the verification fails, the data sequence is determined to be in the unlocked state.

[0176] Optionally, the multiple synchronization codewords may be continuous, that is, the multiple synchronization codewords include N continuous codewords. When the length of each codeword is n bits, the multiple synchronization codewords are obtained by selecting the subsequent N*n continuous bits.

[0177] Optionally, the multiple synchronization codewords may also be discontinuous, and the starting position of each codeword in the multiple synchronization codewords is associated with the synchronization position. Specifically, the interval between the starting position of each synchronization codeword and the synchronization position is an integer multiple of the length of the codeword, that is, the interval between every two synchronization codewords in the multiple synchronization codewords is an integer multiple of the length of the codeword. Furthermore, the interval between every two synchronization codewords in the multiple synchronization codewords may be the same or different.

[0178] Optionally, the characteristic values ​​of the multiple synchronization codewords are verified, and the verification method may be an early termination verification method. Specifically, the characteristic values ​​of each synchronization codeword in the multiple synchronization codewords are accumulated in sequence to obtain a cumulative value, until the cumulative value meets the unlocking condition, the verification fails, and the position of the candidate bit is determined to be the synchronization position.

[0179] The lock-out condition is associated with the characteristic value. Specifically,

[0180] The characteristic value is the number of non-all-zero sequences in the check sequence, and the lock-out condition is that the cumulative value is greater than or equal to the synchronization threshold; or,

[0181] The characteristic value is the number of non-zero elements in the check sequence, and the lock-out condition is that the cumulative value is greater than or equal to the synchronization threshold; or,

[0182] The characteristic value is the number of uncorrectable codewords, and the lock-out condition is that the cumulative value is greater than or equal to a synchronization threshold; or,

[0183] The characteristic value is the number of codewords whose recheck bits are different from the original check bits, and the lock-out condition is that the accumulated value is greater than or equal to the synchronization threshold;

[0184] The length of the codeword is n bits, the first k bits of the codeword are information bits, the last nk bits of the codeword are the original check bits, the re-check bits are obtained based on the information bits, the length of the re-check bits is nk bits, and n and k are integers.

[0185] The value of the synchronization threshold can also be obtained through simulation analysis. In addition, the synchronization threshold in step 250 and the synchronization threshold in step 230 and step 2222 can be the same value or different values.

[0186] Optionally, the characteristic values ​​of the multiple synchronization codewords are verified, and the verification method may be a traversal verification method. Specifically, the characteristic values ​​of all synchronization codewords in the multiple synchronization codewords are added to obtain a total value, and when the total value meets the unlocking condition, the verification fails, and the position of the candidate bit is determined to be the synchronization position.

[0187] The synchronization condition is associated with the characteristic value. Specifically,

[0188] The characteristic value is the number of all-zero sequences in the check sequence, and the lock-out condition is that the total value is less than or equal to the synchronization threshold; or,

[0189] The characteristic value is the number of non-all-zero sequences in the check sequence, and the lock-out condition is that the total value is greater than or equal to the synchronization threshold; or,

[0190] The characteristic value is the number of zero elements in the check sequence, and the lock-out condition is that the total value is less than or equal to the synchronization threshold; or,

[0191] The characteristic value is the number of non-zero elements in the check sequence, and the lock-out condition is that the total value is greater than or equal to the synchronization threshold; or,

[0192] The characteristic value is the number of error-correctable codewords, and the lock-out condition is that the total value is less than or equal to the synchronization threshold; or,

[0193] The characteristic value is the number of uncorrectable codewords, and the lock-out condition is that the total value is greater than or equal to a synchronization threshold; or,

[0194] The characteristic value is the number of codewords with the same recheck bit and original check bit, and the lock-out condition is that the total value is less than or equal to the synchronization threshold; or,

[0195] The characteristic value is the number of codewords where the recheck bit is different from the original check bit, and the lock-out condition is that the total value is greater than or equal to the synchronization threshold;

[0196] The length of the codeword is n bits, the first k bits of the codeword are information bits, the last nk bits of the codeword are the original check bits, the re-check bits are obtained based on the information bits, the length of the re-check bits is nk bits, and n and k are integers.

[0197] The value of the synchronization threshold can also be obtained through simulation analysis. In addition, the synchronization threshold in step 250 and the synchronization threshold in step 230 and step 2222 can be the same value or different values.

[0198] In both the early termination verification method and the traversal verification method, the calculation of the characteristic values ​​can be performed in parallel, that is, multiple calculation units are used to simultaneously calculate the characteristic values ​​of multiple test data blocks. For example, 10 calculation units are used to simultaneously calculate the characteristic values ​​of 10 test data blocks. The parallel calculation method can save calculation time and reduce latency.

[0199] Fig.10 An exemplary process of determining a lock-out is shown. Fig.10 As shown, 5 synchronization codewords are divided from the data sequence according to the synchronization position, and the number of correctable error codewords is counted. For example, in the decoding state, 0 indicates uncorrectable error and 1 indicates correctable error. Fig.10 Among the five synchronization codewords shown, the number of correctable codewords is 1. If the unlocking threshold is 3, the number of correctable codewords is less than the unlocking threshold, and it is determined that the five synchronization codewords meet the unlocking condition, and the data sequence is in the unlocking state.

[0200] Optionally, when the verification has not failed, it is determined that the synchronization lock state of the data sequence has not been lost.

[0201] Optionally, after determining that the synchronization lock state of the data sequence has not been lost, the data sequence may be moved backwards for a certain interval, multiple synchronization code words may be selected, and the multiple synchronization code words selected backwards may be judged to determine whether they meet the lock-loss condition. Optionally, the moving backwards for a certain interval may be a moving of a test data block, that is, for each synchronization code word, multiple synchronization code words are observed backwards starting from the synchronization code word to make a lock-loss judgment.

[0202] S260: Determine that the data sequence is in an unlocked state.

[0203] Optionally, when it is determined that the data sequence is in a lost-lock state, the updated synchronization position of the data sequence is continued to be determined. Specifically, the first stage and the second stage are re-executed, and the synchronization position determined in the re-executed second stage is used as the updated synchronization position. In this way, a closed-loop operation of synchronization lock-lost-synchronization lock is formed, ensuring that the communication system is in a normal working state of synchronization lock for as much time as possible.

[0204] This method can solve the technical problems of adding additional data and poor cascade scalability in the AM synchronization scheme. In addition, there is no need to insert additional data into the data stream at the sending end, and thus there is no need to introduce an idle code block addition and deletion mechanism on the Ethernet interface, no need to design a corresponding logic processing unit, and no need to reserve bandwidth in advance for the inserted AM sequence. If it is necessary to add a level of FEC on the basis of the original FEC and use a two-level FEC cascade, it can be avoided that the original idle code block addition and deletion mechanism cannot be applied to the AM sequence of the second-level FEC, and the technical problem that the addition of the AM sequence to the second-level FEC affects the high-precision clock synchronization performance can be avoided. This method can achieve the technical effect of high-precision codeword synchronization of the data stream at the receiving end, and its synchronization performance achieves a high reliability.

[0205] Steps S240, S250 and S260 are all optional steps, that is, the method can be used only to determine the synchronization position, and error detection or correction processing may not be performed on the data sequence in the synchronization lock state, and it may not be judged whether the data sequence will enter the unlocked state later.

[0206] Through simulation comparison, the codeword synchronization method provided by the present application is superior to the existing AM synchronization scheme in various performance indicators such as average synchronization lock time, average occurrence time of false lock, and average occurrence time of false loss lock. Therefore, from an overall perspective, the codeword synchronization method provided by the present application can achieve better synchronization performance than the AM synchronization scheme.

[0207] Fig.11 The code word synchronization method of an embodiment of the present application is shown. The method comprises the following steps:

[0208] Step 1: Receive a data sequence, wherein the data sequence includes a plurality of bits. The specific process of step 1 can refer to the above description of step S210.

[0209] Step 2: determine a candidate bit in the data sequence, the candidate bit being included in the multiple bits. The candidate bit is the observation bit that is most likely to be located at the synchronization position. The specific process of step 2 can refer to the above description of step S220.

[0210] Step three: determine a synchronization position according to the candidate bit, where the synchronization position is used to indicate a starting position of the codeword.

[0211] Optionally, determining the synchronization position according to the candidate bit may be, after selecting the observation bit most likely to be located at the synchronization position, further verifying whether the position of the observation bit most likely to be located at the synchronization position is the synchronization position. The candidate bit is the observation bit most likely to be located at the synchronization position. At this time, the specific process of step three can refer to the description of step S230 above. At this time, the method at least includes Figure 2 S210, S220, S230 shown.

[0212] Optionally, determining the synchronization position according to the candidate bit may also be after selecting the observation bit most likely to be located at the synchronization position, directly using the observation bit most likely to be located at the synchronization position as the synchronization position. The candidate bit is the observation bit most likely to be located at the synchronization position. In this case, the method at least includes: Figure 2 S210, S220 shown.

[0213] It can be seen that in the above two methods of determining the synchronization position according to the candidate bits, the bit located at the synchronization position is included in the candidate bits, and the candidate bits are the observed bits most likely to be located at the synchronization position.

[0214] Optionally, after step 3, the method further includes: determining that the data sequence is in a synchronization lock state. For the specific process, please refer to the above description of step S240.

[0215] Optionally, after step 3, the method further includes: loss of lock determination. For the specific process, please refer to the above description of step S250.

[0216] Optionally, the method may further include step 4, in response to the data sequence being in a lost-lock state, determining an update synchronization position of the data sequence. For the specific process, please refer to the above description of step S260.

[0217] The codeword synchronization method in the embodiment of the present application is executed by a communication device, and the communication device can be any device that executes FEC, including but not limited to routers, switches, servers, and terminal devices.

[0218] Fig.12 A possible structural diagram of a communication device involved in an embodiment of the present application is shown. Fig.12 The communication device 1200 includes: a receiving unit 1201 and a processing unit 1202. These units can perform the above Figure 2-11 For example,

[0219] The receiving unit 1201 is configured to receive a data sequence, where the data sequence includes a plurality of bits.

[0220] The processing unit 1202 is configured to determine a candidate bit in the data sequence, where the candidate bit is included in the multiple bits; and determine a synchronization position according to the candidate bit, where the synchronization position is used to indicate a starting position of a codeword in the data sequence.

[0221] Fig.13 is another structural diagram of the communication device involved in the embodiment of the present application. Fig.13 The communication device 1300 includes at least one processor 1301 and at least one communication interface 1304 . Optionally, the device 1300 may also include a memory 1303 .

[0222] Processor 1301 can be a central processing unit (CPU), a general processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It can implement or execute various logic boxes, modules and circuits described in conjunction with the disclosure of the embodiments of the present application. The processor can also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The processor can be used to determine the candidate bits in the data sequence, and determine the synchronization position according to the candidate bits. To implement the method provided in the embodiments of the present application.

[0223] Optionally, the communication bus 1302 is used to transmit information between the processor 1301, the communication interface 1304 and the memory 1303. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.13 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0224] The memory 1303 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1303 may exist independently and be connected to the processor 1301 via the communication bus 1302. The memory 1303 may also be integrated with the processor 1301.

[0225] Optionally, the memory 1303 is used to store program codes or instructions for executing the solution of the present application, and the execution is controlled by the processor 1301. Fig.12 In the case of the embodiment shown, and Fig.12 When each unit described in the embodiment is implemented by software, the execution Fig.12 The software or program code required for the functions of each unit in the processor 1301 is stored in the memory 1303. The processor 1301 is used to execute the program code stored in the memory 1303. The program code may include one or more software modules. Optionally, the processor 1301 itself may also store the program code or instructions for executing the solution of the present application.

[0226] The communication interface 1304 uses any transceiver-like device to communicate with other devices or communication networks, and the communication network can be Ethernet, a radio access network (RAN) or a wireless local area network (WLAN), etc. In an embodiment of the present application, the communication interface 1304 can be used to receive messages sent by other nodes in the segment routing network, and can also send messages to other nodes in the segment routing network. The communication interface 1304 can be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface or an Asynchronous Transfer Mode (ATM) interface.

[0227] In a specific implementation, as an embodiment, the device 1300 may include multiple processors, such as Fig.13 1301 and processor 1305 shown in FIG. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0228] In a specific embodiment, the processor 1301 in the network device 1300 is used to receive a data sequence through a communication interface, the data sequence including multiple bits; determine a candidate bit in the data sequence, the candidate bit included in the multiple bits; determine a synchronization position according to the candidate bit, the synchronization position is used to indicate the starting position of a codeword in the data sequence. Please refer to the above for the detailed processing process of the processor Figure 2 In the embodiment shown, steps S210, S220, S230, S240, S250, S260, Figure 3 In the illustrated embodiment, steps S221, S222, and Fig.11 The detailed description of steps one to three is omitted here.

[0229] The communication interface in the network device 1300 is used for the network device 1300 to receive and send data sequences through the network system. Figure 2 In the illustrated embodiment, S210, and Fig.11 The detailed description of step 1 is omitted here.

[0230] Fig.14 Another structural diagram of the communication device involved in the embodiment of the present application. When the communication device is a forwarding device in the network, such as a router or a switch, the communication device can refer to Fig.14The schematic diagram of the device structure shown in FIG. 1400 includes a main control board and one or more interface boards, and the main control board is connected to the interface board in communication. The main control board is also called a main processing unit (MPU) or a route processing card. The main control board is responsible for controlling and managing each component in the device 1400, including routing calculation, device management and maintenance functions. The interface board is also called a line processing unit (LPU) or a line card, which is used to forward data. In some embodiments, the device 1400 may also include a switching fabric board, which is connected to the main control board and the interface board in communication. The switching fabric board is used to forward data between the interface boards. The switching fabric board may also be called a switch fabric unit (SFU). The interface board includes a central processing unit, a memory, a forwarding chip and a physical interface card (PIC). The central processing unit is connected to the memory, the network processor and the physical interface card in communication. The memory is used to store a forwarding table. The forwarding chip is used to forward the received data frame based on the forwarding table stored in the memory. If the destination address of the data frame is the address of the device 1400, the data frame is sent to the CPU for processing; if the destination address of the data frame is not the address of the device 1400, the next hop and the output interface corresponding to the destination address are found from the forwarding table according to the destination address, and the data frame is forwarded to the output interface corresponding to the destination address. The forwarding chip can be a network processor (NP). The PIC is also called a daughter card, which can be installed on the interface board and is responsible for converting the photoelectric signal into a data frame and forwarding the data frame to the forwarding chip for processing after checking the legitimacy of the data frame. In some embodiments, the central processing unit can also perform the functions of the forwarding chip, such as realizing software forwarding based on a general-purpose CPU, so that the forwarding chip is not required in the interface board. The communication connection between the main control board, the interface board, and the switching network board can be realized through a bus. In some embodiments, the forwarding chip can be realized by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0231] Logically, device 1400 includes a control plane and a forwarding plane. The control plane includes a main control board and a central processing unit, and the forwarding plane includes various components for performing forwarding, such as a memory, a PIC, and an NP. The control plane performs functions such as a router, generates a forwarding table, processes signaling and protocol messages, and configures and maintains the status of PE1. The control plane sends the generated forwarding table to the forwarding plane. On the forwarding plane, the NP forwards the message received by the PIC of device 1400 based on the forwarding table sent by the control plane. The forwarding table sent by the control plane can be stored in a memory. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same device.

[0232] In a specific embodiment, the interface board is used to receive a data sequence, and the data sequence includes a plurality of bits. Figure 2 In the illustrated embodiment, S210, and Fig.11 The detailed description of step 1 is omitted here. The main control board is used to determine the candidate bit in the data sequence, and the candidate bit is included in the multiple bits; determine the synchronization position according to the candidate bit, and the synchronization position is used to indicate the starting position of the codeword in the data sequence. For detailed processing, please refer to the above Figure 2 In the embodiment shown, steps S210, S220, S230, S240, S250, S260, Figure 3 In the illustrated embodiment, steps S221, S222, and Fig.11 The detailed description of steps one to three is omitted here.

[0233] In a possible implementation, an inter-process communication (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate through the IPC channel.

[0234] The present application embodiment provides a chip, which includes a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory to execute the method in the above method embodiment, that is, Figure 2-11 The method in the illustrated embodiment.

[0235] Optionally, the chip only includes a processor, and the processor is used to read and execute a computer program stored in the memory. When the computer program is executed, the processor executes the method in the method embodiment, that is, Figure 2-11 The method in the illustrated embodiment.

[0236] Optionally, the chip can be used in an application scenario of a two-stage FEC cascade. Specifically, the two-stage FEC cascade includes an inner FEC and an outer FEC, and the chip provided in the embodiment of the present application is used for the inner FEC. The inner FEC adopts the codeword synchronization method described in the present application, also referred to as FEC1; the outer FEC can adopt an AM synchronization scheme, also referred to as FEC2. At this time, the FEC1 and the FEC2 can be located on the same chip or on different chips. That is, the chip provided in the embodiment of the present application can include only the FEC1, or can include the FEC1 and the FEC2.

[0237] The embodiment of the present application provides a network system. The network system includes a receiving device and a sending device. The receiving device is used to receive a data sequence sent by the sending device. The receiving device can perform the above Figure 2-11 Steps in the illustrated embodiment.

[0238] An embodiment of the present application also provides a non-volatile storage medium for storing software instructions used in the aforementioned embodiments, which includes a program for executing the method shown in the aforementioned embodiments. When the program is executed on a computer or network device, it enables the computer or network device to execute the method in the aforementioned method embodiment.

[0239] The embodiment of the present application also provides a computer program product including computer program instructions. When the computer program product is executed on a computer, the network node executes the method in the aforementioned method embodiment.

[0240] It should be noted that any of the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the embodiment drawings of the network device or host provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art can understand and implement it without paying creative labor.

[0241] The steps of the method or algorithm described in the disclosure of the embodiments of the present application can be implemented in hardware or by executing software instructions by a processor. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), hard disk, mobile hard disk, optical disk or any other form of storage medium known in the art. The storage medium is coupled to the processor so that the processor can read information from the storage medium. Of course, the storage medium can also be a component of the processor.

[0242] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only the specific implementation method of the present application and is not intended to limit the scope of protection of the present application. Any modifications, replacements, improvements, etc. made on the basis of the technical solutions of the present application should be included in the scope of protection of the present application.

[0243] In the present application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various described examples, a first test data block may be referred to as a second test data block, and similarly, a second test data block may be referred to as a first test data block. Both the first test data block and the second test data block may be test data blocks, and in some cases, may be separate and different test data blocks.

[0244] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple second messages means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0245] It should be understood that the terms used in the description of the various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0246] It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and / or" is a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0247] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0248] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0249] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0250] It should also be understood that the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrase "if it is determined that ..." or "if [a stated condition or event] is detected" may be interpreted to mean "upon determining that ..." or "in response to determining that ..." or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0251] It should be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. A codeword synchronization method, characterized in that: The method comprises: receiving a data sequence, the data sequence comprising a plurality of bits; determining a candidate bit in the data sequence, the candidate bit being included in the plurality of bits; Determine a plurality of second test data blocks in the data sequence according to the candidate bits; wherein the positions of the candidate bits are the starting positions of the plurality of second test data blocks, or the starting positions of the plurality of second test data blocks are separated from the candidate bits by a plurality of data blocks; verifying characteristic values ​​of the plurality of second test data blocks; When the verification succeeds, the position of the candidate bit is determined as a synchronization position, and the synchronization position is used to indicate a starting position of a codeword in the data sequence.

2. The method according to claim 1, characterized in that The verifying the characteristic values ​​of the plurality of second test data blocks comprises: The characteristic values ​​of the respective second test data blocks in the plurality of second test data blocks are accumulated in sequence to obtain an accumulated value, and the verification is successful when the accumulated value satisfies a synchronization condition.

3. The method according to claim 2, characterized in that The characteristic value is a characteristic value of a verification sequence.

4. The method according to claim 2 or 3, characterized in that: The characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold.

5. The method according to claim 1, characterized in that The verifying the characteristic values ​​of the plurality of second test data blocks comprises: The characteristic values ​​of all the second test data blocks in the plurality of second test data blocks are added together to obtain a total value, and when the total value satisfies a synchronization condition, the verification is successful.

6. The method according to claim 5, characterized in that The characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold.

7. The method according to claim 1, characterized in that The determining of the candidate bits in the data sequence comprises: Selecting at least one observation bit from the data sequence; According to the characteristic value of at least one group of first test data blocks corresponding to the at least one observation bit, one observation bit is selected from the at least one observation bit as the candidate bit, wherein each group of first test data blocks in the at least one group of first test data blocks includes multiple first test data blocks, and the position of each observation bit in the at least one observation bit is the starting position of each group of first test data blocks in the at least one group of first test data blocks.

8. The method according to claim 7, characterized in that in, The selecting, according to the characteristic value of at least one group of first test data blocks corresponding to the at least one observation bit, an observation bit from the at least one observation bit as the candidate bit comprises: sequentially determining whether the characteristic value of each group of first test data blocks in the at least one group of first test data blocks satisfies the candidate condition, until determining that the characteristic value of a group of first test data blocks satisfies the candidate condition; The observation bits corresponding to the group of first test data blocks that meet the candidate condition are used as the candidate bits.

9. The method according to claim 8, characterized in that The characteristic value of the group of first test data blocks is the total value of the number of all-zero sequences in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to the synchronization threshold.

10. The method according to claim 8, characterized in that The characteristic value of the group of first test data blocks is the cumulative value of the number of all-zero sequences in the check sequences of the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold, and X is an integer greater than 0.

11. The method according to claim 7, characterized in that in, The selecting, according to the characteristic value of at least one group of first test data blocks corresponding to the at least one observation bit, an observation bit from the at least one observation bit as the candidate bit comprises: The characteristic value of each group of first test data blocks in the at least one group of first test data blocks is compared, and the observation bits corresponding to the group of first test data blocks whose characteristic values ​​are extreme values ​​are used as the candidate bits.

12. The method according to claim 11, characterized in that The characteristic value is the number of all-zero sequences in the check sequence, and the extreme value is the maximum value.

13. The method according to claim 6, 9 or 10, characterized in that The synchronization threshold is smaller than the number of the plurality of second test data blocks.

14. The method according to any one of claims 7 to 12, characterized in that: in, The selecting at least one observation bit from the data sequence comprises: Selecting one bit from the data sequence every T bits as the observation bit, where T is an integer greater than zero; or, One bit is selected from the data sequence every L*n+T bits as the observation bit, where L is the number of the interval test data blocks, the length of the test data block is the n bits, and L and T are integers greater than zero.

15. The method according to any one of claims 7 to 12, characterized in that: The data sequence is a modulated signal, and the data sequence includes a plurality of modulation symbols, wherein: The selecting at least one observation bit from the data sequence comprises: Selecting the starting bit of a modulation symbol at intervals of T modulation symbols from the data sequence as the observation bit, where T is an integer greater than zero; or From every L*m + T modulation code elements in the data sequence, select the starting bit of the modulation code element as the observation bit, where L is the number of the interval test data blocks, the length of the test data block is the m modulation code elements, and L and T are integers greater than zero.

16. The method according to any one of claims 7 to 12, characterized in that: The at least one observation bit includes a plurality of observation bits.

17. The method according to any one of claims 7 to 12, characterized in that: in, The at least one set of first test data blocks is partially identical to or different from the plurality of second test data blocks.

18. The method according to claim 1, characterized in that The method further comprises: In response to the data sequence being in an out-of-lock state, an update synchronization position of the data sequence is determined.

19. The method according to claim 18, characterized in that in, The step of determining an update synchronization position of the data sequence comprises: reselecting at least one observation bit from the data sequence; Re-selecting an observation bit from the at least one observation bit as a candidate bit according to the characteristic value of the at least one group of first test data blocks corresponding to the at least one observation bit, wherein each group of first test data blocks in the at least one group of first test data blocks includes a plurality of first test data blocks, and the position of each observation bit in the at least one observation bit is the starting position of each group of first test data blocks in the at least one group of first test data blocks; Re-determine a plurality of second test data blocks in the data sequence according to the candidate bit; wherein the position of the candidate bit is the starting position of the plurality of second test data blocks, or the starting position of the plurality of second test data blocks is separated from the candidate bit by a plurality of data blocks; re-verifying the characteristic values ​​of the plurality of second test data blocks; When the verification succeeds, the position of the candidate bit is determined as the update synchronization position.

20. The method according to claim 18 or 19, characterized in that in, The method further comprises: Determining a plurality of synchronization codewords from the data sequence according to the synchronization position, wherein the synchronization position is a starting position of the plurality of synchronization codewords; The characteristic values ​​of the plurality of synchronization code words are verified, and when the verification fails, the data sequence is determined to be in the unlocked state.

21. The method according to claim 20, characterized in that The verifying the characteristic values ​​of the multiple synchronization code words includes: The characteristic values ​​of each synchronization codeword in the plurality of synchronization codewords are accumulated in sequence to obtain an accumulated value, and when the accumulated value satisfies a lock-out condition, the verification fails.

22. The method according to claim 21, characterized in that The characteristic value is the number of non-all-zero sequences in the check sequence, and the lock-out condition is that the accumulated value is greater than or equal to the synchronization threshold.

23. The method according to claim 20, characterized in that The verifying the characteristic values ​​of the multiple synchronization code words includes: The characteristic values ​​of all synchronization code words in the multiple synchronization code words are added together to obtain a total value, and when the total value meets the lock-out condition, the verification fails.

24. The method according to claim 23, characterized in that The characteristic value is the number of non-all-zero sequences in the check sequence, and the lock-out condition is that the total value is greater than or equal to the synchronization threshold.

25. The method according to claim 1, characterized in that The data sequence is a linear block code.

26. The method according to claim 1, characterized in that The method further comprises: The data sequence is received from a transmitting end.

27. The method according to claim 1, characterized in that The length of the test data block is the same as the length of the codeword.

28. The method according to claim 1, characterized in that The length of each data block in the plurality of data blocks is the same as the length of the codeword.

29. A communication device, characterized in that: The communication device is used to execute the method according to any one of claims 1 to 28.

30. A chip, characterized in that: The chip is used to execute the method according to any one of claims 1 to 28.

31. A chip system, characterized in that: The chip system comprises at least one chip, and the at least one chip is used to execute the method according to any one of claims 1-28.

32. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program runs on a processor, the method described in any one of claims 1 to 28 is implemented.

33. A network system, characterized in that: The network system includes a sending device and a receiving device, and the receiving device is used to execute the method according to any one of claims 1-28.

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