A carrier index chaotic keying method and system based on chaotic shaping filter

Abstract

The present invention discloses a carrier index chaotic keying method and system based on a chaotic shaping filter, which relates to the field of communication technology, including: collecting LPS data bits for preprocessing; inputting a chaotic shaping filter, outputting a chaotic signal, and performing carrier index mapping; combining the chaotic signal with a carrier to generate a modulated signal, which is sent through an antenna; the antenna receives a product signal from a transmitting end, performs time domain sampling through a corresponding matching filter, and outputs a discrete sequence; performs demodulation processing, recovers the carrier index bit and the parallel LPS data bit; and combines them into a demodulated serial modulated bit stream through parallel-to-serial conversion. The present invention utilizes the advantage of the chaotic shaping filter carrying the LPS data bit within a symbol period, carries the index bit information and the modulation bit information on the carrier and sends them, so that the carrier resources are more utilized, the modulation data bit transmission rate is improved, and the index bit data bit can have a better bit error rate performance.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a carrier index chaotic keying method and system based on a chaotic shaping filter. Background Art

[0002] Incoherent demodulation has been widely used in chaotic communications because it avoids chaotic synchronization that is difficult to achieve in coherent demodulation due to channel interference and system parameter mismatch. The classic method of incoherent demodulation is Differential Chaos Shift Keying (DCSK, which has good robustness and good bit error rate performance because the reference signal and the information signal experience the same channel distortion. However, the message transmission rate of this method is relatively low because the reference signal uses half of the time slot for transmission.

[0003] Chaotic communication shows its advantages, such as using the simplest matched filter to maximize the signal-to-noise ratio and improve the resistance to multipath interference. Chaotic shaping filter (CSF) is proposed to generate chaotic baseband signals in wireless communication. Another advantage of chaotic shaping filter is that it can generate chaotic signals as extended sequences in chaotic keying and encode the information in the sequence.

[0004] Index modulation (IM) is a new technology developed in multi-carrier systems. It uses the subcarrier index as a resource to carry information. IM is developed based on subcarrier IM technology. It transmits information in an on-off keying manner and requires a perfect feedforward from the transmitter to the receiver to implement the mapping method of the subcarrier index bit. Summary of the invention

[0005] In view of the above-mentioned problems, the present invention is proposed.

[0006] Therefore, the technical problem solved by the present invention is: how to provide a carrier index chaotic keying method and system based on a chaotic shaping filter to solve the problem that the existing CI-DCSK2 modulation and demodulation method has a general data transmission rate and poor bit error performance.

[0007] To solve the above technical problems, the present invention provides the following technical solutions: a carrier index chaotic keying method based on chaotic shaping filter, which comprises the following steps:

[0008] Collect serial LPS data bits for pre-processing.

[0009] The processed LPS data bits are input into the chaotic shaping filter and a chaotic signal is output.

[0010] The HPS data bits are used as carrier index bits for carrier index mapping.

[0011] The chaotic signal is combined with a carrier to generate a modulated signal, and multiple modulated signals are added together and sent through the antenna.

[0012] The antenna receives the signal from the transmitter and multiplies it with the synchronized subcarriers respectively, outputs the product signal, samples the product signal in the time domain through the corresponding matched filter, outputs the discrete sequence for corresponding demodulation processing, and recovers the carrier index bit and the parallel LPS data bit.

[0013] The recovered parallel LPS data bits are combined into a demodulated serial modulation bit stream through parallel-to-serial conversion. As a preferred solution of the carrier index chaotic keying method based on chaotic shaping filter described in the present invention, the preprocessing includes converting (M-1)*k LPS data bits as modulation bits b into serial bipolar bits b through a polarity converter. ’ ;

[0014] Transform (M-1)*k serial bipolar modulation bits b ’ , converted into M-1 groups of parallel modulation bits through a serial-to-parallel converter.

[0015] As a preferred solution of the carrier index chaotic keying method based on the chaotic shaping filter described in the present invention, wherein: the chaotic signal is inputting the processed LPS data bits into the chaotic shaping filter to generate M-1 groups of chaotic signals ;

[0016] The p HPS data bits are used as carrier index bits for index mapping, and one subcarrier is indexed and selected from the M subcarriers to be inactive and send 0, and the remaining M-1 subcarriers are activated and send M-1 groups of chaotic signals carrying LPS data;

[0017] The chaotic signal is combined with the subcarrier to generate M modulated signals, and the M modulated signals are added together to obtain the signal h, which is sent through the antenna.

[0018] As a preferred solution of the carrier index chaotic keying method based on chaotic shaping filter described in the present invention, wherein: the M-1 groups of chaotic signals It is generated by each group of k LPS data bits from the 1st group to the M-1th group through a chaotic shaping filter.

[0019] The center frequency of the subcarrier is .

[0020] The index bit is composed of p HPS data as the carrier index bit S p, obtained through the serial-to-parallel converter, the expression is:

[0021] ,

[0022] Where M is the number of subcarriers available in the system, is the number of carrier index bits.

[0023] The bipolar bits are obtained by converting the polarity of each group of k LPS data bits from the 1st group to the M-1th group.

[0024] The expression of the first group of LPS data bits is:

[0025] S 1 = [ s 1,1 … s 1,k ] T ,

[0026] in, is the first LPS bit of group 1, is the kth LPS bit of group 1.

[0027] The expression of the LPS data bits of group M-1 is:

[0028] ,

[0029] in, is the LPS data bit of group 1, It is the LPS data bit of the M-1th group.

[0030] As a preferred solution of the carrier index chaotic keying method based on chaotic shaping filter described in the present invention, wherein: the product signal is when the antenna receives the signal from the transmitting end, the signal is multiplied by the frequency The M synchronized subcarriers are multiplied respectively to obtain M product signals.

[0031] As a preferred solution of the carrier index chaotic keying method based on chaotic shaping filter described in the present invention, wherein: the discrete sequence is obtained by sampling M product signals in the time domain through corresponding matched filters respectively. and stored in the matrix In the generated matrix The M discrete sequences in are squared and summed row by row to obtain a new matrix as the decision matrix .

[0032] The decision matrix Input minimum detector, output the minimum value in the matrix, confirm the row coordinate of the minimum value, restore to binary data, and output the demodulated index bit .

[0033] from Remove the row with the minimum square sum from the matrix and select the remaining M-1 rows of correlation values ​​for threshold decision. The first row sequence is , perform threshold judgment on the k values ​​of the sequence and recover the k LPS data bits of the first group , the second row sequence is , perform threshold judgment on the k values ​​of the sequence, and recover the k LPS data bits of the second group , then after the M-1th corresponding threshold decision, the M-1th row sequence is , perform threshold judgment on the k values ​​of the sequence and recover the k LPS data bits of the M-1th group .

[0034] The recovered M-1 groups of parallel LPS data bits are combined into a demodulated serial modulation bit stream through parallel-to-serial conversion .

[0035] Another object of the present invention is to provide a carrier index chaotic keying system based on a chaotic shaping filter, which can transmit a reference signal through the LPS data bits of the chaotic shaping filter itself and does not need to use half of the time slot, thereby solving the problem of the general data transmission rate and poor bit error rate performance of the existing CIDCSK2.

[0036] To solve the above technical problems, the present invention provides the following technical solutions: a carrier index chaotic keying system based on a chaotic shaping filter, comprising: a first digital device, a first analog device, a second digital device and a second analog device.

[0037] The first digital device includes a serial-to-parallel converter, a polarity converter, and an index selector.

[0038] The first analog device includes M-1 chaotic shaping filters, M first carrier multipliers and carrier adders.

[0039] The chaos shaping filter is used to perform chaos shaping on the LPS data bits to form a modulation signal.

[0040] The first carrier multiplier is used to multiply the chaotically shaped signal with M carrier signals respectively to generate M carrier modulated signals.

[0041] The carrier adder is used to add M carrier modulated signals and then send them through the antenna;

[0042] The chaotic shaping filter is used to generate a chaotic signal sequence.

[0043] The polarity converter is used to convert the original bit stream into polarity modulation bits; the serial-to-parallel converter is used to convert the serial modulation bits into parallel modulation bits.

[0044] The index selector is used to map the carrier index bits, select one subcarrier among the M subcarriers to send no information bit but 0, and the remaining M-1 subcarriers are used to send M-1 chaotic signals carrying LPS data.

[0045] The second digital device includes M square summers, a parallel-to-serial converter, and a DSP chip.

[0046] The second analog device includes M second carrier multipliers, M matched filters and M sampling switches.

[0047] The second carrier multiplier is used to multiply the received modulated signal with M synchronous carriers of corresponding frequencies to generate M product signals.

[0048] The matched filter is used to perform matched filtering on the M product signals.

[0049] The sampling switch is used to perform time domain sampling on the M matched filtered product signals, and the recovered discrete sequence is: , store the obtained M discrete sequences in the matrix middle.

[0050] The square summator is used to calculate the M discrete sequences The squares are summed separately and the results are stored in the matrix middle.

[0051] The DSP chip is used to calculate the matrix The minimum value in is selected, and the carrier index bit is restored according to the position of the minimum value. Then, one correlation value corresponding to the restored index bit is removed, and the remaining M-1 correlation values ​​are selected to restore the modulation bit.

[0052] The parallel-to-serial converter is used to restore the demodulated parallel modulation bits to serial modulation bits.

[0053] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the carrier index chaotic keying method based on a chaotic shaping filter are implemented.

[0054] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of a carrier index chaotic keying method based on a chaotic shaping filter as described above.

[0055] The beneficial effects of the present invention are as follows: within one symbol period, the present invention utilizes the advantage of the LPS data bits of the chaotic shaping filter to carry the index bit information and the modulation bit information on the carrier for transmission, which enables better utilization of carrier resources, effectively improves the transmission rate of the modulation data bits (LPS bits), and enables the index bit data bits (HPS bits) to have better bit error rate performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0057] Figure 1 An overall flow chart of a carrier index chaotic keying method based on a chaotic shaping filter provided in the first embodiment of the present invention.

[0058] Figure 2 A schematic structural diagram of a carrier index chaotic keying modulator in a carrier index chaotic keying system based on a chaotic shaping filter provided in the second embodiment of the present invention.

[0059] Figure 3 A schematic structural diagram of a carrier index chaotic keying demodulator in a carrier index chaotic keying system based on a chaotic shaping filter provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0061] Example 1, reference Figure 1 As an embodiment of the present invention, a carrier index chaotic keying method based on a chaotic shaping filter is provided, including: a modulation method and a demodulation method.

[0062] The steps of the carrier index chaotic keying modulation method based on chaotic shaping filter are as follows:

[0063] S1: p data bits are used as carrier index bits S p ,in .

[0064] S2: Take k*(M-1) data bits as modulation bits b and convert them into bipolar bits b through polarity conversion ’ .

[0065] S3: k*(M-1) serial modulated bits b ’ After the serial-to-parallel converter, the 1st to M-1th groups of data are generated. , each group includes k modulation bits.

[0066] S4: Input M-1 groups of modulated bits into the chaotic shaping filter (CSF) to generate M-1 modulated signals .

[0067] S5: Carrier index mapping is performed on the carrier index bits generated in S1, M-1 subcarriers are activated, and 1 subcarrier remains unactivated.

[0068] S6: Divide the frequency band required for signal transmission into M subcarrier frequency bands, generating a center frequency of data carrier.

[0069] S7: M-1 activated subcarriers send the M-1 modulated signals generated in S4, and the remaining 1 inactivated subcarrier sends a signal of 0. These M signals are multiplied with the data carriers generated in S6 to generate M modulated signals.

[0070] S8: Add the modulated signals generated by S7 to obtain a signal h, which is sent through the antenna.

[0071] S9: Further, after the modulation method described in the embodiment is used for the carrier index differential chaotic keying based on the chaotic shaping filter, a demodulation method can be performed, and the steps are as follows:

[0072] R1: The antenna receives the signal from the transmitter (including channel noise), obtains the signal r and compares it with the frequency The M synchronized subcarriers are multiplied respectively to generate M product signals.

[0073] R2: The M product signals generated in R1 are matched filtered respectively, and then sampled in the time domain to obtain the M discrete sequences Stored in matrix middle.

[0074] R3: The matrix generated in R2 The elements in are squared and summed row by row to obtain a new matrix as the decision matrix .

[0075] R4: The decision matrix obtained in R3 Enter the Minimum Detector to find the minimum value in a matrix.

[0076] R5; find the row coordinate of the minimum value in R4 and restore it to binary data, which is the demodulated carrier index bit .

[0077] R6: Remove the row with the minimum sum of squares from the elements and select the remaining M-1 rows of related sequences for threshold decision.

[0078] R7: For the first row of the correlation sequence in R6 The k values ​​of are used for threshold judgment to recover the k LPS data bits of the first group. ; For the second row of related sequences The k values ​​of are used for threshold decision, and the k LPS data bits of the second group are recovered. ; Then after the M-1th corresponding threshold decision, the M-1th row correlation sequence The k values ​​of are used for threshold judgment to recover the k LPS data bits of the M-1th group. ; A total of M-1 groups of data are recovered, each group containing k modulated bits.

[0079] R8: Combines the modulated bits generated in R7 into a demodulated serial modulated bit stream through parallel-to-serial conversion .

[0080] The overall content of the carrier index chaotic keying modulation and demodulation method based on chaotic shaping filter described in the present invention is as follows:

[0081] Step 1: First, data is collected in the current symbol period to obtain (M-1)*k+p data bits, and the bit signal-to-noise ratio value Eb / N0 is measured in the channel.

[0082] Step 2: Use p data as index bits S p ,in .

[0083] Step 3: Use (M-1)*k data bits as modulation bits b and convert them into bipolar bits b through polarity conversion. ’ .

[0084] Step 4: Convert (M-1)*k serial modulation bits b ’ After the serial-to-parallel converter, the 1st to M-1th groups of data are generated , each group includes k modulation bits.

[0085] Step 5: Input the modulated bits obtained in step 4 into the chaotic shaping filter (CSF) to generate M-1 modulated signals .

[0086] Step 6: Map the index bits generated in step 2 to carrier indexes, and activate M-1 subcarriers.

[0087] Step 7: Divide the frequency band required for signal transmission into M subcarrier frequency bands and generate a center frequency of subcarrier.

[0088] Step 8: M-1 activated subcarriers send the M-1 modulated signals generated in step 5, and the remaining 1 inactivated subcarrier sends a 0 signal. These M signals are multiplied with the subcarriers generated in step 7 to generate M modulated signals.

[0089] Step 9: Add the modulated signals generated in step 8 to obtain signal h, which is sent through the antenna.

[0090] Step 10: Receive the signal sent in step 9 (including channel noise), obtain the signal r and compare it with the frequency The M synchronized subcarriers are multiplied respectively to generate M product signals.

[0091] Step 11: Perform matched filtering on the M product signals generated in step 10, and then perform time domain sampling to obtain the M discrete sequences. Stored in matrix middle.

[0092] Step 12: Convert the matrix generated in step 11 The elements in are squared and summed row by row to obtain a new matrix as the decision matrix .

[0093] Step 13: Substitute the decision matrix obtained in step 12 Enter the Minimum Detector to find the minimum value in a matrix.

[0094] Step 14: Find the row coordinate of the minimum value in step 13 and restore it to binary data, which is the demodulated index bit .

[0095] Step 15: Remove the row with the minimum sum of squares from the elements and select the remaining M-1 rows of related sequences for threshold decision.

[0096] Step 16: For the first row of correlation sequence in step 15 The k values ​​of are used for threshold judgment to recover the k LPS data bits of the first group. ; For the second row of related sequences The k values ​​of are used for threshold judgment, and the k LPS data of the second group are restored. ; Then after the M-1th corresponding threshold decision, the M-1th row correlation sequence The k values ​​of are used for threshold judgment to recover the k LPS data bits of the M-1th group. A total of M-1 groups of data are recovered, each group of k modulated bits; the recovery rule is that when the correlation value > the threshold value, the demodulated polarity modulation bit is "+1", otherwise, the demodulated polarity modulation bit is "-1". The threshold value is 0 in this implementation.

[0097] Step 17: Combine the modulated bits generated in step 16 into a demodulated serial modulated bit stream through parallel-to-serial conversion .

[0098] In summary, within one symbol period, the present invention utilizes the advantage of the LPS data bits of the chaotic shaping filter to carry the index bit information and the modulation bit information on the carrier for transmission, which enables better utilization of carrier resources, effectively improves spectrum utilization, and greatly improves the transmission rate of the modulated data bits, so that the index bit data bits can have better bit error rate performance.

[0099] Example 2, reference Figure 2~Figure 3 , which is an embodiment of the present invention, provides a carrier index chaotic keying modulation and demodulation system based on a chaotic shaping filter, which is used to modulate and demodulate data bits and chaotic sequences within a symbol period. The modulation and demodulation system is divided into a modulation system and a demodulation system. The modulation system modulates the obtained data bits and chaotic sequences and sends them to the demodulation system.

[0100] like Figure 2 The carrier index chaotic keying modulation system based on chaotic shaping filter includes two parts: a first digital device and a first analog device.

[0101] The first digital device is composed of a serial-to-parallel converter, a polarity converter and an index selector.

[0102] Specifically, the polarity converter is used to convert the original bit stream in the current symbol period into polarity modulation bits; the serial-to-parallel converter is used to convert the serial modulation bits into parallel modulation bits; the index selector is used to map the carrier index bits, select one subcarrier among the M subcarriers not to send information bits (send 0), and the remaining M-1 subcarriers are used to send M-1 chaotic signals carrying LPS data;

[0103] Furthermore, the first analog device consists of M-1 chaos shaping filters (CSFs), M first carrier multipliers and a carrier adder; wherein the M-1 chaos shaping filters are used to perform chaos shaping on the LPS data bits into modulated signals; the M first carrier multipliers are used to multiply the chaotically shaped signals with the M carrier signals respectively to generate M carrier modulated signals; and the carrier adder is used to add the M carrier modulated signals and send them through the antenna.

[0104] like Figure 3 This embodiment also provides a carrier index chaotic keying demodulation system based on chaotic shaping filter. Like the modulation system, the demodulation system also consists of two parts: a second digital device and a second analog device.

[0105] Specifically, the second digital device is composed of M square summators, a parallel-to-serial converter, and a DSP chip. The M square summators are used to calculate the M discrete sequences in the matrix A. The squares are summed separately and the results are stored in the matrix DSP chip is used to calculate matrix The minimum value in is selected, and the carrier index bit is restored according to the position of the minimum value, and 1 correlation value corresponding to the restored index bit is removed, and the remaining M-1 correlation values ​​are selected to restore the modulation bit; the parallel-to-serial converter is used to restore the demodulated parallel modulation bits to a serial modulation bit stream.

[0106] Furthermore, the second analog device is composed of M second carrier multipliers, M matched filters and M sampling switches. Among them, the M second carrier multipliers are used to multiply the received modulated signal with M synchronous carriers of corresponding frequencies to generate M product signals; the M matched filters are used to perform matched filtering on the M product signals; the M sampling switches are used to perform time domain sampling on the M matched filtered product signals, and the recovered M discrete sequences are , store the obtained M discrete sequences in the matrix middle.

[0107] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0108] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0109] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0110] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0111] Example 3

[0112] In this embodiment, in order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation and simulation experiments. This embodiment experiments the existing traditional method and the method of this embodiment respectively.

[0113] Step 1: Collect data in the current symbol period to obtain (M-1)*k+p=32 data bits, where k=10, p=2, M=2^p, and measure the bit signal-to-noise ratio Eb / N0=10dB in the channel.

[0114] Step 2: Use p data as index bits S p , where p=2.

[0115] Step 3: Use the remaining (M-1)*k=30 data bits in step 1 as modulation bits b and convert them into bipolar bits b through polarity conversion. ’ .

[0116] Step 4: Convert the 30 serial modulation bits b from step 3 to ’ After the serial-to-parallel converter, the first to third groups of data are generated. , each group has 10 modulation bits.

[0117] Step 5: Input the modulated bits obtained in step 4 into the Chaotic Shaping Filter (CSF) to generate three modulated signals .

[0118] Step 6: Perform index mapping on the index bits generated in step 2, activate 3 subcarriers, and send a 0 signal to the remaining 1 inactivated subcarrier.

[0119] Step 7: Divide the frequency band required for signal transmission into M = 4 subcarrier frequency bands, generating a center frequency of data carrier.

[0120] Step 8: The seven activated subcarriers transmit the three modulated signals generated in step 5, and the remaining one inactivated subcarrier transmits a 0 signal. These four signals are multiplied with the data carriers generated in step 7 to generate four modulated signals.

[0121] Step 9: Add the modulated signals generated in step 8 to obtain signal h, which is sent through the antenna.

[0122] Step 10: Receive the signal sent in step 9 (including channel noise), obtain signal r and multiply it with 4 synchronous carriers of corresponding frequencies to generate 4 product signals.

[0123] Step 11: Perform matched filtering on the four product signals generated in step 10, and then perform time domain sampling to obtain the four discrete sequences. Stored in matrix A.

[0124] Step 12: Square and sum the four discrete sequences in the matrix generated in step 11 row by row to obtain a new matrix as the decision matrix.

[0125] Step 13: Input the decision matrix obtained in step 12 into the minimum detector to find the minimum value in the matrix.

[0126] Step 14: Find the row coordinate of the minimum value in step 13 and restore it to binary data, which is the demodulated index bit .

[0127] Step 15: Remove the row with the minimum square sum of the elements and select the remaining 3 rows of related sequences for threshold decision.

[0128] Step 16: Perform threshold judgment on the 10 values ​​of the first row correlation sequence in step 15 to recover the 10 LPS data bits of the first group; perform threshold judgment on the 10 values ​​of the second row correlation sequence to recover the 10 LPS data bits of the second group; perform threshold judgment on the 10 values ​​of the third row correlation sequence to recover the 10 LPS data bits of the third group; recover 3 groups of data in total, each with 10 modulation bits; the recovery rule is that when the correlation value>threshold value, the demodulated polarity modulation bit is "+1", otherwise, the demodulated polarity modulation bit is "-1". The threshold value is 0 in this implementation.

[0129] Step 17: Combine the modulated bits generated in step 16 into a demodulated serial modulated bit stream through parallel-to-serial conversion .

[0130] In summary, the present invention uses computer simulation to conduct a transmission test on a carrier index chaotic keying modulation and demodulation method based on a chaotic shaping filter provided by the present invention. In the test, the number of transmitted data bits is 32, and the chaotic signal sequence is produce,

[0131] ,

[0132] ,

[0133] The base frequency of the chaotic shaping filter is f = 2.5 MHz, the chaotic signal sampling frequency is fs = 40 MHz, and the symbol duration is , the equivalent number of signal sampling points in each symbol time is fs / f=16, the spread spectrum gain factor L=160, and the center frequency interval of all subcarriers satisfies .

[0134] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A carrier index chaotic keying method based on chaotic shaping filter, characterized in that: include: Collect serial LPS data bits for preprocessing; Inputting the processed LPS data bits into a chaotic shaping filter and outputting a chaotic signal; Carrier index mapping is performed using the HPS data bits as carrier index bits; The chaotic signal is combined with a carrier to generate a modulated signal, and multiple modulated signals are added together and sent through an antenna; The antenna receives the signal from the transmitter and multiplies it with the synchronized subcarriers respectively, outputs the product signal, samples the product signal in the time domain through the corresponding matched filter, outputs the discrete sequence for corresponding demodulation processing, and recovers the carrier index bit and the parallel LPS data bit; Combining the recovered parallel LPS data bits into a demodulated serial modulation bit stream by parallel-to-serial conversion; The LPS data bits are low priority data bits; The HPS data bits are high priority data bits.

2. A carrier index chaotic keying method based on chaotic shaping filter as claimed in claim 1, characterized in that: The preprocessing includes converting (M-1)*k LPS data bits as modulation bits b into serial bipolar bits b' through a polarity converter; The (M-1)*k serial bipolar modulation bits b' are converted into M-1 groups of parallel modulation bits through a serial-to-parallel converter.

3. A carrier index chaotic keying method based on chaotic shaping filter as claimed in claim 2, characterized in that: The chaotic signal is to input the processed LPS data bits into the chaotic shaping filter to generate M-1 groups of chaotic signals c1...c M-1 ; The p HPS data bits are used as the carrier index bits S p Index mapping is performed, and one subcarrier is selected by index from among the M subcarriers to be inactive and send 0, and the remaining M-1 subcarriers are activated and send M-1 groups of chaotic signals carrying LPS data; The chaotic signal is combined with the subcarrier to generate M modulated signals, and the M modulated signals are added together to obtain the signal h, which is sent through the antenna.

4. A carrier index chaotic keying method based on chaotic shaping filter as claimed in claim 3, characterized in that: The M-1 groups of chaotic signals are formed by combining the first group to the M-1th group, and each group of k LPS data bits generates M-1 groups of c1…c carrying LPS data bits through the chaotic shaping filter. M-1 ; The M-1 group of chaotic signals c1…c M-1 It is generated by each group of k LPS data bits from the 1st group to the M-1th group through the chaotic shaping filter; The center frequency of the subcarrier is f1…f M ; The index bit is composed of p HPS data as the carrier index bit S p , obtained through the serial-to-parallel converter, the expression is: Where M is the number of subcarriers available in the system, and p is the number of carrier index bits; The bipolar bits are obtained by converting the polarity of each group of k LPS data bits in the first group to the M-1th group; The expression of the first group of LPS data bits is: S1=[s 1,1 …s 1,k ] T Among them, s 1,1 is the first LPS bit of group 1, s 1,k is the kth LPS bit of group 1; The expression of M-1 groups of LPS data bits is: S1…S M-1 Among them, S1 is the LPS data bit of the first group, S M-1 It is the LPS data bit of the M-1th group.

5. A carrier index chaotic keying method based on chaotic shaping filter as claimed in claim 4, characterized in that: The product signal is the signal received by the antenna from the transmitter and the frequency f1…f M The M synchronized subcarriers are multiplied respectively to obtain M product signals.

6. A carrier index chaotic keying method based on chaotic shaping filter as claimed in claim 5, characterized in that: The discrete sequence is obtained by sampling the M product signals in the time domain through the corresponding matched filters to obtain M discrete sequences B1…B M and stored in matrix A M×k In the above example, the generated matrix A is M×k The M discrete sequences in are squared and summed row by row to obtain a new matrix as the decision matrix C M×1 ; The decision matrix C M×1 Input minimum detector, output the minimum value in the matrix, confirm the row coordinate of the minimum value, restore to binary data, and output the demodulated index bit From A M×k Remove the row with the minimum square sum from the matrix and select the remaining M-1 rows of correlation values ​​for threshold decision. The first row sequence is z 11 …z 1k , perform threshold judgment on the k values ​​of the sequence and recover the k LPS data bits of the first group The second row sequence is z 21 …z 2k , perform threshold judgment on the k values ​​of the sequence, and recover the k LPS data bits of the second group Then after the M-1th corresponding threshold decision, the M-1th row sequence is z (M-1)1 …z (M-1)k , perform threshold judgment on the k values ​​of the sequence and recover the k LPS data bits of the M-1th group The recovered M-1 groups of parallel LPS data bits are combined into a demodulated serial modulation bit stream through parallel-to-serial conversion 7. A system using a carrier index chaotic keying method based on a chaotic shaping filter as claimed in any one of claims 1 to 6, characterized in that: comprising a first digital device, a first analog device, a second digital device and a second analog device; The first digital device includes a serial-to-parallel converter, a polarity converter, and an index selector; The first analog device includes M-1 chaotic shaping filters, M first carrier multipliers and carrier adders; The chaos shaping filter is used to perform chaos shaping on the LPS data bits into a modulation signal; The first carrier multiplier is used to multiply the chaotically shaped signal with M carrier signals respectively to generate M carrier modulated signals; The carrier adder is used to add M carrier modulated signals and then send them through the antenna; The chaotic shaping filter is used to generate a chaotic signal sequence; The polarity converter is used to convert the original bit stream into polarity modulated bits; the serial-to-parallel converter is used to convert the serial modulated bits into parallel modulated bits; The index selector is used to map the carrier index bits, select one of the M subcarriers to send no information bit and send 0, and the remaining M-1 subcarriers are used to send M-1 chaotic signals carrying LPS data; The second digital device includes M square summers, a parallel-to-serial converter, and a DSP chip; The second analog device includes M second carrier multipliers, M matched filters and M sampling switches; The second carrier multiplier is used to multiply the received modulated signal by M synchronous subcarriers of corresponding frequencies to generate M product signals; The matched filter is used to perform matched filtering on the M product signals; The sampling switch is used to perform time domain sampling on the M matched filtered product signals, and the recovered discrete sequence is B1…B M , store the obtained M discrete sequences in matrix A M×k middle; The square summator is used to sum M discrete sequences B1...B M The squares are summed and the results are stored in the matrix C. M×1 middle; The DSP chip is used to calculate the matrix C M×1 The minimum value in , recovering the carrier index bit according to the position of the minimum value, removing 1 correlation value corresponding to the recovered index bit, and selecting the remaining M-1 correlation values ​​to recover the modulation bit; The parallel-to-serial converter is used to restore the demodulated parallel modulation bits to serial modulation bits.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of a carrier index chaotic keying method based on a chaotic shaping filter according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of a carrier index chaotic keying method based on a chaotic shaping filter as described in any one of claims 1 to 6 are implemented.

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