A high efficiency step-down switching power supply circuit with turn-off time control

Abstract

The application relates to a high-efficiency off-time controlled step-down switching power supply circuit, and belongs to the integrated circuit field. A novel off-time generation circuit with temperature compensation function is provided, which reduces the influence of external factors on the switching frequency; a double-path output error amplifier is designed and used for self-adaptive switching mode to solve the energy conversion problem under light load; and the peak current mode control is combined to improve the transient response. The application provides an effective solution of a high-efficiency, fast-transient-response and low-cost Buck chip.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuits, and particularly relates to a high-efficiency buck switching power supply circuit with turn-off time control. BACKGROUND

[0002] In modern electronic devices, the requirements for power supply stability and transient response are increasingly high, especially in the fields of precision instruments, medical devices, and communication devices. At the same time, efficient energy utilization has become a key consideration in electronic devices. By developing a fast-response, high-efficiency, and compact Buck chip, these demands can be met, providing stable and correct power supply and minimizing energy loss and improving energy utilization efficiency. In addition, the market demand for such chips is increasing, and a high-efficiency, fast-response, and compact Buck chip can have an advantage in cost-effectiveness, reducing system cost and reducing the use of external components.

[0003] Currently, switching power supply chips based on on-time / turn-off time control have become a popular research direction due to their own advantages of low cost and high transient response. This method obtains a pseudo-constant switching frequency for control through the proportional relationship between duty cycle and input / output voltage. One study achieved a switching converter with adaptive boost / buck switching function by designing a simple voltage selector combined with adaptive on / off time control. However, this study requires external trimming to ensure the minimum frequency offset, and consumes excessive area. A study proposed a three-mode control buck switching power supply chip that switches adaptively by detecting the output of the error amplifier to achieve high conversion efficiency in the full load range. However, this circuit is based on the voltage mode control method, and the load transient response of the chip is limited. SUMMARY

[0004] The purpose of the present application is to achieve high conversion efficiency in the full load range and good load transient response, and to provide a high-efficiency buck switching power supply circuit with turn-off time control.

[0005] To achieve the above purpose, the technical solution of the present application is: a high-efficiency buck switching power supply circuit with turn-off time control, a turn-off time generation circuit with temperature compensation function is proposed to reduce the influence of external factors on the switching frequency, a dual-output error amplifier is designed for adaptive switching mode to solve the energy conversion problem under light load, and peak current mode control is combined to improve the transient response.

[0006] In an embodiment of the present application, the switching power supply circuit comprises a peak current comparator PCD, an error amplifier, a bandgap reference circuit, a soft start circuit, a zero-crossing current detector ZCD, an over-temperature protection circuit OTP, an under-voltage lockout circuit UVLO, a first power tube switch, a second power tube switch, a digital circuit, and a turn-off time generation circuit; the digital circuit is connected with the peak current comparator PCD, the error amplifier, the zero-crossing current detector ZCD, the over-temperature protection circuit OTP, the under-voltage lockout circuit UVLO, the first power tube switch, the second power tube switch, and the turn-off time generation circuit respectively; the first power tube switch, the second power tube switch, and a load resistor constitute a load circuit; the soft start circuit is connected with the error amplifier first input end through the bandgap reference circuit; the load circuit is connected with the error amplifier second input end; the error amplifier is further connected with the peak current comparator PCD; the peak current comparator PCD, the turn-off time generation circuit, and the zero-crossing current detector ZCD are further connected with the load circuit; and the peak current comparator PCD and the turn-off time generation circuit are further connected with an input power supply.

[0007] In an embodiment of the present application, the error amplifier is a double-way output structure, one way of which is used for seamless switching of working modes and detection of load circuit load states, and the other way of which is used for transmitting feedback information to the peak current comparator PCD and constituting a fast loop.

[0008] In an embodiment of the present application, the error amplifier adopts a Type-II compensator for loop compensation, and the Type-II compensator comprises a capacitor CA, a capacitor CB, and a resistor RA, which are connected in series and then connected in parallel with the capacitor CB.

[0009] In an embodiment of the present application, the load circuit further comprises an inductor L, a capacitor CL, a feedback resistor RF1, and a feedback resistor RF2; a source electrode of the first power tube switch is connected with an input power supply; a gate electrode of the first power tube switch and a gate electrode of the second power tube switch are connected with the digital circuit respectively; a drain electrode of the first power tube switch is connected with a drain electrode of the second power tube switch, and is connected with one end of the inductor L, one end of the capacitor CL, and one end of a load resistor, and simultaneously serves as an output VOUT of the entire switching power supply circuit; a source electrode of the second power tube switch is connected with one end of the feedback resistor RF2, the other end of the capacitor CL, and the other end of the load resistor to GND; and the other end of the feedback resistor RF1 is connected with the other end of the feedback resistor RF2 to the error amplifier second input end.

[0010] In an embodiment of the present application, the turn-off time generating circuit comprises a low-pass filter LPF, a first comparator, a second comparator, a third comparator, an inverter, a current source, a switch, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a diode D1, a diode D2; the voltage VSW at the connection point of the drain of the first power tube switch and the drain of the second power tube switch is amplified by β times, and then connected to the positive input terminal of the first comparator through the LPF, the negative input terminal of the first comparator is connected to GND through R2, the negative input terminal of the first comparator is also connected to the source of M1, the output terminal of the first comparator is connected to the gate of M1, the drain of M1 is connected to the drain of M2, the gate of M3, the gate of M2, the gate of M4, the source of M2 is connected to the source of M3, the source of M4, the source of M7, the source of M8, and the input power supply, the drain of M3 is connected to the drain of M5, the gate of M5, the gate of M6, the source of M5 is connected to the output terminal of the current source, the source of M6, the negative electrode of D1, the negative electrode of D2, one end of C2, and one end of R3, the drain of M4 is connected to the negative electrode of D1, and is connected to the drain of M6, the input terminal of the current source, one end of C1, and the positive input terminal of the third comparator through R1, the gate of M7 is connected to the gate of M8, the drain of M8, and the drain of M9, the drain of M7 is connected to the other end of C2, one end of the switch controlled by VSW, and the negative input terminal of the third comparator, the other end of the switch is connected to the positive electrode of D2, the gate of M9 is connected to the output terminal of the second comparator, the source of M9 is connected to the other end of R3 and the negative input terminal of the second comparator, the positive input terminal of the second comparator is connected to the input power supply amplified by β times, and the output terminal of the third comparator outputs the turn-off time TOFF through the inverter.

[0011] In an embodiment of the present application, the principle of the off-time generation circuit is that: the VSW amplified by β times is converted into a voltage proportional to VOUT through an LPF, and input to the positive input terminal of the first comparator, at this time, the current flowing through M4 and M6 is proportional to VOUT, and similarly, the current flowing through M7 is proportional to the input voltage VIN of the input power supply, and the charging and discharging current is related to VIN and VOUT, thereby obtaining the off-time related to the duty cycle; before the off-time timing starts, the switch is closed, and the voltage at the positive electrode of D2 is the same as the voltage at the other end of C2, when the off-time timing starts, the switch is opened, and since the voltage across C2 cannot change abruptly, at this time, the voltage at the other end of C2 starts to rise from the voltage at the positive electrode of D2, and is charged by the current flowing out of the drain of M7, and the voltage at the drain of M6 starts to drop from high level after the off-time timing starts, and the drop time is related to the time constant formed by R1 and C1, and the charging current is related to VOUT, thus obtaining the off-time TOFF and the duty cycle D, and obtaining the relationship between the off-time TOFF and D.

[0012] In an embodiment of the present application, the off-time TOFF is approximately equal to Where M is a compensation factor.

[0013] In an embodiment of the present application, the duty cycle D is approximately

[0014] In an embodiment of the present application, the off-time TOFF is positively related to (1-D).

[0015] Compared with the prior art, the present application has the following beneficial effects: the novel off-time generation circuit with temperature compensation function reduces the influence of external factors on the switching frequency, the designed dual-path output error amplifier is used for adaptive switching mode to solve the energy conversion problem under light load, and the peak current mode control is combined to improve the transient response. The present application provides an effective solution for a low-cost Buck chip with high efficiency and fast transient response. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a system block diagram of the off-time controlled high-efficiency buck switching power supply circuit of the present application.

[0017] Figure 2 It is an off-time generation circuit.

[0018] Figure 3 It is a load transient response.

[0019] Figure 4 It is a frequency-load current relationship diagram.

[0020] Figure 5 Efficiency-Load Current Graph. DETAILED DESCRIPTION

[0021] The technical solutions of the present application will be described in detail below with reference to the drawings.

[0022] The present application provides a high-efficiency off-time control buck switching power supply circuit, proposes an off-time generation circuit with temperature compensation function to reduce the influence of external factors on switching frequency, designs a dual-output error amplifier for adaptive switching mode to solve the energy conversion problem under light load, and combines peak current mode control to improve transient response. The switching power supply circuit comprises a peak current comparator PCD, an error amplifier, a bandgap reference circuit, a soft start circuit, a zero-crossing current detector ZCD, an over-temperature protection circuit OTP, an under-voltage lockout circuit UVLO, a first power tube switch, a second power tube switch, a digital circuit, and an off-time generation circuit.

[0023] The following is the specific implementation process of the present application.

[0024] The present application provides a high-efficiency off-time control buck switching power supply circuit, proposes an off-time generation circuit with temperature compensation function to reduce the influence of external factors on switching frequency, designs a dual-output error amplifier for adaptive switching mode to solve the energy conversion problem under light load, and combines peak current mode control to improve transient response. The switching power supply circuit comprises a peak current comparator PCD, an error amplifier, a bandgap reference circuit, a soft start circuit, a zero-crossing current detector ZCD, an over-temperature protection circuit OTP, an under-voltage lockout circuit UVLO, a first power tube switch, a second power tube switch, a digital circuit, and an off-time generation circuit. Figure 1 The present application provides a high-efficiency off-time control buck switching power supply circuit, proposes an off-time generation circuit with temperature compensation function to reduce the influence of external factors on switching frequency, designs a dual-output error amplifier for adaptive switching mode to solve the energy conversion problem under light load, and combines peak current mode control to improve transient response. The switching power supply circuit comprises a peak current comparator PCD, an error amplifier, a bandgap reference circuit, a soft start circuit, a zero-crossing current detector ZCD, an over-temperature protection circuit OTP, an under-voltage lockout circuit UVLO, a first power tube switch, a second power tube switch, a digital circuit, and an off-time generation circuit.

[0025] The designed error amplifier is a dual-output structure, one of which is used for seamless switching mode and detecting load state, and the other one transmits feedback information to the peak current comparator and constitutes a fast loop to improve transient response. The designed Buck chip (i.e. the high-efficiency off-time control buck switching power supply circuit of the present application) works in power saving mode under light load, can adaptively skip the number of pulses, and combines the zero-crossing current detector to detect the direction of inductance current, solving the problem of low efficiency under light load in traditional off-time control. The Buck chip works in pulse frequency modulation mode under heavy load to ensure lower ripple and higher output accuracy. Figure 1 In the formula, L, CL and feedback resistors RF1 and RF2 are all external elements of the chip, wherein DCR is the parasitic resistance of the inductor L, ESR is the parasitic resistance of the capacitor CL, and RL is the load resistance. The error amplifier adopts a Type-II compensator for loop compensation, including CA, CB and RA, to ensure the stability of the entire system loop.

[0026] The designed off-time generation circuit of the present application is as shown in Figure 2The VSW information is converted to VOUT by a low-pass filter, and the voltage at node A is proportional to the output voltage. Therefore, the current through M4 and M6 is proportional to the output voltage through the voltage-to-current conversion circuit and the current mirror. The current I2 is a temperature-dependent current independent of the power supply, and is used for temperature compensation. Similarly, the current through M7 is proportional to the input voltage VIN. The charging and discharging current is related to the input and output voltages through the charging and discharging loop formed by R1, C1 and the comparator, and thus the off-time related to the duty cycle is obtained. Before the off-time timer starts, the switch VSW is closed, and the voltage at node C is the same as the voltage of diode D2. When the off-time timer starts, the switch VSW is opened, and the voltage at node C starts to rise from the voltage of diode D2 because the voltage across capacitor C2 cannot change abruptly. The voltage at node B starts to decrease from the high level after the off-time timer starts, and the decrease time is related to the time constant formed by R1 and C1, and the charging current is related to the output voltage. Therefore, the off-time TOFF is approximately equal to where M is a compensation factor. The duty cycle D is approximately equal to Therefore, the off-time TOFF is positively related to (1-D), and the proposed Buck chip obtains a switching frequency almost independent of the load current under heavy load, and reduces the influence of the input and output voltages and temperature on the switching frequency.

[0027] Figure 3 The simulation results of the load transient response of the Buck chip are shown. When the load current changes from 0.1 A to 1.3 A at a slew rate of 1.2 A / μs, the overshoot voltage and undershoot voltage of the Buck chip are 108 mV and 132 mV, respectively, and the recovery time is not more than 24 μs. Figure 4 The relationship between the switching frequency and the load current is shown. Under light load of 0-0.6 A, the Buck chip works in the power saving mode, and the number of skipped pulses can be adaptively adjusted to improve the efficiency. At this time, the switching frequency is positively related to the load current. When the load current exceeds 0.6 A, the Buck chip works in the pulse frequency modulation mode, and the switching frequency is almost independent of the load current. Figure 5 The relationship between the conversion efficiency and the load current is shown. Under light load of 1 mA, the efficiency of the Buck chip is still greater than 89%, and the peak efficiency of 96% occurs at 0.8 A. It can be seen that the proposed Buck chip scheme has high conversion efficiency under full load range.

[0028] The above is the preferred embodiment of the present application. Any changes made according to the technical solutions of the present application, as long as the generated functional effects do not exceed the scope of the technical solutions of the present application, are within the protection scope of the present application.

Claims

1. A high efficiency step-down switching power supply circuit with turn-off time control, characterized by comprising: The peak current comparator PCD, the error amplifier, the band gap reference circuit, the soft start circuit, the zero-crossing current detector ZCD, the over-temperature protection circuit OTP, the under-voltage lockout circuit UVLO, the first power tube switch, the second power tube switch, the digital circuit, and the turn-off time generation circuit are connected respectively. The first power tube switch, the second power tube switch, and the load resistor constitute a load circuit. The soft start circuit is connected to the first input terminal of the error amplifier through the band gap reference circuit. The load circuit is connected to the second input terminal of the error amplifier. The error amplifier is also connected to the peak current comparator PCD. The peak current comparator PCD, the turn-off time generation circuit, and the zero-crossing current detector ZCD are also connected to the load circuit. The peak current comparator PCD and the turn-off time generation circuit are also connected to the input power supply. The turn-off time generation circuit includes a low-pass filter LPF, a first comparator, a second comparator, a third comparator, an inverter, a current source, a switch, transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, resistors R1, R2, R3, capacitors C1, C2, diodes D1, D2. The voltage VSW at the connection point of the drain of the first power tube switch and the drain of the second power tube switch is amplified by β times, connected to the positive input terminal of the first comparator through the LPF, and connected to the GND through the R2 at the negative input terminal of the first comparator. The negative input terminal of the first comparator is also connected to the source of the M1. The output terminal of the first comparator is connected to the gate of the M1. The drain of the M1 is connected to the drain of the M2, the gate of the M2, the gate of the M3, and the gate of the M4. The source of the M2 is connected to the source of the M3, the source of the M4, the source of the M7, and the source of the M8, and connected to the input power supply. The drain of the M3 is connected to the drain of the M5, the gate of the M5, and the gate of the M6. The source of the M5, the output terminal of the current source, the source of the M6, the negative electrode of the D1, the negative electrode of the D2, one end of the C2, and one end of the R3 are connected to the GND. The drain of the M4 is connected to the negative electrode of the D1, and connected to the drain of the M6, the input terminal of the current source, one end of the C1, and the positive input terminal of the third comparator through the R1. The gate of the M7 is connected to the gate of the M8, the drain of the M8, and the drain of the M9. The drain of the M7 is connected to the other end of the C2, one end of the switch controlled by the VSW, and the negative input terminal of the third comparator. The other end of the switch is connected to the positive electrode of the D2. The gate of the M9 is connected to the output terminal of the second comparator. The source of the M9 is connected to the other end of the R3 and the negative input terminal of the second comparator. The positive input terminal of the second comparator is connected to the input power supply amplified by β times. The output terminal of the third comparator is connected to the other end of the C1 through the inverter to output the turn-off time TOFF.

2. The turn-off time controlled high efficiency buck switching power supply circuit according to claim 1, wherein, The error amplifier is a double-way output structure, one way is used for seamless switching working mode and detecting load state of load circuit, and the other way is used for transmitting feedback information to peak current comparator PCD and constituting a fast loop.

3. The turn-off time controlled high efficiency buck switching power supply circuit according to claim 2, wherein, The error amplifier adopts a Type-II compensator for loop compensation, and the Type-II compensator comprises a capacitor CA, a capacitor CB and a resistor RA.

4. The turn-off time controlled high efficiency buck switching power supply circuit according to claim 1, wherein, The load circuit further comprises an inductor L, a capacitor CL, a feedback resistor RF1 and a feedback resistor RF2, the source of the first power tube switch is connected with an input power supply, the gate of the first power tube switch and the gate of the second power tube switch are connected with a digital circuit respectively, the drain of the first power tube switch is connected with the drain of the second power tube switch, and is connected with one end of the inductor L, one end of the feedback resistor RF1, one end of the capacitor CL and one end of a load resistor, and simultaneously serves as an output VOUT of the whole switching power supply circuit, the source of the second power tube switch is connected with the other end of the feedback resistor RF2, the other end of the capacitor CL and the other end of the load resistor to GND, and the other end of the feedback resistor RF1 is connected with the other end of the feedback resistor RF2 to the second input end of the error amplifier.

5. The turn-off time controlled high efficiency buck switching power supply circuit according to claim 1, wherein, The realization principle of the off time generating circuit is that: VSW amplified by beta times is converted into a voltage proportional to VOUT through an LPF, and is input to the positive input end of the first comparator, at this time, the current flowing through M4 and M6 is proportional to VOUT, and the current flowing through M7 is proportional to the input voltage VIN of the input power supply, and the charging and discharging current related to VIN and VOUT is obtained through the loop constituted by R1, C1 and the third comparator, thereby obtaining the off time related to the duty cycle; before the off time timing starts, the switch is closed, and the voltage at the positive electrode of D2 is the same as the voltage at the other end of C2, when the off time timing starts, the switch is opened, and since the voltage across C2 cannot be abruptly changed, the voltage at the other end of C2 starts to rise from the voltage at the positive electrode of D2 as the starting point, and is charged by the current flowing out of the drain of M7, and the voltage at the drain of M6 starts to drop from high level after the off time timing starts, and the drop time is related to the time constant constituted by R1 and C1, and the charging current is related to VOUT, thus obtaining the off time TOFF and the duty cycle D, and obtaining the correlation between the off time TOFF and D.

6. The turn-off time controlled high efficiency buck switching power supply circuit according to claim 5, wherein, The turn-off time TOFF is equal to where M is a compensation factor.

7. The turn-off time controlled high efficiency buck switching power supply circuit according to claim 6, wherein The duty cycle D is 8. The turn-off time controlled high efficiency buck switching power supply circuit according to claim 7, wherein, The off time TOFF is positively correlated with 1-D.

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