A memory testing method, system, device and medium

Abstract

The present invention provides a memory testing method, system, device and medium, the testing method comprising: sequentially powering off, powering on and initializing the memory, and sending a cache function closing instruction to the memory; generating multiple random data; sending one of the random data to the memory, and sequentially powering off, powering on and initializing the received memory; acquiring the storage data in the memory according to the write address and data volume of the random data sent, and comparing the data sequence of the random data with the storage data; when the data sequence of the random data is the same as the storage data, determining that the cache function of the memory is in a closed state, and sending the next random data to the memory for comparison again; when the data sequence of the random data is different from the storage data, determining that the cache function of the memory is in an open state. The present invention can accurately determine whether the cache function of the memory is turned on.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory testing method, system, device and medium. Background Art

[0002] eMMC (Embedded Multi Media Card) is a standard specification for embedded memory established by the MMC Association, mainly for products such as mobile phones or tablets. It consists of an embedded storage solution with an MMC (Multimedia Card) interface, flash memory (nand-flash) and an eMMC controller. An obvious advantage of eMMC is that an eMMC controller is integrated in the package, which provides a standard interface and manages flash memory, allowing mobile phone manufacturers to focus on other parts of product development and shorten the time to market. More and more mobile devices use eMMC as a storage unit.

[0003] The switch of the cache function has a significant impact on the performance of the eMMC storage device. It is also an important factor that needs to be strictly controlled when comparing performance. Therefore, checking whether the eMMC has enabled internal background performance optimization is crucial to the subsequent performance inspection and improvement. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a memory testing method, system, device and medium for accurately determining whether the memory has a cache function enabled.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a memory testing method, comprising:

[0006] The memory is powered off, powered on, and initialized in sequence, and a cache function shutdown instruction is sent to the memory;

[0007] Generate a plurality of random data, wherein the random data represents a random data amount, a write address, and a data sequence;

[0008] Sending one of the random data to the memory, and sequentially powering off, powering on, and initializing the memory after receiving the data;

[0009] Acquire the storage data in the memory according to the write address and data amount of the sent random data, and compare the data sequence of the random data with the storage data;

[0010] When the data sequence of the random data is the same as the stored data, determining that the cache function of the memory is in a closed state, and sending the next random data to the memory for comparison processing again;

[0011] When the data sequence of the random data is different from the stored data, it is determined that the cache function of the memory is in an on state.

[0012] In one embodiment of the present invention, the step of generating a plurality of random data, wherein the random data represents a random data amount, a write address, and a data sequence comprises:

[0013] Acquire the storage capacity of the cache area of ​​the memory;

[0014] Randomly generate a data volume, a write address, and a data sequence, wherein the data volume is less than or equal to the storage capacity of the cache area, the sum of the write address and the data volume is less than or equal to the total capacity of the memory, and each of the data sequences is different from each other;

[0015] The data amount, the write address and the data sequence are combined to generate the random data.

[0016] In one embodiment of the present invention, before the step of obtaining the storage capacity of the cache area of ​​the memory, the step includes:

[0017] Preset reference data is written into the memory, where the preset reference data is different from each of the data sequences.

[0018] In one embodiment of the present invention, the step of sending one of the random data to the memory and sequentially powering off, powering on and initializing the memory after receiving the data includes:

[0019] Sending a write command to the memory and transferring the random data to the memory;

[0020] A status monitoring command is sent to the memory, and after the memory is in a low power consumption state, power-off, power-on and initialization processing are sequentially performed on the memory.

[0021] In one embodiment of the present invention, the step of acquiring the storage data in the memory according to the write address of the sent random data, and comparing the random data with the storage data includes:

[0022] Reading the storage data at the corresponding address in the memory according to the write address and data amount of the sent random data;

[0023] The data sequence of the sent random data is compared with the stored data to determine whether the data sequence is identical to the stored data.

[0024] In one embodiment of the present invention, the steps of sequentially powering off, powering on, and initializing the memory and sending a cache function shutdown instruction to the memory include:

[0025] The memory is powered off, powered on, and initialized in sequence, and status information of a cache function of the memory is obtained;

[0026] When the cache function of the memory is in an on state, a closing instruction is issued to close the cache function.

[0027] In one embodiment of the present invention, the steps of sequentially powering off, powering on, and initializing the memory and acquiring status information of a cache function of the memory include:

[0028] Performing a power-off and power-on operation on the memory to clear existing data in a cache area of ​​the memory;

[0029] Initializing the memory to enable communication between the memory and the host system;

[0030] A read control command is issued to read status information of a cache function of the memory.

[0031] The present invention also provides a memory testing system, comprising:

[0032] A power-on and power-off initialization module, used to sequentially power off, power on and initialize the memory, and send a cache function shutdown instruction to the memory;

[0033] A data generation module, used for generating a plurality of random data, wherein the random data represents a random data amount, a write address and a data sequence;

[0034] A data transmission module, used for sending one of the random data to the memory, and sequentially performing power-off, power-on and initialization processing on the memory after receiving the data;

[0035] A data verification module, used to obtain the storage data in the memory according to the write address and data volume of the sent random data, and compare the data sequence of the random data with the storage data;

[0036] Wherein, when the data sequence of the random data is the same as the stored data, the data verification module is used to determine that the cache function of the memory is in a closed state, and send the next random data to the memory for comparison processing again;

[0037] When the data sequence of the random data is different from the stored data, the data verification module is used to determine that the cache function of the memory is in an enabled state.

[0038] The present invention also provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the steps of any of the above-mentioned memory testing methods when executing the computer program.

[0039] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the memory testing method as described in any one of the above items are implemented.

[0040] As described above, a memory testing method, system, device and medium of the present invention have the following beneficial effects: the present invention can be used to accurately determine whether the memory has a cache function enabled, verify whether the device has an internal background performance optimization behavior enabled, and provide a reference for subsequent memory performance inspection and improvement.

[0041] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0043] Figure 1 Shown is a flow chart of a memory testing method provided by the present invention.

[0044] Figure 2 Display as Figure 1 A flowchart of a specific implementation of step S100 is shown in FIG.

[0045] Figure 3 Display as Figure 2 A flowchart of a specific implementation of step S110 in FIG.

[0046] Figure 4 Display as Figure 1A flowchart of a specific implementation of step S200 is shown in FIG.

[0047] Figure 5 Display as Figure 1 A flowchart of a specific implementation of step S300 is shown in FIG.

[0048] Figure 6 Display as Figure 1 A flowchart of a specific implementation of step S400 is shown in FIG.

[0049] Figure 7 Shown is a structural schematic diagram of a memory testing system provided by the present invention.

[0050] Figure 8 The structure of the computer system shown is suitable for implementing the electronic device of the embodiment of the present invention. DETAILED DESCRIPTION

[0051] The following is an explanation of the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the features in the following embodiments and the embodiments can be combined with each other without conflict. It should also be understood that the terms used in the embodiments of the present invention are intended to describe specific embodiments, rather than to limit the scope of protection of the present invention. The test methods for which specific conditions are not specified in the following examples are usually carried out under conventional conditions or according to the conditions recommended by the manufacturers.

[0052] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0053] It should be noted that the eMMC memory integrates a controller and NAND flash memory particles, providing higher performance and integration than traditional memory cards. The cache function of the eMMC memory is one of its key features to improve read and write performance. The cache function (cache function) is mainly designed to accelerate data read and write operations. It includes two parts: read cache (Read Cache) and write cache (Write Cache), the purpose of which is to alleviate the speed mismatch problem between the main memory and the eMMC flash memory particles. The on and off state of the cache function is an important factor that needs to be strictly controlled during memory testing.

[0054] See also Figures 1 to 8 The present invention provides a memory testing method, system, device and medium, which can verify whether the memory correctly executes the shutdown instruction of the cache function, and whether the memory has the behavior of automatically turning on the cache function, and then judge whether the memory has the behavior of turning on the internal background performance optimization, which plays a vital role in the subsequent inspection and improvement of the memory performance. The following is a detailed description through specific embodiments.

[0055] See also Figure 1 The present invention provides a memory testing method, which may include the following steps:

[0056] Step S100, power off, power on and initialize the memory in sequence, and send a cache function shutdown instruction to the memory;

[0057] Step S200, generating a plurality of random data, wherein the random data represents a random data amount, a write address and a data sequence;

[0058] Step S300, sending one of the random data to the memory, and sequentially powering off, powering on and initializing the memory after receiving the data;

[0059] Step S400, acquiring the storage data in the memory according to the write address and data volume of the sent random data, and comparing the data sequence of the random data with the storage data;

[0060] Step S500: when the data sequence of the random data is the same as the stored data, it is determined that the cache function of the memory is in a closed state, and the next random data is sent to the memory for comparison processing again;

[0061] Step S600: When the data sequence of the random data is different from the stored data, it is determined that the cache function of the memory is in the on state.

[0062] See also Figure 2In one embodiment of the present invention, when executing step S100, the memory is powered off, powered on, and initialized in sequence, and a cache function shutdown instruction is sent to the memory. Specifically, the following steps may be included:

[0063] Step S110, powering off, powering on, and initializing the memory in sequence, and obtaining status information of the cache function of the memory;

[0064] Step S120: When the cache function of the memory is in the on state, a closing instruction is issued to close the cache function.

[0065] See also Figure 3 In one embodiment of the present invention, when executing step S110, the memory is powered off, powered on, and initialized in sequence, and the state information of the cache function of the memory is obtained. Specifically, the following steps may be included:

[0066] Step S111, powering off and then powering on the memory to clear existing data in the cache area of ​​the memory;

[0067] Step S112, initializing the memory to enable communication connection between the memory and the host system;

[0068] Step S113: issue a read control command to read status information of the cache function of the memory.

[0069] In one embodiment of the present invention, when executing steps S111 to S113, specifically, the cache area (Cache) is a memory that temporarily stores data for quick access. When the power is off, the cache area will lose the data stored thereon. Therefore, when performing a memory test, first, the memory is powered off and then powered on by VCC / VCCQ to clear the existing data on the cache area. VCC is responsible for powering the control unit of the eMMC to ensure that the controller can work normally. VCCQ is responsible for powering the I / O (input / output) interface of the eMMC to ensure the stability and speed of data transmission. Then the memory is initialized to ensure stable communication between the memory and the host system. The initialization process may include steps such as hardware reset, identifying memory information, setting the working mode, and turning on / off characteristic functions. Finally, the status information of the cache function in the memory can be read through a specific read control command to confirm that the cache area is in a closed state.

[0070] In one embodiment of the present invention, when step S120 is executed, that is, when the cache function of the memory is turned on, a shutdown instruction is issued to turn off the cache function. Specifically, if the cache function in the memory is turned on, it can be turned off by a preset instruction, and the power-off and initialization process is performed again. If the cache function in the memory cannot be set to off, an abnormality in the memory can be reported to the host.

[0071] In one embodiment of the present invention, before executing step S200, the step of writing preset reference data to the memory is also included. In this embodiment, the total capacity of the memory is first obtained. Then, a random data Pattern_A is generated according to the total capacity. The random data Pattern_A is then divided into multiple batches or sectors, and the write operation is performed one by one to ensure that the entire memory card is effectively filled with the preset reference data. The preset reference data can provide support for subsequent write consistency detection.

[0072] See also Figure 4 When step S200 is executed, a plurality of random data are generated, and the random data represent the random data amount, write address and data sequence. Specifically, the following steps may be included:

[0073] Step S210, obtaining the storage capacity CS of the cache area of ​​the memory;

[0074] Step S220, randomly generate a data volume iK, a write address Rand_lba_i and a data sequence Pattern_i, wherein the data volume iK is less than or equal to the storage capacity CS of the cache area, the write address Rand_lba+data volume iK is less than or equal to the total capacity of the memory, and each data sequence Pattern_i is different from each other;

[0075] Step S230, combining the data amount iK, the write address Rand_lba, and the data sequence Pattern_i to generate the i-th random data.

[0076] In one embodiment of the present invention, when executing steps S210 to S230, specifically, first, the storage capacity (cache size, CS) of the cache area of ​​the cache area is obtained. Then, the data volume iK, the write address Rand_lba_i and the data sequence Pattern_i are randomly generated. Among them, the data volume iK must satisfy: the data volume iK is less than or equal to the storage capacity CS. The write address Rand_lba_i must satisfy: Rand_lba_i+ iK is less than or equal to the total capacity of the memory. The data sequence Pattern_i satisfies that the data sequences generated each time are different from each other and are also different from the preset reference data Pattern_A. Finally, the data volume iK, the random address Rand_lba, and the random data sequence Pattern_i are combined and processed to generate the i-th random data. Repeat steps S220 to S230 to generate multiple random data.

[0077] See also Figure 5 When executing step S300, one of the random data is sent to the memory, and the memory that has received the data is powered off, powered on, and initialized in sequence. Specifically, the following steps may be included:

[0078] Step S310, sending a write command to the memory, and transferring a random data to the memory;

[0079] Step S320: Send a status monitoring command to the memory, and after the memory is in a low power consumption state, perform power-off, power-on and initialization processing on the memory in sequence.

[0080] In one embodiment of the present invention, when step S310 is executed, specifically, the host sends a write command to the memory and transmits the i-th random data to the memory. At this time, the memory can respond to the write command, receive and write the i-th random data into the NAND flash memory of the memory.

[0081] In one embodiment of the present invention, when executing step S320, specifically, after completing sending the i-th random data to the memory, the host sends a status monitoring command to the memory to confirm whether the i-th random data has been written. The present invention determines whether the data writing has been completed based on whether the memory is transferred from a high power consumption state to a low power consumption state. Then, after confirming that the memory is in a low power consumption state, the VCC / VCCQ power-off and power-on operation is performed on it to clear the existing data in the cache area. Then, the memory is initialized to ensure stable communication between the memory and the host system.

[0082] See also Figure 6In one embodiment of the present invention, when executing step S400, that is, according to the sent random data, the storage data at the corresponding address in the memory is subjected to consistency detection processing. Specifically, the following steps may be included:

[0083] Step S410, reading the storage data at the corresponding address in the memory according to the write address and data volume of the sent random data;

[0084] Step S420: Compare the data sequence of the sent random data with the stored data to determine whether the data sequence is the same as the stored data.

[0085] In one embodiment of the present invention, when executing steps S410 to S420, specifically, the information corresponding to the i-th random data is the data volume iK, the address Rand_lba_i, and the data sequence Pattern_i. Therefore, first, the host can read the storage data with the address Rand_lba_i and the data volume iK in the memory according to the information of the i-th random data. Then, the host compares the read storage data with the data sequence Pattern_i corresponding to the i-th random data to determine whether the storage data is the same as the data sequence Pattern_i. As can be seen from the above, the data sequence Pattern_i satisfies that the data sequences generated each time are different from each other, and are also different from the preset reference data Pattern_A. Therefore, Pattern_i is unique, and by comparing whether the storage data is consistent with the data sequence Pattern_i, it can be determined whether the i-th random data is completely written into the NAND flash memory of the memory, thereby determining whether the cache function of the memory is turned on.

[0086] In one embodiment of the present invention, when step S500 is executed, that is, when the data sequence of the random data is the same as the stored data, it is determined that the cache function of the memory is in a closed state, and the next random data is sent to the memory for comparison processing again. Specifically, when the data sequence of the random data is the same as the stored data, that is, when the stored data read according to the address Rand_lba_i and the data amount iK is consistent with the data sequence Pattern_i, it indicates that the i-th random data is completely written into the NAND flash memory of the memory. Therefore, it can be determined that the cache area of ​​the memory is in a closed state when responding to this write instruction. At this time, the next random data can be sent to the memory for comparison processing again. For example, the host can send the i+1th random data to the memory. In this embodiment, the number of random data can be set to, for example, 1000, and then after completing one thousand cycle tests, it can be determined that the cache function of the memory is in a closed state.

[0087] In one embodiment of the present invention, when step S600 is executed, that is, when the data sequence of the random data is different from the stored data, it is determined that the cache function of the memory is in the on state. Specifically, when the data sequence of the random data is different from the stored data, that is, when the stored data read according to the address Rand_lba_i and the data volume iK is inconsistent with the data sequence Pattern_i, it indicates that the i-th random data is not written into the NAND flash memory of the memory, that is, the i-th random data may be written into the cache area first. Therefore, it can be determined that the cache function of the memory is in the on state when responding to this write instruction.

[0088] See also Figure 7 The present invention also provides a memory test system, which corresponds to the test method in the above embodiment. The test system may include a power-on and power-off initialization module 101, a data generation module 102, a data transmission module 103, and a data verification module 104.

[0089] In one embodiment of the present invention, the power-on and power-off initialization module 101 can be used to perform power-off, power-on and initialization processing on the memory in sequence, and send a cache function shutdown instruction to the memory. Specifically, when performing a memory test, the power-on and power-off initialization module 101 is used to first perform a VCC / VCCQ power-off and power-on operation on the memory to clear the existing data on the cache area. VCC is responsible for the power supply of the control unit of the eMMC to ensure that the controller can work normally. VCCQ is responsible for the power supply of the I / O (input / output) interface of the eMMC to ensure the stability and speed of data transmission. Then the memory is initialized to ensure stable communication between the memory and the host system. The initialization process may include steps such as hardware reset, identification of memory information, setting of working mode, and turning on / off characteristic functions. Finally, the status information of the cache function in the memory can be read through a specific read control command. If the cache function in the memory is in the on state, it can be turned off through a preset instruction, and the power-off and initialization process can be performed again. If the cache area in the memory cannot be set to be turned off, the host can be reported that the memory is abnormal.

[0090] In one embodiment of the present invention, the data generation module 102 can be used to generate multiple random data, and the random data represents the random data volume, write address and data sequence. Specifically, the data generation module 102 can first obtain the storage capacity (cache size, CS) of the cache area of ​​the cache area. Then, multiple random data for transmission testing can be generated according to the storage capacity of the cache area. For example, the data generation module 102 first randomly generates the data volume iK, the write address Rand_lba_i and the data sequence Pattern_i, and then combines the data volume iK, the random address Rand_lba, and the random data sequence Pattern_i to generate the i-th random data. Repeating the above steps, the data generation module 102 can generate multiple random data.

[0091] In one embodiment of the present invention, the data generation module 102 needs to write preset reference data to the memory card before generating multiple random data. In this embodiment, the data generation module 102 can first obtain the total capacity of the memory. Then, based on the total capacity, a random data Pattern_A is generated. The random data Pattern_A is then divided into multiple batches or sectors, and the write operation is performed one by one to ensure that the memory card is effectively filled with the preset reference data. The preset reference data can provide support for subsequent write consistency detection.

[0092] In one embodiment of the present invention, the data transmission module 103 can be used to send one of the random data to the memory, and perform power-off, power-on and initialization processing on the memory that has been received. Specifically, the data transmission module 103 sends a plurality of random data generated by the data generation module 102 to the memory. In this embodiment, the data transmission module 103 first sends a write command to the memory, and transmits the i-th random data to the memory. At this time, the memory can respond to the write command, receive and write the i-th random data into the NAND flash memory of the memory. Then, after completing the sending of the i-th random data to the memory, the data transmission module 103 can send a status monitoring command to the memory to confirm whether the i-th random data has been written. The data transmission module 103 can determine whether the data writing has been completed according to whether the memory has been transferred from a high power consumption state to a low power consumption state. After confirming that the memory is in a low power consumption state, the data transmission module 103 first performs a VCC / VCCQ power-off and power-on operation on the memory to clear the existing data on the cache area; and then initializes the memory to ensure stable communication between the memory and the host system.

[0093] In one embodiment of the present invention, the data verification module 104 can be used to obtain the storage data in the memory according to the write address and data volume of the random data sent, and compare the data sequence of the random data with the storage data; when the data sequence of the random data is the same as the storage data, it is determined that the cache function of the memory is in a closed state, and the next random data is sent to the memory for comparison again; when the data sequence of the random data is different from the storage data, it is determined that the cache function of the memory is in an open state. Specifically, the information corresponding to the i-th random data is the data volume iK, the address Rand_lba_i, and the data sequence Pattern_i. Therefore, first, the data verification module 104 can read the storage data with the address Rand_lba_i and the data volume iK in the memory according to the information of the i-th random data. Then, the data verification module 104 compares the read storage data with the data sequence Pattern_i corresponding to the i-th random data to determine whether the storage data is consistent with the data sequence Pattern_i. As can be seen from the above, the data sequence Pattern_i satisfies that the data sequences generated each time are different from each other and are also different from the preset reference data Pattern_A. Therefore, Pattern_i is unique. The data verification module 104 can determine whether the i-th random data is completely written into the NAND flash memory of the memory by comparing whether the written data is the same as the data sequence Pattern_i.

[0094] In this embodiment, when the data verification module 104 determines that the data sequence of the random data is the same as the stored data, that is, when the write data read according to the address Rand_lba_i and the data amount iK is consistent with the data sequence Pattern_i, it indicates that the i-th random data is completely written into the NAND flash memory of the memory. Therefore, it can be determined that the cache function of the memory is in a closed state when responding to this write instruction. At this time, the next random data can be sent to the memory through the data transmission module 103, and the comparison process is performed again. For example, the data transmission module 103 can send the i+1th random data to the memory. In this embodiment, the number of random data can be set to, for example, 1000. Then after completing one thousand cycle tests, it can be determined that the cache function of the memory is in a closed state.

[0095] In one embodiment of the present invention, when the data verification module 104 determines that the data sequence of the random data is different from the stored data, that is, the stored data read according to the address Rand_lba_i and the data amount iK is inconsistent with the data sequence Pattern_i, it indicates that the i-th random data is not written into the NAND flash memory of the write memory. Therefore, it can be determined that the cache function of the memory is turned on when responding to the write instruction this time, because Pattern_i is written into the cache area of ​​the memory.

[0096] The specific definition of the memory test system can be found in the definition of the test method above, which will not be repeated here. Each module in the above test system can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0097] An embodiment of the present invention also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by one or more processors, the electronic device implements the memory testing method provided in the above-mentioned embodiments.

[0098] See also Figure 8 , Figure 8 The structure diagram of the computer system of the electronic device suitable for implementing the embodiment of the present invention is shown. It should be noted that: Figure 8 The computer system 200 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0099] See also Figure 8 The computer system 200 includes a central processing unit (CPU) 201, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 202 or the program loaded from the storage part 208 to the random access memory (RAM) 203, such as executing the method in the above embodiment. In the RAM 203, various programs and data required for system operation are also stored. The CPU 201, the ROM 202 and the RAM 203 are connected to each other through the bus 204. The input / output (I / O) interface 205 is also connected to the bus 204.

[0100] The following components are connected to the I / O interface 205: an input section 206 including a keyboard, a mouse, etc.; an output section 207 including a cathode ray tube (CRT), an organic light emitting diode (OLED), a liquid crystal display (LCD), etc., and a speaker; a storage section 208 including a hard disk, etc.; and a communication section 209 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 209 performs communication processing via a network such as the Internet. A drive 210 is also connected to the I / O interface 205 as needed. A removable medium 211, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 210 as needed so that a computer program read therefrom is installed into the storage section 208 as needed.

[0101] In particular, according to an embodiment of the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication part 209, and / or installed from the removable medium 211. When the computer program is executed by the central processing unit (CPU) 1001, various functions defined in the system of the present invention are executed.

[0102] It should be noted that the computer-readable medium shown in the embodiment of the present invention may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0103] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. Among them, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0104] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0105] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor of a computer, causes the computer to execute the memory test method as described above. The computer-readable storage medium may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device.

[0106] Another aspect of the present invention further provides a computer program product or a computer program, the computer program product or the computer program includes computer instructions, the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the memory test method provided in each of the above embodiments.

[0107] In summary, the present invention provides a memory testing method, system, device and medium, which can be used to accurately determine whether the memory correctly executes the shutdown instruction of the cache function, verify whether the memory has the behavior of turning on internal background performance optimization, and provide a reference for subsequent memory performance inspection and improvement.

[0108] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A memory testing method, characterized in that: include: The memory is powered off, powered on, and initialized in sequence, and a cache function shutdown instruction is sent to the memory; Generate a plurality of random data, wherein the random data represents a random data amount, a write address, and a data sequence; Sending one of the random data to the memory, and sequentially powering off, powering on, and initializing the memory after receiving the data; Acquire the storage data in the memory according to the write address and data amount of the sent random data, and compare the data sequence of the random data with the storage data; When the data sequence of the random data is the same as the stored data, the next random data is sent to the memory for comparison again, until a preset number of cycles are completed, and it is determined that the cache function of the memory is in a closed state; When the data sequence of the random data is different from the stored data, it is determined that the cache function of the memory is in an on state.

2. The memory testing method according to claim 1, characterized in that: The step of generating a plurality of random data, wherein the random data represents a random data amount, a write address and a data sequence comprises: Acquire the storage capacity of the cache area of ​​the memory; Randomly generate a data volume, a write address, and a data sequence, wherein the data volume is less than or equal to the storage capacity of the cache area, the sum of the write address and the data volume is less than or equal to the total capacity of the memory, and each of the data sequences is different from each other; The data amount, the write address and the data sequence are combined to generate the random data.

3. The memory testing method according to claim 2, characterized in that: Before the step of obtaining the storage capacity of the cache area of ​​the memory, the method includes: Preset reference data is written into the memory, where the preset reference data is different from each of the data sequences.

4. The memory testing method according to claim 1, characterized in that: The step of sending one of the random data to the memory and sequentially powering off, powering on and initializing the memory after receiving the data comprises: Sending a write command to the memory and transferring the random data to the memory; A status monitoring command is sent to the memory, and after the memory is in a low power consumption state, power-off, power-on and initialization processing are sequentially performed on the memory.

5. The memory testing method according to claim 1, characterized in that: The step of acquiring the storage data in the memory according to the write address of the sent random data and comparing the random data with the storage data comprises: Reading the storage data at the corresponding address in the memory according to the write address and data amount of the sent random data; The data sequence of the sent random data is compared with the stored data to determine whether the data sequence is identical to the stored data.

6. The memory testing method according to claim 1, characterized in that: The steps of sequentially powering off, powering on and initializing the memory and sending a cache function closing instruction to the memory include: The memory is powered off, powered on, and initialized in sequence, and status information of a cache function of the memory is obtained; When the cache function of the memory is in an on state, a closing instruction is issued to close the cache function.

7. The memory testing method according to claim 6, characterized in that: The steps of sequentially powering off, powering on and initializing the memory and acquiring status information of the cache function of the memory include: Performing a power-off and power-on operation on the memory to clear existing data in a cache area of ​​the memory; Initializing the memory to enable communication between the memory and the host system; A read control command is issued to read status information of a cache function of the memory.

8. A memory testing system, characterized in that: include: A power-on and power-off initialization module, used to sequentially power off, power on and initialize the memory, and send a cache function shutdown instruction to the memory; A data generation module, used for generating a plurality of random data, wherein the random data represents a random data amount, a write address and a data sequence; A data transmission module, used for sending one of the random data to the memory, and sequentially performing power-off, power-on and initialization processing on the memory after receiving the data; A data verification module, used to obtain the storage data in the memory according to the write address and data volume of the sent random data, and compare the data sequence of the random data with the storage data; When the data sequence of the random data is the same as the stored data, the next random data is sent to the memory for comparison again until a preset number of cycles are completed, and it is determined that the cache function of the memory is in a closed state; When the data sequence of the random data is different from the stored data, the data verification module is used to determine that the cache function of the memory is in an enabled state.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the steps of the memory testing method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the memory testing method according to any one of claims 1 to 7 are implemented.

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