Compiling method and electronic device

Abstract

The embodiment of the present application provides a compilation method and an electronic device, the method comprising: receiving a first operation of a user on a first application; obtaining the number of executions of each instruction physical address executed by the first application in response to the first operation and the function to which each instruction physical address belongs; obtaining the number of executions of each function in the first application; determining the compilation information corresponding to each function in the first application according to the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function in the first application, the compilation information including at least one of a heat level, a branch jump probability, and a loop count; based on the compilation information, performing AOT compilation on each function in the first application respectively. The present application can perform targeted and differentiated AOT compilation for each function, can improve the quality of the generated target code, and improve the running performance of the application.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a compilation method and electronic equipment. Background Art

[0002] When an electronic device runs an application (APP), the application code needs to be compiled before it can be executed.

[0003] At present, the code execution methods supported by the Android operating system mainly include interpretation execution, just-in-time (JIT) compilation execution and ahead-of-time (AOT) compilation execution. Among them, AOT compilation execution compiles functions (i.e. hot functions) whose interpretation execution times reach a certain threshold.

[0004] As the application usage time increases, the number of hot functions will continue to increase, which makes the proportion of AOT compilation execution also increase, generally reaching 80%. Therefore, the quality of the machine code generated by AOT compilation directly affects the running performance of the application.

[0005] However, it was found during use that the quality of the machine code generated by AOT compilation in the related technology was low, resulting in low running performance of the application and affecting the user experience. Summary of the invention

[0006] The present application provides a compilation method and an electronic device, which can perform targeted and differentiated AOT compilation for each function based on the compilation information of the function, thereby improving the quality of the generated target code and enhancing the running performance of the application.

[0007] In a first aspect, the present application provides a compilation method, which is applied to an electronic device. The method may include: receiving a first operation of a user on a first application; obtaining the number of executions of each instruction physical address executed by the first application in response to the first operation and the function to which each instruction physical address belongs; obtaining the number of executions of each function in the first application; determining the compilation information corresponding to each function in the first application according to the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function in the first application, the compilation information including at least one of a heat level, a branch jump probability, and a loop count, and performing AOT compilation on each function in the first application based on the compilation information.

[0008] The first application may be any application installed in the electronic device, such as application 1 in the following text. For example, the first application may be a video application, an instant messaging application, a social application, a music application, a game application, a call application, a shopping application, etc. The embodiment of the present application does not specifically limit the type of the first application. The first operation may be any operation performed by the user on the first application.

[0009] A function is a block of code in an application. Usually, an application consists of multiple functions, each of which is used to implement a specific function. The number of executions of a function (hereinafter referred to as the number of function executions) refers to the number of times a function is called during the process of an electronic device running an application. It should be noted that the number of function executions refers to the cumulative value of the number of times a function is called during multiple runs of an application, starting from the first time an electronic device runs an application.

[0010] The instruction physical address refers to the actual address in the memory of the electronic device. The processor of the electronic device executes the instruction in the memory through the instruction physical address. Therefore, by monitoring the instruction physical address executed by the processor, the instructions inside the function actually executed by the processor can be tracked. It should be noted that each instruction physical address can be understood as a variety of different instruction physical addresses among the multiple instruction physical addresses collected when the first application responds to the first operation, that is, each of the above instruction physical addresses is different.

[0011] In the embodiment of the present application, since the execution times of a function can reflect the actual calling frequency of the function during the running of the application, the execution times of the instruction physical address can reflect the specific execution status of the instructions inside the function when the application responds to user operations. Therefore, based on the collected execution times of each instruction physical address, the function to which each instruction physical address belongs, and the execution times of each function in the application, the compilation information reflecting the actual execution status of each function can be determined. Based on the compilation information of the function, targeted and differentiated AOT compilation is performed for each function, which can improve the quality of the generated target code and enhance the running performance of the application.

[0012] The heat level is used to indicate the frequency of function calls. The branch jump probability is used to indicate the jump probability of each branch corresponding to the branch instruction in the function. The number of loops is used to indicate the number of loops in the loop body inside the function.

[0013] In this way, by utilizing the heat level of the function, different degrees of function inline optimization can be performed on functions of different heat levels. In this way, when executing the target code generated based on the optimized function, the number of function calls can be reduced, the response speed of the application can be improved, and the increase in the amount of code can be effectively controlled, saving the memory space of the electronic device. Furthermore, based on the jump probability of each branch corresponding to the branch instruction in the function, the functions in the application can be compiled more carefully, which can improve the success rate of branch prediction, reduce branch misses, and improve the running performance of the application. In addition, based on the number of loops in the loop body inside the function, loop expansion optimization is performed on each function in the application, which can reduce loop control overhead and improve the running performance of the application.

[0014] In a possible implementation of the first aspect, the compilation information includes a heat level. The above-mentioned AOT compilation is performed on each function in the first application based on the compilation information, including: determining a first threshold and a second threshold according to the heat level of the first function, wherein the first function is any function in the first application, and the size of the first threshold is positively correlated with the heat level, and the size of the second threshold is positively correlated with the heat level; if the number of instructions of the first function is less than or equal to the first threshold, and the number of instructions of the second function is less than or equal to the second threshold, embedding the second function in the first function to obtain a third function, wherein the second function is a function called by the first function; and generating target code according to the third function.

[0015] Among them, the first threshold is used to limit the maximum number of instructions (i.e., the amount of code) allowed as an inline function (i.e., the fixed inline function hereinafter), that is, when the number of instructions of a function is less than or equal to the first threshold, the function can be used as an inline function. The first threshold is the code amount threshold 1 hereinafter. The second threshold is used to limit the maximum number of instructions allowed as an inlined function (i.e., the inlined function hereinafter), that is, when the number of instructions of a function is less than or equal to the second threshold, the function can be embedded in the corresponding inline function. The second threshold is the code amount threshold 2 hereinafter. In other words, if the first threshold is larger, more functions in the application can be used as inline functions. On the contrary, if the first threshold is smaller, fewer functions in the application can be used as inline functions. Similarly, if the second threshold is larger, more functions in the application can be used as inlined functions. On the contrary, if the second threshold is smaller, fewer functions in the application can be used as inlined functions. Therefore, different first thresholds and second thresholds can be set for functions of different heat levels.

[0016] For example, taking the first function as an example, if the number of instructions of the first function is less than or equal to the first threshold, and the number of instructions of the second function is less than or equal to the second threshold, the second function is embedded in the first function, that is, the third function is obtained. The bytecode of the third function is converted to generate the target code (i.e., machine code). In this way, after the electronic device starts the first application again, when the first function is called, the processor directly runs the target code.

[0017] In this implementation, since the calling frequency of functions with higher heat levels is higher, a larger first threshold and second threshold are set for functions with higher heat levels. In this way, during AOT compilation, more functions with higher heat levels will be optimized for function inlining, and target code will be generated based on the optimized functions, so that when the target code is executed, the called function can be run directly, which can reduce the number of function calls to a greater extent and improve the response speed of the application. Furthermore, since the calling frequency of functions with lower heat levels is lower, a smaller first threshold and second threshold are set for functions with lower heat levels. Unlike functions with higher heat levels, functions with lower heat levels are less likely to be optimized for function inlining, which can effectively control the increase in the amount of code in the target code and save memory space of electronic devices.

[0018] In a possible implementation of the first aspect, the compilation information includes a loop count. The AOT compilation is performed on each function in the first application based on the compilation information, including: determining a loop expansion multiple corresponding to the first loop body according to the loop count of a first loop body in the first function and the number of instructions inside the first loop body, wherein the first function is any function in the first application, the first loop body is any loop body in the first function, the loop expansion multiple is negatively correlated with the number of instructions inside the loop body, and the loop expansion multiple is positively correlated with the loop count of the loop body; based on the loop expansion multiple corresponding to the first loop body, loop expansion optimization is performed on the first loop body to obtain a fourth function; and according to the fourth function, a target code is generated.

[0019] The loop body refers to the structural part of a function used to repeatedly execute a certain section of code, such as loop body 1 in the following text.

[0020] The number of instructions in a loop body refers to the total number of instructions to be executed in the loop body when the loop body is executed each iteration.

[0021] The loop expansion multiple refers to the number of times the instructions in the loop body are repeatedly executed each time the loop body is entered during the function execution process. Optionally, for loop bodies with more loops and fewer instructions inside, a larger loop expansion multiple is set. For loop bodies with fewer loops and more instructions inside, a smaller loop expansion multiple is set.

[0022] That is to say, if the number of loops in the loop body of a function is large and there are few instructions inside the loop body, a larger loop expansion multiple is used to optimize the loop expansion of the function, and the target code is generated according to the optimized function, so that when the target code is executed, the loop control overhead can be reduced and the application's running performance can be improved. However, if the number of loops in the loop body of a function is small and there are many instructions inside the loop body, a smaller loop expansion multiple is used to optimize the loop expansion of the function, which can avoid negative benefits caused by loop expansion. Of course, for loop bodies with fewer loops and more internal instructions, loop expansion can also be omitted.

[0023] In a possible implementation of the first aspect, the compilation information includes a branch jump probability. The above-mentioned AOT compilation is performed on each function in the first application based on the compilation information, including: obtaining the sorting of basic blocks in the first function, where the first function is any function in the first application; determining the jump probabilities of at least two branches corresponding to a target branch instruction in the first function, where the target branch instruction is any branch instruction in the first function; adjusting the sorting of basic blocks in the first function based on the jump probabilities of at least two branches so that the first basic block is located after the second basic block, to obtain a fifth function, wherein the first basic block is the basic block corresponding to the branch with the highest jump probability among the at least two branches, and the second basic block is the basic block corresponding to the target branch instruction; and generating target code according to the fifth function.

[0024] A function may consist of multiple basic blocks. Each basic block may include a series of continuous instructions. A branch instruction may be the end of a basic block and used to determine the next basic block to be executed. A branch instruction may correspond to at least two branches. The jump probability of a branch may reflect the possibility of the branch being executed.

[0025] In this implementation, during AOT compilation, the order of basic blocks in the function can be adjusted based on the jump probabilities of each branch of the branch instruction in the function, so that the basic blocks corresponding to the branches with the highest jump probabilities are arranged together with the basic blocks corresponding to the branch instructions. In this way, when executing the target code generated based on the optimized function, the accuracy of branch prediction can be improved, the branch misses during the function execution process can be reduced, and the running efficiency of the target code can be improved.

[0026] In a possible implementation of the first aspect, the compilation information includes a heat level. The AOT compilation is performed on each function in the first application based on the compilation information, including: generating target code for each function in the first application; sorting the functions in the first application in descending order of heat level to obtain an optimized compilation file (i.e., an odex file), wherein the optimized compilation file includes the target code for each function in the first application.

[0027] In this implementation, after generating the target code of each function in the application, the target code of each function is sorted in order from high to low according to the heat level of the function, so that the functions of different heat levels can be separated, and the functions with higher heat levels are arranged in the front position. In this way, when the Android runtime starts the application next time, it can load the functions with higher heat levels into the cache first according to the order of each function in the application. In this way, when the processor executes the function with higher heat level, it can directly read the corresponding instructions from the cache without searching from the main memory, which can improve the cache hit rate and enhance the running performance of the application.

[0028] In a possible implementation of the first aspect, the above-mentioned determination of compilation information corresponding to each function in the first application based on the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function in the first application includes: determining the heat level of the first function based on the number of executions of the first function; the first function is any function in the first application; determining the jump probability of each branch in the first function based on the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function; determining the number of loops of each loop body in the first function based on the number of executions of each instruction physical address and the function to which each instruction physical address belongs.

[0029] In a possible implementation of the first aspect, determining the heat level of the first function based on the number of executions of the first function includes: determining a target threshold interval to which the number of executions of the first function belongs; and determining the heat level corresponding to the target threshold interval as the heat level of the first function.

[0030] The heat level is determined based on the number of times a function is executed. The more times a function is executed, the higher the heat level of the function. Conversely, the fewer times a function is executed, the lower the heat level of the function. For example, the heat levels from low to high can be divided into the coldest level, the second coldest level, the medium level, the second hottest level, and the hottest level.

[0031] Exemplarily, multiple preset threshold intervals are set, and the number of executions of the first function is compared with the multiple preset threshold intervals to determine the target threshold interval to which the number of executions of the first function belongs, and then the heat level corresponding to the target threshold interval is determined as the heat level of the first function.

[0032] In this implementation, the heat level of a function is determined based on the number of times the function is executed, so that the heat level of the function can be used to perform AOT compilation on the function later, which can improve the quality of the generated target code.

[0033] In a possible implementation of the first aspect, the above-mentioned determination of the jump probability of each branch in the first function based on the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function includes: determining the instruction physical address of the function to which each instruction physical address belongs, as the instruction physical address corresponding to the first function; determining the instruction physical address of the first branch, the first branch being any branch in the instruction physical addresses corresponding to the first function; determining the number of executions of the instruction physical address of the first branch; and determining the jump probability of the first branch based on the number of executions of the first function and the number of executions of the instruction physical address of the first branch.

[0034] That is to say, during the running process of the application, the execution times of the instruction physical addresses corresponding to at least two branches of the branch instruction in the function are obtained, and the jump probability of the branch can be determined based on the execution times of the instruction physical addresses corresponding to the branches and the execution times of the instruction physical addresses of the branch instructions. In this way, when performing AOT compilation, the functions in the application can be compiled more carefully based on the jump probabilities of each branch corresponding to the branch instructions in the function, which can improve the success rate of branch prediction, reduce branch misses, and improve the running performance of the application.

[0035] For the implementation method, please refer to the relevant descriptions of S901 to S905 below.

[0036] In a possible implementation of the first aspect, the above-mentioned determining the number of loops of each loop body in the first function according to the number of executions of each instruction physical address and the function to which each instruction physical address belongs includes: determining the first instruction physical address and the second instruction physical address in the instruction physical address corresponding to the first function; wherein the first instruction physical address (i.e., instruction physical address 1 hereinafter) is the last instruction physical address before entering the first loop body in the first function, the second instruction physical address (i.e., instruction physical address 2 hereinafter) is the first instruction physical address in the first loop body, and the first loop body is any loop body in the first function; determining the number of executions of the first instruction physical address and the number of executions of the second instruction physical address; and determining the number of loops of the first loop body according to the number of executions of the first instruction physical address and the number of executions of the second instruction physical address.

[0037] That is to say, based on the execution times of the physical address of the last instruction entering the loop body in the function and the execution times of the physical address of the first instruction in the loop body, the number of loops of the loop body can be estimated. In this way, when AOT compilation is performed, loop unrolling optimization is performed on each function in the application based on the loop number of the loop body inside the function, which can reduce loop control overhead and improve the running performance of the application.

[0038] For the implementation method, please refer to the relevant descriptions of S1101 to S1103 below.

[0039] In a possible implementation of the first aspect, the above-mentioned determining the compilation information corresponding to each function in the first application based on the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function in the first application includes: when the electronic device is in an idle state, the electronic device is in a charging state, and the battery power of the electronic device is greater than or equal to a preset power threshold, determining the compilation information corresponding to each function in the first application based on the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function in the first application.

[0040] In this implementation, since AOT compilation requires a large amount of memory resources, AOT compilation is performed when the electronic device is in an idle state, the electronic device is in a charging state, and the battery power of the electronic device is greater than or equal to a preset power threshold. This can avoid affecting the normal operation of the electronic device and improve the user experience.

[0041] In a possible implementation of the first aspect, the above-mentioned obtaining the execution count of each instruction physical address executed by the first application in response to the first operation and the function to which each instruction physical address belongs includes: obtaining the execution count of each instruction physical address in response to the first operation; and parsing each instruction physical address separately to determine the function to which each instruction physical address belongs.

[0042] In a possible implementation of the first aspect, the above-mentioned parsing of each instruction physical address separately to determine the function to which each instruction physical address belongs includes: converting the third instruction physical address into a virtual address, wherein the third instruction physical address is any instruction physical address; and determining the function to which the third instruction physical address belongs based on the virtual address.

[0043] In a possible implementation of the first aspect, the above-mentioned determining the function to which the physical address of the third instruction belongs based on the virtual address includes: obtaining the instruction address range corresponding to each function in the first application; determining the instruction address range to which the virtual address belongs from the instruction address range corresponding to each function in the first application; and determining the function corresponding to the instruction address range to which the virtual address belongs as the function to which the physical address of the third instruction belongs.

[0044] In the embodiment of the present application, an instruction physical address uniquely corresponds to a virtual address, and a virtual address is within the instruction address range of a function. Therefore, the instruction physical address is converted into a virtual address, and based on the virtual address corresponding to the instruction physical address, the instruction address range to which the virtual address belongs is queried to determine the function to which the instruction physical address belongs. After determining the function to which the instruction physical address belongs, the instruction physical address can be stored in association with the function to which it belongs, so that based on the function to which the instruction physical address belongs, the instruction physical address corresponding to each function can be determined, and then combined with the number of executions of the function, the number of executions of each instruction physical address corresponding to the function, and the function to which each instruction physical address belongs, the compilation information of the function can be determined more accurately.

[0045] In a possible implementation of the first aspect, the above-mentioned respectively parsing each instruction physical address to determine the function to which each instruction physical address belongs includes: when the electronic device is in an idle state and the electronic device is in a charging state, respectively parsing each instruction physical address to determine the function to which each instruction physical address belongs.

[0046] In this implementation, since the parsing process requires a large amount of memory resources, parsing the physical address of each instruction when the electronic device is idle and charging can avoid affecting the normal operation of the electronic device and improve the user experience.

[0047] In a possible implementation of the first aspect, the above-mentioned obtaining the execution count of each instruction physical address in response to the first operation includes: determining the operation type of the first operation in response to the first operation; determining the sampling frequency and sampling duration corresponding to the first operation according to the operation type of the first operation; obtaining the instruction physical address executed by the first application when responding to the first operation according to the sampling frequency; and counting the execution count of each instruction physical address in a time period from the first operation to the sampling duration.

[0048] That is to say, when the user's operation on the application is monitored, the physical address of the instruction executed when the application responds to the user's operation is collected according to the sampling frequency, and the timing starts from the time the first operation is received. If the timing duration reaches the sampling duration, the sampling is stopped, that is, multiple physical addresses of instructions executed when multiple applications respond to user operations are obtained, and the execution times of each instruction physical address are counted. In this way, the execution times of each instruction physical address obtained are more in line with the actual use of the application. Furthermore, based on the execution times of each instruction physical address, the function to which each instruction physical address belongs, and the execution times of each function in the application, the compilation information of each function is determined, and AOT compilation is performed on each function according to the compilation information, which can improve the quality of the generated target code.

[0049] For the implementation method, please refer to the relevant descriptions of S501 to S508 below.

[0050] In a possible implementation of the first aspect, the operation type includes an operation of launching an application and / or an operation acting on an application interface; the operation acting on the application interface includes at least one of a click operation on a control in the application interface, a switching operation of the application interface, and a switching operation of an application widget.

[0051] In a second aspect, the present application provides a device, which is included in an electronic device, and the device has the function of implementing the electronic device behavior in the above-mentioned first aspect and the possible implementation of the above-mentioned first aspect. The function can be implemented by hardware, or it can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above-mentioned functions. For example, a sampling module or unit, a parsing module or unit, a compiling module or unit, etc.

[0052] In a third aspect, the present application provides an electronic device, comprising: a processor, a memory, and an interface; the processor, the memory, and the interface cooperate with each other so that the electronic device executes any one of the methods in the technical solution of the first aspect.

[0053] In a fourth aspect, the present application provides a chip, including a processor. The processor is used to read and execute a computer program stored in a memory to perform the method in the first aspect and any possible implementation thereof.

[0054] Optionally, the chip also includes a memory, and the memory is connected to the processor via a circuit or wire.

[0055] Further optionally, the chip also includes a communication interface.

[0056] In a fifth aspect, the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the processor executes any one of the methods in the technical solution of the first aspect.

[0057] In a sixth aspect, the present application provides a computer program product, the computer program product comprising: a computer program code, when the computer program code runs on an electronic device, the electronic device executes any one of the methods in the technical solution of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 is a partial schematic diagram of an example of function A provided in an embodiment of the present application;

[0059] Figure 2 is a partial schematic diagram of another example of function A provided in an embodiment of the present application;

[0060] Figure 3 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0061] Figure 4 is a software structure block diagram of the electronic device provided in the embodiment of the present application;

[0062] Figure 5 It is a flowchart of a hardware sampling process provided by an embodiment of the present application;

[0063] Figure 6 It is a flowchart of an example of a parsing process provided in an embodiment of the present application;

[0064] Figure 7 This is a flowchart of an AOT compilation process provided by an embodiment of the present application;

[0065] Figure 8 It is a flowchart of another example of the AOT compilation process provided by an embodiment of the present application;

[0066] Fig. 9 is a flowchart of a process for determining a branch jump probability provided by an embodiment of the present application;

[0067] Fig.10 is a partial schematic diagram of another example of function A provided in an embodiment of the present application;

[0068] Fig.11 It is a flowchart of a process for determining the number of cycles provided in an embodiment of the present application;

[0069] Fig.12 is a partial schematic diagram of another example of function A provided in an embodiment of the present application;

[0070] Fig.13 This is a flow chart of function inline optimization of a function provided in an embodiment of the present application;

[0071] Fig.14 This is a schematic diagram of a principle for setting a function inline strategy provided by an embodiment of the present application;

[0072] Fig.15 This is a flow chart of loop unrolling optimization of a function provided in an embodiment of the present application;

[0073] Fig.16 This is a schematic diagram of a principle of setting a loop unrolling strategy provided in an embodiment of the present application;

[0074] Fig.17 is a schematic diagram of a basic block rearrangement process provided by an embodiment of the present application;

[0075] Fig.18It is a schematic diagram of an example of basic block rearrangement of function 1 provided in an embodiment of the present application;

[0076] Fig.19 This is a schematic diagram of an example of function layout optimization for application 1 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0077] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0078] In the following, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features.

[0079] References to "one embodiment" or "some embodiments" etc. described in the specification of the present application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in the specification of the present application do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0080] In order to better understand the embodiments of the present application, the terms or concepts that may be involved in the embodiments are explained below.

[0081] 1. Interpreted execution, JIT compilation execution and AOT compilation execution

[0082] Interpreted execution: When an electronic device runs an application, it interprets the application's bytecode line by line into executable instructions and runs the executable instructions.

[0083] JIT compilation and execution: When an electronic device runs an application, the JIT compiler monitors the number of times each function is interpreted and executed. When the number of times certain functions are interpreted and executed reaches a threshold (such as 65535 times), the JIT compiler starts to compile the bytecodes of these functions (such as dalvik bytecode) to generate machine code. After generating the machine code, the JIT compiler saves the machine code in memory so that the next time these functions are called, the corresponding machine code in the memory can be directly executed. It should be noted that when the application stops running, the process corresponding to the application ends, and the Android operating system releases the resources occupied by the process, that is, destroys the generated machine code.

[0084] In addition, during the JIT compilation execution process, the JIT compiler records the functions that reach the number threshold into the profile file of the Android runtime. For the sake of convenience, the functions that reach the number threshold are referred to as hot functions in the following text.

[0085] AOT compilation and execution: Before running the application (such as when the electronic device is idle and charging), the Dalvik bytecode of the hot function recorded in the profile file is compiled to a higher degree to generate machine code, and the generated machine code is saved in an optimized Dalvik executable file (referred to as odex file). When the electronic device runs the application, if the function in the odex file is called, the machine code generated after compilation and optimization in the odex file is directly executed.

[0086] It should be understood that compared with JIT compilation, AOT compilation is a higher-level and more optimized compilation method, so AOT compilation can generally be called compilation optimization.

[0087] 2. Dalvik executable file (DEX file for short), odex file

[0088] The dex file is used to record the source code (i.e., Dalvik bytecode) of all functions in the application, that is, the dex file includes the Dalvik bytecode of the hot functions in the application. The dex file is generally included in the Android application package (APK file) of the application, so the dex file can be read from the APK file of the application. It should be noted that the APK file of the application can include one or more dex files.

[0089] The odex file refers to an optimized dex file generated after AOT compilation of the dalvik bytecode in the dex file. In the embodiment of the present application, during the AOT compilation process, the dalvik bytecode of the hot function in the dex file is usually compiled to generate directly executable machine code. It should be understood that different applications correspond to different odex files, which can ensure data security and isolation between different applications.

[0090] 3. Instruction physical address, virtual address and instruction address range

[0091] The instruction physical address refers to the actual address in the memory of the electronic device. The processor of the electronic device executes the instruction in the memory through the instruction physical address. In other words, by monitoring the instruction physical address executed by the processor, the instruction actually executed by the processor can be tracked.

[0092] A virtual address is an abstract memory address provided by the operating system. The operating system allocates virtual address spaces to applications to ensure that different applications run in isolated address spaces without interfering with each other. Each virtual address uniquely corresponds to a location in the virtual address space. Applications can access memory through virtual addresses.

[0093] In the embodiment of the present application, the instruction address range refers to the virtual address range corresponding to the function, that is, one function corresponds to one instruction address range. In other words, the instruction address range corresponding to a function is a continuous address sequence formed by the virtual addresses of multiple instructions constituting the function, that is, the entire address interval starting from the virtual address of the first instruction of the function and ending with the virtual address of the last instruction of the function.

[0094] It should be noted that a physical address of an instruction uniquely corresponds to a virtual address, and a virtual address belongs to the instruction address range of a function. Based on this, in the embodiment of the present application, after monitoring the physical address of the instruction executed by the processor, based on the virtual address corresponding to the physical address of the instruction, the instruction address range to which the virtual address belongs is queried, so that the function to which the physical address of the instruction belongs can be obtained, that is, the function to which the instruction actually executed by the processor belongs.

[0095] 4. Function, basic block, branch instruction, loop body

[0096] A function is a block of code in an application. Usually, an application consists of multiple functions, each of which is used to implement a specific function.

[0097] A basic block is a sequence of consecutive instructions. A function can consist of multiple basic blocks, each containing a series of consecutive instructions. For example, see Figure 1, function A may include basic block 1, basic block 2 and basic block 3.

[0098] A branch instruction is an instruction in a function that changes the flow of program execution. A branch instruction can be used to end a basic block and determine the next basic block to be executed. For example, see Figure 1 , the last instruction of basic block 1 in function A is a branch instruction (such as an if statement). If the value returned by the if statement is yes, basic block 2 is executed. If the value returned by the if statement is no, basic block 3 is executed.

[0099] A loop body is a structure in a function that repeatedly executes a certain section of code. A loop body can include one or more basic blocks. For example, see Figure 2 , function A can include loop body 1.

[0100] 5. Function inlining, fixed inline functions, and inlined functions

[0101] Function inlining means embedding the function code directly into the location where the function is called, thus avoiding the overhead of calling the function. For example, when function A calls function B, the code of function B is directly embedded into the calling point of function A.

[0102] A fixed inline function is a function that needs to call other functions during execution.

[0103] An inlined function is a function called by a fixed inline function when the fixed inline function is inlined. For example, when function A calls function B during its execution, function A is a fixed inline function and function B is an inlined function.

[0104] 6. Loop Unrolling

[0105] Loop unrolling refers to copying the code to be executed in the loop a certain number of times, so that the code in the loop can be repeatedly executed multiple times in each iteration, reducing the number of loop iterations and improving execution efficiency.

[0106] The above section describes three common code execution methods and other related concepts in the Android operating system. According to the above description, AOT compilation and execution is compiled for hot functions in the profile file. After analysis, the inventor found that in the related art, hot functions are judged based on the number of times the function is interpreted and executed, that is, when the number of times the function is interpreted and executed reaches the set number threshold, the function is a hot function. For example, when the running time of the application reaches 10s, the number of times the interpretation and execution of a function reaches the number threshold, then the function is a hot function. Similarly, when the running time of the application reaches 2h, the number of times the interpretation and execution of a function reaches the number threshold, then the function will also be considered a hot function. However, this judgment method will cause some functions that are not frequently executed to be mistaken for hot functions because the running time of the application is long. In this way, during the AOT compilation process, while compiling and optimizing the frequently executed hot functions, the functions that are mistaken for hot functions because the running time of the application is long will also be compiled in the same way, which will affect the quality of the machine code generated by the AOT compilation, resulting in low running performance of the application and affecting the user's experience.

[0107] In addition, the inventors have found through analysis that in the related technology, when the number of interpreted executions of a function reaches a threshold number, the function will be AOT compiled without paying attention to the jump probability of each branch of the branch instructions inside the function. This leads to branch prediction failures when processing branch instructions, increases the number of cache misses, and affects the response speed of the application.

[0108] In order to solve the above technical problems, the embodiment of the present application provides a compilation method, during the operation of the application, the compilation information of each function in the application is obtained, and the compilation information may include at least one of the heat level, the branch jump information of the function and the number of loops of the function. In this way, using the heat level of the function, the functions of different heat levels can be optimized for inline functions to different degrees, which can reduce the number of function calls and improve the response speed of the application. At the same time, the increase in the amount of code can be effectively controlled, saving the memory space of the electronic device. Furthermore, based on the jump probability of each branch corresponding to the branch instruction in the function, the functions in the application can be compiled more carefully, which can improve the success rate of branch prediction, reduce branch misses, and improve the running performance of the application. In addition, based on the number of loops of the loop body inside the function, loop expansion optimization is performed on each function in the application, which can reduce the loop control overhead and improve the running performance of the application. In other words, based on the compilation information of the function, targeted and differentiated AOT compilation is performed for each function, which can improve the quality of the generated target code and improve the running performance of the application.

[0109] Before introducing the compilation method provided in the embodiment of the present application, the electronic device to which the compilation method provided in the present application is applicable is first described.

[0110] The compilation method provided in the embodiments of the present application can be applied to electronic devices that can install application programs, such as mobile phones, tablet computers, wearable devices, vehicle-mounted devices, augmented reality (AR) / virtual reality (VR) devices, laptop computers, ultra-mobile personal computers (UMPCs), netbooks, and personal digital assistants (PDAs). The embodiments of the present application do not impose any restrictions on the specific types of electronic devices.

[0111] For example, Figure 3 1 is a schematic diagram of the structure of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0112] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0113] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0114] The controller may be the nerve center and command center of the electronic device 100. The controller may generate an operation control signal according to the instruction operation code and the timing signal to complete the control of fetching and executing instructions.

[0115] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0116] In some embodiments, when the electronic device runs an application, the processor 110 executes the machine code of the application generated by AOT compilation.

[0117] In some embodiments, an embedded trace macrocell (ETM) may also be provided in the processor 110. The ETM is used to monitor the detailed instruction flow when the processor executes a program. In the embodiment of the present application, the ETM is used to monitor the physical address of the instruction executed by the processor. A performance monitor unit (PMU) may also be provided in the processor 110. The PMU is used to monitor and count various hardware events in the processor, such as instruction execution, clock cycle, cache access, etc. In the embodiment of the present application, the PMU is used to record the number of executions of the physical address of the instruction.

[0118] The electronic device 100 implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0119] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. In some embodiments, the electronic device 100 may include 1 or N display screens 194, where N is a positive integer greater than 1.

[0120] The internal memory 121 can be used to store computer executable program codes, and the executable program codes include instructions. The processor 110 executes various functional applications and data processing of the electronic device 100 by running the instructions stored in the internal memory 121. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area can store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0121] The electronic device to which the compiling method provided by the present application is applicable is described above. Next, the software system of the electronic device is described.

[0122] The software system of the electronic device 100 may adopt a layered architecture, an event-driven architecture, a micro-core architecture, a micro-service architecture, or a cloud architecture. The embodiment of the present application takes the Android system of the layered architecture as an example to exemplify the software structure of the electronic device 100.

[0123] Figure 4 1 is a software structure diagram of the electronic device 100 of the embodiment of the present application. The layered architecture divides the software into several layers, each layer has a clear role and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom, namely, the application layer, the application framework layer (also called the Java framework layer), the native layer (also called the C++ framework layer), the Android runtime and the system library.

[0124] The application layer may include a series of application packages. Figure 4As shown, the application package may include applications such as calls, videos, instant messaging, music, short messages, games, and cameras.

[0125] The application framework layer provides an application programming interface (API) and programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0126] As an example of this application, Figure 4 As shown, the application framework layer may include an activity manager service (AMS), a task scheduler, and a user behavior module. The user behavior module may include a scene recognition unit, a sampling strategy control unit, and a parsing scheduling unit.

[0127] like Figure 4 As shown, the local layer may include a sampling module and a parsing module. The sampling module may include a data sampling unit and a sampling reporting unit. The parsing module may include a data parsing unit and a parsing reporting unit.

[0128] Among them, AMS is a core component of the Android operating system. It is the manager of Android applications and is responsible for managing the application life cycle, task stack, switching between processes and activities, etc. AMS plays a vital role in the Android system, ensuring that applications can run correctly and interact with users. Task stack management refers to the mechanism for organizing and managing the activities of applications in the Android system. Each task stack corresponds to an application or a group of related activities. When a user starts a new activity of an application, the system adds the task to which the activity belongs to a task stack. For each activity started in an application, there is an ActivityRecord corresponding to it. ActivityRecord is used to monitor and record the state changes of the activity and report the monitoring information to AMS, which then reports the monitoring information to the scene recognition unit in the user behavior module. Among them, the monitoring information includes the application information of the application and the operation type of operation 1.

[0129] After receiving the monitoring information sent by the AMS, the scene recognition unit sends the application information and operation type in the monitoring information to the sampling strategy control unit.

[0130] The sampling strategy control unit is used to determine the sampling parameters corresponding to the user operation according to the operation type. After determining the sampling parameters, the sampling strategy control unit sends a sampling instruction to the data sampling unit. The sampling instruction carries the sampling parameters and application information.

[0131] The data sampling unit is used to respond to the sampling instruction and, according to the sampling parameters, obtain the physical address of the instruction executed by the processor when the application responds to the user operation and the number of executions of each instruction physical address (i.e., the hardware sampling information in the following text), and write the hardware sampling information into a temporary file corresponding to the application.

[0132] The sampling reporting unit is used to obtain the current load information of the electronic device during the sampling process of the data sampling unit, and send the current load information to the sampling strategy control unit. The sampling strategy control unit is also used to adjust the sampling parameters based on the current load information of the electronic device, and send the adjusted sampling parameters to the data sampling unit. The data sampling unit is also used to perform sampling based on the adjusted sampling parameters.

[0133] The task scheduler is used to monitor whether the electronic device meets the parsing condition. If the electronic device meets the parsing condition, the task scheduler sends a parsing scheduling message to the parsing scheduling unit.

[0134] The parsing scheduling unit is used to send a data parsing instruction to the data parsing unit after receiving the parsing scheduling message. The data parsing instruction is used to instruct the data sampling unit to parse the hardware sampling information obtained by the data sampling unit.

[0135] The data analysis unit is used to obtain the hardware sampling information of the application from the temporary file corresponding to the application after receiving the data analysis instruction. The data analysis unit analyzes the hardware sampling information to obtain the function to which each instruction physical address in the hardware sampling information belongs, and associates the execution times of each instruction physical address with the function to which it belongs and stores it in the profile file of the application.

[0136] The analysis reporting unit is used to obtain the current load information of the electronic device during the analysis of the data analysis unit, and send the current load information to the data analysis scheduling unit. The data analysis scheduling unit is also used to control the analysis process of the data analysis unit based on the current load information of the electronic device.

[0137] Android runtime includes core libraries and virtual machines. Android runtime is responsible for scheduling and management of the Android system. The core library consists of two parts: one is the function that the Java language needs to call, and the other is the Android core library. The application layer and the application framework layer run in the virtual machine. The virtual machine executes the Java files of the application layer and the application framework layer as binary files. The virtual machine is used to perform object life cycle management, stack management, thread management, security and exception management, and garbage collection.

[0138] As an example of this application, Figure 4 As shown, the Android runtime may include a compilation scheduling module and a compilation module. Among them, the compilation scheduling module is used to start the AOT compilation task after receiving the compilation task scheduling information sent by the task scheduler. After starting the AOT compilation task, the compilation scheduling module sends a compilation instruction to the compilation module. After receiving the compilation instruction, the compilation module performs AOT compilation on the application.

[0139] like Figure 4 As shown, the compilation module may include a precompile unit, a front-end processing unit, an intermediate expression unit, an initialization unit, an optimizer, an instruction scheduling unit, a basic block reordering unit, a register allocation unit, a code generator, and a function layout unit.

[0140] Among them, the precompilation unit is used to obtain the profile file and dex file of the application.

[0141] The front-end processing unit is used to read the bytecode corresponding to each function from the dex file and perform front-end processing (such as syntax analysis and semantic analysis) on the bytecode corresponding to each function.

[0142] The intermediate representation unit is used to convert the bytecode corresponding to each function processed by the front-end processing unit into an intermediate representation (IR).

[0143] The initialization unit is used to read the execution times and the functions to which the physical addresses of multiple instructions belong, as well as the function execution times of each function in the application program from the profile file after the intermediate expression unit completes the conversion of the bytecode, and determine the compilation information corresponding to each function in the application program according to the read data. The compilation information includes at least one of the heat level, branch jump information, and loop count.

[0144] The optimizer is used to optimize the bytecode of each function based on the compilation information. Exemplarily, the optimizer can perform optimization processing such as function inline optimization, loop optimization, instruction simplification, and dead code elimination on the bytecode of each function. Among them, loop optimization can include loop unrolling optimization, loop fusion optimization, and loop splitting optimization.

[0145] The instruction scheduling unit is used to perform instruction scheduling processing on the optimized bytecodes corresponding to each function sent by the optimizer.

[0146] The basic block reordering unit is used to reorder the basic blocks of each function based on the branch jump information after the instruction scheduling process is completed.

[0147] The register allocation unit is used to allocate register addresses to each function after completing the basic block reordering.

[0148] The code generator is used to convert the optimized bytecode corresponding to each function after allocating the register address, and generate the machine code corresponding to each function.

[0149] The function layout unit is used to optimize the function layout of the functions in the application based on the heat level, and obtain the odex file of the application. The odex file includes the machine code corresponding to each function.

[0150] The system library can include multiple functional modules. For example: surface manager, media libraries, 3D graphics processing library (for example: OpenGL ES), 2D graphics engine (for example: SGL), etc. The surface manager is used to manage the display subsystem and provide fusion of 2D and 3D layers for multiple applications. The media library supports playback and recording of a variety of commonly used audio and video formats, as well as static image files, etc. The media library can support a variety of audio and video encoding formats, such as: MPEG4, H.264, MP3, AAC, AMR, JPG, PNG, etc. The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, synthesis, and layer processing, etc. The 2D graphics engine is a drawing engine for 2D drawing.

[0151] For ease of understanding, the overall process of the compilation method provided in the embodiment of the present application is first schematically described. In addition, the application program is referred to as application in the following text.

[0152] In an embodiment of the present application, the compilation method may include a sampling phase, a parsing phase, and an AOT compilation phase. In the sampling phase, sampling information of applications in electronic devices is obtained, and the sampling information includes the function execution times of each function in the application, the instruction physical addresses executed by the processor during the application running process, and the execution times of each instruction physical address. In the parsing phase, for each application, the physical addresses of each instruction obtained by sampling are parsed to determine the functions to which each instruction physical address belongs. In the AOT compilation phase, the compilation task is started, and AOT compilation is performed on the application. In the AOT compilation phase, the compilation information of each function in the application is determined according to the function execution times of each function in the application, the execution times of each instruction physical address during the application running process, and the functions to which each instruction physical address belongs. The compilation information may include at least one of the heat level, the branch jump information of the function, and the number of loops of the function. Based on the compilation information of each function, a corresponding compilation strategy is set for each function. Then, AOT compilation is performed on each function according to the corresponding compilation strategy to generate an odex file corresponding to the application.

[0153] The following has Figure 3 and Figure 4 Taking the electronic device with the structure shown as an example, the sampling stage, the parsing stage and the AOT compilation stage are respectively described in detail.

[0154] 1. Sampling stage

[0155] In the embodiment of the present application, sampling may include hardware sampling and software sampling. Among them, software sampling is used to obtain the function execution times of each function in the application. Hardware sampling is used to obtain the physical address of the instruction executed by the processor during the application running process and the execution times of each instruction physical address.

[0156] For example, taking an electronic device with multiple applications installed as an example, when the electronic device is running application 1, the function execution count of each function in application 1 is obtained in real time through software sampling. At the same time, the physical address of the instruction executed by the processor during the running of application 1 and the execution count of each instruction physical address are obtained through hardware sampling, that is, the sampling information of application 1. Similarly, when the electronic device is running application 2, the function execution count of each function in application 2 is obtained in real time through software sampling. At the same time, the physical address of the instruction executed by the processor during the running of application 2 and the execution count of each instruction physical address are obtained through hardware sampling, that is, the sampling information of application 2. In this way, the sampling information of each application in the electronic device can be obtained.

[0157] It should be noted that each instruction physical address can be understood as a variety of different instruction physical addresses among multiple instruction physical addresses collected during the application running process, that is, each of the above instruction physical addresses is different.

[0158] A. Software Sampling

[0159] The number of function executions refers to the total number of times a function is called each time the electronic device runs an application since the electronic device first runs the application, that is, the cumulative value of the number of times the function is called when the electronic device runs the application multiple times. In addition, the electronic device running the application mentioned here can refer to running the application in the foreground or in the background.

[0160] In some examples, the software sampling method may be Android runtime instrumentation sampling. Taking application 1 as an example, when a function is called during the electronic device running application 1, the Android runtime performs instrumentation processing on the function to record the function execution count of the function. In this way, the function execution count of each function in application 1 can be obtained. After obtaining the function execution count of each function in the application, each function is associated with its corresponding function execution count and stored in profile file 1 of application 1.

[0161] Optionally, by associating the index information of the function with the function execution count of the function, each function can be associated and stored with its corresponding function execution count. The function index information is used to uniquely identify the function in the application. Exemplarily, the function index information can be, for example, the name of the function or the identity identification number of the function (referred to as function ID).

[0162] For example, if the function A is executed 1000 times, in profile file 1, the function A can be expressed as: function A-1000 times. For another example, if the function B is executed 2000 times, in profile file 1, the function B can be expressed as: function B-2000 times.

[0163] B. Hardware Sampling

[0164] Hardware sampling can be triggered by user operations on applications, that is, when user operations on an application are monitored, the physical addresses of instructions executed by the processor when the application responds to the user operations and the execution times of each instruction physical address are obtained.

[0165] For example, when the electronic device is running application 1, if the user's operation 1 on application 1 is detected, the physical address of the instruction executed by the processor when application 1 responds to operation 1 and the execution count of each instruction physical address are obtained. Similarly, if the user's operation 2 on application 1 is detected, the physical address of the instruction executed by the processor when application 1 responds to operation 2 and the execution count of each instruction physical address are obtained. By repeatedly executing the aforementioned sampling process, the physical address of the instruction executed by the processor and the execution count of each instruction physical address each time application 1 responds to a user's operation can be obtained. In this way, the physical addresses of all instructions executed by the processor and the execution count of each instruction physical address during the running of application 1 can be obtained.

[0166] It should be noted that each instruction physical address can be understood as a different instruction physical address among a plurality of instruction physical addresses collected when the first application responds to the first operation, that is, each of the above instruction physical addresses is different.

[0167] It should be noted that the software sampling process and the hardware sampling process can be executed in a certain order or simultaneously. The execution order between the software sampling process and the hardware sampling process is not specifically limited in the embodiments of the present application.

[0168] The following uses the application running on the electronic device as application 1 and the user's operation as operation 1 as an example to schematically illustrate the process of hardware sampling. Figure 5 As shown, the hardware sampling process may include the following steps:

[0169] S501, application 1 receives operation 1 input by a user.

[0170] S502, ActivityRecord detects that the Activity state has changed, and reports monitoring information to AMS, where the monitoring information includes application information of application 1 and operation type of operation 1.

[0171] The application information is used to indicate the application involved in the user operation. Exemplarily, the application information may be ApplicationInfo.

[0172] User operations can be divided into multiple types. In some examples, the operation types can be divided according to the functions of the operations. Exemplarily, the operation types may include operations to start an application and operations acting on the application interface. Among them, the operation to start an application refers to a click operation on the icon of the application. The operation acting on the application interface may include at least one of a click operation on a control in the application interface, a switching operation on the application interface, and an application window switching operation. For example, taking a video application as an example, the operation acting on the control may include, for example, a click operation on a video sending control, a click operation on a video like control, a click operation on a video collection control, etc. The operation acting on the control may also be an operation on a tab control, such as a click operation on a "recommended" tab control, a click operation on a "home" tab control, and a click operation on a "my" tab control. The switching operation of the application interface may be, for example, an operation of flipping through different videos. The application window switching operation is used to display the application in a floating window form.

[0173] In other examples, the operation type may be divided according to the operation triggering mode. Exemplarily, the operation type may include a click operation, a slide operation, a long press operation, etc. In the embodiment of the present application, the operation type is not specifically limited.

[0174] Monitoring information refers to the Activity status information recorded by ActivityRecord when it detects a change in Activity status. In some examples, Activity status information may include but is not limited to: ProcessRecordapp (in which process it is running), TaskRecordtask (in which task it is running), Activity Type (Activity type), Activitystate (Activity status), Applicatoinf (in which application it is running), SystemTime (system time), etc. Among them, Activity status can reflect user operations. If the operation type of the user operation changes, the Activity status will also change.

[0175] That is, ActivityRecord reports the Activity status to AMS so that AMS knows what type of user operation it is. In addition, ActivityRecord associates the Activity status with the application (such as the application identifier) ​​and reports it to AMS so that AMS knows which application's Activity status it is.

[0176] S503 , the AMS sends application information of application 1 and operation type of operation 1 to the scene recognition unit.

[0177] S504 : The scene recognition unit sends application information of application 1 and operation type of operation 1 to the sampling strategy control unit.

[0178] S505 : The sampling strategy control unit determines a sampling parameter corresponding to the operation 1 according to the operation type of the operation 1 .

[0179] In some examples, the sampling parameters may include a sampling duration and a sampling frequency. The sampling duration may be determined according to the response duration of the user operation. Optionally, the sampling duration may be greater than or equal to the response duration of the user operation.

[0180] For example, as shown in Table 1, it lists the response time and sampling time corresponding to different types of operations.

[0181] Table 1 Response time and sampling time corresponding to different types of operations

[0182]

[0183] Exemplarily, the sampling frequency may be a preset frequency value. Exemplarily, the sampling frequency may also be determined according to the response time of the user operation. For example, if the response time of the user operation is short, a higher sampling frequency is set. If the response time of the user operation is long, a lower sampling frequency is set.

[0184] In the embodiment of the present application, since different types of operations correspond to different response times, the sampling frequency and sampling time are determined according to the operation type of the user operation, so that the physical address of the instruction executed by the processor when the application responds to the user operation is subsequently obtained according to the sampling frequency and sampling time, which can improve the accuracy of sampling.

[0185] S506 , the sampling strategy control unit sends a sampling instruction to the data sampling unit, where the sampling instruction carries application information of application 1 and sampling parameters corresponding to operation 1 .

[0186] S507 , the data sampling unit responds to the sampling instruction and, according to the sampling parameters corresponding to operation 1 , obtains the physical addresses of the instructions executed by the processor when application 1 responds to operation 1 and the number of executions of each physical address of the instructions.

[0187] Exemplarily, taking the sampling parameters corresponding to operation 1 including sampling frequency f1 and sampling duration t1 as an example, when receiving the sampling instruction (i.e., monitoring the user input operation 1), the data sampling unit starts the sampling process, and starts collecting the physical addresses of the instructions executed by the processor when application 1 responds to operation 1 according to the sampling frequency f1, and counts the number of executions of the physical addresses of the instructions. Also, the timing starts from the start time of the sampling process. If the timing duration reaches the sampling duration t1, the sampling process is terminated, that is, multiple instruction physical addresses and the number of executions of each instruction physical address are collected. For the sake of convenience, the collected multiple instruction physical addresses and the number of executions of each instruction physical address are referred to as hardware sampling information.

[0188] In some examples, it can be seen from the description of the software structure of the aforementioned electronic device that the sampling module can also include a sampling reporting unit. In the process of obtaining the hardware sampling information of application 1, the sampling reporting unit can obtain the current load information of the electronic device and send the current load information of the electronic device to the sampling strategy control unit. In this way, the sampling strategy control unit can adjust the sampling parameters corresponding to operation 1 based on the current load information of the electronic device.

[0189] Among them, the load information may include CPU usage and memory occupancy. For example, if the current CPU usage of the electronic device is greater than the first preset CPU usage, and / or the current memory occupancy of the electronic device is greater than the first preset memory occupancy, the sampling strategy control unit may lower the sampling frequency and send the lowered sampling frequency to the data sampling unit. Furthermore, the data sampling unit may obtain the physical addresses of multiple instructions executed by the processor when application 1 responds to operation 1 according to the lowered sampling frequency. In this way, during the hardware sampling process, the sampling parameters are adjusted in real time based on the current load information of the electronic device, so that when the overall load of the electronic device is high, the sampling frequency can be reduced, the resource occupation of the sampling process can be reduced, and the normal operation of the electronic device can be avoided from being affected.

[0190] S508 , the data sampling unit writes the physical address of the instruction executed by the processor and the number of executions of each physical address of the instruction (ie, hardware sampling information) into temporary file 1 corresponding to application 1 .

[0191] Exemplarily, after collecting the hardware sampling information, the data sampling unit associates each instruction physical address with its corresponding execution number and stores it in the temporary file 1 of the application 1.

[0192] For example, taking the execution number of instruction physical address a (0x00001125) as 100 times, in temporary file 1, the execution number of instruction physical address a can be expressed as: 0x00001125-100 times.

[0193] For example, taking the execution number of instruction physical address b (0x00001188) as 900 times, in temporary file 1, the execution number of instruction physical address b can be expressed as: 0x00001188-900 times.

[0194] Optionally, each application corresponds to a temporary file, and the temporary file is used to store the hardware sampling information of the corresponding application. For example, when the user's operation on application 1 is monitored, the hardware sampling information of application 1 in response to the user's operation is written into temporary file 1 of application 1. When the user's operation on application 2 is monitored, the hardware sampling information of application 2 in response to the user's operation is written into temporary file 2 of application 2. In this way, data security and isolation between different applications can be guaranteed.

[0195] Exemplarily, when an electronic device starts an application for the first time, a temporary file corresponding to the application can be generated, and the temporary file of the application can be stored in association with the application information of the application. In this way, after obtaining the hardware sampling information of the application in response to the user operation, the data sampling unit can search for the temporary file of the application based on the application information of the application, and write the hardware sampling information into the temporary file of the application. Furthermore, in the parsing stage, the data parsing unit can directly read the hardware sampling information of the application from the temporary file of the application and parse the hardware sampling information.

[0196] The above is a schematic illustration of the process of hardware sampling, taking operation 1, in which the user operation acts on application 1, as an example. It is understandable that the process of obtaining hardware sampling information when application 1 responds to other operations can refer to S501 to S508 above. Similarly, the process of obtaining hardware sampling information when other applications respond to user operations can also refer to S501 to S508 above, which will not be repeated here.

[0197] 2. Parsing stage

[0198] In the parsing stage, the hardware sampling information of the application is parsed to obtain the function to which the physical address of each instruction in the application belongs.

[0199] like Figure 6 As shown, the parsing process may include the following steps:

[0200] S601, the task scheduler determines whether the electronic device meets the parsing condition. If the electronic device meets the parsing condition, S602 is executed, otherwise, it continues to determine whether the electronic device meets the parsing condition.

[0201] The parsing condition is used to limit the timing of the electronic device parsing data. In one embodiment, the parsing condition may be: the electronic device is in an idle and charging state. In some examples, the task scheduler may determine whether the electronic device is in an idle and charging state through the operation information of the electronic device. Among them, the operation information is used to characterize the operation state of the electronic device. Optionally, the operation information may include CPU usage, memory occupancy, and battery status. Specifically, the task scheduler may obtain the current CPU usage, current memory occupancy, and current battery status of the electronic device; determine whether the current CPU usage is less than the second preset CPU usage, whether the current memory occupancy is less than the second preset memory occupancy, and whether the current battery status is a charging state; if the current CPU usage is less than the second preset CPU usage, and the current memory occupancy is less than the second preset memory occupancy, and the current battery status is a charging state, it is determined that the electronic device meets the parsing condition; otherwise, it is determined that the electronic device does not meet the parsing condition. In this embodiment, since the parsing process requires a large amount of memory resources, the sampling information is parsed when the electronic device is in an idle and charging state, which can avoid affecting the normal operation of the electronic device and improve the user experience.

[0202] S602: The task scheduler sends a parsing scheduling message to the parsing scheduling unit, wherein the parsing scheduling message is used to indicate that the electronic device meets the parsing condition.

[0203] S603, after receiving the parsing scheduling message, the parsing scheduling unit sends a data parsing instruction to the data parsing unit. The data parsing instruction may include application information, and the data parsing instruction is used to instruct the data parsing unit to parse the hardware sampling information applied in the electronic device.

[0204] Optionally, the data parsing instruction may instruct to parse the hardware sampling information of one application in the electronic device, or may instruct to parse the hardware sampling information of multiple applications (e.g., all applications) in the electronic device. The following is an example in which the data parsing instruction instructs to parse the hardware sampling information of all applications in the electronic device. The parsing process is described in detail by taking application 1 as an example.

[0205] S604 , after receiving the data parsing instruction, the data parsing unit obtains the hardware sampling information of the application 1 from the temporary file 1 of the application 1 .

[0206] Specifically, the data parsing unit searches for the temporary file 1 corresponding to the application 1 based on the application information corresponding to the application 1 carried in the parsing instruction, and reads the hardware sampling information of the application 1 from the temporary file 1 .

[0207] S605: The data parsing unit obtains profile file 1 of application 1.

[0208] It should be noted that the above S604 and S605 can be performed according to Figure 6 The execution sequence shown in the embodiment shown in the figure may also be executed in other sequences, or S604 and S605 may be executed simultaneously. The embodiment of the present application does not impose any limitation on the execution sequence of the above S604 and S605.

[0209] S606: The data parsing unit converts each instruction physical address in the hardware sampling information of the application 1 into a virtual address, and determines the function to which each instruction physical address belongs based on the virtual address corresponding to each instruction physical address.

[0210] In the embodiment of the present application, a physical address of an instruction uniquely corresponds to a virtual address, and a virtual address is within the instruction address range of a function. Therefore, the physical address of the instruction is converted into a virtual address, and based on the virtual address corresponding to the physical address of the instruction, the instruction address range to which the virtual address belongs is queried to determine the function to which the physical address of the instruction belongs.

[0211] For example, taking the instruction physical address as instruction physical address a, the virtual address corresponding to instruction physical address a is 0x00001125, and the instruction address range of function A is [0x00001100 ~ 0x00001200]. It can be seen that the virtual address 0x00001125 is within the instruction address range [0x00001100 ~ 0x00001200], indicating that the instruction executed by instruction physical address a belongs to function A, that is, the function to which instruction physical address a belongs is function A.

[0212] Since the instructions executed by the instruction physical address (i.e. the instructions actually executed by the processor) mainly come from two sources, one is the machine code generated by AOT compilation in the application's odex file, and the other is the original dalvik bytecode in the application's dex file. Therefore, determining the function to which the instruction physical address belongs means querying the function to which the instruction physical address belongs from the application's odex file or dex file.

[0213] In addition, in the Android operating system, when the processor executes the instructions of the application, it first queries the odex file of the application. If the processor finds the machine code corresponding to the instruction to be executed in the odex file of the application, the processor will preferentially execute the machine code compiled by AOT. If the processor does not find the machine code corresponding to the instruction to be executed in the odex file of the application, the processor interprets and executes the original dalvik bytecode corresponding to the instruction to be executed in the dex file of the application.

[0214] Based on this, in some examples, taking application 1 as an example, based on the virtual address corresponding to the instruction physical address, the process of determining the function to which the instruction physical address belongs is as follows: the data parsing unit obtains the odex file 1 and dex file 1 of application 1 based on the application information of application 1 carried in the parsed instruction. It is determined whether the virtual address corresponding to the instruction physical address is within the instruction address range of a function in odex file 1. If the virtual address corresponding to the instruction physical address is within the instruction address range of a function in odex file 1, the function is identified as the function to which the instruction physical address belongs. Otherwise, the function to which the instruction physical address belongs is queried from dex file 1.

[0215] In addition, when obtaining the dex file 1 of the application 1, the APK file 1 of the application 1 is obtained, and the dex file 1 is read from the APK file 1.

[0216] Optionally, after obtaining the dex file 1 of the application 1, the data parsing unit can obtain the file identifier of the dex file 1, and write the file identifier of the dex file 1 into the profile file 1. The file identifier of the dex file is used to indicate the location of the bytecode executed by the instruction physical address. In this way, in the AOT compilation stage, the compilation module can read the dalvik bytecode to be compiled based on the file identifier of the dex file to compile the read dalvik bytecode.

[0217] It should be noted that, in the embodiment of the present application, the odex file of the application mentioned above refers to the odex file generated when the electronic device last performed AOT compilation on the application. For example, when the electronic device meets the AOT compilation conditions, the AOT compilation task is executed to compile the functions in the application (such as hotspot functions) to generate the odex file of the application. When the electronic device meets the AOT compilation conditions next time, the AOT compilation task is executed again to recompile the hotspot functions in the application and generate a new odex file, and the new odex file overwrites the odex file generated last time. It should be noted that the hotspot functions focused on by each AOT compilation can be the same or different.

[0218] S607, the data parsing unit associates the execution times of each instruction physical address with the function to which it belongs and stores them in profile file 1.

[0219] That is, after determining the function to which each instruction physical address belongs, the number of executions of the instruction physical addresses belonging to the same function can be associated with the function to which it belongs.

[0220] For example, continuing to take instruction physical address a and instruction physical address b as an example, if the functions to which instruction physical address a and instruction physical address b belong are both function A, then the number of executions of instruction physical address a (such as 100 times) and the number of executions of instruction physical address a (900 times) are both associated with function A, that is, the data recorded in the profile file can be expressed as:

[0221] [Function A-[0x00001125-100 times]-[0x00001188-900 times]].

[0222] That is to say, profile file 1 may include the sampled instruction physical address, the number of executions of the instruction physical address, and the function to which the instruction physical address belongs. Profile file 1 may also include the file identifier of the dex file to which the bytecode executed by the instruction physical address belongs (referred to as the file identifier of the dex file corresponding to the instruction physical address). Optionally, in the profile file, the instruction physical address can be represented by dex pc, the number of executions of the instruction physical address can be represented by dex count, and the file identifier of the dex file can be represented by dex code.

[0223] S608, the data parsing unit determines whether to traverse each application in the electronic device. If it is determined to traverse each application in the electronic device, the parsing process ends. Otherwise, the next application is taken as application 1 and the process returns to S604, that is, the process of parsing the hardware sampling information of the next application.

[0224] It should be noted that the process of parsing the hardware sampling information of the next application may be specifically referred to in S604 to S607 above, which will not be described in detail here.

[0225] In some examples, it can be seen from the description of the software structure of the aforementioned electronic device that the parsing module can also include a parsing reporting unit. During the parsing process of the hardware sampling information, the parsing reporting unit can obtain the current load information of the electronic device and send the current load information of the electronic device to the parsing scheduling unit. Furthermore, the parsing scheduling unit can control the parsing process based on the current load information of the electronic device. In this way, during the parsing process, the parsing process can be controlled in real time based on the current load information of the electronic device, thereby reducing the occupation of resources by the parsing process when the entire load of the electronic device is high, and avoiding affecting the normal operation of the electronic device.

[0226] 3. AOT compilation phase

[0227] As can be seen from the description of the sampling stage and the parsing stage, the profile file can include the function execution count of each function in the application. The profile file can also include the execution count of the instruction physical address executed during the application running process and the function to which the instruction physical address belongs. Therefore, in the AOT compilation stage, the application is AOT compiled based on the execution count of each instruction physical address, the function to which each instruction physical address belongs, and the function execution count of each function recorded in the profile file of the application.

[0228] like Figure 7 As shown, the AOT compilation process can include the following steps:

[0229] S701, the task scheduler determines whether the electronic device meets the AOT compilation conditions. If the electronic device meets the AOT compilation conditions, S702 is executed. Otherwise, it continues to determine whether the electronic device meets the AOT compilation conditions.

[0230] The AOT compilation condition is used to limit the timing of AOT compilation of the electronic device. In some examples, the AOT compilation condition may be related to the operation information of the electronic device. Among them, the operation information may include CPU usage, memory occupancy, battery status and battery power. In a specific embodiment, the AOT compilation condition may be: the CPU usage is less than the second preset CPU usage, and the memory occupancy is less than the second preset memory occupancy, and the battery status is a charging state, and the battery power is greater than a preset power threshold.

[0231] Specifically, the task scheduler can obtain the current CPU usage rate, current memory occupancy rate, current battery status and current battery power of the electronic device; determine whether the current CPU usage rate is less than a second preset CPU usage rate, whether the current memory occupancy rate is less than the second preset memory occupancy rate, whether the current battery status is a charging status, and whether the current battery power is greater than a preset power threshold; if the current CPU usage rate is less than the second preset CPU usage rate, and the current memory occupancy rate is less than the second preset memory occupancy rate, and the current battery status is a charging status, and the current battery power is greater than the preset power threshold, then it is determined that the electronic device meets the AOT compilation conditions; otherwise, it is determined that the electronic device does not meet the AOT compilation conditions.

[0232] S702: The task scheduler sends a compilation task scheduling message to the compilation scheduling module, wherein the compilation task scheduling message is used to indicate that the electronic device meets the AOT compilation condition.

[0233] S703: After receiving the compilation task scheduling message, the compilation scheduling module starts the AOT compilation task.

[0234] Starting the AOT compilation task can be understood as starting to perform AOT compilation on each application in the electronic device. For ease of description, the application in the electronic device is taken as application 1 as an example to schematically illustrate the AOT compilation process of the application.

[0235] S704: The compilation scheduling module sends a compilation instruction 1 to the compilation module, where the compilation instruction 1 carries application information of the application 1. The compilation instruction 1 is used to instruct to perform AOT compilation on the application 1.

[0236] S705 , after receiving the compilation instruction 1 , the compilation module performs AOT compilation on the application 1 .

[0237] S706, after performing AOT compilation on application 1, the compilation module sends a compilation completion message to the compilation scheduling module, wherein the compilation completion message is used to indicate that the AOT compilation process of application 1 is finished.

[0238] S707, the compilation scheduling module determines whether to traverse all applications in the electronic device. If it is determined to traverse all applications in the electronic device, the AOT compilation task is terminated, otherwise S708 is executed.

[0239] S708, the compilation scheduling module sends a compilation instruction 2 to the pre-compilation unit, and the compilation instruction 2 carries the application information of the next application. The compilation instruction 2 is used to instruct to perform AOT compilation on the next application.

[0240] After receiving the compile instruction 2, the compile module takes the next application as the application 1 and returns to S705, ie, starts AOT compiling the next application, until the compile module completes the AOT compilation of each application in the electronic device, ie, the compilation task is completed.

[0241] Next, we will take Application 1 as an example to explain the detailed process of AOT compilation. Figure 8 As shown, the AOT compilation process of application 1 may include the following steps:

[0242] S801, the pre-compilation unit obtains profile file 1 and dex file 1 of application 1.

[0243] In the embodiment of the present application, the precompilation unit can be used as the starting point of the AOT compilation of the application, that is, in the aforementioned S704, after starting the AOT compilation task, the compilation scheduling module sends a compilation instruction 1 to the precompilation unit in the compilation module to instruct the precompilation unit to start AOT compilation of application 1. Therefore, after receiving the compilation instruction 1, the precompilation unit obtains the profile file 1 of application 1 according to the application information of application 1 carried in the compilation instruction 1. And, the precompilation unit obtains the APK file 1 of application 1 according to the application information of application 1, and reads the dex file 1 from the APK file 1.

[0244] In some examples, the precompilation unit is also used to prepare the AOT compilation environment and parse compilation parameters.

[0245] S802, the pre-compilation unit sends a pre-compilation completion message to the front-end processing unit.

[0246] S803, after receiving the pre-compilation completion message, the front-end processing unit reads the bytecode corresponding to each function of the application 1 from the dex file 1, and performs front-end processing on the bytecode corresponding to each function.

[0247] Exemplarily, the front-end processing may include syntax analysis and semantic analysis. Specifically, the bytecode corresponding to each function in application 1 is subjected to syntax analysis to determine whether the bytecode corresponding to each function conforms to the syntax rules. If the bytecode corresponding to the function conforms to the syntax rules, the bytecode corresponding to the function is subjected to semantic analysis to determine whether the semantics of the bytecode corresponding to the function is correct. When AOT compilation is performed on each function in the application, front-end processing is performed on each function first, which can improve the accuracy of the machine code generated by AOT compilation.

[0248] Optionally, the front-end processing unit may perform front-end processing on the bytecodes corresponding to each hotspot function in application 1. The hotspot function is a function to be AOT compiled in application 1, that is, a function whose number of interpreted executions in application 1 reaches a threshold number of times.

[0249] In some examples, hot functions can be recorded in the profile file 1 of application 1 in the form of a hot function list. Specifically, the hot function list can include index information of multiple hot functions. In this regard, before front-end processing is performed on the bytecodes corresponding to each function, the front-end processing unit reads the hot function list in the profile file 1, that is, reads the index information of each hot function of application 1. In this way, the front-end processing unit can read the bytecodes corresponding to each hot function of application 1 from the dex file 1 according to the index information of each hot function, and perform front-end processing on the read bytecodes.

[0250] It should be noted that the hot function list may include some functions in the application, or may include all functions in the application. In the embodiment of the present application, the hot function is not specifically limited.

[0251] S804, the front-end processing unit sends the bytecode corresponding to each function of application 1 to the intermediate expression unit.

[0252] Optionally, the front-end processing unit may send the bytecodes corresponding to each hotspot function of application 1 to the intermediate expression unit.

[0253] S805, the intermediate expression unit converts the bytecode corresponding to each function of application 1 into an intermediate form.

[0254] Exemplarily, the intermediate form may include, for example, a control flow graph (CFG), a data flow graph (DFG), and an abstract syntax tree (AST).

[0255] Optionally, the intermediate expression unit may also convert the bytecode corresponding to each hotspot function of application 1 into an intermediate form.

[0256] S806: The intermediate expression unit sends the converted bytecodes corresponding to each function to the optimizer.

[0257] Optionally, the intermediate expression unit may send the converted bytecodes corresponding to each hotspot function to the optimizer.

[0258] S807: The intermediate expression unit sends a conversion completion message to the initialization unit.

[0259] It should be noted that the above S806 and S807 can be Figure 8 The execution sequence shown in the embodiment shown in the figure may also be executed in other sequences, or S806 and S807 may be executed simultaneously. The embodiment of the present application does not impose any limitation on the execution sequence of the above S806 and S807.

[0260] S808, after receiving the conversion completion message, the initialization unit reads the execution times and the functions to which the physical addresses of multiple instructions belong, as well as the function execution times of each function in application 1 from profile file 1.

[0261] Optionally, the initialization unit reads the execution times and the functions to which the physical addresses of multiple instructions belong, as well as the function execution times of each hotspot function in application 1 from profile file 1.

[0262] S809, the initialization unit determines the compilation information corresponding to each function in application 1 according to the execution times and the functions to which each of the plurality of instruction physical addresses belongs, and the function execution times of each function in application 1.

[0263] Among them, the compilation information may include at least one of the heat level, branch jump information and number of loops. The heat level is used to indicate the frequency of function calls. The branch jump information is used to indicate the jump probability of each branch corresponding to the branch instruction in the function. It can be understood that the function executes branches through branch instructions, and one branch instruction can correspond to at least two branches. Therefore, one branch instruction can correspond to a set of branch jump information. The number of loops information is used to indicate the number of loops in the internal loop body of the function. Among them, the process of the initialization unit determining the compilation information corresponding to the function can be specifically referred to the description of Section 3.1 below.

[0264] Optionally, the initialization unit may also determine the compilation information corresponding to each hotspot function in application 1 according to the execution counts and the functions to which each of the multiple instruction physical addresses belongs, and the function execution counts of each function in application 1.

[0265] S810 , the initialization unit writes the compilation information of each function into profile file 1 of application 1 .

[0266] Optionally, the initialization unit may also write the compilation information of each hotspot function into the profile file 1 of the application 1.

[0267] S811, the initialization unit sends an initialization completion message to the optimizer.

[0268] S812, after receiving the initialization completion message, the optimizer reads the compilation information corresponding to each function of application 1 from profile file 1.

[0269] Optionally, the optimizer may read compilation information corresponding to each hotspot function of application 1 from profile file 1 .

[0270] S813, the optimizer optimizes the bytecode corresponding to each function in the application 1 according to the compilation information to obtain the optimized bytecode corresponding to each function.

[0271] Specifically, based on the branch jump information in the compilation information, each function is optimized for inlining. And, based on the number of loops in the compilation information, each function is optimized for loop unrolling. It should be noted that the bytecode corresponding to each function here refers to the converted bytecode sent by the intermediate expression unit to the optimizer (S806). The process of the optimizer optimizing the bytecode corresponding to the function can be specifically referred to in the description of Section 3.2 below.

[0272] In some examples, the optimizer can also perform other loop optimizations on individual functions, such as loop fusion optimization and loop splitting optimization.

[0273] In some examples, after optimizing the loop of a function, the optimizer can also simplify the instructions of the function, which can reduce the amount of data of the instructions in the function and reduce the running overhead. In addition, the optimizer can also eliminate dead code in the function to remove the code that will not be executed in the function and reduce the size of the generated machine code.

[0274] Optionally, the optimizer may optimize the bytecodes corresponding to each hotspot function in application 1 according to the compilation information.

[0275] S814, the optimizer sends the optimized bytecode corresponding to each function to the instruction scheduling unit.

[0276] Optionally, the optimizer may also send optimized bytecodes corresponding to each hotspot function to the code generator.

[0277] S815, the instruction scheduling unit performs instruction scheduling processing on the optimized bytecode corresponding to each function.

[0278] Since a function is composed of multiple basic blocks, and a basic block includes multiple consecutive instructions, the instruction scheduling unit sorts the instructions in each basic block in the function, that is, sorts the optimized bytecodes corresponding to each instruction in the basic block.

[0279] Optionally, the instruction scheduling unit may also perform instruction scheduling processing on the optimized bytecode corresponding to each hotspot function.

[0280] S816, the instruction scheduling unit sends an instruction scheduling completion message to the basic block reordering unit.

[0281] S817, the basic block reordering unit reads the branch jump information of each function from the profile file 1, and reorders the basic blocks of each function based on the branch jump information.

[0282] Specifically, the basic block reordering unit obtains the order of basic blocks in each function and adjusts the order of basic blocks based on branch jump information. The process of reordering basic blocks for a function can be specifically described in section 3.3 below.

[0283] Optionally, the basic block reordering unit may also reorder the basic blocks of each hotspot function based on the branch jump information.

[0284] It should be noted that the above instruction scheduling (S815) and basic block reordering (S817) can be performed according to Figure 8 The execution sequence shown in the illustrated embodiment may also be executed in other sequences, such as first reordering the basic blocks and then scheduling the instructions. The embodiment of the present application does not impose any limitation on the execution sequence of the above instruction scheduling and basic block reordering.

[0285] S818: The basic block reordering unit sends a basic block reordering completion message to the register allocation unit.

[0286] S819: The register allocation unit allocates register addresses to each function.

[0287] Optionally, the register allocation unit may also allocate register addresses to each hotspot function.

[0288] S820, the register allocation unit sends an address allocation completion message to the code generator.

[0289] S821, after receiving the address allocation completion message, the code generator converts the optimized bytecode corresponding to each function in application 1 into machine code.

[0290] Optionally, the code generator may also convert the optimized bytecode corresponding to each hotspot function in application 1 into machine code.

[0291] S822, the code generator sends the machine code corresponding to each function to the function layout unit.

[0292] S823 , the function layout unit reads the heat level of each function in application 1 from profile file 1 , and optimizes the function layout of the functions in application 1 based on the heat level to obtain odex file 1 of application 1 .

[0293] Specifically, the function layout optimization unit sorts the functions in application 1 in descending order of heat level based on the heat level of each function, that is, sorts the machine codes corresponding to the functions in application 1 to obtain odex file 1 of application 1. In this way, when the electronic device runs application 1 again, the processor can directly execute the machine code generated by AOT compilation in odex file 1, which can improve the running efficiency of the machine code and the running performance of application 1.

[0294] The function layout unit optimizes the function layout of the functions in the application. For details, please refer to the description of Section 3.4 below.

[0295] Optionally, the function layout unit may also optimize the function layout of hot functions in application 1 based on the heat level.

[0296] The above part is a detailed description of the AOT compilation process of the application using application 1 as an example. The AOT compilation process of other applications in the electronic device can also be specifically referred to in the above S801 to S823, which will not be repeated here.

[0297] The above is a schematic description of the overall process of the AOT compilation phase. The following schematically describes the process of determining the compilation information corresponding to the function (S809), the process of optimizing the bytecode corresponding to the function (S813), the process of basic block rearrangement (S817), and the process of function layout optimization (S823).

[0298] 3.1. The process of determining the compilation information corresponding to the function

[0299] 3.11. Heat Level

[0300] The heat level is determined based on the number of function executions of a function. The more times a function is executed, the higher the heat level of the function. Conversely, the fewer times a function is executed, the lower the heat level of the function. For example, the heat levels can be divided into the coldest level, the second coldest level, the medium level, the second hottest level, and the hottest level from low to high.

[0301] In some examples, the initialization unit compares the function execution times of the function with a plurality of preset threshold intervals, and determines the hotspot level of the function based on the comparison result. Specifically, taking function 1 in application 1 as an example, S809 may include: determining the threshold interval to which the execution times of function 1 belong; determining the hotspot level corresponding to the threshold interval to which the execution times of function 1 belong as the hotspot level of function 1. It should be noted that the preset threshold interval can be set according to actual needs, and in the embodiment of the present application, the specific numerical value corresponding to the preset threshold interval is not limited.

[0302] Optionally, the embodiment of the present application can also determine the heat level of each hot function in the application. The heat level determination process of the hot function can be specifically referred to the heat level determination process of the function, which will not be repeated here.

[0303] 3.12 Branch jump information

[0304] The function may include a branch instruction, and one branch instruction corresponds to at least two branches. The branch jump information may include the jump probability of at least two branches. The jump probability of a branch may reflect the possibility of the corresponding branch being executed.

[0305] Combine the following Fig. 9 , Continuing to take function 1 in application 1 as an example, the process of determining the jump probability of a branch is schematically explained.

[0306] like Fig. 9 As shown, S809 may include the following steps:

[0307] S901, the initialization unit determines the instruction physical address whose function matches function 1 as the instruction physical address corresponding to function 1 according to the function to which each instruction physical address belongs.

[0308] From the above descriptions of the sampling stage and the parsing stage, it can be seen that the instruction physical address and its corresponding execution times are stored in association, and the execution times of the instruction physical address and the function to which the instruction physical address belongs are stored in association. Therefore, after reading the functions to which each instruction physical address belongs from profile file 1, the initialization unit determines whether there is a function matching function 1 in the functions to which the instruction physical address belongs. If there is a function matching function 1, the instruction physical address corresponding to the function is determined as the instruction physical address corresponding to function 1.

[0309] For example, taking the data recorded in profile file 1 as [function A-[0x00001125-100 times]-[0x00001188-900 times]], the initialization unit can determine that the instruction physical addresses corresponding to function A include instruction physical address a (0x00001125) and instruction physical address b (0x00001188).

[0310] S902, the initialization unit determines the instruction physical address corresponding to branch 1 from the instruction physical address corresponding to function 1. Branch 1 is any branch in the instruction physical address corresponding to function 1.

[0311] In the embodiment of the present application, function 1 may include a branch instruction, and one branch instruction includes at least two branches. The initialization unit determines the instruction physical address corresponding to each of the at least two branches from the instruction physical address corresponding to function 1.

[0312] like Fig.10 As shown, the last instruction of basic block 1 is a branch instruction (i.e., an if statement), and the if statement corresponds to two branches, namely, branch a and branch b. The physical address of the instruction corresponding to branch a is the first instruction address of basic block 2 (0x00001125), and the physical address of the instruction corresponding to branch b is the first instruction address of basic block 3 (0x00001188).

[0313] S903, the initialization unit determines the execution count of the instruction physical address corresponding to branch 1.

[0314] That is, the initialization unit determines the execution number of the instruction physical address corresponding to the branch according to the execution number of each instruction physical address.

[0315] S904, the initialization unit determines the function execution times of function 1 according to the function execution times of each function.

[0316] From the relevant descriptions of the aforementioned sampling phase and parsing phase, it can be seen that functions and their corresponding function execution times are stored in association. Therefore, based on the association between functions and function execution times, the function execution times of function 1 can be obtained from the function execution times of each function.

[0317] For example, taking the data recorded in profile file 1 as function A-1000 times as an example, it can be identified that the number of executions corresponding to function A is 1000 times.

[0318] S905 , the initialization unit determines the jump probability of branch 1 according to the function execution count of function 1 and the execution count of the instruction physical address corresponding to branch 1 .

[0319] Exemplarily, the ratio of the execution times of the instruction physical address corresponding to branch 1 to the function execution times of function 1 is used as the jump probability of the branch.

[0320] For example, let's continue to take branch 1 as the branch of the if statement in function A. Fig.10 As shown in the figure, based on the number of function executions of function A (1000 times) and the number of executions of the first instruction address (0x00001125) of basic block 2 (100 times), the jump probability of branch a is calculated to be 10%. Similarly, based on the number of function executions of function A (1000 times) and the number of executions of the first instruction address (0x00001188) of basic block 3 (900 times), the jump probability of branch b is calculated to be 90%.

[0321] It should be understood that after determining the jump probability of each branch of the branch instruction in function 1, the initialization unit can write the jump probability of each branch of the branch instruction in function 1 into profile file 1, so that the subsequent steps read the jump probability of each branch of the branch instruction in function 1 from profile file 1.

[0322] The above is a schematic illustration of the process of determining the branch jump probability using branch 1 as an example. The process of determining the jump probability of other branches can be specifically referred to the process of determining the branch jump probability of branch 1 above, which will not be described in detail here.

[0323] Optionally, the embodiment of the present application can also determine the branch jump information of each hot function in the application. The determination process of the branch jump information of the hot function can be specifically referred to the determination process of the branch jump information of the above function 1, which will not be repeated here.

[0324] 3.13. Cycle times information

[0325] Combine the following Fig.11 Continuing with the example of function 1 in application 1, the process of determining the number of loops of the loop body is schematically described. Fig.11 As shown, S809 may include the following steps:

[0326] S1101, the initialization unit determines the instruction physical address whose function matches function 1 as the instruction physical address corresponding to function 1 according to the function to which each instruction physical address belongs.

[0327] Specifically, for the specific implementation of S1101, please refer to the relevant description of S901 mentioned above, which will not be repeated here.

[0328] S1102, the initialization unit determines instruction physical address 1 and instruction physical address 2 from the instruction physical addresses corresponding to function 1, and obtains the execution count of instruction physical address 1 and the execution count of instruction physical address 2. Instruction physical address 1 is the last instruction physical address before entering loop body 1 in function 1, instruction physical address 2 is the first instruction physical address in loop body 1, and loop body 1 is any loop body in function 1.

[0329] S1103, the initialization unit determines the number of loops of loop body 1 according to the number of executions of instruction physical address 1 and the number of executions of instruction physical address 2.

[0330] Exemplarily, the ratio of the execution times of instruction physical address 2 to the execution times of instruction physical address 1 is used as the loop times of loop body 1. It should be noted that the loop times obtained here are estimated values ​​calculated based on the execution times of instruction physical address 1 and the execution times of instruction physical address 2.

[0331] For example, taking loop body 1 in function A as an example, Fig.12 As shown in the figure, the physical address of the last instruction before entering loop body 1 (i.e., instruction physical address 1) is the last instruction address of basic block 1 (0x00001125), and its execution count is 100 times. The physical address of the first instruction in loop body 1 (i.e., instruction physical address 2) is the first instruction address of basic block 2 (0x00001188), and its execution count is 900 times. Therefore, by calculation, it can be obtained that the execution count of loop body 1 is 9 times.

[0332] It should be understood that after determining the number of loops of loop body 1 in function 1, the initialization unit can write the number of loops of loop body 1 in function 1 into profile file 1 so that the number of loops of loop body 1 in function 1 can be read from profile file 1 in subsequent steps.

[0333] The above is a schematic description of the process of determining the number of cycles using loop body 1 as an example. The process of determining the number of cycles of other loop bodies can be specifically referred to the process of determining the number of cycles of loop body 1 above, which will not be repeated here.

[0334] Optionally, the embodiment of the present application can also determine the number of loops in the loop body of each hotspot function in the application. The process of determining the number of loops in the hotspot function can be specifically referred to the process of determining the number of loops in the loop body 1 in the above function 1, which will not be repeated here.

[0335] According to the above process, the heat level of each function in the application, the branch jump information of the branch instructions in each function and the number of loops in the loop body in each function can be obtained, that is, the compilation information of each function to be AOT compiled can be obtained.

[0336] The above schematically illustrates the process of determining the compilation information of a function. The following describes in detail the process of optimizing the bytecode of the function based on the compilation information of the function.

[0337] 3.2 Optimization Process

[0338] In the embodiment of the present application, the process of optimizing the bytecode of a function may mainly include a function inline optimization process and a loop unrolling optimization process.

[0339] 3.21 Function inline optimization process

[0340] Combine the following Fig.13 , continue to use function 1 in application 1 as an example to schematically illustrate the process of function inline optimization. Fig.13 As shown, S813 may include the following steps:

[0341] S1301, the optimizer reads the heat level of function 1 from profile file 1.

[0342] S1302: The optimizer determines a function inline strategy corresponding to function 1 according to the heat level of function 1, and performs function inline optimization on function 1 according to the function inline strategy corresponding to function 1.

[0343] The function inline policy is used to indicate the size of the code volume threshold 1 corresponding to the fixed inline function and the code volume threshold 2 corresponding to the inlined function. Among them, the code volume threshold 1 is used to limit the maximum code volume allowed for the fixed inline function, that is, when the code volume of the function is less than or equal to the code volume threshold 1, the function can be used as a fixed inline function to perform the function inline operation. The code volume threshold 2 is used to limit the maximum code volume allowed for the inlined function, that is, when the code volume of the function is less than or equal to the code volume threshold 2, the function can be used as an inlined function and embedded in the corresponding fixed inline function. In other words, if the code volume threshold 1 is larger, more functions in the application can be used as fixed inline functions. On the contrary, if the code volume threshold 1 is smaller, fewer functions in the application can be used as fixed inline functions. Similarly, if the code volume threshold 2 is larger, more functions in the application can be used as inlined functions. On the contrary, if the code volume threshold 2 is smaller, fewer functions in the application can be used as inlined functions.

[0344] Based on this, in the embodiment of the present application, based on the heat level of the function, the code volume threshold 1 and / or the code volume threshold 2 are set, that is, the function inline strategy is set for the function 1. Optionally, the value of the code volume threshold 1 is positively correlated with the heat level of the function, and the value of the code volume threshold 2 is positively correlated with the heat level of the function.

[0345] Exemplarily, for a function with a higher heat level, a larger code volume threshold 1 and code volume threshold 2 are set, that is, a more aggressive function inline strategy is set. On the contrary, for a function with a lower heat level, a smaller code volume threshold 1 and code volume threshold 2 can be set, that is, a more conservative function inline strategy is set.

[0346] For example, the heat levels include the coldest level, the second coldest level, the medium level, the second hottest level and the hottest level. Fig.14 As shown, for the medium-level function, the code volume threshold 1 is the preset value 1, and the code volume threshold 2 is the preset value 2. The preset value 1 and the preset value 2 are used as the benchmark to set the code volume threshold 1 and the code volume threshold 2 of other heat levels. For functions with a heat level higher than the medium level, the code volume threshold 1 is set to be greater than the preset value 1, and the code volume threshold 2 is set to be greater than the preset value 2. The higher the heat level, the larger the code volume threshold 1 and the larger the code volume threshold 2. For functions with a heat level lower than the medium level, the code volume threshold 1 is set to be less than the preset value 1, and the code volume threshold 2 is set to be less than the preset value 2. The lower the heat level, the smaller the code volume threshold 1 and the smaller the code volume threshold 2.

[0347] In the embodiment of the present application, since the calling frequency of functions with higher heat levels is higher, a larger code amount threshold 1 and code amount threshold 2 are set for functions with higher heat levels. In this way, during AOT compilation, more functions with higher heat levels will be optimized for function inlining, so that when executing the target code generated based on the optimized function, the called function can be directly run, which can reduce the number of function calls to a greater extent and improve the response speed of the application. Furthermore, since the calling frequency of functions with lower heat levels is lower, a smaller code amount threshold 1 and code amount threshold 2 are set for functions with lower heat levels. In this way, during AOT compilation, functions with lower heat levels are less likely to be optimized for function inlining, which can effectively control the increase in the code amount of the target code and save memory space of the electronic device.

[0348] Optionally, the embodiment of the present application can also perform function inline optimization on each hotspot function in the application. The process of performing function inline optimization on the hotspot function can be specifically referred to the process of performing function inline optimization on the above function 1, which will not be repeated here.

[0349] In some embodiments, profile file 1 may also include virtual function information during the operation of application 1. When a function calls another function, it is necessary to know the location and class of the called function. In some scenarios, when a function needs to call another function, the location and class of the called function are not known in advance. Therefore, the called function with such unknown location and class is called a virtual function. In this regard, during the operation of application 1, the virtual function information corresponding to a function may be recorded. The virtual function information may include the virtual function called by the function and the calling location corresponding to the virtual function. In this way, when performing function inline optimization on the function of application 1, the function may be inline optimized based on the virtual function information corresponding to the function collected during the last operation of application 1.

[0350] Specifically, when performing function inline optimization, the heat level of function 1 is read. If the heat level of function 1 is higher than or equal to the preset heat level, the virtual function information of function 1 is obtained, wherein the virtual function information may include the virtual function called by function 1 and the calling position corresponding to the virtual function. The calling position of the virtual function in function 1 is embedded with the corresponding virtual function. In this way, the function inline ratio of functions with higher heat levels can be increased.

[0351] The above is a schematic description of the process of function inline optimization using function 1 as an example. The process of function inline optimization of other functions can be specifically referred to the process of function inline optimization of function 1 above, which will not be repeated here.

[0352] 3.22 Loop unrolling optimization process

[0353] Combine the following Fig.15 , continue to use function 1 in application 1 as an example to schematically illustrate the process of loop unrolling optimization. Fig.15 As shown, S815 may include the following steps:

[0354] S1501, the optimizer reads the number of loops of loop body 1 in function 1 from profile file 1.

[0355] S1502, the optimizer determines the loop unrolling multiple of loop body 1 according to the number of loops of loop body 1 in function 1 and the number of instructions inside loop body 1.

[0356] The number of instructions in a loop body refers to the total number of instructions to be executed in the loop body at each iteration of the loop body. Fig.12 Taking loop body 1 in function A shown as an example, the number of instructions inside loop body 1 is the number of instructions included in basic block 3.

[0357] The loop unrolling multiple refers to the number of times the instructions in the loop body are repeatedly executed each time the loop body is entered during the function execution. Fig.12 Taking loop body 1 in function A as an example, the loop expansion multiple refers to the number of times basic block 3 is repeatedly executed. Exemplarily, the loop expansion multiple is generally 2 to the power of N, such as the loop expansion multiple is 2 times, 4 times, 8 times, etc.

[0358] It is understandable that during the running process of the application, most of the running time is spent on executing the loop body of the function. Therefore, in order to reduce the number of loop iterations and improve the running performance of the application, the loop body can be optimized by loop unrolling according to the loop unrolling multiple. For example, taking the loop number of the loop body as 80 times and the loop unrolling multiple as 8 times as an example, the function code is optimized by loop unrolling. Each time the loop body is entered, the number of times the instructions in the loop body are repeatedly executed increases to 8, so that the number of loop iterations of the loop body is reduced from 80 times to 10 times.

[0359] Optionally, the loop unrolling factor is negatively correlated with the number of instructions within the loop body, and the loop unrolling factor is positively correlated with the number of loops of the loop body.

[0360] Exemplarily, for loop bodies with more loops and fewer instructions inside, a larger loop expansion multiple is set, that is, a more aggressive loop expansion strategy is set. For example, for functions with more than 8 loops (such as 100 times) and fewer instructions inside the loop body, the loop expansion multiple is set to 16 times or 32 times. For loop bodies with fewer loops and more instructions inside, a smaller loop expansion multiple is set, that is, a more conservative loop expansion strategy is set. For example, for functions with less than 8 loops (such as 100 times) and more instructions inside the loop body, the loop expansion multiple is set to 2 times. Of course, for loop bodies with fewer loops and more instructions inside, loop expansion may not be performed.

[0361] In a more specific example, Fig.16 As shown, for a function whose number of loops is within a preset number range and whose number of instructions in the loop body is within a preset number range, the loop expansion multiple is set to a preset multiple, such as 8 times. Based on the preset multiple, for a function whose number of loops is large (such as the number of loops is greater than the upper limit of the preset number range) and whose instructions in the loop body are small (such as the number of instructions in the loop body is smaller than the lower limit of the preset number range), the loop expansion multiple is set to be larger than the preset multiple. It should be understood that the more loops there are and the fewer instructions there are in the loop body, the larger the loop expansion multiple. For a function whose number of loops is small (such as the number of loops is smaller than the lower limit of the preset number range) and whose instructions in the loop body are large (such as the number of instructions in the loop body is larger than the upper limit of the preset number range), the loop expansion multiple is set to be smaller than the preset multiple. It should be understood that the fewer loops there are and the more instructions there are in the loop body, the smaller the loop expansion multiple.

[0362] S1503, performing loop unrolling optimization on loop body 1 according to the loop unrolling multiple of loop body 1, and obtaining optimized bytecode corresponding to function 1.

[0363] In an embodiment of the present application, if the number of loops in the loop body of a function is large and the number of instructions inside the loop body is small, a larger loop expansion multiple is used to optimize the loop expansion of the function, so that when the machine code generated by the optimized function is executed, the loop control overhead can be reduced and the running performance of the application can be improved. However, if the number of loops in the loop body of a function is small and the number of instructions inside the loop body is large, a smaller loop expansion multiple is used to optimize the loop expansion of the function, which can avoid negative benefits due to loop expansion. Of course, for loop bodies with fewer loops and more internal instructions, loop expansion may not be performed.

[0364] The above is a schematic description of the loop unrolling optimization process using loop body 1 as an example. The loop unrolling optimization process of other loop bodies can be specifically referred to the loop unrolling optimization process of loop body 1 above, which will not be repeated here.

[0365] Optionally, the embodiment of the present application can also perform loop unrolling optimization on each hotspot function in the application. The process of loop unrolling optimization on the hotspot function can be specifically referred to the process of loop unrolling optimization on the above function 1, which will not be repeated here.

[0366] 3.3 Basic Block Rearrangement Process

[0367] A function consists of multiple basic blocks. The basic block reordering unit obtains the order of basic blocks in each function and adjusts the order of basic blocks in the function based on the branch jump information of the function.

[0368] In some examples, the process of basic block rearrangement is described by taking function 1 as an example. Fig.17 As shown, S817 may include:

[0369] S1701, the basic block reordering unit obtains the order of the basic blocks in function 1.

[0370] Exemplarily, the basic blocks in function 1 may be arranged in the execution order of the control flow.

[0371] S1702 , the basic block reordering unit obtains jump probabilities of at least two branches corresponding to branch instruction 1 in function 1 , where branch instruction 1 is any branch instruction in function 1 .

[0372] S1703 , the basic block reordering unit adjusts the order of the basic blocks in function 1 based on the jump probabilities of at least two branches, so that the basic block corresponding to the branch with the highest jump probability is located after the basic block corresponding to branch instruction 1 .

[0373] The basic block corresponding to the branch with the highest jump probability is located after the basic block corresponding to branch instruction 1, which can be understood as arranging the basic block corresponding to the branch with the highest jump probability next to the basic block corresponding to branch instruction 1.

[0374] For example, taking function 1 as function A, Fig.10 As shown, function A includes basic block 1, basic block 2 and basic block 3. The last instruction of basic block 1 in function A is a branch instruction (such as an if statement), and the if statement corresponds to two branches, namely branch a and branch b. Among them, the jump probability of branch a is 10%, and the jump probability of branch b is 90%.

[0375] like Fig.18As shown in (a) in the figure, if the basic blocks in the function are sorted according to the default rule, the first instruction address of basic block 2 (0x00001125) is generally arranged after basic block 1, that is, basic block 2 corresponding to branch a is arranged together with basic block 1 where the if statement is located. However, since the jump probability of branch a is less than that of branch b, this arrangement is likely to cause branch prediction failure, resulting in branch misses.

[0376] For this reason, Fig.18 As shown in (b), in the embodiment of the present application, the basic block reordering unit readjusts the order of each basic block of function A based on the jump probability of branch a (10%) and the jump probability of branch b (90%), so that the basic block 3 corresponding to branch b is arranged together with the basic block 1 where the if statement is located, and the basic block 3 corresponding to branch b is located after the basic block 1. In other words, the basic block corresponding to the branch with the highest jump probability is arranged together with the basic block corresponding to the branch instruction, which can improve the accuracy of branch prediction and reduce branch misses during function execution.

[0377] The above is a schematic description of the process of basic block rearrangement using function 1 as an example. The process of basic block rearrangement of other functions can be specifically referred to the process of basic block rearrangement of function 1 above, which will not be described in detail here.

[0378] Optionally, the embodiment of the present application can also perform basic block rearrangement on each hotspot function in the application. The process of performing basic block rearrangement on the hotspot function can be specifically referred to the above process, which will not be repeated here.

[0379] 3.4. Function layout optimization process

[0380] After the basic blocks in the function are rearranged, multiple functions in the application are rearranged according to the heat level of each function.

[0381] Exemplarily, S823 may include: the function layout unit arranges the multiple functions in the application in order of heat levels from high to low.

[0382] For example, taking application 1 as an example, Fig.19 As shown in (a) in the figure, multiple functions in application 1 are sorted according to the default rule, and the sorting results are: function 1, function 2, function 3, function 4, function 5, function 6, function 7 and function 8. The words "hot" and "cold" are marked after the function to indicate the heat level of each function. Fig.19From (a) in the figure, we can see that the heat levels of functions 1, 5, and 7 are high, while the heat levels of functions 2, 3, 4, 6, and 8 are low. In addition, the layouts of functions 1, 5, and 7 are relatively scattered, such as functions 5 and 7 are arranged at the back. In other words, for this method, since the heat level of the function is not considered, the layout of functions with high heat levels is relatively scattered, resulting in some functions with high heat levels being arranged at the back, which is prone to cache misses and affects the running performance of the application.

[0383] For this reason, Fig.19 As shown in (b), in the embodiment of the present application, multiple functions in application 1 are sorted based on the heat level of each function, and the sorting results are: function 1, function 5, function 7, function 2, function 3, function 4, function 6 and function 8.

[0384] In the embodiment of the present application, after the target code of each function in the application is generated, the target code of each function is sorted in order from high to low according to the heat level of the function, so that the functions of different heat levels can be separated, and the functions with higher heat levels are arranged in the front position. In this way, when the Android runtime starts the application next time, the functions with higher heat levels can be loaded into the cache first according to the order of each function in the application. In this way, when the processor executes the function with higher heat level, the corresponding instruction can be read directly from the cache without searching from the main memory, which can improve the cache hit rate and enhance the running performance of the application.

[0385] Optionally, the embodiment of the present application can also optimize the function layout of each hotspot function in the application. The process of optimizing the function layout of the hotspot function can be specifically referred to the above process, which will not be repeated here.

[0386] The above describes in detail an example of the compilation method provided by the embodiment of the present application. It is understandable that, in order to realize the above functions, the electronic device includes hardware and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in conjunction with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered to exceed the scope of the present application.

[0387] The embodiment of the present application can divide the functional modules of the electronic device according to the above method example. For example, each function can be divided into various functional modules, such as a detection unit, a processing unit, a display unit, etc., or two or more functions can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0388] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0389] The electronic device provided in this embodiment is used to execute the above-mentioned compilation method, and thus can achieve the same effect as the above-mentioned implementation method.

[0390] In the case of an integrated unit, the electronic device may further include a processing module, a storage module and a communication module. The processing module may be used to control and manage the actions of the electronic device. The storage module may be used to support the electronic device to execute stored program codes and data, etc. The communication module may be used to support the electronic device to communicate with other devices.

[0391] Among them, the processing module can be a processor or a controller. It can implement or execute various exemplary logic boxes, modules and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor (DSP) and a microprocessor, etc. The storage module can be a memory. The communication module can specifically be a device that interacts with other electronic devices, such as a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, etc.

[0392] In one embodiment, when the processing module is a processor and the storage module is a memory, the electronic device involved in this embodiment may be a Figure 3 Device of the structure shown.

[0393] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the processor executes the compilation method of any of the above embodiments.

[0394] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the compilation method in the above-mentioned embodiment.

[0395] In addition, an embodiment of the present application also provides a device, which may specifically be a chip, a component or a module, and the device may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the device is running, the processor may execute the computer execution instructions stored in the memory so that the chip executes the compilation method in the above-mentioned method embodiments.

[0396] Among them, the electronic device, computer-readable storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above and will not be repeated here.

[0397] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0398] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0399] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0400] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0401] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0402] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A compiling method, applied to electronic equipment, characterized in that: The method comprises: receiving a first operation of a user on a first application; Obtaining the number of executions of each instruction physical address executed by the first application in response to the first operation and the function to which each instruction physical address belongs; Obtaining the execution times of each function in the first application; Determine, according to the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function in the first application, the compilation information corresponding to each function in the first application, the compilation information including a heat level, a branch jump probability, and a loop count, wherein the heat level is used to indicate the frequency of function calls, the branch jump probability is used to indicate the jump probability of each branch corresponding to a branch instruction in the function, and the loop count is used to indicate the loop count of a loop body inside the function; According to the heat level of the first function, determine the function inline strategy corresponding to the first function, and perform function inline optimization on the first function according to the function inline strategy corresponding to the first function, wherein the function inline optimization strategy is used to indicate the size of the first threshold and the second threshold; according to the number of loops of a first loop body in the first function and the number of instructions in the first loop body, determine the loop expansion multiple corresponding to the first loop body, and perform loop expansion optimization on the first loop body based on the loop expansion multiple corresponding to the first loop body, wherein the first loop body is any loop body in the first function; according to the branch jump probability of each branch of the branch instruction in the first function, adjust the sorting of basic blocks in the first function; and according to the heat level of each function in the first application, perform function layout optimization on the functions in the first application; the first function is any function in the first application.

2. The method according to claim 1, characterized in that The first threshold is positively correlated with the heat level, the second threshold is positively correlated with the heat level, and the function inline optimization of the first function according to the function inline strategy corresponding to the first function includes: If the number of instructions of the first function is less than or equal to the first threshold, and the number of instructions of the second function is less than or equal to the second threshold, embedding the second function into the first function to obtain a third function, wherein the second function is a function called by the first function; According to the third function, a target code is generated.

3. The method according to claim 1, characterized in that The loop unrolling multiple is negatively correlated with the number of instructions in the loop body, and the loop unrolling multiple is positively correlated with the number of loops of the loop body.

4. The method according to claim 1, characterized in that: The adjusting the order of basic blocks in the first function according to the branch jump probability of each branch of the branch instruction in the first function includes: Obtaining the order of basic blocks in the first function; Determine the jump probabilities of at least two branches corresponding to a target branch instruction in the first function, where the target branch instruction is any branch instruction in the first function; Based on the jump probabilities of the at least two branches, adjusting the order of basic blocks in the first function so that the first basic block is located after the second basic block, to obtain a fifth function, wherein the first basic block is a basic block corresponding to a branch with the highest jump probability among the at least two branches, and the second basic block is a basic block corresponding to the target branch instruction; According to the fifth function, a target code is generated.

5. The method according to claim 1, characterized in that The step of optimizing the function layout of the functions in the first application according to the heat level of each function in the first application includes: Generate object codes for each function in the first application; The functions in the first application are sorted in descending order of heat levels to obtain an optimized compiled file, wherein the optimized compiled file includes target codes of each function in the first application.

6. The method according to claim 1, characterized in that Determining the compilation information corresponding to each function in the first application according to the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function in the first application includes: Determining a heat level of a first function according to the number of executions of the first function; the first function is any function in the first application; Determine the jump probability of each branch in the first function according to the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function; The number of loops of each loop body in the first function is determined according to the number of executions of each instruction physical address and the function to which each instruction physical address belongs.

7. The method according to claim 6, characterized in that The determining the heat level of the first function according to the number of executions of the first function includes: Determine a target threshold interval to which the number of executions of the first function belongs; The heat level corresponding to the target threshold interval is determined as the heat level of the first function.

8. The method according to claim 6, characterized in that Determining the jump probability of each branch in the first function according to the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function includes: According to the functions to which the instruction physical addresses belong, determining the instruction physical addresses whose functions match the first function as the instruction physical addresses corresponding to the first function; Determine an instruction physical address of a first branch, where the first branch is any branch in the instruction physical addresses corresponding to the first function; Determining the number of executions of the physical address of the instruction of the first branch; The jump probability of the first branch is determined according to the number of executions of the first function and the number of executions of the instruction physical address of the first branch.

9. The method according to claim 8, characterized in that Determining the number of loops of each loop body in the first function according to the number of executions of each instruction physical address and the function to which each instruction physical address belongs includes: Determine a first instruction physical address and a second instruction physical address in the instruction physical addresses corresponding to the first function, wherein the first instruction physical address is the last instruction physical address before entering a first loop body in the first function, the second instruction physical address is the first instruction physical address in the first loop body, and the first loop body is any loop body in the first function; Determining the number of executions of the first instruction physical address and the number of executions of the second instruction physical address; The number of loops of the first loop body is determined according to the number of executions of the first instruction physical address and the number of executions of the second instruction physical address.

10. The method according to claim 1, characterized in that Determining the compilation information corresponding to each function in the first application according to the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function in the first application includes: When the electronic device is in an idle state, the electronic device is in a charging state, and the battery power of the electronic device is greater than or equal to a preset power threshold, the compilation information corresponding to each function in the first application is determined according to the number of executions of each instruction physical address, the function to which each instruction physical address belongs, and the number of executions of each function in the first application.

11. The method according to any one of claims 1 to 10, characterized in that The obtaining of the execution count of each instruction physical address executed by the first application in response to the first operation and the function to which each instruction physical address belongs includes: In response to the first operation, obtaining the number of executions of each physical address of the instruction; Each of the instruction physical addresses is parsed respectively to determine the function to which each of the instruction physical addresses belongs.

12. The method according to claim 11, characterized in that The step of respectively parsing each of the instruction physical addresses to determine the function to which each of the instruction physical addresses belongs includes: Converting a third instruction physical address into a virtual address, wherein the third instruction physical address is any one of the instruction physical addresses; The function to which the physical address of the third instruction belongs is determined according to the virtual address.

13. The method according to claim 12, characterized in that Determining the function to which the physical address of the third instruction belongs according to the virtual address includes: Obtaining instruction address ranges corresponding to each function in the first application; Determine, from instruction address ranges corresponding to functions in the first application, an instruction address range to which the virtual address belongs; The function corresponding to the instruction address range to which the virtual address belongs is determined as the function to which the third instruction physical address belongs.

14. The method according to claim 11, characterized in that The step of respectively parsing each of the instruction physical addresses to determine the function to which each of the instruction physical addresses belongs includes: When the electronic device is in an idle state and in a charging state, each of the instruction physical addresses is parsed respectively to determine the function to which each of the instruction physical addresses belongs.

15. The method according to claim 14, characterized in that The step of obtaining the execution times of each physical address of the instruction in response to the first operation includes: In response to the first operation, determining an operation type of the first operation; Determining a sampling frequency and a sampling duration corresponding to the first operation according to an operation type of the first operation; Acquire, according to the sampling frequency, a physical address of an instruction executed by the first application in response to the first operation; The number of executions of each of the instruction physical addresses within a time period from the first operation to the sampling time is counted.

16. The method according to claim 15, characterized in that The operation types include operations of launching an application and / or operations acting on an application interface; the operations acting on an application interface include at least one of click operations on controls in the application interface, switching operations on the application interface, and switching operations on an application widget.

17. An electronic device, characterized in that: include: Processors, memory, and interfaces; The processor, the memory and the interface cooperate with each other so that the electronic device executes the method as claimed in any one of claims 1 to 16.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor is caused to perform the method according to any one of claims 1 to 16.

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