A combined control circuit for a heating table

Abstract

The present invention discloses a combined control circuit for a heating table, comprising a first operational amplifier, a second digital potentiometer, a third trigger, a second triode, a first resistor, a second resistor, a third resistor, a sixth resistor, a seventh resistor, a first capacitor, a first diode, a third diode, a seventh diode, a first switch, and a second switch; the in-phase end of the first operational amplifier, the third pin of the second digital potentiometer, one end of the third resistor and a Vrer end are connected, the inverting end of the first operational amplifier, one end of the first resistor, one end of the second resistor, one end of the first capacitor and a Vsen end are connected, the output end of the first operational amplifier is connected to the second pin of the second digital potentiometer, and the seventh pin of the second digital potentiometer is connected to the fifth pin of the third trigger.

Description

Technical Field

[0001] The invention relates to the technical field of intelligent control, and in particular to a combined control circuit for a heating table. Background Art

[0002] The design of the heating table fully considers the diverse needs of users and realizes the convenient lifting function. In addition to the traditional manual adjustment method, which requires users to rotate the lifting handle by themselves, although this method is a bit laborious and slow, the more modern and popular is the electric adjustment method, which uses an electric motor or pneumatic device for lifting and lowering. Users only need to touch the lifting button on the control panel of the electric heating table. However, the electric adjustment method has the problem of repeatedly pressing the button each time it is used, and the lifting height needs to be set manually, which increases the complexity of the operation to some extent. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a heating table combination control circuit, including a first operational amplifier U1, a second digital potentiometer U2, a third trigger U3, a second transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a first diode D1, a third diode D3, a seventh diode D7, a first switch SW1, and a second switch SW2;

[0004] The in-phase end of the first operational amplifier U1, the third pin of the second digital potentiometer U2, one end of the third resistor R3 and the Vref end are connected, the inverting end of the first operational amplifier U1, one end of the first resistor R1, one end of the second resistor R2, one end of the first capacitor C1 and the Vsen end are connected, the output end of the first operational amplifier U1 is connected to the second pin of the second digital potentiometer U2, the seventh pin of the second digital potentiometer U2 is connected to the fifth pin of the third trigger U3, the first pin of the third trigger U3, one end of the first switch SW1, one end of the second switch SW2, the other end of the third resistor R3 and the power supply are connected, the second pin of the third trigger U3 is connected to the sixth pin of the third trigger U3, and the third pin of the third trigger U3 is connected. The fourth pin of the third trigger U3 is connected to one end of the seventh resistor R7, the collector of the second transistor Q2 is connected to the other end of the second resistor R2, the base of the second transistor Q2, the cathode of the third diode D3 and A2 are connected, the other end of the first switch SW1 is connected to the anode of the first diode D1, the cathode of the first diode D1 is connected to the other end of the first resistor R1, the other end of the second switch SW2 is connected to the anode of the third diode D3, the fifth pin of the second digital potentiometer U2, the sixth pin of the second digital potentiometer U2, the emitter of the second transistor Q2, the other end of the sixth resistor R6, the other end of the seventh resistor R7, the other end of the first capacitor C1 and the ground are connected.

[0005] Furthermore, it also includes a fourth AND gate U4, a fifth trigger U5, a sixth AND gate U6, a seventh AND gate U7, a first transistor Q1, an eighth resistor R8, a ninth resistor R9, a second diode D2, a fourth diode D4, a fifth diode D5, a sixth diode D6, an eighth diode D8, and a third switch SW3;

[0006] The output end of the fourth AND gate U4 is connected to one end of the sixth resistor R6, the first connection end of the fourth AND gate U4 is connected to one end of the seventh resistor R7, the second connection end of the fourth AND gate U4 is connected to the seventh pin of the second digital potentiometer U2, the fourth pin of the fifth trigger U5, the second connection end of the sixth AND gate U6, and the second connection end of the seventh AND gate U7, the first pin of the fifth trigger U5, one end of the third switch SW3, the collector of the first transistor Q1 and the power supply are connected, the second pin of the fifth trigger U5 is connected to the sixth pin of the fifth trigger U5, and the first connection end of the seventh AND gate U7, the third pin of the fifth trigger U5 is connected to one end of the ninth resistor R9, the other end of the third switch SW3, and the anode of the seventh diode D7, and the fifth pin of the fifth trigger U5 is connected to the first connection end of the sixth AND gate U6 , the output end of the sixth AND gate U6 is connected to the A2 end, the output end of the seventh AND gate U7, the anode of the eighth diode D8 are connected to the A1 end, the emitter of the first transistor Q1 is connected to the anode of the fourth diode D4, the base of the first transistor Q1 is connected to the cathode of the fifth diode D5, the cathode of the sixth diode D6, and one end of the eighth resistor R8, the anode of the second diode D2 is connected to the second pin of the third trigger U3, the cathode of the second diode D2 is connected to the cathode of the fourth diode D4, and one end of the seventh resistor R7, the anode of the fifth diode D5 is connected to the anode of the first diode D1, the anode of the sixth diode D6 is connected to the anode of the third diode D3, the cathode of the eighth diode D8 is connected to the cathode of the first diode D1, and the other end of the eighth resistor R8 and the other end of the ninth resistor R9 are connected to the ground end.

[0007] Furthermore, it also includes an eighth operational amplifier U8, a ninth operational amplifier U9, and a third field effect transistor Q3;

[0008] The inverting end of the eighth operational amplifier U8, the non-inverting end of the ninth operational amplifier U9 and the Vsen end are connected, the output end of the eighth operational amplifier U8 and the output end of the ninth operational amplifier U9 and the gate of the third field effect transistor Q3 are connected, the inverting end of the ninth operational amplifier U9 and the Vref end are connected, the source of the third field effect transistor Q3 is connected to the Vsen end, and the drain of the third field effect transistor Q3 is connected to the Vout end.

[0009] Furthermore, it also includes a tenth resistor R10 and an eleventh resistor R11;

[0010] One end of the tenth resistor R10 is connected to the power supply, the other end of the tenth resistor R10 is connected to one end of the eleventh resistor R11 and the in-phase terminal of the eighth operational amplifier U8, and the other end of the eleventh resistor R11 is connected to the ground.

[0011] Furthermore, it also includes a fourth resistor R4 and a fifth resistor R5;

[0012] One end of the fourth resistor R4 is connected to the second pin of the second digital potentiometer U2, one end of the fifth resistor R5 is connected to the seventh pin of the second digital potentiometer U2, and the other ends of the fourth resistor R4 and the fifth resistor R5 are connected to the ground.

[0013] Furthermore, the tenth resistor R10 or the eleventh resistor R11 is an adjustable resistor.

[0014] Furthermore, it also includes a twelfth resistor R12;

[0015] One end of the twelfth resistor R12 is connected to the gate of the third field effect transistor Q3, and the other end of the twelfth resistor R12 is connected to the ground.

[0016] The beneficial effects of the present invention compared with the prior art are:

[0017] The circuit will intelligently track the range voltage changes of the lifting motor during manual lifting. When the one-key lifting function is activated, the circuit will sample the previous range voltage and use the sample throughout the subsequent one-key lifting process. If the user switches to operate the manual lifting button, the control circuit will automatically reset and prepare for the next automatic control. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 , Figure 2 A schematic diagram of the circuit structure provided by the present invention. DETAILED DESCRIPTION

[0020] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0021] The present invention discloses a combined control circuit for a heating table, comprising a first operational amplifier U1, a second digital potentiometer U2, a third trigger U3, a second triode Q2, a first resistor R1, a second resistor R2, a third resistor R3, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a first diode D1, a third diode D3, a seventh diode D7, a first switch SW1, and a second switch SW2;

[0022] The in-phase end of the first operational amplifier U1, the third pin of the second digital potentiometer U2, one end of the third resistor R3 and the Vref end are connected, the inverting end of the first operational amplifier U1, one end of the first resistor R1, one end of the second resistor R2, one end of the first capacitor C1 and the Vsen end are connected, the output end of the first operational amplifier U1 is connected to the second pin of the second digital potentiometer U2, the seventh pin of the second digital potentiometer U2 is connected to the fifth pin of the third trigger U3, the first pin of the third trigger U3, one end of the first switch SW1, one end of the second switch SW2, the other end of the third resistor R3 and the power supply are connected, the second pin of the third trigger U3 is connected to the sixth pin of the third trigger U3, and the third pin of the third trigger U3 is connected. The fourth pin of the third trigger U3 is connected to one end of the seventh resistor R7, the collector of the second transistor Q2 is connected to the other end of the second resistor R2, the base of the second transistor Q2, the cathode of the third diode D3 and A2 are connected, the other end of the first switch SW1 is connected to the anode of the first diode D1, the cathode of the first diode D1 is connected to the other end of the first resistor R1, the other end of the second switch SW2 is connected to the anode of the third diode D3, the fifth pin of the second digital potentiometer U2, the sixth pin of the second digital potentiometer U2, the emitter of the second transistor Q2, the other end of the sixth resistor R6, the other end of the seventh resistor R7, the other end of the first capacitor C1 and the ground are connected.

[0023] Specifically, it also includes a fourth AND gate U4, a fifth trigger U5, a sixth AND gate U6, a seventh AND gate U7, a first transistor Q1, an eighth resistor R8, a ninth resistor R9, a second diode D2, a fourth diode D4, a fifth diode D5, a sixth diode D6, an eighth diode D8, and a third switch SW3;

[0024] The output end of the fourth AND gate U4 is connected to one end of the sixth resistor R6, the first connection end of the fourth AND gate U4 is connected to one end of the seventh resistor R7, the second connection end of the fourth AND gate U4 is connected to the seventh pin of the second digital potentiometer U2, the fourth pin of the fifth trigger U5, the second connection end of the sixth AND gate U6, and the second connection end of the seventh AND gate U7, the first pin of the fifth trigger U5, one end of the third switch SW3, the collector of the first transistor Q1 and the power supply are connected, the second pin of the fifth trigger U5 is connected to the sixth pin of the fifth trigger U5, and the first connection end of the seventh AND gate U7, the third pin of the fifth trigger U5 is connected to one end of the ninth resistor R9, the other end of the third switch SW3, and the anode of the seventh diode D7, and the fifth pin of the fifth trigger U5 is connected to the first connection end of the sixth AND gate U6 , the output end of the sixth AND gate U6 is connected to the A2 end, the output end of the seventh AND gate U7, the anode of the eighth diode D8 are connected to the A1 end, the emitter of the first transistor Q1 is connected to the anode of the fourth diode D4, the base of the first transistor Q1 is connected to the cathode of the fifth diode D5, the cathode of the sixth diode D6, and one end of the eighth resistor R8, the anode of the second diode D2 is connected to the second pin of the third trigger U3, the cathode of the second diode D2 is connected to the cathode of the fourth diode D4, and one end of the seventh resistor R7, the anode of the fifth diode D5 is connected to the anode of the first diode D1, the anode of the sixth diode D6 is connected to the anode of the third diode D3, the cathode of the eighth diode D8 is connected to the cathode of the first diode D1, and the other end of the eighth resistor R8 and the other end of the ninth resistor R9 are connected to the ground end.

[0025] Specifically, it also includes an eighth operational amplifier U8, a ninth operational amplifier U9, and a third field effect transistor Q3;

[0026] The inverting end of the eighth operational amplifier U8, the non-inverting end of the ninth operational amplifier U9 and the Vsen end are connected, the output end of the eighth operational amplifier U8 and the output end of the ninth operational amplifier U9 and the gate of the third field effect transistor Q3 are connected, the inverting end of the ninth operational amplifier U9 and the Vref end are connected, the source of the third field effect transistor Q3 is connected to the Vsen end, and the drain of the third field effect transistor Q3 is connected to the Vout end.

[0027] Specifically, it also includes a tenth resistor R10 and an eleventh resistor R11;

[0028] One end of the tenth resistor R10 is connected to the power supply, the other end of the tenth resistor R10 is connected to one end of the eleventh resistor R11 and the in-phase terminal of the eighth operational amplifier U8, and the other end of the eleventh resistor R11 is connected to the ground.

[0029] Specifically, it also includes a fourth resistor R4 and a fifth resistor R5;

[0030] One end of the fourth resistor R4 is connected to the second pin of the second digital potentiometer U2, one end of the fifth resistor R5 is connected to the seventh pin of the second digital potentiometer U2, and the other ends of the fourth resistor R4 and the fifth resistor R5 are connected to the ground.

[0031] Specifically, the tenth resistor R10 or the eleventh resistor R11 is an adjustable resistor.

[0032] Specifically, it also includes a twelfth resistor R12;

[0033] One end of the twelfth resistor R12 is connected to the gate of the third field effect transistor Q3, and the other end of the twelfth resistor R12 is connected to the ground.

[0034] See also Figure 1 , in which A1 is an automatic lifting signal, A2 is an automatic lowering signal, the first switch SW1 is a manual lifting button, the second switch SW2 is a manual lowering button, and the third switch SW3 is an automatic lifting signal. After the third switch SW3 is pressed, the current range voltage is sampled, and the third switch SW3 is lowered and returned to its original position after the first pressing of the third switch SW3. When it is pressed for the second time, Vsen is reset to the sampled range voltage. When the first switch SW1 or the second switch SW2 is adjusted again, the third switch SW3 is re-sampled. Vsen is used to feedback the current range voltage signal, and Vref is used to feedback the maximum lifting limit signal. Vsen and Vref are input to the limit circuit to limit the microprocessor to control the start of the lifting circuit;

[0035] When the first switch SW1 is pressed, the signal is input to the first capacitor C1 through the first diode D1 and the first resistor R1. The potential of the first capacitor C1 terminal rises and is input to the microcontroller through Vsen and the limit circuit. The microcontroller controls the motor to rotate forward or reverse to increase after comparing the maximum lifting limit signal of Vref. When the second switch SW2 is pressed, the power signal is input to the base of the second transistor Q2 through the second switch SW2, and the second transistor Q2 is turned on. The first capacitor C1 is then pulled down through the second resistor R2, the collector, emitter, and grounding loop of the second transistor Q2. The voltage at the first capacitor C1 terminal is input to the microcontroller through Vsen and the limit circuit. After comparing the minimum falling signal, the microcontroller controls the motor to reverse or rotate forward to decrease. The manual part control is completed. The forward and reverse circuit is not shown in the attached figure. The forward and reverse start is determined by comparing the voltage fed back by the motor encoder with the range voltage regulated by Vsen by the microcontroller. The first diode D1 prevents the first capacitor C1 from backflowing.Assume that after the adjustment is completed through the first switch SW1 and the second switch SW2, the third switch SW3 is used for automatic lifting and lowering. The third switch SW3 is closed, and the signal is input to the third pin of the third trigger U3 through the seventh diode D7 in one way, and is directly input to the third pin of the fifth trigger U5 in the other way. The third trigger U3 is used to control the second digital potentiometer U2 to sample the range voltage of the current Vsen feedback. When the third pin of the third trigger U3 is input, the fifth pin outputs a signal to the seventh pin of the second digital potentiometer U2, and the second digital potentiometer U2 is cut off. At the same time, in the initial power-on state, after any of the first switch SW1 and the second switch SW2 are pressed, the first switch SW1 signal is output through the fifth diode D5. The power is input to the base of the first transistor Q1, the first transistor Q1 is turned on, the power is input to the fourth pin of the third trigger U3 through the first transistor Q1 and the fourth diode D4, the fourth pin and the first pin of the third trigger U3 are both input, the fifth pin of the third trigger U3 is cut off, the sixth pin is output, the seventh pin of the second digital potentiometer U2 has no input and passes through the fifth resistor R5 and the ground terminal loop, the second digital potentiometer U2 starts the range following, the control signal followed by the second digital potentiometer U2 is output through the first operational amplifier U1, the first operational amplifier U1 detects the voltage of the third resistor R3 and the third pin connection terminal of the second digital potentiometer U2 at the same phase terminal, detects the voltage of the first capacitor C1 terminal at the inverting terminal, and outputs after comparison. The signal is sent to the second pin of the second digital potentiometer U2 to control the position of the fifth pin of the second digital potentiometer U2 from the sixth pin or the third pin. When the third switch SW3 is pressed, the fifth pin of the third trigger U3 outputs, and the second digital potentiometer U2 stops sampling. At the same time, when the fifth pin of the third trigger U3 outputs, it is also fed back to the fourth pin of the fifth trigger U5, the sixth AND gate U6 and the second pin of the seventh AND gate U7. The fourth pin and the third pin of the fifth trigger U5 have inputs, and the fifth pin of the fifth trigger U5 outputs to the first pin of the sixth AND gate U6. The sixth AND gate U6 outputs a signal to A2 to control the second transistor Q2 to turn on. After the voltage at the end of the first capacitor C1 passes through the second resistor R2 and the second transistor Q2 loop, Then it is fed back to the above-mentioned Vsen signal loop to control the motor to reverse or forward and decrease. When the third switch SW3 is pressed again and the first switch SW1 and the second switch SW2 are not pressed during this period, the third pin of the fifth trigger U5 inputs a signal again, the sixth pin of the fifth trigger U5 outputs, the fifth pin is cut off, the seventh AND gate U7 outputs a signal to A1 and passes through the eighth diode D8, the first resistor R1, and the first capacitor C1. The voltage of the first capacitor C1 rises again and is fed back to Vsen. After being pressed again, the fifth pin of the fifth trigger U5 outputs again, and the voltage at the first capacitor C1 will drop again. The signal at the connection end of the second digital potentiometer U2 and the third resistor R3 is input to the limit circuit through Vref to set the limit range voltage;Assuming that during the period when the third switch SW3 is automatically raised or lowered, when the Vref range voltage needs to be adjusted, the first switch SW1 or the second switch SW2 can be directly pressed to remove the current sampling range of the second digital potentiometer U2. When the first switch SW1 is pressed, the signal is input to the first transistor Q1 through the fifth diode D5, and when the second switch SW2 is pressed, the signal is input to the base of the first transistor Q1 through the sixth diode D6. After the first transistor Q1 is turned on, in addition to being fed back to the fourth pin of the third trigger U3, it is also input to the first pin of the fourth AND gate U4. The second pin of the fourth AND gate U4 is fed back due to the output of the fifth pin of the third trigger U3 after the third switch SW3 is pressed. At this time, the fourth AND gate U4 outputs a signal to the third pin of the third trigger U3, and the fifth pin of the third trigger U3 is cut off. The second digital potentiometer U2 samples again until the third switch SW3 is pressed again. The second pin and the seventh pin of the third trigger U3 are pulled down through the fifth resistor R5 and the fourth resistor R4 when the manual adjustment of the second digital potentiometer U2 and the interruption function are not allowed. ;

[0036] See also Figure 2 The Vref signal is the maximum lifting signal of the limit, and the signal is fed back to the inverting terminal of the ninth operational amplifier U9. The Vsen signal is input to the inverting terminal of the eighth operational amplifier U8 and the non-inverting terminal of the ninth operational amplifier U9, and the other way is fed back to the microcontroller through the third field effect transistor Q3 and Vout. The non-inverting terminal of the eighth operational amplifier U8 sets the minimum falling signal. When the one-key lifting function is not started, the Vref voltage will be synchronized with the second digital potentiometer U2 and the first capacitor C1. The vref voltage is confirmed after the third switch SW3 is pressed to avoid incorrect limit voltage.

[0037] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A heating table combined control circuit, characterized in that: It includes a first operational amplifier, a second digital potentiometer, a third trigger, a second triode, a first resistor, a second resistor, a third resistor, a sixth resistor, a seventh resistor, a first capacitor, a first diode, a third diode, a seventh diode, a first switch, a second switch, an eighth operational amplifier, a ninth operational amplifier, a third field effect transistor, a tenth resistor, and an eleventh resistor; The in-phase end of the first operational amplifier, the third pin of the second digital potentiometer, one end of the third resistor and the Vref end are connected, the inverting end of the first operational amplifier, one end of the first resistor, one end of the second resistor, one end of the first capacitor and the Vsen end are connected, the output end of the first operational amplifier is connected to the second pin of the second digital potentiometer, the seventh pin of the second digital potentiometer is connected to the fifth pin of the third trigger, the first pin of the third trigger, one end of the first switch, one end of the second switch, the other end of the third resistor and the power supply are connected, the second pin of the third trigger is connected to the sixth pin of the third trigger, the third pin of the third trigger is connected to one end of the sixth resistor and the cathode of the seventh diode, the fourth pin of the third trigger is connected to one end of the seventh resistor, the collector of the second transistor is connected to the other end of the second resistor, the base of the second transistor, the cathode of the third diode and A2 are connected, the other end of the first switch is connected to the The anode of the first diode is connected, the cathode of the first diode is connected to the other end of the first resistor, the other end of the second switch is connected to the anode of the third diode, the fifth pin of the second digital potentiometer, the sixth pin of the second digital potentiometer, the emitter of the second triode, the other end of the sixth resistor, the other end of the seventh resistor, the other end of the first capacitor and the ground are connected, the inverting end of the eighth operational amplifier, the non-inverting end of the ninth operational amplifier and the Vsen end are connected, the output end of the eighth operational amplifier and the output end of the ninth operational amplifier and the gate of the third field effect tube are connected, the inverting end of the ninth operational amplifier and the Vref end are connected, the source of the third field effect tube is connected to the Vsen end, the drain of the third field effect tube is connected to the Vout end, one end of the tenth resistor is connected to the power supply, the other end of the tenth resistor is connected to one end of the eleventh resistor and the non-inverting end of the eighth operational amplifier, and the other end of the eleventh resistor is connected to the ground.

2. The heating table combined control circuit according to claim 1 is characterized in that: It also includes a fourth AND gate, a fifth trigger, a sixth AND gate, a seventh AND gate, a first triode, an eighth resistor, a ninth resistor, a second diode, a fourth diode, a fifth diode, a sixth diode, an eighth diode, and a third switch; The output end of the fourth AND gate is connected to one end of the sixth resistor, the first connection end of the fourth AND gate is connected to one end of the seventh resistor, the second connection end of the fourth AND gate is connected to the seventh pin of the second digital potentiometer, the fourth pin of the fifth trigger, the second connection end of the sixth AND gate, and the second connection end of the seventh AND gate, the first pin of the fifth trigger, one end of the third switch, the collector of the first transistor and the power supply are connected, the second pin of the fifth trigger is connected to the sixth pin of the fifth trigger, and the first connection end of the seventh AND gate, the third pin of the fifth trigger is connected to one end of the ninth resistor, the other end of the third switch, and the anode of the seventh diode, and the fifth pin of the fifth trigger is connected to the first connection end of the sixth AND gate. , the output end of the sixth AND gate is connected to the A2 end, the output end of the seventh AND gate, the anode of the eighth diode are connected to the A1 end, the emitter of the first transistor is connected to the anode of the fourth diode, the base of the first transistor is connected to the cathode of the fifth diode, the cathode of the sixth diode, and one end of the eighth resistor, the anode of the second diode is connected to the second pin of the third trigger, the cathode of the second diode is connected to the cathode of the fourth diode, and one end of the seventh resistor is connected, the anode of the fifth diode is connected to the anode of the first diode, the anode of the sixth diode is connected to the anode of the third diode, the cathode of the eighth diode is connected to the cathode of the first diode, and the other end of the eighth resistor, the other end of the ninth resistor and the ground end are connected.

3. The heating table combined control circuit according to claim 1 is characterized in that: Also includes a fourth resistor and a fifth resistor; One end of the fourth resistor is connected to the second pin of the second digital potentiometer, one end of the fifth resistor is connected to the seventh pin of the second digital potentiometer, and the other ends of the fourth resistor and the fifth resistor are connected to the ground.

4. The heating table combined control circuit according to claim 1, characterized in that: The tenth resistor or the eleventh resistor is an adjustable resistor.

5. The heating table combined control circuit according to claim 1, characterized in that: Also included is a twelfth resistor; One end of the twelfth resistor is connected to the gate of the third field effect transistor, and the other end of the twelfth resistor is connected to the ground end.

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