Light emitting diode and light emitting device

Abstract

The application discloses a light emitting diode and a light emitting device. The light emitting diode comprises a semiconductor stack, a first electrode, an insulating layer and a first pad. The first electrode is arranged on the surface of the exposed first semiconductor layer of the semiconductor stack, and the first electrode comprises a metal stack and a first adhesive layer in sequence on the surface of the exposed first semiconductor layer. The insulating layer covers the semiconductor stack and the first electrode, and contacts the first adhesive layer of the first electrode. The insulating layer is provided with a first opening corresponding to the position of the first electrode. The first opening penetrates the insulating layer and the first adhesive layer of the first electrode, and exposes the metal stack of the first electrode. The first pad is arranged above the first opening of the insulating layer, fills the first opening, and contacts the metal stack of the first electrode exposed by the first opening. Thus, the application can improve the adhesion between the pad and the electrode, and ensure the normal electrical performance of the chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and specifically to a light-emitting diode and a light-emitting device. Background Technology

[0002] Light-emitting diodes (LEDs) are solid-state light-emitting devices that convert electrical energy into light energy. Due to their advantages such as long lifespan, small size, good shock resistance, energy saving, high efficiency, fast response time, low driving voltage, and environmental friendliness, they are widely used in many fields such as indication, display, decoration, and lighting. In recent years, the enormous application value of ultraviolet LEDs, especially deep ultraviolet LEDs, has attracted much attention and become a new research hotspot.

[0003] Currently, improving the reliability of light-emitting diodes (LEDs) has reached a research bottleneck, especially for deep ultraviolet (DUV) LEDs, where reliability is of paramount importance. How to further improve the reliability of LEDs has become an urgent technical problem to be solved. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a light-emitting diode and a light-emitting device to further improve the reliability of the light-emitting diode or the light-emitting device.

[0005] To achieve the above and other related objectives, the present invention provides a light-emitting diode, which includes:

[0006] A semiconductor stack, comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially;

[0007] A first electrode is disposed on the surface of a first semiconductor layer; the first electrode comprises a metal stack and a first adhesion layer sequentially on the surface of the first semiconductor layer.

[0008] An insulating layer covers the semiconductor stack and the first electrode, and contacts the first adhesive layer of the first electrode; the insulating layer has a first opening at the position corresponding to the first electrode, the first opening penetrates the insulating layer and the first adhesive layer of the first electrode, and exposes the metal stack of the first electrode;

[0009] The first pad is disposed above the first opening of the insulating layer and fills the first opening, and contacts the metal stack of the first electrode exposed by the first opening.

[0010] According to one aspect of the invention, a light-emitting diode is also included, the light-emitting diode comprising:

[0011] A semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially; the semiconductor stack has a portion of its surface exposing the first semiconductor layer.

[0012] A first insulating layer covers the surface of the semiconductor stack and has a first opening on the surface of the first semiconductor layer exposed in the semiconductor stack;

[0013] The first connecting electrode covers the first insulating layer, fills the first opening, and is electrically connected to the first semiconductor layer through the first opening; the first connecting electrode includes a metal stack and a first adhesive layer in sequence on the side near the semiconductor stack.

[0014] A second insulating layer covers the first connecting electrode, and a third opening is formed on the second insulating layer. The third opening penetrates the second insulating layer and the first adhesive layer of the first connecting electrode, and exposes the metal stack of the first connecting electrode.

[0015] The first pad is disposed above the third opening of the second insulating layer, fills the third opening, and contacts the metal stack of the first connecting electrode exposed by the third opening.

[0016] According to one aspect of the invention, a light-emitting device is also included, which comprises a light-emitting diode according to any one of the above claims.

[0017] Compared with the prior art, the light-emitting diode and light-emitting device described in this invention have at least the following beneficial effects:

[0018] The light-emitting diode of the present invention includes a semiconductor stack, a first electrode, an insulating layer, and a first pad. The first electrode is disposed on the surface of an exposed first semiconductor layer of the semiconductor stack, and the first electrode sequentially includes a metal stack and a first adhesive layer on the exposed surface of the first semiconductor layer. The insulating layer covers the semiconductor stack and the first electrode, and contacts the first adhesive layer of the first electrode. A first opening is provided in the insulating layer corresponding to the position of the first electrode, the first opening penetrating the insulating layer and the first adhesive layer of the first electrode, and exposing the metal stack of the first electrode. The first pad is disposed above the first opening in the insulating layer, filling the first opening, and contacting the metal stack of the first electrode exposed by the first opening. Thus, the electrode of the present invention includes an adhesive layer. When an opening is formed on the insulating layer where the pad contacts the electrode, the opening is directly etched to remove the adhesive layer, avoiding oxidation of the adhesive layer exposed on the bottom surface of the opening, which would affect the bonding or adhesion between the pad and the electrode. It also avoids the formation of an oxide layer affecting the current transmission between the electrode and the pad, ensuring the normal electrical performance of the chip.

[0019] The light-emitting device of the present invention includes the above-mentioned light-emitting diode and similarly possesses the above-mentioned technical effects. Attached Figure Description

[0020] Figure 1 This is a top view of the light-emitting diode structure in Embodiment 1 of the present invention;

[0021] Figure 2 For along Figure 1 Cross-sectional view along line A-A';

[0022] Figure 3a , Figure 3b for Figure 2 Enlarged view of point a in the middle;

[0023] Figure 4 This is a top view of the light-emitting diode in Embodiment 2 of the present invention;

[0024] Figure 5 For along Figure 4 Cross-sectional view along line B-B';

[0025] Figure 6 for Figure 5 Enlarged view of point b in the middle;

[0026] Figure 7 for Figure 5 An enlarged view of an embodiment at point c;

[0027] Figure 8 for Figure 5 Enlarged view at point d;

[0028] Figure 9 for Figure 5 An enlarged view of another embodiment at point c;

[0029] Figure 10 This is a top view of the light-emitting diode structure in Embodiment 3 of the present invention;

[0030] Figure 11 For along Figure 10 A cross-sectional view along the C-C' direction;

[0031] Figure 12 for Figure 11 An enlarged view of an embodiment at point e;

[0032] Figure 13 for Figure 11 An enlarged view of another embodiment at point e;

[0033] Figure 14 for Figure 11 Enlarged view at point f;

[0034] Figure 15 for Figure 11 A magnified view of point g in the middle.

[0035] List of reference numerals in the attached diagram:

[0036] 100 substrate 200 Semiconductor stack 201 First semiconductor layer 202 Active layer 203 Second semiconductor layer 300 transparent conductive layer 410 First electrode 420 Second electrode 411 Electrode hole 500 Insulation layer 510 First insulating layer 501 First opening 502 Third opening 601 First connecting electrode 602 First contact electrode 700 Second insulating layer 701 Second opening 702 Fourth opening 703 mesa 801 First pad 802 Second pad 900 Second Adhesive Layer 01 First Adhesion Layer 02 Metal stack 021 Etching stop layer 0211 First horizontal surface 0212 Second horizontal surface 0213 Inclined surface 022 Other metal layers 03 Ohmic contact layer Detailed Implementation

[0037] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0038] It should be understood that the illustrations provided in the embodiments of this invention are merely schematic representations of the basic concept of the invention. Although the illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of components in implementation, the shape, quantity, and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complex. The structures, proportions, sizes, etc., shown in the accompanying drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the invention can produce, should still fall within the scope of the technical content disclosed in this application.

[0039] To further improve the reliability of light-emitting diodes (LEDs), especially deep ultraviolet (DUV) LEDs, the inventors discovered during their research that: In existing technologies, an insulating layer is typically formed above the electrodes of the chip, with openings in this layer to allow subsequent bonding pads to form electrical contacts with the electrodes. An adhesion layer is also generally formed on the electrode surface, which increases the adhesion between the electrode and the insulating layer and bonding pads. The adhesion layer is typically made of Ti or Cr, and the bonding pads directly contact the adhesion layer material on the electrode surface through the openings in the insulating layer. However, during the formation of bonding pads on the insulating layer, the openings expose part of the adhesion layer on the electrode surface. This exposed adhesion layer is extremely prone to oxidation in air, and the resulting oxide layer affects the adhesion between the bonding pads and the adhesion layer, leading to decreased chip reliability. Furthermore, the presence of this oxide layer can also easily cause an increase in chip voltage, which is detrimental to chip manufacturing yield.

[0040] To address the background technology and the aforementioned technical problems, this embodiment provides a light-emitting diode and a light-emitting device. This light-emitting diode can avoid the oxidation of the adhesive layer exposed in the opening of the insulating layer, further improve the adhesion of the electrode, maintain the normal electrical performance of the chip, and thus improve the reliability of the chip.

[0041] Specifically, this embodiment provides a light-emitting diode, including:

[0042] Semiconductor stacking,

[0043] It includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence;

[0044] A first electrode is disposed on the surface of a first semiconductor layer; the first electrode comprises a metal stack and a first adhesion layer sequentially on the surface of the first semiconductor layer.

[0045] An insulating layer covers the semiconductor stack and the first electrode, and contacts the first adhesive layer of the first electrode; the insulating layer has a first opening at the position corresponding to the first electrode, the first opening penetrates the insulating layer and the first adhesive layer of the first electrode, and exposes the metal stack of the first electrode;

[0046] The first pad is disposed above the first opening of the insulating layer and fills the first opening, contacting the metal stack of the first electrode exposed by the first opening. Thus, in this embodiment, the first adhesion layer is etched away within the first opening until etching stops on the surface or inside the etch stop layer, avoiding oxidation problems after exposure, which would affect the interfacial bonding between the first pad formed subsequently within the first opening and the first adhesion layer. At the same time, it avoids the oxide layer affecting the electrical performance of the chip.

[0047] Optionally, the metal stack also includes an etch stop layer near the first adhesion layer and other metal layers near the semiconductor stack. The etch stop layer on the metal stack prevents over-etching.

[0048] Optionally, the first opening penetrates the etch stop layer of the first electrode, and the bottom wall of the first opening exposes the etch stop layer.

[0049] Optionally, the thickness of the first adhesion layer ranges from 1 to 300 nm. On the one hand, this avoids the phenomenon that incomplete etching due to excessive thickness of the first adhesion layer can easily lead to voltage increases; on the other hand, it is necessary to ensure that the first adhesion layer has a certain thickness to guarantee its adhesion effect.

[0050] Optionally, the thickness of the etching stop layer ranges from 50 to 1000 nm. On the one hand, it is necessary to ensure that the etching stop layer has a certain thickness to avoid over-etching; on the other hand, if the etching stop layer is too thick, it will not only increase the cost but also increase the stress.

[0051] Optionally, the light-emitting diode also includes:

[0052] A second adhesion layer is disposed between the first pad and the metal stack of the insulating layer and the first electrode. The second adhesion layer can further increase the bonding force between the pad and the insulating layer and electrode layer, and will not cause the problem of poor bonding performance between the pad and the metal stack within the opening due to the removal of the first adhesion layer within the opening.

[0053] Optionally, the angle between the sidewall and the bottom wall of the first opening is greater than 90°. In this embodiment, the first opening is inclined, which can increase the contact area between the pad and the sidewall of the opening and further improve the adhesion of the pad.

[0054] Optionally, the metal stack has a first horizontal surface covered by an insulating layer, a second horizontal surface located within a first opening, and an inclined surface connecting the first and second horizontal surfaces; the first and second horizontal surfaces are substantially parallel to the surface of the first semiconductor layer; the angle between the inclined surface and the second horizontal surface is greater than 90°. This increases the contact area between the pads and the metal stack, avoiding the problem of poor bonding performance between the pads and the metal stack within the opening due to the removal of the first adhesive layer within the opening.

[0055] Optionally, the angle between the inclined surface of the metal stack and the second horizontal surface of the metal stack is greater than the angle between the sidewall of the insulating layer located at the first opening and the second horizontal surface of the metal stack. This allows the sidewall of the first opening to form a two-stage inclined angle, with the inclination gradually decreasing from top to bottom. This further increases the contact area between the first pad and the sidewall of the first opening, and also facilitates the subsequent coverage of the metal layer. Therefore, this embodiment can improve the adhesion between the pad and the electrode while ensuring the normal electrical performance of the chip.

[0056] This embodiment also provides a light-emitting diode, including:

[0057] A semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially; the semiconductor stack has a portion of its surface exposing the first semiconductor layer.

[0058] A first insulating layer covers the surface of the semiconductor stack and has a first opening on the surface of the first semiconductor layer exposed in the semiconductor stack;

[0059] The first connecting electrode covers the first insulating layer, fills the first opening, and is electrically connected to the first semiconductor layer through the first opening; the first connecting electrode includes a metal stack and a first adhesive layer in sequence on the side near the semiconductor stack.

[0060] A second insulating layer covers the first connecting electrode, and a third opening is formed on the second insulating layer. The third opening penetrates the second insulating layer and the first adhesive layer of the first connecting electrode, and exposes the metal stack of the first connecting electrode.

[0061] The first pad is disposed above the third opening of the second insulating layer, fills the third opening, and contacts the metal stack of the first connection electrode exposed by the third opening. Thus, similarly, removing the first adhesive layer of the first connection electrode exposed in the third opening can prevent surface oxidation of the exposed first adhesive layer, which would affect the bonding strength of the subsequent pads formed in the third opening, and also avoid affecting the electrical performance of the chip.

[0062] Optionally, the light-emitting diode also includes:

[0063] A first contact electrode is disposed on the surface of the exposed first semiconductor layer of the semiconductor stack and exposed within a first opening. The first contact electrode comprises a metal stack and a first adhesive layer sequentially on the surface of the exposed first semiconductor layer. The first opening penetrates the first insulating layer and the first adhesive layer of the first contact electrode, exposing the metal stack of the first contact electrode. A first connecting electrode contacts the metal stack of the first contact electrode exposed within the first opening. In this embodiment, a first contact electrode is disposed between the first semiconductor layer and the first connecting electrode to improve current transmission capability and reduce chip voltage.

[0064] Optionally, the light-emitting diode also includes:

[0065] Electrode holes are spaced apart and exposed on the surface of the semiconductor stack, penetrating or partially penetrating the first semiconductor layer. A first contact electrode is disposed on the first semiconductor layer exposed by the electrode holes and fills the electrode holes. Electrode holes are commonly used in deep ultraviolet (DUV) light-emitting diodes (LEDs). Because the epitaxial layer of a DUV is doped with a high concentration of Al, it is difficult to form an ohmic contact at the N-terminal epitaxial layer. Furthermore, the material properties of the epitaxial layer itself result in poor lateral current propagation within the epitaxial layer, leading to a relatively high overall operating voltage. Penetrating the first semiconductor layer through electrode holes increases the contact area between the electrode and the first semiconductor layer, while simultaneously allowing current to be shunt and laterally injected into the first semiconductor layer, enhancing the lateral propagation of current within the first semiconductor layer and thus reducing the voltage of the DUV.

[0066] Optionally, the light-emitting diode also includes:

[0067] The second pad is disposed above the second insulating layer and spaced apart from the first pad. The second pad is electrically connected to the second semiconductor layer. The first opening is disposed below the first pad and / or below the second pad, and the third opening is disposed below the first pad.

[0068] Optionally, the light-emitting diode also includes:

[0069] The second electrode is disposed on the second semiconductor layer of the semiconductor stack; the second electrode includes a metal stack and a first adhesion layer sequentially on the surface of the second semiconductor layer.

[0070] The first insulating layer also includes a second opening disposed at a position on the first insulating layer corresponding to the second electrode. The second opening penetrates the first insulating layer and the first adhesive layer of the second electrode, exposing the metal stack of the second electrode.

[0071] The second insulating layer also includes a fourth opening, which is disposed at a position in the second insulating layer corresponding to the second opening and penetrates the second insulating layer;

[0072] The second pad is positioned above the second and fourth openings and spaced apart from the first pad. It fills the second and fourth openings and forms contact with the metal stack of the second electrode exposed by the second and fourth openings. Removing the first adhesive layer of the second electrode at the second opening location can also prevent the exposed first adhesive layer from undergoing an oxidation reaction, which would affect the adhesion between the second pad subsequently formed in the second opening and the first adhesive layer. It also avoids the resulting oxide layer from affecting the electrical properties of the chip.

[0073] Optionally, the width of the fourth opening in the direction from the second pad to the second electrode is equal or gradually decreases, the width of the second opening in the direction from the second pad to the second electrode is equal or gradually decreases, the width of the third opening in the direction from the first pad to the first connecting electrode is equal or gradually decreases, and the width of the first opening in the direction from the first connecting electrode to the first semiconductor layer is equal or gradually decreases.

[0074] Optionally, the maximum width of the second opening is less than or equal to the minimum width of the fourth opening.

[0075] Optionally, the angle between the sidewall and bottom wall of the first opening is greater than 90°; the angle between the sidewall and bottom wall of the third opening is greater than 90°; the angle between the sidewall and bottom wall of the second opening is greater than 90°; and the angle between the sidewall and bottom wall of the fourth opening is greater than 90°. The inclined sidewalls of the openings increase the contact area between the pads and the insulating and electrode layers, further improving the bonding force between the pads and the electrodes.

[0076] Optionally, the thickness of the first adhesion layer ranges from 1 to 300 nm. On the one hand, this avoids the phenomenon that incomplete etching due to excessive thickness of the first adhesion layer can easily lead to voltage increases; on the other hand, it is necessary to ensure that the first adhesion layer has a certain thickness to guarantee its adhesion effect.

[0077] Optionally, the metal stack also includes an etch stop layer near the first adhesion layer and other metal layers near the semiconductor stack.

[0078] Optionally, the first opening penetrates the etch stop layer of the first contact electrode, exposing the etch stop layer of the first contact electrode at its bottom wall; the third opening penetrates the etch stop layer of the first connecting electrode, exposing the etch stop layer of the first connecting electrode at its bottom wall; and the second opening penetrates the etch stop layer of the second electrode, exposing the etch stop layer of the second electrode at its bottom wall.

[0079] Optionally, the thickness of the etching stop layer ranges from 50 to 1000 nm. On the one hand, it is necessary to ensure that the etching stop layer has a certain thickness to avoid over-etching; on the other hand, if the etching stop layer is too thick, it will not only increase the cost but also increase the stress.

[0080] Optionally, the light-emitting diode also includes:

[0081] A transparent conductive layer is disposed between the second semiconductor layer and the second electrode.

[0082] Optionally, the thickness of the etch stop layer of the second electrode is greater than the thickness of the etch stop layer of the first connecting electrode or the first contact electrode. Since the second electrode is formed above the transparent conductive layer, as a metal conductive layer in direct contact with the transparent conductive layer, the etch stop layer needs to have a certain thickness to avoid affecting current conduction due to over-etching.

[0083] Optionally, when the maximum width of the second opening is less than the minimum width of the fourth opening, the thickness of the etch stop layer of the second electrode is greater than the thickness of the etch stop layer of the first connecting electrode. When the first insulating layer and the second insulating layer form the second and fourth openings through step-by-step etching, the maximum width of the second opening is usually less than the minimum width of the fourth opening. In this case, on the one hand, since the second electrode is a metal conductive layer in direct contact with the transparent conductive layer, it is necessary to ensure that the etch stop layer has a certain thickness to avoid affecting current conduction due to over-etching; on the other hand, since the second opening needs to be etched on the first insulating layer first, and then the fourth opening needs to be etched on the second insulating layer to complete the step-by-step etching, the etch stop layer of the second electrode will undergo two etchings. Therefore, the etch stop layer of the second electrode needs to be thickened to avoid over-etching of the second electrode after two etchings.

[0084] Optionally, when the maximum width of the second opening is equal to the minimum width of the fourth opening, the thickness of the etch stop layer of the first connecting electrode is greater than or equal to the thickness of the etch stop layer of the second electrode. When the first insulating layer and the second insulating layer form the second and fourth openings through a single etching step, the maximum width of the second opening is usually equal to the minimum width of the fourth opening. In this case, since the area covered by the second pad needs to have the fourth opening etched on the second insulating layer before the second opening is etched on the first insulating layer to expose the lower second electrode, the area covered by the first pad will be simultaneously etched. After the third opening is formed on the second insulating layer, the lower first connecting electrode will be etched simultaneously. Therefore, the etch stop layer of the first connecting electrode needs to be thickened to ensure that the area covered by the second pad can be cleanly etched during simultaneous etching, while avoiding over-etching of the first connecting electrode below the first pad. Furthermore, since the second electrode is a metal conductive layer that is in direct contact with the transparent conductive layer, the etching stop layer needs to have a certain thickness to avoid affecting current conduction due to over-etching. Therefore, the thickness of the etching stop layer of the second electrode can also be increased to be equal to the thickness of the etching stop layer of the first connecting electrode.

[0085] In other words, compared to forming the fourth and second openings through a single etching step, when the first and second insulating layers are etched in stages to form the fourth and second openings, the thickness of the etch stop layer of the second electrode can be increased to avoid affecting current conduction due to over-etching. Furthermore, the thickness of the etch stop layer of the second electrode during staged etching is greater than that during single-step etching. Optionally, when the first and second insulating layers are etched in stages to form the fourth and second openings, the thickness of the etch stop layer of the second electrode ranges from 60 to 1000 nm; the thickness of the etch stop layer of the first connecting electrode ranges from 50 to 800 nm.

[0086] Meanwhile, when the first insulating layer and the second insulating layer form the fourth opening and the second opening through a one-step etching, in order to avoid over-etching of the first connection electrode under the first pad, the thickness of the etching stop layer of the first connection electrode can be increased, and the thickness of the etching stop layer of the first connection electrode during one-step etching is greater than the thickness of the etching stop layer of the first connection electrode during step-by-step etching. Optionally, when the first insulating layer and the second insulating layer form the fourth opening and the second opening through one-step etching, the thickness of the etching stop layer of the first connection electrode is between 60 and 1000 nm; the thickness of the etching stop layer of the second electrode is between 50 and 800 nm.

[0087] Optionally, the light-emitting diode also includes:

[0088] A second adhesive layer is disposed on the second insulating layer and fills the second opening, and a first pad is disposed on the second adhesive layer; the second adhesive layer also fills the third opening and the fourth opening, and a second pad is disposed on the second adhesive layer.

[0089] Optionally, the material of the first adhesion layer includes Cr, Ni, or Ti.

[0090] Alternatively, the material for the etch stop layer may include Pt, Ni, Ti, Cr, Rh, Ru, Mo, W, or Cu.

[0091] This embodiment also provides a light-emitting device, which includes the light-emitting diode described above.

[0092] The present invention will now be described in detail with reference to specific embodiments.

[0093] Example 1

[0094] This embodiment provides a light-emitting diode, as shown in the reference. Figure 1 and 2 The light-emitting diode includes a substrate 100, a semiconductor stack 200, a first electrode 410, an insulating layer 500, and a first pad 801.

[0095] The substrate 100 is the growth substrate 100 of the semiconductor stack 200. Optionally, the material of the substrate 100 can be sapphire, silicon carbide, silicon, or gallium nitride. In this embodiment, the substrate 100 is a sapphire substrate 100.

[0096] A semiconductor stack 200 is disposed on the surface of a substrate 100. The semiconductor stack 200 includes a first semiconductor layer 201, an active layer 202, and a second semiconductor layer 203 stacked sequentially on the surface of the substrate 100. The semiconductor stack 200 has a portion of the surface of the first semiconductor layer 201 exposed. The shape of the exposed surface of the first semiconductor layer 201 in the semiconductor stack 200 can be arbitrary. In this embodiment, referring to… Figure 1 On the surface of the semiconductor stack 200, a first semiconductor layer 201 in an annular shape and two spaced-apart finger-shaped structures is exposed. In other embodiments, refer to... Figure 4 or Figure 10 The surface of the semiconductor stack 200 is exposed with a plurality of spaced circular, elongated or square first semiconductor layers 201. At this time, a plurality of spaced electrode holes 411 are formed on the semiconductor stack 200. Each electrode hole extends downward from the second semiconductor layer 203 on the surface of the semiconductor stack 200, through the active layer 202, to the surface of the first semiconductor layer 201. The exposed circular, elongated or square first semiconductor layer 201 serves as the bottom surface of the electrode hole.

[0097] Reference Figure 2In step 3, the first electrode 410 is disposed on the surface of the exposed first semiconductor layer 201 of the semiconductor stack 200 and forms an electrical connection with the first semiconductor layer 201 within the electrode hole. The first electrode 410 sequentially includes a metal stack 02 and a first adhesion layer 01 on the surface of the exposed first semiconductor layer 201. Optionally, the thickness of the first adhesion layer 01 of the first electrode 410 ranges from 1 to 300 nm. For example, 5 to 50 nm.

[0098] Reference Figure 3a and Figure 3b An insulating layer 500 covers the semiconductor stack 200 and the first electrode 410, and simultaneously contacts the first adhesion layer 01 of the first electrode 410. A first opening 501 is provided in the insulating layer 500 corresponding to the position of the first electrode 410. The first opening 501 penetrates the insulating layer 500 and the first adhesion layer 01 of the first electrode 410, exposing the metal stack 02. Therefore, in this embodiment, the first adhesion layer 01 is etched away within the first opening 501 until etching stops on the surface or inside the etch stop layer 021, avoiding oxidation problems after exposure that could affect the interfacial bonding between the first pad 801 subsequently formed within the first opening 501 and the first adhesion layer 01. Simultaneously, it prevents the oxide layer from affecting the electrical performance of the chip.

[0099] Optionally, refer to Figure 3a and Figure 3b The metal stack 02 includes an etch stop layer 021 near the first adhesion layer 01 and other metal layers 022 near the semiconductor stack 200. At this time, the first opening 501 penetrates both the insulating layer 500 and the first adhesion layer 01, and also partially penetrates the etch stop layer 021 of the metal stack 02 of the first electrode 410. The exposed surface of the etch stop layer 021 forms the bottom wall of the first opening 501. Optionally, the thickness of the etch stop layer 021 of the first electrode 410 ranges from 50 to 1000 nm. For example, 100 to 300 nm.

[0100] Optionally, refer to Figure 3a The angle between the sidewall and the bottom wall of the first opening 501 is greater than 90°, for example, 120~160°. The inclined sidewall of the first opening 501 is more conducive to the bonding performance between the first pad 801 and the sidewall of the first opening 501.

[0101] Reference Figure 2 and 3a3b. A first pad 801 is disposed above and fills the first opening 501 of the insulating layer 500, and contacts the metal stack 02 of the first electrode 410 exposed by the first opening 501. Optionally, a second adhesion layer 900 is further disposed between the first pad 801 and the insulating layer 500 and the metal stack 02 of the first electrode 410. The second adhesion layer 900 is formed before the formation of the first pad 801. This second adhesion layer 900 can increase the adhesion performance between the first pad 801 and the insulating layer 500 and the metal stack 02 of the first electrode 410, and will not cause poor bonding performance between the first pad 801 and the metal stack 02 in the first opening 501 due to the removal of the first adhesion layer 01 in the first opening 501.

[0102] Optionally, refer to Figure 3b The metal stack 02 has a first horizontal surface 0211 covered by an insulating layer 500, a second horizontal surface 0212 located within the first opening 501, and an inclined surface 0213 connecting the first horizontal surface 0211 and the second horizontal surface 0212. The first horizontal surface 0211 and the second horizontal surface 0212 are substantially parallel to the surface of the first semiconductor layer 201, and the included angle α1 between the inclined surface 0213 and the second horizontal surface 0212 is greater than 90°. For example, 120°~179°, preferably 140°~179°. This increases the contact area between the first pad 801 and the metal stack 02, that is, it increases the contact area between the second adhesive layer 900 and the metal stack 02, thereby avoiding the problem of poor bonding performance between the first pad 801 and the metal stack 02 within the first opening 501 due to the removal of the first adhesive layer 01 within the first opening 501. In this embodiment, more specifically, the first horizontal surface 0211, the second horizontal surface 0212, and the inclined surface 0213 all refer to the surfaces of the etching stop layer 021 of the metal stack 02.

[0103] Furthermore, optionally, refer to Figure 3bThe angle α1 between the inclined surface 0213 of the metal stack 02 and the second horizontal surface 0212 of the metal stack 02 is greater than the angle α2 between the sidewall of the insulating layer 500 located at the first opening 501 and the second horizontal surface 0212 of the metal stack 02. For example, the angle α1 between the inclined surface 0213 of the metal stack 02 and the second horizontal surface 0212 of the metal stack 02 is 160°~179°, and the angle α2 between the sidewall of the insulating layer 500 located at the first opening 501 and the second horizontal surface 0212 of the metal stack 02 (an auxiliary line parallel to the second horizontal surface 0212 is drawn in the figure) is 120°~160°. This allows the sidewall formed by the first opening 501 when penetrating the insulating layer 500 to part of the etch stop layer 021 to form a two-stage tilt angle, with the tilt gradually decreasing from top to bottom. On the one hand, this can further increase the overall contact area between the first pad 801 and the sidewall of the first opening 501, thereby improving the adhesion between the pad and the electrode. On the other hand, the gradually decreasing tilt from top to bottom can be more conducive to the subsequent coverage of the metal layer, preventing the metal layer from breaking, and thus ensuring the normal electrical performance of the chip.

[0104] In this embodiment, refer to Figure 2 The light-emitting diode also includes a second electrode 420, a second opening 701, and a second pad 802. It should be noted that the arrangement of the second electrode 420, the second opening 701, and the second pad 802 is not shown in the accompanying drawings, but the connection structure between the second electrode 420 and the second semiconductor layer 203, and the connection structure between the first electrode 410 and the first semiconductor layer 201, can be referenced accordingly. Figure 3a In this case, the first semiconductor layer 201 can be regarded as the second semiconductor layer 203, the first opening 501 as the second opening 701, the first electrode 410 as the second electrode 420, and the first pad 801 as the second pad 802. The second electrode 420 is disposed on the surface of the second semiconductor layer 203 of the semiconductor stack 200, and the second electrode 420 sequentially includes a metal stack 02 and a first adhesion layer 01 on the surface of the second semiconductor layer 203. The second opening 701 is disposed in the insulating layer 500 at a position corresponding to the second electrode 420, and the second opening 701 penetrates the insulating layer 500 and the first adhesion layer 01 of the second electrode 420, exposing the metal stack 02 of the second electrode 420. Similarly, removing the first adhesion layer 01 of the second electrode 420 within the second opening 701 can prevent surface oxidation of the exposed first adhesion layer 01, which would affect the bonding force between the pad and the adhesion, and also avoid affecting the electrical performance of the chip.

[0105] Optionally, refer to Figure 2In addition to layer 3, the metal stack 02 of the second electrode 420 also includes an etch stop layer 021 near the first adhesion layer 01 and other metal layers 022 near the semiconductor stack 200. At this time, the second opening 701 penetrates the insulating layer 500 and the first adhesion layer 01 of the second electrode 420, and partially penetrates the etch stop layer 021 of the second electrode 420. The exposed surface of the etch stop layer 021 of the second electrode 420 forms the bottom wall of the second opening 701. Optionally, the angle between the sidewall and the bottom wall of the second opening 701 is greater than 90°, for example, 120~160°. Optionally, the thickness of the first adhesion layer 01 of the second electrode 420 ranges from 1 nm to 300 nm, for example, 100~300 nm. The thickness of the etch stop layer 021 of the second electrode 420 ranges from 50 nm to 1000 nm, for example, 100~300 nm. Optionally, in some embodiments, the thickness of the etch stop layer 021 of the second electrode 420 can be greater than the thickness of the etch stop layer 021 of the first electrode 410. This is because the second electrode 420 is formed above the transparent conductive layer 300. As a metal conductive layer that is in direct contact with the transparent conductive layer 300, the etch stop layer 021 needs to have a certain thickness to avoid affecting current conduction due to over-etching.

[0106] Optionally, refer to Figure 2 In section 3, the second pad 802 is disposed above the second opening 701 of the insulating layer 500, and the first pads 801 are spaced apart. The second pad 802 fills the second opening 701 and forms contact with the metal stack 02 of the second electrode 420 exposed by the second opening 701. Optionally, a second adhesion layer 900 is further disposed between the second pad 802 and the insulating layer 500 and the metal stack 02 of the second electrode 420. The function of the second adhesion layer 900 is also to increase the bonding performance between the pad and the metal stack 02 in the second opening 701.

[0107] Optionally, the first electrode 410 is an N-type electrode, and the second electrode 420 is a P-type electrode. The thickness of the etching stop layer of the P-type electrode can be greater than the thickness of the etching stop layer of the N-type electrode. Since a transparent conductive layer is generally disposed below the P-type electrode, the electrode layer above the transparent conductive layer is generally made thicker to avoid over-etching to the transparent conductive layer and affecting current transmission. Optionally, the materials of the first adhesion layer 01 of the first electrode 410 and the second electrode 420 can be the same or different. The material of the first adhesion layer 01 can be one or more of Cr, Ni, or Ti. In this embodiment, the material of the first adhesion layer 01 is Ti. Optionally, the materials of the etching stop layer 021 of the first electrode 410 and the second electrode 420 can be the same or different. The material of the etching stop layer 021 includes one or more of Pt, Ni, Ti, Cr, Rh, Ru, Mo, W, or Cu. In this embodiment, the material of the etching stop layer 021 is Pt. Optionally, all metal stacks 02 further include other metal layers 022 located between the etch stop layer 021 and the semiconductor stack 200. These other metal layers 022 may sequentially include, but are not limited to, an adhesion layer, a thermally conductive layer, a barrier layer, a planarization layer, a reflective layer, and an adhesion layer (not shown in the figure). Optionally, the reflective layer is made of Al or Ag, the planarization layer is made of Ti, Rh, Ru, Mo, W, or Cu, the barrier layer is made of Pt, Rh, or Ru, the thermally conductive layer is made of Au, Cu, or Rh, and the adhesion layer is made of Cr, Ni, or Ti. Optionally, the first electrode 410 further includes an ohmic contact layer 03 in contact with the first semiconductor layer 201. This ohmic contact layer 03 is used to optimize the electrical contact between the first electrode 410 and the semiconductor layer, improving current transmission capability.

[0108] Example 2

[0109] This embodiment provides a light-emitting diode, as shown in the reference. Figure 4 and Figure 5 The light-emitting diode includes a substrate 100, a semiconductor stack 200, a first insulating layer 510, a first connecting electrode 601, a second insulating layer 700, and a first pad 801.

[0110] Reference Figure 5 The substrate 100 is the growth substrate 100 of the semiconductor stack 200. Optionally, the material of the substrate 100 can be sapphire, silicon carbide, silicon, or gallium nitride. In this embodiment, the substrate 100 is a sapphire substrate 100.

[0111] Reference Figure 5A semiconductor stack 200 is disposed on the surface of a substrate 100. The semiconductor stack 200 includes a first semiconductor layer 201, an active layer 202, and a second semiconductor layer 203 stacked sequentially on the surface of the substrate 100. The semiconductor stack 200 has a portion of the surface of the first semiconductor layer 201 exposed. The shape of the exposed surface of the first semiconductor layer 201 can be arbitrary. In this embodiment, a plurality of electrode holes 411 are disposed on the semiconductor stack 200. Each electrode hole 411 extends downward from the second semiconductor layer 203 on the surface of the semiconductor stack 200, penetrates the active layer 202, and reaches the surface of the first semiconductor layer 201, with the exposed first semiconductor layer 201 serving as the bottom surface of the electrode hole. Optionally, the shape of the electrode hole 411 can be circular. Current deep ultraviolet (DUV) LEDs suffer from drawbacks such as high operating voltage. Specifically, because the epitaxial layer of a DUV LED is doped with a high concentration of Al, it is difficult to form an ohmic contact at the N-terminal epitaxial layer. Furthermore, the material properties of the LED itself limit the lateral propagation of current within the epitaxial layer, resulting in a high overall operating voltage. In this embodiment, the LED is a deep ultraviolet LED. To reduce the voltage of the deep ultraviolet LED, several electrode holes 411 on the semiconductor stack 200 completely penetrate the first semiconductor layer 201 and expose the surface of the substrate 100. This increases the contact between the electrodes and the first semiconductor layer 201, improves the lateral current propagation capability, and reduces the voltage.

[0112] Reference Figure 5 and Figure 6 A first insulating layer 510 covers the surface of the semiconductor stack 200 and has a first opening 501 on the surface of the exposed first semiconductor layer 201 of the semiconductor stack 200. A first connecting electrode 601 covers the first insulating layer 510, fills the first opening 501, and is electrically connected to the first semiconductor layer 201 through the first opening 501. Optionally, the first connecting electrode 601 includes a metal stack 02 and a first adhesion layer 01 in sequence on the side near the semiconductor stack 200. It should be noted that other layers may also be included between the first connecting electrode 601 disposed in the first opening 501 and the exposed first semiconductor layer 201 in the first opening 501, or the first connecting electrode 601 may be directly formed on the first semiconductor layer 201 in the first opening 501, as long as an electrical connection can be formed between the first connecting electrode 601 and the first semiconductor layer 201.

[0113] In this embodiment, refer to Figure 6A first contact electrode 602 is also disposed on the surface of the first semiconductor layer 201 exposed by the first opening 501. The first connection electrode 601 is disposed on the first insulating layer 510 and fills the first opening 501, covering the first contact electrode 602 within the first opening 501. The first contact electrode 602 is disposed above the first semiconductor layer 201 exposed by the electrode hole 411 and fills the electrode hole 411. The first contact electrode 602 sequentially includes a metal stack 02 and a first adhesion layer 01 on the surface of the exposed first semiconductor layer 201. Optionally, the metal stack 02 includes an etch stop layer 021 near the first adhesion layer 01 and other metal layers 022 near the semiconductor stack 200. In this case, the first opening 501 partially penetrates the etch stop layer 021 of the first contact electrode 602, exposing the etch stop layer 021 of the first contact electrode 602 to the bottom wall of the first opening 501. In other embodiments, the first contact electrode 602 may not be provided on the surface of the first semiconductor layer 201 exposed in the first opening 501, so that the first connection electrode 601 directly forms an electrical contact with the first semiconductor layer 201 exposed in the first opening 501.

[0114] Reference Figure 7 A second insulating layer 700 covers the first connecting electrode 601. A third opening 502 is formed on the second insulating layer 700, penetrating the second insulating layer 700 and the first adhesive layer 01 of the first connecting electrode 601, and exposing the metal stack 02 of the first connecting electrode 601. Similarly, removing the first adhesive layer 01 of the first connecting electrode 601 exposed in the third opening 502 can prevent surface oxidation of the exposed first adhesive layer 01, which would affect the bonding strength of the subsequent pads formed in the third opening 502, and at the same time avoid affecting the electrical performance of the chip.

[0115] Optionally, refer to Figure 7 The metal stack 02 of the first connecting electrode 601 also includes an etch stop layer 021 near the first adhesion layer 01 and other metal layers 022 near the semiconductor stack 200. The third opening 502 partially penetrates the etch stop layer 021 of the first connecting electrode 601, so that the bottom wall of the third opening 502 exposes the etch stop layer 021 of the first connecting electrode 601.

[0116] Reference Figure 7 The first pad 801 is disposed above the third opening 502 of the second insulating layer 700, filling the third opening 502 and contacting the metal stack 02 of the first connecting electrode 601 exposed by the third opening 502. Optionally, a second adhesion layer 900 is further disposed between the second insulating layer 700, the third opening 502 and the first pad 801. The second adhesion layer 900 can increase the bonding force between the first pad 801 and the second insulating layer 700.

[0117] In this embodiment, refer to Figure 5 , 6 7. The first opening 501 may be located below the first pad 801 and / or below the second pad 802, and the third opening 502 may be located below the first pad 801. The first opening 501 located below the first pad 801 and / or below the second pad 802 may be connected via a first connecting electrode 601 to a first contact electrode 602 within the third opening 502 below the first pad 801, thus forming an electrical connection with the first pad 801.

[0118] Optionally, the opening widths of the first opening 501 and the third opening 502 are equal or gradually decrease in the direction from the first connecting electrode 601 to the first semiconductor layer 201. In this embodiment, referring to... Figure 6 The first opening 501 has a uniform width in the direction from the first connecting electrode 601 to the first semiconductor layer 201. The third opening 502 has a gradually decreasing width in the direction from the first connecting electrode 601 to the first semiconductor layer 201. Optionally, the angle α between the sidewall and the bottom wall of the third opening 502 is greater than 90°, for example, 120~160°.

[0119] In this embodiment, refer to Figure 7 The light-emitting diode also includes a second electrode 420. The second electrode 420 is disposed on the second semiconductor layer 203 of the semiconductor stack 200. The second electrode 420 sequentially includes a metal stack 02 and a first adhesion layer 01 on the surface of the second semiconductor layer 203. The metal stack 02 further includes an etch stop layer 021 near the first adhesion layer 01 and other metal layers 022 near the semiconductor stack 200. Optionally, a transparent conductive layer 300 is further disposed between the second semiconductor layer 203 and the second electrode 420.

[0120] Reference Figure 8 Above the second electrode 420, a second opening 701 and a fourth opening 702 are respectively provided. The second opening 701 is located on the first insulating layer 510 corresponding to the second electrode 420. The second opening 701 penetrates the first insulating layer 510 and the first adhesive layer 01 of the second electrode 420, exposing the metal stack 02 of the second electrode 420. Removing the first adhesive layer 01 of the second electrode 420 at the location of the second opening 701 can also prevent the exposed first adhesive layer 01 from undergoing an oxidation reaction, which would affect the bonding force between the second pad 802 subsequently formed within the second opening 701 and the first adhesive layer 01, and also avoid the impact of the generated oxide layer on the electrical properties of the chip.

[0121] Optionally, refer to Figure 8The metal stack 02 of the second electrode 420 also includes an etch stop layer 021 near the first adhesion layer 01 and other metal layers 022 near the semiconductor stack 200. In this case, the second opening 701 partially penetrates the etch stop layer 021 of the second electrode 420, exposing the bottom wall of the second opening 701 to the etch stop layer 021 of the second electrode 420. A fourth opening 702 is disposed in the second insulating layer 700 at a position corresponding to the second opening 701, penetrating the second insulating layer 700.

[0122] Reference Figure 9 The second pad 802 is disposed above the second opening 701 and the fourth opening 702, and is spaced apart from the first pad 801. It fills the second opening 701 and the fourth opening 702, and forms contact with the metal stack 02 of the second electrode 420 exposed by the second opening 701 and the fourth opening 702. Optionally, a second adhesion layer 900 is further disposed between the second pad 802 and the second opening 701, the fourth opening 702 and the second insulating layer 700.

[0123] The maximum width of the second opening 701 is less than or equal to the minimum width of the fourth opening 702. For example, the opening width of the second opening 701 in the direction from the second pad 802 to the second electrode 420 is equal or gradually decreases, and the opening width of the fourth opening 702 in the direction from the second pad 802 to the second electrode 420 is equal or gradually decreases.

[0124] In one example, refer to Figure 8 The width of the fourth opening 702 gradually decreases in the direction from the second pad 802 to the second electrode 420. The lower opening of the fourth opening 702 has the same width as the upper opening of the second opening 701, and the width of the second opening 701 gradually decreases in the direction from the second pad 802 to the second electrode 420. Optionally, the angle α between the sidewall and the bottom wall of the second opening 701 is greater than 90°, and the angle α between the sidewall and the bottom wall of the fourth opening 702 is greater than 90°. For example, 120°~160°.

[0125] In one example, refer to Figure 9 The fourth opening 702 has the same width in the direction from the second pad 802 to the second electrode 420. The lower opening of the fourth opening 702 has a wider opening than the upper opening of the second opening 701, forming a horizontal platform 703 between the fourth opening 702 and the second opening 701. The opening width of the second opening 701 gradually decreases in the direction from the second pad 802 to the second electrode 420. The angle α between the sidewall and the bottom wall of the second opening 701 is greater than 90°, for example, 120°~160°.

[0126] Optionally, the thickness of the first adhesion layer 01 ranges from 1 to 300 nm, for example, 100 to 300 nm. The material of the first adhesion layer 01 includes Cr, Ni, or Ti. The material of the etch stop layer 021 includes Pt, Ni, Ti, Cr, Rh, Ru, Mo, W, or Cu. Optionally, all metal stacks 02 also include other metal layers 022 located between the etch stop layer 021 and the semiconductor stack 200. The other metal layers 022 include, but are not limited to, adhesion layers, thermally conductive layers, barrier layers, planarization layers, reflective layers, and adhesion layers (not shown in the figure). Optionally, the material of the reflective layer is Al or Ag, the material of the planarization layer is Ti, Rh, Ru, Mo, W, or Cu, the material of the barrier layer is Pt, Rh, or Ru, the material of the thermally conductive layer is Au, Cu, or Rh, and the material of the adhesion layer includes Cr, Ni, or Ti. Optionally, the first electrode 410 also includes an ohmic contact layer 03 to improve current transmission capability.

[0127] In one example, refer to Figure 8 The second opening 701 formed on the first insulating layer 510 and the fourth opening 702 formed on the second insulating layer 700 are formed in a single etching step. That is, after the first insulating layer 510 and the second insulating layer 700 are formed respectively, the second opening 701 and the fourth opening 702 are formed in a single etching step. (Refer to...) Figure 7 and 8At this point, the maximum width of the second opening 701 is equal to the minimum width of the fourth opening 702, and the thickness of the etch stop layer 021 of the first connecting electrode 601 is greater than or equal to the thickness of the etch stop layer 021 of the second electrode 420. The etch stop layer 021 of the first connecting electrode 601 of the light-emitting diode formed using this process needs to be thicker because, during the etching process to form the fourth opening 702 and the second opening 701, the area covered by the second pad 802 needs to have the fourth opening 702 etched on the second insulating layer 700 before the second opening 701 can be etched on the first insulating layer 510 to expose the lower second electrode 420. Simultaneously, the area covered by the first pad 801 is also etched synchronously. After the third opening 502 is etched on the second insulating layer 700, the lower first connecting electrode 601 is etched synchronously. Therefore, the etching stop layer 021 of the first connecting electrode 601 needs to be thickened to ensure that the area covered by the second pad 802 can be cleanly etched during synchronous etching, while avoiding over-etching of the first connecting electrode 601 below the first pad 801. Furthermore, since the second electrode 420 is a metal conductive layer in direct contact with the transparent conductive layer, the etching stop layer 021 needs to have a certain thickness to avoid affecting current conduction due to over-etching. Therefore, the thickness of the etching stop layer 021 of the second electrode 420 can also be increased to be equal to the thickness of the etching stop layer 021 of the first connecting electrode 601. Optionally, the thickness of the etching stop layer 021 of the first connecting electrode 601 ranges from 60 to 1000 nm, for example, 100 to 500 nm. The thickness of the etching stop layer 021 of the second electrode 420 ranges from 50 to 800 nm, for example, 100 to 300 nm.

[0128] In one example, refer to Figure 9The first insulating layer 510 and the second insulating layer 700 are etched in stages to form the fourth opening 702 and the second opening 701. In this process, the maximum width of the second opening 701 is generally smaller than the minimum width of the fourth opening 702, and the thickness of the etching stop layer 021 of the second electrode 420 is greater than the thickness of the etching stop layer 021 of the first connecting electrode 601. When the fourth opening 702 and the second opening 701 are formed by staged etching, the steps are: after forming the first insulating layer 510, the second opening 701 is etched on the first insulating layer 510; then, the second insulating layer 700 is formed on the first insulating layer 510 where the second opening 701 is formed; and then the fourth opening 702 is formed. Thus, the etching stop layer 021 on the second electrode 420 requires two etching operations, so its thickness needs to be thicker than the etching stop layer 021 in a single etching process that forms the fourth opening 702 and the second opening 701. On the one hand, since the second electrode 420 is a metal conductive layer in direct contact with the transparent conductive layer, the etching stop layer 021 needs to have a certain thickness to avoid affecting current conduction due to over-etching. On the other hand, since the second opening 701 needs to be etched on the first insulating layer 510 first, and then the fourth opening 702 needs to be etched on the second insulating layer 700 during step etching, the etching stop layer 021 of the second electrode 420 will undergo two etching processes. Therefore, the etching stop layer 021 of the second electrode 420 needs to be thickened to avoid over-etching of the second electrode after two etching processes. Optionally, the thickness of the etching stop layer 021 of the first connecting electrode 601 is between 50 and 800 nm, for example, 100 to 300 nm. The thickness of the etching stop layer 021 of the second electrode 420 is between 60 and 1000 nm, for example, 100 to 500 nm.

[0129] Optionally, when the first insulating layer 510 and the second insulating layer 700 form the fourth opening 702 and the second opening 701 through step-by-step etching, in order to avoid affecting current conduction due to over-etching, the thickness of the etching stop layer 021 of the second electrode 420 can be increased, and the thickness of the etching stop layer 021 of the second electrode 420 during step-by-step etching is greater than the thickness of the etching stop layer 021 of the second electrode 420 during one-step etching. When the first insulating layer 510 and the second insulating layer 700 form the fourth opening 702 and the second opening 701 through one-step etching, in order to avoid over-etching of the first connection electrode 601 below the first pad 801, the thickness of the etching stop layer 021 of the first connection electrode 601 can be increased, and the thickness of the etching stop layer 021 of the first connection electrode 601 during one-step etching is greater than the thickness of the etching stop layer 021 of the first connection electrode 601 during step-by-step etching.

[0130] Optionally, in this embodiment, reference is made to Figure 3bThe metal stack 02 / etch stop layer 021 also has a first horizontal surface 0211 covered by the insulating layer 500, a second horizontal surface 0212 located within the first opening 501, and an inclined surface 0213 connecting the first horizontal surface 0211 and the second horizontal surface 0212; the first horizontal surface 0211 and the second horizontal surface 0212 are substantially parallel to the surface of the first semiconductor layer 201; the included angle α1 between the inclined surface 0213 and the second horizontal surface 0212 is greater than 90°. For example, 120°~179°, preferably 140°~179°. This is more conducive to increasing the contact area between the first pad 801 and the metal stack 02, and improving the bonding performance between the first pad 801 and the metal stack 02 within the first opening 501. See the specific illustration for details. Figure 3b This will not be elaborated upon here.

[0131] Further, optionally, in this embodiment, the angle between the inclined surface 0213 of the metal stack 02 and the second horizontal surface 0212 of the metal stack 02 is greater than the angle between the sidewall of the first insulating layer 510 located at the first opening 501 / second opening 701 and the second horizontal surface 0212 of the metal stack 02; the angle between the inclined surface 0213 of the metal stack 02 and the second horizontal surface 0212 of the metal stack 02 is greater than the angle between the sidewall of the second insulating layer 700 located at the third opening 502 / fourth opening 702 and the second horizontal surface 0212 of the metal stack 02. For example, the angle between the inclined surface 0213 of the metal stack 02 and the second horizontal surface 0212 of the metal stack 02 is 160°~179°; the angle between the sidewall of the first insulating layer 510 located at the first opening 501 / second opening 701 and the second horizontal surface 0212 of the metal stack 02 is 120°~160°; and the angle between the sidewall of the second insulating layer 700 located at the third opening 502 / fourth opening 702 and the second horizontal surface 0212 of the metal stack 02 is 120°~160°. This allows the sidewall of the first opening 501 to form a two-stage inclined angle, with the inclination gradually decreasing from top to bottom. This further increases the overall contact area between the first pad 801 and the sidewall of the first opening 501, and also facilitates the subsequent coverage of the metal layer, preventing metal layer breakage. Thus, while improving the adhesion between the pad and the electrode, it also ensures the normal electrical performance of the chip. See the detailed illustration for reference. Figure 3b This will not be elaborated upon here.

[0132] Example 3

[0133] This embodiment provides a light-emitting diode (LED). The similarities between this LED and that of Embodiment 2 will not be repeated here. The difference lies in that, referring to… Figure 10 , 11In this embodiment, no first contact electrode 602 is provided between the first connecting electrode 601 and the first semiconductor layer 201 exposed in the first opening 501, and the first connecting electrode 601 is directly connected to the first semiconductor layer 201 exposed in the first opening 501.

[0134] Similarly, the maximum width of the second opening 701 is less than or equal to the minimum width of the fourth opening 702. For example, the opening width of the second opening 701 in the direction from the second pad 802 to the second electrode 420 is equal or gradually decreases, and the opening width of the fourth opening 702 in the direction from the second pad 802 to the second electrode 420 is equal or gradually decreases.

[0135] In one example, refer to Figure 12 The width of the fourth opening 702 gradually decreases in the direction from the second pad 802 to the second electrode 420, and the width of the lower opening of the fourth opening 702 is equal to the width of the upper opening of the second opening 701. Furthermore, the width of the second opening 701 gradually decreases in the direction from the second pad 802 to the second electrode 420. Optionally, the angle α between the sidewall and the bottom wall of the second opening 701 is greater than 90°, and the angle α between the sidewall and the bottom wall of the fourth opening 702 is greater than 90°. For example, 120°~160°.

[0136] In one example, refer to Figure 13 The width of the fourth opening 702 gradually decreases in the direction from the second pad 802 to the second electrode 420. The width of the lower opening of the fourth opening 702 is the same as the width of the upper opening of the second opening 701, forming a horizontal platform 703 between the fourth opening 702 and the second opening 701. The width of the second opening 701 also gradually decreases in the direction from the second pad 802 to the second electrode 420. Optionally, the angle α between the sidewall and the bottom wall of the second opening 701 is greater than 90°, and the angle α between the sidewall and the bottom wall of the fourth opening 702 is greater than 90°, for example, 120°~160°.

[0137] Same as in Example 2, refer to Figure 13 and 14The thickness of the etch stop layer 021 of the first connection electrode 601 located below the first pad 801 is greater than the thickness of the etch stop layer 021 of the first connection electrode 601 located below the second pad 802. This allows the area to be covered by the second pad 802 to be etched with the second opening 701 and the fourth opening 702 during synchronous etching, while the area to be covered by the first pad 801 only needs to be etched with the third opening 502 to complete the etching process. Furthermore, the third opening 502 also etches away the first adhesion layer 01 of the first connection electrode 601 and stops etching at the etch stop layer of the first connection electrode 601. The first pad 801 is formed within the third opening and forms an electrical connection with the etch stop layer of the first connection electrode 601.

[0138] Similar to Embodiment 2, in this embodiment, the metal stack 02 / etch stop layer 021 also has a first horizontal surface 0211 covered by the insulating layer 500, a second horizontal surface 0212 located within the first opening 501, and an inclined surface 0213 connecting the first horizontal surface 0211 and the second horizontal surface 0212; the first horizontal surface 0211 and the second horizontal surface 0212 are substantially parallel to the surface of the first semiconductor layer 201; the angle between the inclined surface 0213 and the second horizontal surface 0212 is greater than 90°. For example, 120°~179°, preferably 140°~179°, thereby improving the bonding performance between the first pad 801 and the metal stack 02 within the first opening 501. Furthermore, in this embodiment, the angle between the inclined surface 0213 of the metal stack 02 and the second horizontal surface 0212 of the metal stack 02 is greater than the angle between the sidewall of the first insulating layer 510 located at the first opening 501 / second opening 701 and the second horizontal surface 0212 of the metal stack 02; the angle between the inclined surface 0213 of the metal stack 02 and the second horizontal surface 0212 of the metal stack 02 is greater than the angle between the sidewall of the second insulating layer 700 located at the third opening 502 / fourth opening 702 and the second horizontal surface 0212 of the metal stack 02. For example, the angle between the inclined surface 0213 of the metal stack 02 and the second horizontal surface 0212 of the metal stack 02 is 160°~179°; the angle between the sidewall of the first insulating layer 510 located at the first opening 501 / second opening 701 and the second horizontal surface 0212 of the metal stack 02 is 120°~160°; and the angle between the sidewall of the second insulating layer 700 located at the third opening 502 / fourth opening 702 and the second horizontal surface 0212 of the metal stack 02 is 120°~160°. This improves the adhesion between the pads and electrodes while ensuring the normal electrical performance of the chip. See the detailed illustration for reference. Figure 3b This will not be elaborated upon here.

[0139] Example 4

[0140] This embodiment provides a light-emitting device, which includes any one of the light-emitting diodes in embodiments 1 to 3 above. Because this light-emitting device includes the aforementioned light-emitting diode, the bonding or adhesion between the pads and electrodes is better, resulting in higher reliability and superior electrical performance.

[0141] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A light-emitting diode, characterized in that, include: A semiconductor stack, comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially; The first electrode is disposed on the surface of the first semiconductor layer; The first electrode comprises a metal stack and a first adhesion layer sequentially on the surface of the first semiconductor layer; An insulating layer covers the semiconductor stack and the first electrode, and a first adhesive layer contacts the first electrode; The insulating layer has a first opening corresponding to the position of the first electrode. The first opening penetrates the insulating layer and the first adhesive layer of the first electrode and extends into the metal stack, such that the metal stack has a first horizontal surface covered by the insulating layer, a second horizontal surface located in the first opening, and an inclined surface connecting the first horizontal surface and the second horizontal surface. The second horizontal surface is lower than the first horizontal surface. The first adhesive layer is completely removed at the bottom of the first opening, thereby exposing the second horizontal surface and the inclined surface of the metal stack of the first electrode. A second adhesive layer covers at least the first opening, the metal stack covering the first electrode exposed by the first opening, and the insulating layer located on the sidewall inside the first opening; A first pad is disposed above and fills the first opening of the insulating layer, and contacts the metal stack of the first electrode exposed by the first opening through the second adhesive layer.

2. The light-emitting diode according to claim 1, characterized in that, The metal stack also includes an etch stop layer near the first adhesion layer and other metal layers near the semiconductor stack.

3. The light-emitting diode according to claim 2, characterized in that, The first opening penetrates a portion of the etch stop layer of the first electrode, and the bottom wall of the first opening exposes the etch stop layer.

4. The light-emitting diode according to claim 1, characterized in that, The light-emitting diode also includes: A second adhesion layer is disposed between the first pad and the insulating layer and the metal stack of the first electrode.

5. The light-emitting diode according to claim 1, characterized in that, The angle between the sidewall of the first opening and the bottom wall of the first opening is greater than 90°.

6. The light-emitting diode according to claim 1, characterized in that, The first horizontal surface and the second horizontal surface are parallel to the surface of the first semiconductor layer; the angle between the inclined surface and the second horizontal surface is greater than 90°.

7. The light-emitting diode according to claim 6, characterized in that, The angle between the inclined surface of the metal stack and the second horizontal surface of the metal stack is greater than the angle between the sidewall of the insulating layer located at the first opening and the second horizontal surface of the metal stack.

8. The light-emitting diode according to claim 2, characterized in that, The material of the etching stop layer includes Pt, Ni, Ti, Cr, Rh, Ru, Mo, W or Cu.

9. A light-emitting diode, characterized in that, include: A semiconductor stack, comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially; The semiconductor stack has a portion of its surface that exposes the first semiconductor layer; A first insulating layer covers the surface of the semiconductor stack and has a first opening on the surface of the first semiconductor layer exposed in the semiconductor stack; A first connecting electrode covers the first insulating layer, fills the first opening, and is electrically connected to the first semiconductor layer through the first opening; The first connection electrode includes a metal stack and a first adhesion layer on the side closest to the semiconductor stack; A second insulating layer covers the first connecting electrode. A third opening is formed on the second insulating layer, which penetrates the second insulating layer and the first adhesive layer of the first connecting electrode and extends into the metal stack. The metal stack has a first horizontal surface covered by the second insulating layer, a second horizontal surface located in the third opening, and an inclined surface connecting the first horizontal surface and the second horizontal surface. The second horizontal surface is lower than the first horizontal surface. The first adhesive layer is completely removed at the bottom of the third opening, thereby exposing the second horizontal surface and the inclined surface of the metal stack of the first connecting electrode. The second adhesion layer covers at least the third opening, covering the metal stack of the first connecting electrode exposed by the third opening and the sidewall of the insulating layer located within the third opening; A first pad is disposed above a third opening in the second insulating layer, fills the third opening, and contacts the metal stack of the first connecting electrode exposed by the third opening through the second adhesive layer.

10. The light-emitting diode according to claim 9, characterized in that, The light-emitting diode also includes: A first contact electrode is disposed on the surface of the first semiconductor layer exposed by the semiconductor stack and exposed within the first opening; the first contact electrode comprises a metal stack and a first adhesive layer sequentially on the surface of the exposed first semiconductor layer; the first opening penetrates the first insulating layer and the first adhesive layer of the first contact electrode, exposing the metal stack of the first contact electrode; the first connecting electrode contacts the metal stack of the first contact electrode exposed within the first opening.

11. The light-emitting diode according to claim 10, characterized in that, The light-emitting diode also includes: Electrode holes are spaced out on the surface of the semiconductor stack, and the electrode holes penetrate or partially penetrate the first semiconductor layer; the first contact electrode is disposed on the first semiconductor layer exposed by the electrode holes and fills the electrode holes.

12. The light-emitting diode according to claim 9, characterized in that, The light-emitting diode also includes: The second pad is disposed above the second insulating layer and spaced apart from the first pad. The second pad is electrically connected to the second semiconductor layer. The first opening is disposed below the first pad and / or below the second pad, and the third opening is disposed below the first pad.

13. The light-emitting diode according to claim 9 or 10, characterized in that, The light-emitting diode also includes: The second electrode is disposed on the second semiconductor layer of the semiconductor stack; the second electrode comprises a metal stack and a first adhesion layer sequentially on the surface of the second semiconductor layer. The first insulating layer further includes a second opening disposed at a position on the first insulating layer corresponding to the second electrode. The second opening penetrates the first insulating layer and the first adhesive layer of the second electrode, exposing the metal stack of the second electrode. The second insulating layer further includes a fourth opening, which is disposed in the second insulating layer at a position corresponding to the second opening and penetrates the second insulating layer; The second pad is disposed above the second opening and the fourth opening, and is spaced apart from the first pad. It fills the second opening and the fourth opening, and forms contact with the metal stack of the second electrode exposed by the second opening and the fourth opening.

14. The light-emitting diode according to claim 13, characterized in that, The width of the fourth opening in the direction from the second pad to the second electrode is equal or gradually decreases; the width of the second opening in the direction from the second pad to the second electrode is equal or gradually decreases; the width of the third opening in the direction from the first pad to the first connecting electrode is equal or gradually decreases; and the width of the first opening in the direction from the first connecting electrode to the first semiconductor layer is equal or gradually decreases.

15. The light-emitting diode according to claim 14, characterized in that, The maximum width of the second opening is less than or equal to the minimum width of the fourth opening.

16. The light-emitting diode according to claim 15, characterized in that, The angle between the sidewall of the first opening and the bottom wall of the first opening is greater than 90°; the angle between the sidewall of the third opening and the bottom wall of the third opening is greater than 90°; the angle between the sidewall of the second opening and the bottom wall of the second opening is greater than 90°; and the angle between the sidewall of the fourth opening and the bottom wall of the fourth opening is greater than 90°.

17. The light-emitting diode according to claim 1 or 9, characterized in that, The thickness of the first adhesion layer ranges from 1 to 300 nm.

18. The light-emitting diode according to claim 13, characterized in that, The metal stack also includes an etch stop layer near the first adhesion layer and other metal layers near the semiconductor stack.

19. The light-emitting diode according to claim 10, characterized in that, The first opening penetrates the etch stop layer of the first contact electrode, exposing the bottom wall of the first opening to the etch stop layer of the first contact electrode. The third opening penetrates the etch stop layer of the first connecting electrode, exposing the bottom wall of the third opening to the etch stop layer of the first connecting electrode.

20. The light-emitting diode according to claim 13, characterized in that, The second opening penetrates the etch stop layer of the second electrode, exposing the bottom wall of the second opening to the etch stop layer of the second electrode.

21. The light-emitting diode according to claim 2 or 18, characterized in that, The thickness of the etch stop layer ranges from 50 to 1000 nm.

22. The light-emitting diode according to claim 13, characterized in that, The light-emitting diode also includes: A transparent conductive layer is disposed between the second semiconductor layer and the second electrode.

23. The light-emitting diode according to claim 13, characterized in that, The thickness of the etch stop layer of the second electrode is greater than the thickness of the etch stop layer of the first connecting electrode or the first contact electrode.

24. The light-emitting diode according to claim 13, characterized in that, When the maximum width of the second opening is less than the minimum width of the fourth opening, the thickness of the etch stop layer of the second electrode is greater than the thickness of the etch stop layer of the first connecting electrode.

25. The light-emitting diode according to claim 13, characterized in that, When the maximum width of the second opening is equal to the minimum width of the fourth opening, the thickness of the etch stop layer of the first connecting electrode is greater than or equal to the thickness of the etch stop layer of the second electrode.

26. The light-emitting diode according to claim 13, characterized in that, The light-emitting diode further includes: a second adhesive layer disposed on the second insulating layer and filling the second opening, and the first pad disposed on the second adhesive layer; the second adhesive layer also fills the third opening and the fourth opening, and the second pad is disposed on the second adhesive layer.

27. The light-emitting diode according to claim 1 or 9, characterized in that, The material of the first adhesion layer includes Cr, Ni or Ti.

28. The light-emitting diode according to claim 18, characterized in that, The material of the etching stop layer includes Pt, Ni, Ti, Cr, Rh, Ru, Mo, W or Cu.

29. A light-emitting device, characterized in that, The light-emitting device includes a light-emitting diode as described in any one of claims 1 to 28.

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