A method for reference clock phase synchronization and fine adjustment and a pulse generator

Abstract

The present invention discloses a method for reference clock phase synchronization and fine adjustment and a pulse generator. The method includes: Step 3, the host computer or the accelerator control system issues parameter configuration; Step 4, determine the reference clock selection mode; Step 5, when an external reference clock is selected, the pulse generator receives an external reference clock signal with a frequency of 10 MHz to 500 MHz; Step 6, according to the pulse parameter values set in Step 3, calculate the theoretically pulse repetition frequency count value, pulse width count value, and pulse delay count value. The present invention calculates the theoretically pulse repetition frequency count value, pulse width count value, and pulse delay count value through the parameter configuration issued by the host computer or the accelerator control system, enabling the pulse generator to generate stable and adjustable pulse signals with ns-level precision and to maintain phase synchronization with the input reference clock under different working conditions to meet different particle acceleration and control requirements.

Description

Technical Field

[0001] The present invention relates to bit synchronization and a finely adjustable pulse generator, and specifically to a method and a pulse generator for reference clock phase synchronization and fine adjustment. Background Art

[0002] In an accelerator system, precise phase synchronization and an adjustable pulse generator are crucial for achieving high-precision particle acceleration and control.

[0003] An accelerator system usually consists of multiple components or subsystems, and multiple components or subsystems all need to use pulse signals for accelerating and controlling a particle beam. To ensure precise timing control and coordinated operation of these pulse signals, a phase synchronization pulse generator is widely used.

[0004] The main function of a phase synchronization pulse generator is to synchronize output pulses to a specific phase relationship of an input reference clock. Therefore, this pulse generator can provide a unified clock reference signal for multiple accelerator systems, as well as clock signals with different frequencies having a coherent relationship required by each system.

[0005] On the other hand, an adjustable pulse generator is also an important part of an accelerator system.

[0006] An adjustable pulse generator can flexibly adjust various parameters of an output timing signal according to specific application requirements, including pulse width, pulse delay, repetition frequency, output amplitude, etc., and the adjustment precision of the pulse width and delay can both reach the ns level.

[0007] By synchronizing with the input reference clock phase and finely adjusting the output pulse signal, each system in the accelerator device can work properly at the set delay moment, thereby achieving precise timing control, which is very important for key operations such as particle injection, acceleration, and beam diagnosis in the accelerator device.

[0008] Therefore, how to make each system in the accelerator device work properly at the set delay moment through phase synchronization with the input reference clock and fine adjustment of the output pulse signal, so as to achieve a precise timing control method, is a problem that needs to be solved currently. Summary of the Invention

[0009] Object of the Invention: To provide a method and a pulse generator for reference clock phase synchronization and fine adjustment to solve the above problems existing in the prior art.

[0010] Technical Solution: A method for reference clock phase synchronization and fine adjustment includes:

[0011] Step 1, initializing the pulse generator device;

[0012] Step 2: The host computer or the accelerator control system establishes a communication connection with the pulse generator;

[0013] Step 3: The host computer or the accelerator control system issues parameter configurations, including reference clock selection, the repetition operating frequency of the generated pulse signal, the width value of the generated pulse signal, and the relative delay value of the generated pulse signal;

[0014] Step 4: Determine the reference clock selection mode;

[0015] Step 5: When selecting to input an external reference clock, the pulse generator receives an external reference clock signal with a frequency of 10 MHz to 500 MHz;

[0016] When selecting the internal clock reference, the internal 125 MHz reference clock on the FPGA is used;

[0017] Step 6: According to the pulse parameter values set in Step 3, calculate the theoretically pulse repetition frequency count value, pulse width count value, and pulse delay count value;

[0018] Calculation of the pulse repetition frequency count value: To achieve phase synchronization between the pulse output signal and the reference clock, the pulse repetition frequency count value should be , otherwise the pulse output signal cannot be phase-locked and synchronized with the reference clock signal;

[0019] where is the input reference clock value, is the pulse repetition frequency value set by the host computer, is the 125 MHz operating clock of the FPGA, is the operating cycle of the FPGA ( ), which is implemented through the internal counting module of the FPGA.

[0020] Calculation of the pulse width count value: The performances of different FPGAs are different, and the highest internal logic operating clock generally does not exceed 300 MHz. Then, the resolution of counting through the FPGA is 3.3 ns, so ns-level accuracy cannot be obtained. Based on the DDR mode of the FPGA OSERDESE3 module to complete the serial output of 8-bit parallel data, design the input clock of the FPGA OSERDESE3 module to be 125 MHz. Then, after the parallel-to-serial conversion, the data transmission rate can reach 1000 Mb / s, and ns-level pulse width adjustment accuracy is achieved through cascading.

[0021] Specifically, calculate the pulse width count value (8 bits) according to the pulse width value set in Step 3, and call the OSERDESE3 module to achieve ns-level adjustable accuracy of the pulse signal;

[0022] Calculation of the pulse delay counter value: To achieve higher delay adjustment accuracy, first, the 8-bit parallel data is serially output based on the DDR mode of the FPGA OSERDESE3 module, so that the data transfer rate reaches 1000 Mb / s. Then, based on the FPGA ODELAYE3 module, the ps-level delay adjustment accuracy of the pulse output signal is achieved.

[0023] Specifically, the pulse delay counter value (8 bits) is calculated according to the pulse delay value set in step 3, and the OSERDESE3 module is called to achieve the adjustable accuracy of the pulse signal at the ns level. For delays with an accuracy higher than the ns level, the counter value is passed to the ODELAYE3 module for delay.

[0024] Step 7: When the pulse signal is calibrated, the pulse signal of the corresponding channel is output.

[0025] Through the parameters configured by the host computer or the accelerator control system, the present invention calculates the theoretically pulse repetition frequency counter value, pulse width counter value, and pulse delay counter value, enabling the pulse generator to generate stable and adjustable pulse signals with ns-level accuracy and to maintain phase synchronization with the input reference clock under different working conditions to meet different particle acceleration and control requirements.

[0026] In a further embodiment, the method for outputting the 125 MHz clock signal of the phase synchronization unit in step 5 further includes:

[0027] Step A: Input the external reference clock signal into the external input port of the pulse generator.

[0028] Step B: Initially configure or modify the control register configuration parameters. The phase synchronization unit saves the correct configuration parameters to the EEPROM. When powering on again next time, the pulse generator can load the configuration parameters saved in the EEPROM before and enter the phase synchronization mode to maintain the same configuration and output characteristics.

[0029] Step C: As needed, use the frequency divider module to divide the input external reference clock signal.

[0030] Step D: The adjustable delay unit compensates for the edge timing delay caused by the frequency divider.

[0031] Step E: The frequency divider in the PLL feedback circuit divides the clock signal to 125 MHz. The PLL module monitors the phase and propagation delay of the output clock and adjusts through real-time feedback control to achieve stable alignment of the output clock with the reference clock.

[0032] A pulse generator for reference clock phase synchronization and fine adjustment, comprising:

[0033] At least one phase synchronization fine-adjustable pulse generator;

[0034] The phase synchronization fine-adjustable pulse generator includes an interface module and a control module;

[0035] The interface module is used to receive an external clock reference signal, a Gate signal, and an external trigger signal;

[0036] The control module includes a host computer, an FPGA, an RS232 interface, and an Ethernet interface;

[0037] Output channels for multiple pulse signals, which are connected to the FPGA.

[0038] Among them, the external clock reference signal, the Gate signal, and the external trigger signal are received and converted by the high-speed comparator on the interface module to complete the corresponding level reception and then sent to the control module.

[0039] Beneficial effects: The present invention discloses a method and a pulse generator for reference clock phase synchronization and fine adjustment. The present invention calculates the theoretically pulse repetition frequency count value, pulse width count value, and pulse delay count value through the parameter configuration issued by the host computer or the accelerator control system, enabling the pulse generator to generate stable and adjustable pulse signals with ns-level precision, and being able to maintain phase synchronization with the input reference clock under different working conditions to meet different particle acceleration and control requirements. Description of the Drawings

[0040] Figure 1 It is the working flow chart of the pulse generator of the present invention.

[0041] Figure 2 It is the flow chart of outputting a pulse signal with an adjustable repetition frequency and phase synchronization with the reference clock of the present invention.

[0042] Figure 3 It is the flow chart of outputting a pulse signal with an ns-level pulse width adjustment accuracy of the present invention.

[0043] Figure 4 It is the flow chart of outputting a pulse signal with a ps-level delay adjustment accuracy of the present invention.

[0044] Figure 5 It is the schematic diagram of realizing the phase invariance of the reference clock signal based on the phase synchronization unit of the present invention.

[0045] Figure 6 It is the timing diagram of the phase synchronization unit of the present invention.

[0046] Figure 7It is the flowchart of the 125MHz clock signal operation of the output phase synchronization unit of the present invention.

[0047] Figure 8 It is the schematic diagram of the pulse generator of the present invention. Specific embodiments

[0048] This application relates to a method and a pulse generator for reference clock phase synchronization and fine adjustment. The following is a detailed explanation through specific embodiments.

[0049] A method for reference clock phase synchronization and fine adjustment includes:

[0050] Step 1, initialize the pulse generator device;

[0051] Step 2, establish a communication connection between the host computer or the accelerator control system and the pulse generator;

[0052] Step 3, the host computer or the accelerator control system issues parameter configurations, including reference clock selection, the repetition working frequency of the generated pulse signal, the width value of the generated pulse signal, and the relative delay value of the generated pulse signal;

[0053] Step 4, determine the reference clock selection mode;

[0054] Step 5, when an external reference clock is selected, the pulse generator receives an external reference clock signal with a frequency of 10MHz to 500MHz;

[0055] When the internal clock reference is selected, the internal 125MHz reference clock on the FPGA is used;

[0056] Step 6, according to the pulse parameter values set in Step 3, calculate the theoretically pulse repetition frequency count value, pulse width count value, and pulse delay count value;

[0057] Calculation of the pulse repetition frequency count value: To achieve phase synchronization between the pulse output signal and the reference clock, the pulse repetition frequency count value should be , otherwise the pulse output signal cannot be phase-locked and synchronized with the reference clock signal;

[0058] where is the input reference clock value, is the pulse repetition frequency value set by the host computer, is the 125MHz working clock of the FPGA, is the working cycle of the FPGA ( ), which is implemented through the internal counting module of the FPGA.

[0059] Calculation of pulse width count value: Different FPGAs have different performances. The maximum internal logic operating clock generally does not exceed 300 MHz. Then, the resolution of counting through the FPGA is 3.3 ns. Therefore, ns-level accuracy cannot be obtained. Based on the DDR mode of the FPGA OSERDESE3 module, 8-bit parallel data is serially output. The input clock of the FPGA OSERDESE3 module is designed to be 125 MHz. Then, after parallel-to-serial conversion, the data transmission rate can reach 1000 Mb / s, and ns-level pulse width adjustment accuracy is achieved through cascading.

[0060] Specifically, the pulse width count value (8 bits) is calculated according to the pulse width value set in step 3, and the OSERDESE3 module is called to achieve ns-level adjustable accuracy of the pulse signal.

[0061] Calculation of pulse delay count value: To achieve higher delay adjustment accuracy, first, 8-bit parallel data is serially output based on the DDR mode of the FPGA OSERDESE3 module, so that the data transmission rate reaches 1000 Mb / s. Then, the FPGA ODELAYE3 module is used to achieve ps-level delay adjustment accuracy of the pulse output signal.

[0062] Specifically, the pulse delay count value (8 bits) is calculated according to the pulse delay value set in step 3, and the OSERDESE3 module is called to achieve ns-level adjustable accuracy of the pulse signal. For delays with accuracy higher than ns level, the count value is passed to the ODELAYE3 module for delay.

[0063] Step 7: When the pulse signal is calibrated, the pulse signal of the corresponding channel is output.

[0064] In the accelerator, to ensure that the radio frequency acceleration phases of the particles are consistent, it is required that the phase relationship between the rising edge of the trigger pulse signal and the external reference clock signal is the same every time the power is turned on and does not change. Otherwise, phase calibration needs to be performed every time the pulse generator is powered on again. To ensure that the phase relationship between the rising edge of the output pulse and the external input reference source is the same every time the power is turned on, since the internal processing logic time of the FPGA is fixed, it is necessary to ensure that the phase between the reference clock signal input to the pulse generator and the clock of the external reference source is the same every time the power is turned on.

[0065] Since the radio frequency operating frequency of the accelerator varies depending on the type of accelerator, the frequencies of the external reference signals input to the pulse generator are different (generally 10 MHz to 500 MHz). Therefore, a PLL-based phase synchronization unit is designed to align the edges of the output signal with the edges of the reference source. When the input frequency is higher than 250 MHz, since the input reference frequency of the phase-locked loop is generally 10 MHz to 250 MHz, a frequency divider needs to be added before the phase-locked loop to make the external reference source adapt to the phase detection input frequency of the phase-locked loop.

[0066] Specifically, as shown in the appendix Figure 5 shown, the appendix Figure 5 mainly contains four modules, namely the frequency divider module, the adjustable delay unit, the phase-locked loop (Phase-Locked Loop, PLL) module, the real-time feedback circuit, and the output driver module.

[0067] To obtain a 125 MHz output signal from a clock signal with an input frequency range of 10 to 500 MHz, the frequency divider module needs to be used to first divide the external reference clock signal into the phase detection frequency range of the phase-locked loop. The adjustable delay module compensates for the edge timing of the delay caused by the frequency divider. Due to the function of the PLL module, the signal clock edge at point ① in the feedback circuit is aligned with the external reference clock edge at the input, as shown in the following figure. The frequency division module in the PLL real-time feedback circuit is used to divide the frequency to obtain a 125 MHz output signal. The adjustable delay unit in the real-time feedback circuit can compensate for the propagation delay in the circuit. Before compensation, the clock edge at point ② is one propagation delay ahead of the clock edge at point ①. After compensation, the clock edge of the output signal output is aligned with the clock edge of ①. Then, the clock edges of the output signal output and the external reference signal are also aligned. The adjustable delay unit is completed by an analog adjustable phase shifter (0 - 360°).

[0068] A method for outputting a 125 MHz clock signal of the phase synchronization unit includes:

[0069] Step A: Input the external reference clock signal into the external input port of the pulse generator;

[0070] Step B: Initially configure or modify the configuration parameters of the control register. The phase synchronization unit saves the correct configuration parameters to the EEPROM. When powering on again next time, the pulse generator can load the configuration parameters saved in the EEPROM before and enter the phase synchronization mode to maintain the same configuration and output characteristics;

[0071] Step C: Divide the input external reference clock signal using the frequency divider module as needed;

[0072] Step D: The adjustable delay unit compensates for the edge timing of the delay caused by the frequency divider;

[0073] Step E: The frequency divider in the PLL feedback circuit divides the clock signal to 125 MHz. The PLL module monitors the phase and propagation delay of the output clock and adjusts it through real-time feedback control to achieve stable alignment of the output clock with the reference clock.

[0074] A pulse generator for reference clock phase synchronization and fine adjustment, comprising:

[0075] At least one phase synchronization fine-adjustable pulse generator;

[0076] The phase synchronization fine-adjustable pulse generator includes an interface module and a control module;

[0077] The interface module is used to receive an external clock reference signal, a Gate signal, and an external trigger signal;

[0078] The control module includes a host computer, an FPGA, an RS232 interface, and an Ethernet interface;

[0079] Output channels for multiple pulse signals, which are connected to the FPGA.

[0080] Among them, the external clock reference signal, the Gate signal, and the external trigger signal complete the corresponding level reception conversion through the high-speed comparator on the interface module and are sent to the control module.

[0081] Principle description:

[0082] Step 1: Initialize the pulse generator device;

[0083] Step 2: Establish a communication connection between the host computer or the accelerator control system and the pulse generator;

[0084] Step 3: The host computer or the accelerator control system issues parameter configurations, including reference clock selection, the repetition working frequency of the generated pulse signal, the width value of the generated pulse signal, and the relative delay value of the generated pulse signal;

[0085] Step 4: Determine the reference clock selection mode;

[0086] Step 5: When selecting to input an external reference clock, the pulse generator receives an external reference clock signal with a frequency of 10 MHz to 500 MHz;

[0087] When selecting an internal clock reference, the internal 125 MHz reference clock on the FPGA is used;

[0088] Step 6: According to the pulse parameter values set in Step 3, calculate the theoretically pulse repetition frequency count value, pulse width count value, and pulse delay count value;

[0089] Step 7: After the pulse signal is calibrated, output the pulse signal of the corresponding channel.

[0090] The preferred specific embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above specific embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A method for finely adjusting reference clock phase synchronization, comprising: Step 1, initialization of the pulse generator device; Step 2: The host computer establishes a communication connection with the pulse generator; Step 3: The host computer sends down parameter configuration, including reference clock selection, repetitive working frequency of the generated pulse signal, width value of the generated pulse signal, and relative delay value of the generated pulse signal; Step 4: Determine the reference clock selection mode; Step 5: When the external reference clock is selected, the pulse generator receives an external reference clock signal with a frequency of 10 MHz to 500 MHz; When the internal clock reference is selected, the internal 125MHz reference clock on the FPGA is used; The step 5 also includes a method for outputting a 125 MHz clock signal of a phase synchronization unit, including: Step A, inputting an external reference clock signal to an external input port of a pulse generator; Step B, initial configuration or modification of control register configuration parameters, phase synchronization unit, save the correct configuration parameters to EEPROM, when the power is turned on again next time, the pulse generator can load the configuration parameters previously saved in EEPROM and enter the phase synchronization mode to maintain the same configuration and output characteristics; Step C: divide the input external reference clock signal using a frequency divider module as needed; Step D, adjusting the delay unit to perform edge timing compensation for the delay caused by the frequency divider; Step E: The frequency divider in the PLL feedback circuit divides the clock signal to 125 MHz. The PLL module monitors the phase and propagation delay of the output clock and adjusts it through real-time feedback control to achieve stable alignment of the output clock with the reference clock. Step 6: According to the pulse parameter value set in step 3, the theoretical pulse repetition frequency count value, pulse width count value, and pulse delay count value are calculated; Step 7: After the pulse signal is calibrated, the pulse signal of the corresponding channel is output.

2. A method for finely adjusting reference clock phase synchronization according to claim 1, characterized in that: The step 6 comprises step 61: calculating the pulse repetition frequency count value: in order to achieve phase synchronization between the pulse output signal and the reference clock, the pulse repetition frequency count value Should be , otherwise the pulse output signal cannot be phase-locked with the reference clock signal; in, is the input reference clock value, The pulse repetition frequency value set for the host computer, The 125MHz working clock of FPGA, is the FPGA's duty cycle ( ).

3. A method for finely adjusting reference clock phase synchronization according to claim 1, characterized in that: The step 6 comprises a step 62: Calculation of pulse width count value: Based on the FPGAOSERDESE3 module DDR mode, 8 bits of parallel data serial output is completed. The FPGAOSERDESE3 module input clock is designed to be 125MHz. After parallel-to-serial conversion, the data transmission rate reaches 1000Mb / s, and the pulse width regulation accuracy of ns is achieved through cascading.

4. The method for finely adjusting reference clock phase synchronization according to claim 1, characterized in that: The step 6 comprises a step 63: Calculation of pulse delay count value: Based on the FPGAOSERDESE3 module DDR mode, 8 bits of parallel data serial output is completed, so that the data transmission rate reaches 1000 Mb / s, and the pulse output signal delay adjustment accuracy of ps level is achieved based on the FPGA ODELAYE3 module.

5. A pulse generator for reference clock phase synchronization and fine adjustment, used to implement the method according to any one of claims 1 to 4, characterized in that: include: at least one phase synchronized finely adjustable pulse generator; The phase-synchronous finely adjustable pulse generator comprises an interface module and a control module; The interface module is used to receive an external clock reference signal, a Gate signal, and an external trigger signal; The control module includes a host computer, FPGA, RS232 interface, and Ethernet interface; The output channels of multiple pulse signals are connected to the FPGA.

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