Scan circuit, gate drive circuit and display panel

Abstract

This application relates to a scanning circuit, a gate driving circuit, and a display panel. The scanning circuit includes an input module, a node potential control module, an output module, and a potential stabilization module. The input module transmits an input signal to a first node and a first power supply signal to a second node under the control of a first clock signal. The node potential control module controls the potentials of the first and second nodes. The output module responds to the effective potential of a third node by outputting a scanning signal according to a second clock signal; and responds to the effective potential of a fourth node by outputting a scanning signal according to a second power supply signal. The potential stabilization module is located between the first and third nodes, and / or between the second and fourth nodes. It switches to an on state before the input signal transitions from an invalid potential to an effective potential; and switches to an off state after the scanning signal transitions from an effective potential to an invalid potential. This effectively improves the problem of poor output stability of the scanning circuit.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a scanning circuit, a gate driving circuit, and a display panel. Background Technology

[0002] As the application range of display products becomes increasingly wide, display technology is also developing rapidly. Array substrate row driving technology can integrate TFT (Thin Film Transistor) gate switching circuits on the array substrate of the display panel to form a scanning drive for the display panel, thereby narrowing the bezel of the display panel.

[0003] Currently, gate drive circuits typically consist of multiple cascaded scanning circuits, which sequentially input scanning signals to each row of gate lines on the display panel. However, existing scanning circuits suffer from poor output stability, affecting the improvement of display panel quality. Summary of the Invention

[0004] Therefore, it is necessary to provide a scanning circuit, a gate driving circuit, and a display panel to address the problem of poor output stability of the scanning circuit.

[0005] In a first aspect, embodiments of the present invention provide a scanning circuit, comprising:

[0006] The input module is used to receive an input signal, a first power signal, and a first clock signal, and to transmit the input signal to a first node and the first power signal to a second node under the control of the first clock signal.

[0007] A node potential control module is used to receive a second power supply signal, a first clock signal, and a second clock signal. The node potential control module is connected to the first node and the second node respectively. When the second node is at an effective potential, it responds to the effective potential of the second clock signal and controls the potential of the first node according to the second power supply signal; it is also used to respond to the effective potential of the first node and control the potential of the second node according to the first clock signal.

[0008] An output module is used to receive the second clock signal and the second power signal. The output module is connected to the third node and the fourth node respectively. It is used to respond to the effective potential of the third node and output a scan signal according to the second clock signal; and respond to the effective potential of the fourth node and output a scan signal according to the second power signal. The third node is used to connect to the first node, and the fourth node is used to connect to the second node.

[0009] A potential stabilization module is disposed between the first node and the third node, and / or between the second node and the fourth node; the potential stabilization module switches to a conducting state before the input signal changes from an invalid potential to an effective potential; and switches to a disconnected state after the scan signal changes from an effective potential to an invalid potential.

[0010] In some embodiments, the potential stabilization module is used to receive a scan control signal and turn on / off according to the scan control signal; the scan signal is used to output to the pixel circuit, and the timing of the scan control signal matches the timing of the light emission control stage of the pixel circuit;

[0011] Optionally, the scanning circuit includes a signal transmission circuit, which receives a transmission signal and outputs the scanning control signal according to the transmission signal.

[0012] In some embodiments, the potential stabilization module includes a first stabilizing transistor and / or a second stabilizing transistor, and the scan control signal includes a first scan control signal and / or a second scan control signal;

[0013] The control terminal of the first stable transistor is used to receive the first scan control signal. The first terminal of the first stable transistor is connected to the first node, and the second terminal of the first stable transistor is connected to the third node.

[0014] The control terminal of the second stabilizing transistor is used to receive the second scan control signal. The first terminal of the second stabilizing transistor is connected to the second node, and the second terminal of the second stabilizing transistor is connected to the fourth node.

[0015] In some embodiments, the first stable transistor is an N-type transistor;

[0016] Optionally, the second stabilizing transistor is an N-type transistor, and both the first scan control signal and the second scan control signal are light emission control signals of the pixel circuit;

[0017] Optionally, the second stabilizing transistor is a P-type transistor, the first scan control signal is the light emission control signal of the pixel circuit, and the potential state of the second scan control signal is opposite to the potential state of the first scan control signal.

[0018] In some embodiments, the first stable transistor is a P-type transistor;

[0019] Optionally, the second stabilizing transistor is a P-type transistor, the potential state of the first scan control signal is opposite to the potential state of the light emission control signal of the pixel circuit, and the potential state of the second scan control signal is synchronized with that of the first scan control signal.

[0020] Optionally, the width of the channel of the first stable transistor is less than or equal to its length;

[0021] Optionally, the width of the channel of the second stable transistor of the P type is less than or equal to its length;

[0022] Optionally, the second stabilizing transistor is an N-type transistor, the second scan control signal is the light emission control signal of the pixel circuit, and the potential state of the first scan control signal is opposite to the potential state of the second scan control signal.

[0023] In some embodiments, the input module includes:

[0024] The first input unit is configured to receive the input signal and the first clock signal, and to transmit the input signal to the first node under the control of the first clock signal.

[0025] The second input unit is used to receive the first power signal and the first clock signal, and to transmit the first power signal to the second node under the control of the first clock signal.

[0026] Optionally, the first input unit includes a first input transistor, the control terminal of the first input transistor is used to receive the first clock signal, the first terminal of the first input transistor is used to receive the input signal, and the second terminal of the first input transistor is connected to the first node;

[0027] Optionally, the second input unit includes a second input transistor, the control terminal of the second input transistor is used to receive the first clock signal, the first terminal of the second input transistor is used to receive the first power signal, and the second terminal of the second input transistor is connected to the second node.

[0028] In some embodiments, the node potential control module includes:

[0029] The first mutual control unit is used to receive the first clock signal. The first mutual control unit is connected to the first node and the second node respectively. It is used to respond to the effective potential of the first node and control the potential of the second node according to the first clock signal.

[0030] The second mutual control unit is used to receive the second clock signal and the second power signal. The second mutual control unit is connected to the first node and the second node respectively, and is used to respond to the effective potential of the second node and the effective potential of the second clock signal, and control the potential of the first node according to the second power signal.

[0031] Optionally, the first mutual control unit includes a first mutual control transistor, the control terminal of the first mutual control transistor is connected to the first node, the first terminal of the first mutual control transistor is used to receive the first clock signal, and the second terminal of the first mutual control transistor is connected to the second node.

[0032] Optionally, the second mutual control unit includes a second mutual control transistor and a third mutual control transistor. The control terminal of the second mutual control transistor is connected to the second node. The first terminal of the second mutual control transistor is used to receive the second power signal. The second terminal of the second mutual control transistor is connected to the first terminal of the third mutual control transistor. The control terminal of the third mutual control transistor is used to receive the second clock signal. The second terminal of the third mutual control transistor is connected to the first node.

[0033] In some embodiments, the output module includes a first output unit and a second output unit; the first output unit is configured to receive the second clock signal, the first output unit is connected to a third node, and the first output unit is configured to output a scan signal in response to the effective potential of the third node according to the second clock signal;

[0034] The second output unit is used to receive the second power signal. The second output unit is connected to the fourth node and the first output unit respectively. The second output unit is used to respond to the effective potential of the fourth node and output a scan signal according to the second power signal.

[0035] Optionally, the first output unit includes a first output transistor and a first capacitor. The control terminal of the first output transistor is connected to the third node. The first terminal of the first output transistor is used to receive the second clock signal, and the second terminal of the first output transistor is the output terminal of the first output unit. The first terminal of the first capacitor is connected to the control terminal of the first output transistor, and the second terminal of the first capacitor is connected to the second terminal of the first output transistor.

[0036] Optionally, the second output unit includes a second output transistor and a second capacitor. The control terminal of the second output transistor is connected to the fourth node. The first terminal of the second output transistor is used to receive the second power signal. The second terminal of the second output transistor is connected to the output terminal of the first output unit. The first terminal of the second capacitor is connected to the control terminal of the second output transistor. The second terminal of the second capacitor is connected to the first terminal of the second output transistor.

[0037] Secondly, embodiments of the present invention provide a gate driving circuit, including multiple cascaded scanning circuits as described above; wherein, the signal input terminal of the first-stage scanning circuit is electrically connected to the start signal line, and the signal input terminal of the (i+1)th-stage scanning circuit is electrically connected to the output terminal of the ith-stage scanning circuit, wherein i is an integer greater than 0.

[0038] Thirdly, embodiments of the present invention provide a display panel, including the gate driving circuit as described above;

[0039] Optionally, the display panel includes multiple pixel circuits and multiple cascaded light emission control signal generation circuits. The light emission control signal output by the light emission control signal generation circuit is provided to the corresponding pixel circuit, and the scan signal output by the scan circuit is provided to the corresponding pixel circuit.

[0040] Optionally, the potential stabilization module in the scanning circuit is used to receive the scanning control signal and turn on / off according to the scanning control signal; the light emission control signal output by the light emission control signal generation circuit is used as the scanning control signal, or the signal output by the light emission control signal generation circuit that is opposite to the potential state of the light emission control signal is used as the scanning control signal.

[0041] The aforementioned scanning circuit, gate driving circuit, and display panel, with the output module controlled by the third and fourth nodes respectively, allow the potential stabilization module to switch from a cutoff state to a conduction state before the input signal transitions from an invalid to an valid potential. This connects the third node to the first node and the fourth node to the second node, enabling the output module to output the scanning signal normally. After the output scanning signal transitions from a valid to an invalid potential, the potential stabilization module switches to a disconnected state, breaking the connection between the first and third nodes. This prevents leakage in the node potential control module and input module from lowering the potential of the third node. Similarly, disconnecting the connection between the second and fourth nodes prevents leakage in the node potential control module and input module from lowering the potential of the fourth node. Therefore, by disconnecting the potential stabilization module, the potentials of the third and / or fourth nodes can be kept stable, effectively improving the poor output stability of the scanning circuit and thus enhancing the display quality of the display panel. Attached Figure Description

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 This is a schematic diagram of the circuit structure of a scanning circuit in a related technology;

[0044] Figure 2 This is a schematic diagram of a scanning circuit module in one embodiment;

[0045] Figure 3 This is a schematic diagram of the scanning circuit module in another embodiment;

[0046] Figure 4 This is a schematic diagram of the scanning circuit module in yet another embodiment;

[0047] Figure 5 This is a schematic diagram of the scanning circuit module in yet another embodiment;

[0048] Figure 6 This is a schematic diagram of the scanning circuit module in yet another embodiment;

[0049] Figure 7 This is a schematic diagram of the scanning circuit in one embodiment;

[0050] Figure 8 This is a timing diagram of the scanning circuit in one embodiment;

[0051] Figure 9 This is a comparison diagram of the voltage waveform of the third node of the scanning circuit in one embodiment and the scanning circuit in related technologies;

[0052] Figure 10 for Figure 9 A magnified view of a portion of the waveform comparison diagram;

[0053] Figure 11 A comparison diagram of the voltage waveform of the fourth node of the scanning circuit in one embodiment and the scanning circuit in related technologies;

[0054] Figure 12 A comparison diagram of the current waveforms of the third node of a scanning circuit in one embodiment and a scanning circuit in a related art.

[0055] Figure 13 A comparison diagram of the current waveforms of the fourth node of a scanning circuit in one embodiment and a scanning circuit in a related art.

[0056] Figure 14 This is a schematic diagram of a gate drive circuit module in one embodiment;

[0057] Figure 15 This is a schematic diagram of the connection of the gate driving circuit in a display panel in one embodiment;

[0058] Figure 16 This is a schematic diagram of the connection of the gate driving circuit in the display panel in another embodiment.

[0059] Explanation of reference numerals in the attached figures:

[0060] 100 - Input module, 200 - Node potential control module, 300 - Output module, 400 - Potential stabilization module, SIN - Input signal, VGL - First power supply signal, VGH - Second power supply signal, SCK1 - First clock signal, SCK2 - Second clock signal, Gout - Scan signal, CL - Scan control signal, T1 - First stabilizing transistor, T2 - Second stabilizing transistor, 110 - First input unit, 120 - Second input unit, 210 - First inter-control unit, 220 - Second inter-control unit, 310 - First output unit, 320 - Second output unit, T3 - First input transistor, T4 - Second input transistor, T5 - First inter-control transistor, T6 - Second inter-control transistor, T7 - ​​Third inter-control transistor, T8 - First output transistor, T9 - Second output transistor, C1 - First capacitor, C2 - Second capacitor, 1 - Figure 7 The voltage waveform at the third node N3 of the scanning circuit shown, 2- Figure 1 The voltage waveform at node B of the scanning circuit shown in Figure 4- Figure 1 The voltage waveform at node A of the scanning circuit shown in Figure 5- Figure 7 The voltage waveform at the fourth node N4 of the scanning circuit shown in Figure 6- Figure 1 The current waveform at node B of the scanning circuit shown in Figure 7- Figure 7 The current waveform at the third node N3 of the scanning circuit shown in Figure 8- Figure 1 The current waveform at node A of the scanning circuit shown in Figure 9- Figure 7 The current waveform of the fourth node N4 of the scanning circuit shown is as follows: EIN - input signal of the light emission control signal generation circuit; EM_1~EM_N - light emission control signals output by the first-level light emission control signal generation circuit to the Nth-level light emission control signal generation circuit; EMB_1~EMB_N - signals with opposite potentials to the light emission control signals output by the first-level light emission control signal generation circuit to the Nth-level light emission control signal generation circuit; Gout1~Goutn - scan signals output by the first-level scanning circuit to the Nth-level scanning circuit. Detailed Implementation

[0061] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0063] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0064] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0065] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0066] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0067] As described in the background section, the scanning circuit of the display panel in the related art suffers from poor output stability, affecting the quality improvement of the display panel. In the related art, the structure of the scanning circuit is as follows: Figure 1As shown, node A is connected to the gate of output transistor M6, and node B is connected to the gate of output transistor M7. Output transistor M6 responds to the potential of node A, and output transistor M7 responds to the potential of node B. The potentials of nodes A and B can be controlled by the input signal SIN, clock signals SCK1 and SCK2, power supply signals VGH and VGL, which in turn control the output transistors M6 and M7 to output the drive signal SN_OUT. Thus, multiple cascaded scanning circuits can provide drive signals for line-by-line scanning, driving the pixel circuit to complete processes such as reset and data writing. In the cascaded scanning circuit, the current line scanning circuit needs to delay the waveform of the input signal by one line before outputting it to the next stage as the input signal for the next stage scan. Each scanning circuit acts as a shift register. After the current stage outputs, the output of the scanning circuit remains high until the next frame period arrives, at which point it outputs the current stage signal SN_OUT as low.

[0068] However, the output stability of this type of scanning circuit is poor. In particular, as the screen resolution increases, the problem of poor output stability of the display scanning circuit becomes more prominent, which seriously affects the improvement of the display panel quality.

[0069] Based on the above-mentioned technical problems, the inventors discovered through long-term research that during the display process of the display panel, after the local scanning circuit outputs the signal SN_OUT, the local scanning circuit is still related to the clock signals SCK1 and SCK2. Due to the coupling effect of the clock signals, the scanning circuit has an unstable output problem.

[0070] Specifically, the display panel has N levels of scanning circuits, each connected to the signal lines of clock signals SCK1 and SCK2. When a scanning circuit at a given level is operating, it normally outputs a low-level drive signal SN_OUT based on clock signals SCK1 and SCK2. During this process, the other N-1 level scanning circuits do not need to output drive signals; they only need to maintain a high level. However, these N-1 level scanning circuits also continuously receive clock signals SCK1 and SCK2. Transistors M3, M4, and M5 will couple with the clock signals, causing leakage current. This leakage current occurs during the continuous switching on and off of the transistors, resulting in a voltage drop at the connected node A. Simulation results for a display panel at a refresh rate of 60Hz show that the voltage drop at node A reaches approximately 2V. This voltage fluctuation may cause the output transistor M6 to change its operating state, such as from on to off, thus affecting the output capability and consequently the stability of the output. Furthermore, since transistor M8 is in a normally conducting state, there is leakage current in two paths: transistor M1 and transistor M2. According to the simulation results, the average voltage of node B is low, which affects the turn-off effect of output transistor M7 and thus also affects the stability of the output.

[0071] As the resolution of the screen increases and the number of rows on the screen increases, the voltage fluctuations at nodes A and B become more severe, making the problem of poor output stability of the display scanning circuit more prominent and seriously affecting the improvement of display panel quality.

[0072] Based on this, the inventors further developed the technical solution of the embodiments of the present invention. Specifically, the embodiments of the present invention provide a scanning circuit, including an input module, a node potential control module, an output module, and a potential stabilization module. The input module is used to receive an input signal, a first power signal, and a first clock signal, and is used to transmit the input signal to a first node and the first power signal to a second node under the control of the first clock signal. The node potential control module is used to receive a second power signal, the first clock signal, and a second clock signal. The node potential control module is connected to the first node and the second node respectively, and is used to control the potential of the first node according to the second power signal in response to the effective potential of the second clock signal when the second node is at an effective potential; it is also used to control the potential of the second node according to the first clock signal in response to the effective potential of the first node. The output module is used to receive the second clock signal and the second power signal, and is connected to a third node and a fourth node respectively, and is used to output a scanning signal according to the second clock signal in response to the effective potential of the third node; and to output a scanning signal according to the second power signal in response to the effective potential of the fourth node. The potential stabilization module is located between the first node and the third node, and / or between the second node and the fourth node; the potential stabilization module switches to the on state before the input signal changes from an invalid potential to an effective potential; and switches to the off state after the scan signal changes from an effective potential to an invalid potential.

[0073] Using the above technical solution, the output module is controlled by the third and fourth nodes respectively. Before the input signal changes from an invalid potential to an effective potential, the potential stabilization module switches from the cutoff state to the conduction state, connecting the third node to the first node and the fourth node to the second node, allowing the output module to output the scan signal normally. After the output scan signal changes from an effective potential to an invalid potential, the potential stabilization module switches to the off state, disconnecting the connection between the first and third nodes. This prevents leakage in the node potential control module and the input module from lowering the potential of the third node. Similarly, disconnecting the connection between the second and fourth nodes prevents leakage in the node potential control module and the input module from lowering the potential of the fourth node. Therefore, by disconnecting the potential stabilization module, the potentials of the third and / or fourth nodes can be kept stable, effectively improving the poor output reliability of the scanning circuit, thereby enhancing the display quality of the display panel and facilitating the development of high-resolution display panels.

[0074] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0075] Figure 2 A schematic diagram of a scanning circuit provided in an embodiment of the present invention is shown below. Figure 2 As shown, the scanning circuit provided in this embodiment of the invention includes: an input module 100, a node potential control module 200, an output module 300, and a potential stabilization module 400.

[0076] The input module 100 is used to receive the input signal SIN, the first power signal VGL, and the first clock signal SCK1, and to transmit the input signal SIN to the first node N1 and the first power signal VGL to the second node N2 under the control of the first clock signal SCK1.

[0077] The node potential control module 200 is used to receive a second power supply signal VGH, a first clock signal SCK1, and a second clock signal SCK2. The node potential control module 200 is connected to the first node N1 and the second node N2 respectively. When the second node N2 is at an effective potential, it responds to the effective potential of the second clock signal SCK2 and controls the potential of the first node N1 according to the second power supply signal VGH. It is also used to respond to the effective potential of the first node N1 and control the potential of the second node N2 according to the first clock signal SCK1.

[0078] Output module 300 is used to receive the second clock signal SCK2 and the second power supply signal VGH. Output module 300 is connected to the third node N3 and the fourth node N4 respectively. It is used to respond to the effective potential of the third node N3 by outputting a scan signal Gout according to the second clock signal SCK2; and to respond to the effective potential of the fourth node N4 by outputting a scan signal Gout according to the second power supply signal VGH. The third node N3 is used to connect to the first node N1, and the fourth node N4 is used to connect to the second node N2.

[0079] A potential stabilization module 400 is disposed between the first node N1 and the third node N3, and / or between the second node N2 and the fourth node N4. Before the input signal SIN changes from an invalid potential to an valid potential, the potential stabilization module 400 switches to the on state; after the scan signal Gout changes from a valid potential to an invalid potential, the potential stabilization module 400 switches to the off state.

[0080] Specifically, the input module 100 is turned on or off under the control of the first clock signal SCK1. When the input module 100 is turned on, it can transmit the input signal SIN to the first node N1 and the first power signal VGL to the second node N2.

[0081] The input signal SIN can be set according to actual conditions, such as being an input to an external circuit or an output signal from an upper-level scanning circuit. In practical implementation, this scanning circuit can be used in a display panel, which includes a gate drive circuit composed of multiple cascaded scanning circuits. The signal input terminal of the first-stage scanning circuit is electrically connected to the start signal line, receiving the start signal as its input signal. The signal input terminal of the (i+1)th-stage scanning circuit is electrically connected to the output terminal of the ith-stage scanning circuit, and the scanning signal Gout output by the ith-stage scanning circuit serves as the input signal for the next-stage scanning circuit. Here, i is an integer greater than 0.

[0082] The node potential control module 200 is controlled by the potential of the first node N1, the potential of the second node N2, and the second clock signal SCK2. For example, when the first node N1 is at a valid potential, the node potential control module 200 controls the potential of the second node N2 according to the first clock signal SCK1, that is, transmits the first clock signal SCK1 to the second node N2. When the second clock signal SCK2 is at a valid potential, in response to the valid potential of the second clock signal SCK2, the module controls the potential of the first node N1 according to the second power signal VGH, that is, transmits the second power signal VGH to the first node N1.

[0083] The first power signal VGL and the second power signal VGH have different potentials. In some embodiments, the second power signal VGH is at a high potential, and the first power signal VGL is at a low potential. The specific potential values ​​of the second power signal VGH and the first power signal VGL need to be set according to actual needs. The first power signal VGL, the second power signal VGH, the first clock signal SCK1, and the second clock signal SCK2 can be input by external circuitry. The pulse widths of the first clock signal SCK1 and the second clock signal SCK2 need to be set according to actual needs. In some embodiments, the first clock signal SCK1 and the first clock signal SCK2 have the same period but are phase-shifted by one row cycle. When the scan signal Gout is active low, the low potential of the input signal SIN includes the complete low potential of the first clock signal SCK1 in one cycle. The duration of the low potential of the first clock signal SCK1 and the second clock signal SCK2 can be shorter than the duration of the high potential. The scan circuit can shift and delay the active potential pulse of the input signal SIN before outputting it. One of the active and inactive potentials of the input signal SIN is low, and the other is high.

[0084] Output module 300 responds to the valid potentials of the third node N3 and the fourth node N4. Specifically, when the third node N3 is at a valid potential, it outputs a scan signal Gout according to the second clock signal SCK2, that is, it outputs the second clock signal SCK2 to the output terminal of the scan circuit; when the fourth node N4 is at a valid potential, it outputs a scan signal Gout according to the second power supply signal VGH, that is, it outputs the second power supply signal VGH to the output terminal of the scan circuit; when both the third node N3 and the fourth node N4 are at valid potentials, it outputs a scan signal Gout according to the second clock signal SCK2 and the second power supply signal VGH.

[0085] The configuration of the potential stabilization module 400 is not unique. In one embodiment, the potential stabilization module 400 is located between the first node N1 and the third node N3, and the second node N2 is connected to the fourth node N4. The potential of the fourth node N4 is equal to the potential of the second node N2. Before the input signal SIN changes from an invalid potential to an effective potential, i.e., before the effective potential of the input signal SIN is received, the potential stabilization module 400 switches from a cutoff state to a conduction state. The first node N1 and the third node N3 are connected, and the potential of the first node N1 is transmitted to the third node N3 through the potential stabilization module 400. Afterward, the potential of the third node N3 follows the potential changes of the first node N1. After the input signal SIN changes from an invalid potential to an effective potential, under the action of the input module 100 and the node potential control module 200, the potential states of the third node N3 and the fourth node N4 change. The output module 300 responds to the effective potential of the third node N3 and the fourth node N4, and the output scan signal Gout changes from an invalid potential to an effective potential to drive the corresponding pixel circuit. After the driving is completed, the scan signal Gout changes from an effective potential to an invalid potential. After the scan signal Gout changes from an invalid potential to an effective potential, the potential stabilization module 400 switches to the off state, disconnecting the connection between the first node N1 and the third node N3. Consequently, the third node N3 is disconnected from the node potential control module 200 and the input module 100, preventing the voltage of the third node N3 from being pulled down by leakage paths in the node potential control module 200 and the input module 100. This ensures that the potential of the third node N3 remains stable, thereby improving the output stability of the output module 300.

[0086] In another embodiment, such as Figure 3As shown, the potential stabilization module 40 is positioned between the second node N2 and the fourth node N4. The first node N1 is connected to the third node N3, and the potential of the third node N3 is equal to that of the first node N1. Before the input signal SIN changes from an invalid potential to a valid potential, the potential stabilization module 400 switches from a cutoff state to a conduction state, connecting the second node N2 and the fourth node N4, making the potential of the fourth node N4 equal to that of the second node N2. After the input signal SIN changes from an invalid potential to a valid potential, under the action of the input module 100 and the node potential control module 200, the potential states of the third node N3 and the fourth node N4 change. The output module 300 responds to the valid potential of the third node N3 and the fourth node N4, and the output scan signal Gout changes from an invalid potential to a valid potential, and then from a valid potential to an invalid potential. After the scan signal Gout changes from an invalid potential to a valid potential, the potential stabilization module 400 switches to a disconnected state, disconnecting the connection between the second node N2 and the fourth node N4. Therefore, the fourth node N4 is disconnected from the node potential control module 200 and the input module 100 to prevent the voltage of the fourth node N4 from being pulled down by the leakage path in the node potential control module 200 and the input module 100. This allows the potential of the fourth node N4 to remain stable, thereby improving the output stability of the output module 300.

[0087] In yet another embodiment, such as Figure 4 As shown, the potential stabilization module 400 is located between the first node N1 and the third node N3, and between the second node N2 and the fourth node N4. Before the input signal SIN changes from an invalid potential to an effective potential, the potential stabilization module 400 switches from a cutoff state to a conduction state, connecting the first node N1 and the third node N3, and connecting the second node N2 and the fourth node N4. After the input signal SIN changes from an invalid potential to an effective potential, under the action of the input module 100 and the node potential control module 200, the potential states of the third node N3 and the fourth node N4 change. The output module 300 responds to the effective potential of the third node N3 and the fourth node N4, and the output scan signal Gout changes from an invalid potential to an effective potential, and then from an effective potential to an invalid potential. After the scan signal Gout changes from an effective potential to an invalid potential, the potential stabilization module 400 switches to a disconnected state, disconnecting the connection between the third node N3 and the first node N1, and disconnecting the connection between the fourth node N4 and the second node N2. Therefore, the third node N3 and the fourth node N4 are disconnected from the node potential control module 200 and the input module 100 to prevent the voltage of the third node N3 and the fourth node N4 from being pulled down by the leakage path in the node potential control module 200 and the input module 100. This allows the potential of the third node N3 and the fourth node N4 to remain stable, thereby improving the output stability of the output module 300.

[0088] It should be noted that the conduction time of the potential stabilization module 400 can be set according to actual conditions. It only needs to conduct before the input signal SIN changes from an invalid potential to an valid potential, without affecting the valid potential output of the scan signal Gout. The de-energization time of the potential stabilization module 400 also does not need to be limited. It can be de-energized as soon as the output of the scan circuit ends, i.e., after the scan signal Gout changes from a valid potential to an invalid potential. After the potential stabilization module 400 is de-energized, the potentials of the third node N3 and the fourth node N4 remain unchanged. The output module 300 keeps the scan signal Gout in an invalid potential state based on the potentials of the third node N3 and the fourth node N4.

[0089] In the aforementioned scanning circuit, the output module 300 is controlled by the third node N3 and the fourth node N4, respectively. Before the input signal SIN changes from an invalid potential to an effective potential, the potential stabilization module 400 switches from the off state to the on state, connecting the third node N3 to the first node N1 and the fourth node N4 to the second node N2, allowing the output module 300 to output the scanning signal Gout normally. After the output scanning signal Gout changes from an effective potential to an invalid potential, the potential stabilization module 400 switches to the off state. When the connection between the first node N1 and the third node N3 is disconnected, leakage in the leakage path of the node potential control module 200 and the input module 100 is prevented from pulling down the third node N3; when the connection between the second node N2 and the fourth node N4 is disconnected, leakage in the leakage path of the node potential control module 200 and the input module 100 is prevented from pulling down the fourth node N4. Therefore, by disconnecting the potential stabilization module 400, the potential of the third node N3 and / or the fourth node N4 can be kept stable, thereby improving the output stability of the output module 300, which in turn improves the display quality of the display panel and is conducive to the development of high resolution of the display panel.

[0090] Furthermore, by disconnecting the leakage path of the third node N3 and / or the fourth node N4, the power consumption of the scanning circuit can be reduced, which can effectively reduce the power consumption of the display panel with a large number of scanning circuits.

[0091] In one embodiment, the potential stabilization module 400 is used to receive the scan control signal CL and turn it on / off according to the scan control signal CL; the scan signal Gout is used to output to the pixel circuit, and the timing of the scan control signal CL matches the timing of the light emission control stage of the pixel circuit.

[0092] Specifically, the light-emitting control phase of the pixel circuit includes a light-emitting phase and a non-light-emitting phase. In the light-emitting phase, the pixel circuit outputs a driving current to the light-emitting element, causing the element to conduct and emit light. The non-light-emitting phase includes an initialization phase, a data writing phase, and a threshold compensation phase. In the non-light-emitting phase, the corresponding transistor in the pixel circuit can be turned on in response to the effective potential of the scan signal Gout, thereby coordinating the operation of the pixel circuit to achieve a high-quality display image. For example, the pixel circuit includes a data writing transistor, a storage module, a driving transistor, a threshold compensation transistor, and a light-emitting control transistor. The storage module is connected between the control terminal of the driving transistor and the first power signal line; the threshold compensation transistor is connected between the control terminal of the driving transistor and the first terminal of the driving transistor; the data writing transistor is connected to the second terminal of the driving transistor; and the light-emitting control transistor, the driving transistor, and the light-emitting element are connected in series between the first power signal line and the second power signal line. The scan signal Gout can be provided to the data writing transistor and the threshold compensation transistor, and the light-emitting control signal output by the light-emitting control signal generation circuit is provided to the light-emitting control transistor. In the light-emitting phase, the scan signal Gout remains in an inactive potential state.

[0093] In this embodiment, by matching the timing of the scan control signal CL with the timing of the light emission control phase of the pixel circuit, the potential stabilization module 400 in the scan circuit connected to the pixel circuit can be turned on when the pixel circuit is in the non-light emission phase, thereby allowing the output module 300 to output a scan signal Gout at an effective potential. When the pixel circuit is in the light emission phase, the potential stabilization module 400 in the scan circuit connected to the pixel circuit is turned off, thereby keeping the potentials of the third node N3 and / or the fourth node N4 stable. This ensures the output reliability of the scan circuit to drive the pixel circuit to work normally. Furthermore, it keeps the potentials of the third node N3 and / or the fourth node N4 stable, improving the output stability of the output module 300 and thus enhancing the driving performance of the pixel circuit.

[0094] In the display panel, when the scanning circuit of this stage outputs a low-potential scanning signal Gout, the leakage path of the third node N3 and the fourth node N4 of the scanning circuit of this stage is disconnected. During the line-by-line scanning process of other scanning circuits, they are in an open state, which can save a lot of power consumption and is therefore more conducive to the development of display panels towards higher resolution and higher refresh rate.

[0095] In one embodiment, the scanning circuit further includes a signal transmission circuit, which receives a transmission signal and outputs a scanning control signal CL based on the transmission signal.

[0096] The structure of the signal transmission circuit is not limited and can be set according to actual needs. The transmission signal can be configured according to actual requirements. In one embodiment, the gate driving circuit in the display panel includes multiple cascaded scanning circuits. Since the timing of the scan control signal CL for each scanning circuit is different, multiple cascaded signal transmission circuits (which can be shift registers) are correspondingly set to output the scan control signal CL to each scanning circuit step by step. The signal input terminal of the (n+1)th stage signal transmission circuit is electrically connected to the output terminal of the nth stage signal transmission circuit. The scan control signal CL output by the nth stage signal transmission circuit serves as the transmission signal for the next stage signal transmission circuit. The input terminal of the first stage signal transmission circuit receives the transmission signal input from an external circuit. Here, n is an integer greater than 0. In another embodiment, the transmission signal is input from an external circuit, and the signal transmission circuit outputs the scan control signal CL according to the received transmission signal. The timing of the scan control signal CL matches the timing of the light emission control stage of the pixel circuit.

[0097] In one embodiment, such as Figure 5 As shown, the potential stabilization module 400 includes a first stabilizing transistor T1 and / or a second stabilizing transistor T2; the scan control signal CL includes a first scan control signal CL1 and / or a second scan control signal CL2. The control terminal of the first stabilizing transistor T1 receives the first scan control signal CL1. The first terminal of the first stabilizing transistor T1 is connected to a first node N1, and the second terminal of the first stabilizing transistor T1 is connected to a third node N3. The control terminal of the second stabilizing transistor T2 receives the second scan control signal CL2. The first terminal of the second stabilizing transistor T2 is connected to a second node N2, and the second terminal of the second stabilizing transistor T2 is connected to a fourth node N4.

[0098] Specifically, in some embodiments, the potential stabilization module 400 includes a first stabilizing transistor T1, and a second node N2 connected to a fourth node N4. In other embodiments, the potential stabilization module 400 includes a second stabilizing transistor T2, and the first node N1 connected to a third node N3. In some preferred embodiments, the potential stabilization module 400 includes both a first stabilizing transistor T1 and a second stabilizing transistor T2. For ease of explanation, the following description uses the example of the potential stabilization module 400 including both a first stabilizing transistor T1 and a second stabilizing transistor T2.

[0099] When the first scan control signal CL1 is at an effective potential, the first stabilizing transistor T1 is turned on, connecting the first node N1 and the third node N3. When the second scan control signal CL2 is at an effective potential, the second stabilizing transistor T2 is turned on, connecting the second node N2 and the fourth node N4.

[0100] When the first scan control signal CL1 is in an invalid potential state, the first stabilizing transistor T1 is turned off to disconnect the third node N3 from other circuits. When the second scan control signal CL2 is in an invalid potential state, the second stabilizing transistor T2 is turned off to disconnect the fourth node N4 from other circuits. This improves the leakage current of the third node N3 and the fourth node N4, making their potentials more stable. In actual implementation, the timing of the first scan control signal CL1 and the second scan control signal CL2 can be set according to the actual situation; they can be the same or different.

[0101] The types of the first stable transistor T1 and the second stable transistor T2 need to be set according to the actual situation. Those skilled in the art will understand that the first and second terminals of the transistors also need to be determined according to the type of transistor and the actual use. This embodiment does not limit this. In order to make the potentials of the third node N3 and the fourth node N4 more stable and the leakage current further reduced, the first stable transistor T1 and the second stable transistor T2 can also use dual-gate or triple-gate devices.

[0102] In one embodiment, the first stable transistor T1 is an N-type transistor.

[0103] In this embodiment, the second stable transistor can be either an N-type transistor or a P-type transistor.

[0104] When both the first stabilizing transistor T1 and the second stabilizing transistor T2 are N-type transistors, the first scan control signal CL1 and the second scan control signal CL2 can be the same signal. Preferably, both the first scan control signal CL1 and the second scan control signal CL2 can be the light emission control signal EM of the pixel circuit. Therefore, by multiplexing the light emission control signal EM of the pixel circuit, there is no need to add additional control signals as the first scan control signal CL1 and the second scan control signal CL2, thus eliminating the need to increase the product bezel. Compared to setting up a signal transmission circuit, this also reduces circuit costs.

[0105] When the first stabilizing transistor T1 is an N-type transistor and the second stabilizing transistor is a P-type transistor, the potential state of the second scan control signal CL2 is opposite to that of the first scan control signal CL1. Preferably, the first scan control signal CL1 can reuse the light emission control signal EM from the pixel circuit, and the second scan control signal CL2 can be a signal EMB with a potential opposite to that of the light emission control signal EM. It should be noted that in actual implementation, the light emission control signal generation circuit can obtain not only the light emission control signal EM, but also the signal EMB with a potential opposite to that of the light emission control signal EM (for example, the potential of the gate of the output transistor of the light emission control signal generation circuit; when the output transistor is turned on, it can output the light emission control signal EM, at which time the potential of the light emission control signal is opposite to the potential of the gate of the output transistor; for example, when the potential of the gate of the output transistor is low, the potential of the light emission control signal is high). Therefore, by reusing the signals EM and EMB, no additional control signals are needed, and thus there is no need to increase the product bezel.

[0106] In one embodiment, such as Figure 6 As shown, the first stabilizing transistor T1 is a P-type transistor. In this embodiment, the second stabilizing transistor can be either an N-type transistor or a P-type transistor.

[0107] When both the first stabilizing transistor T1 and the second stabilizing transistor T2 are P-type transistors, the potential state of the first scan control signal CL1 is opposite to the potential state of the light emission control signal EM of the pixel circuit, and the potential state of the second scan control signal CL2 is synchronized with the potential state of the first scan control signal CL1. Preferably, both the first scan control signal CL1 and the second scan control signal CL2 are signals EMB whose potentials are opposite to those of the light emission control signal EM.

[0108] Furthermore, the channel width of the first P-type stable transistor T1 is less than or equal to its length, and the channel width of the second P-type stable transistor T2 is less than or equal to its length. Since the P-type transistor with a channel width less than its length has more stable performance, the disconnection effect on the third node N3 and the fourth node N4 can be improved, thereby improving the reliability of the scanning circuit.

[0109] When the first stabilizing transistor T1 is a P-type transistor and the second stabilizing transistor T2 is an N-type transistor, the second scan control signal CL2 can be the light emission control signal EM of the pixel circuit, and the potential state of the first scan control signal CL1 is opposite to the potential state of the second scan control signal CL2. Preferably, the second scan control signal CL2 can be a signal EMB with a potential opposite to that of the light emission control signal EM.

[0110] In one embodiment, such as Figure 7As shown, the input module 100 includes a first input unit 110 and a second input unit 120. The first input unit 110 is used to receive the input signal SIN and the first clock signal SCK1, and is used to transmit the input signal SIN to the first node N1 under the control of the first clock signal SCK1.

[0111] The second input unit 120 is used to receive the first power signal VGL and the first clock signal SCK1, and to transmit the first power signal VGL to the second node N2 under the control of the first clock signal SCK1.

[0112] In actual implementation, the circuit structures of the first input unit 110 and the second input unit 120 can be set according to actual needs. In one embodiment, the first input unit 110 may include a first input transistor T3, the control terminal of the first input transistor T3 is used to receive a first clock signal SCK1, the first terminal of the first input transistor T3 is used to receive an input signal SIN, and the second terminal of the first input transistor T3 is connected to the first node N1.

[0113] The second input unit 120 may include a second input transistor T4. The control terminal of the second input transistor T4 is used to receive a first clock signal SCK1, the first terminal of the second input transistor T4 is used to receive a first power supply signal VGL, and the second terminal of the second input transistor T4 is connected to the second node N2.

[0114] The types of the first input transistor T3 and the second input transistor T4 need to be set according to the actual situation. Figure 7 In the illustrated embodiment, both the first input transistor T3 and the second input transistor T4 are P-type transistors.

[0115] Specifically, when the first clock signal SCK1 is at a low level, both the first input transistor T3 and the second input transistor T4 are turned on. The first input transistor T3 transmits the input signal SIN to the first node N1, and the second input transistor T4 transmits the first power supply signal VGL to the second node N2.

[0116] In one embodiment, the node potential control module 200 includes a first inter-control unit 210 and a second inter-control unit 220. The first inter-control unit 210 is used to receive a first clock signal SCK1. The first inter-control unit 210 is connected to the first node N1 and the second node N2 respectively, and is used to control the potential of the second node N2 according to the first clock signal SCK1 in response to the effective potential of the first node N1.

[0117] The second mutual control unit 220 is used to receive the second clock signal SCK2 and the second power signal VGH. The second mutual control unit 220 is connected to the first node N1 and the second node N2 respectively, and is used to respond to the effective potential of the second node N2 and the effective potential of the second clock signal SCK2, and control the potential of the first node N1 according to the second power signal VGH.

[0118] The first mutual control unit 210 controls the potential of the second node N2, and the second mutual control unit 220 controls the potential of the first node N1. For example, the first mutual control unit 210 can pull the second node N2 to a high potential, and the second mutual control unit 220 can pull the potential of the second node N2 to a high potential. Thus, by combining the first mutual control unit 210 and the second mutual control unit 220, the input module 100 can make the potentials of the first node N1 and the second node N2 change according to actual control needs, thereby accurately controlling the output of the output module 300.

[0119] In actual implementation, the circuit structures of the first mutual control unit 210 and the second mutual control unit 220 can be set according to actual needs. In one embodiment, the first mutual control unit 210 may include a first mutual control transistor T5, the control terminal of the first mutual control transistor T5 is connected to the first node N1, the first terminal of the first mutual control transistor T5 is used to receive the first clock signal SCK1, and the second terminal of the first mutual control transistor T5 is connected to the second node N2.

[0120] The second mutual control unit 220 may include a second mutual control transistor T6 and a third mutual control transistor T7. The control terminal of the second mutual control transistor T6 is connected to the second node N2. The first terminal of the second mutual control transistor T6 is used to receive the second power supply signal VGH. The second terminal of the second mutual control transistor T6 is connected to the first terminal of the third mutual control transistor T7. The control terminal of the third mutual control transistor T7 is used to receive the second clock signal SCK2. The second terminal of the third mutual control transistor T7 is connected to the first node N1.

[0121] When the first node N1 is at an effective potential (e.g., a low potential), the first inter-control transistor T5 is turned on, transmitting the first clock signal SCK1 to the second node N2. When the second node N2 is at an effective low potential and the second clock signal SCK2 is at an effective potential (e.g., a low potential), both the second inter-control transistor T6 and the third inter-control transistor T7 are turned on, transmitting the second power supply signal VGH to the first node N1, thereby realizing the potential inter-control between the first node N1 and the second node N2.

[0122] In one embodiment, the output module 300 includes a first output unit 310 and a second output unit 320. The first output unit 310 is used to receive a second clock signal SCK2, and is connected to a third node N3. In response to the effective potential of the third node N3, the first output unit 310 outputs a scan signal Gout according to the second clock signal SCK2.

[0123] The second output unit 320 is used to receive the second power signal VGH. The second output unit 320 is connected to the fourth node N4 and the first output unit 310 respectively. In response to the effective potential of the fourth node N4, the second output unit 320 outputs the scan signal Gout according to the second power signal VGH.

[0124] Specifically, the first output unit 310 may include a first output transistor T8 and a first capacitor C1. The control terminal of the first output transistor T8 is connected to the third node N3. The first terminal of the first output transistor T8 is used to receive the second clock signal SCK2. The second terminal of the first output transistor T8 is the output terminal of the first output unit 310 (or the output terminal of the scanning circuit). The first terminal of the first capacitor C1 is connected to the control terminal of the first output transistor T8, and the second terminal of the first capacitor C1 is connected to the second terminal of the first output transistor T8.

[0125] The second output unit 320 may include a second output transistor T9 and a second capacitor C2. The control terminal of the second output transistor T9 is connected to the fourth node N4. The first terminal of the second output transistor T9 is used to receive the second power supply signal VGH. The second terminal of the second output transistor T9 is connected to the output terminal of the first output unit 310 (or the output terminal of the scanning circuit). The common terminal of the connection serves as the output terminal of the output module 300. The first terminal of the second capacitor C2 is connected to the control terminal of the second output transistor T9, and the second terminal of the second capacitor C2 is connected to the first terminal of the second output transistor T9.

[0126] To better understand the above embodiments, the following is combined with... Figure 7 and Figure 8 Provide a detailed explanation. Figure 7 In this embodiment, taking the first stable transistor T1 and the second stable transistor T2 as N-type transistors and the remaining transistors as P-type transistors, the scanning control signal connected to the first stable transistor T1 and the second stable transistor T2 is multiplexed with the light emission control signal EM.

[0127] Figure 8 This is a timing diagram of a scanning circuit in one embodiment. The operation of the scanning circuit may include stages ①-⑥:

[0128] In stage ①, the first clock signal SCK1 is at a low level, the first input transistor T3 and the second input transistor T4 are turned on, the first input transistor T3 transmits the high level of the input signal SIN to the first node N1, and the first node N1 is at a high level; the second input transistor T4 transmits the first power supply signal VGL to the second node N2, and the second node N2 is at a low level.

[0129] When the EM signal is at a low potential, the first stabilizing transistor T1 and the second stabilizing transistor T2 are off. The third node N3 maintains the high potential of the previous stage, the fourth node N4 maintains the low potential, and the second output transistor T9 is turned on, transmitting the second power supply signal VGH to the output terminal of the output module 300. Therefore, the scan signal Gout is at a high potential.

[0130] In stage ②, the first inter-controller T5 is off in response to the high potential of the first node N1. The second inter-controller T6 is turned on in response to the low potential of the second node N2, and the third inter-controller T7 is turned on in response to the low potential of the second clock signal SCK2. The second power supply signal VGH is transmitted to the first node N1 through the second inter-controller T6 and the third inter-controller T7, and the first node N1 is at a high potential.

[0131] When the EM signal is at a high potential, the first stabilizing transistor T1 and the second stabilizing transistor T2 are turned on. The high potential of the first node N1 is transmitted to the third node N3 through the first stabilizing transistor T1, making the third node N3 high. The low potential of the second node N2 is transmitted to the fourth node N4 through the second stabilizing transistor T2, making the fourth node N4 low. At this time, the second output transistor T9 is turned on, transmitting the second power supply signal VGH to the output terminal of the output module 300. Therefore, the scan signal Gout is at a high potential.

[0132] In stage ③, the first clock signal SCK1 is at a low level, the first input transistor T3 and the second input transistor T4 are turned on, the first input transistor T3 transmits the input signal SIN at a low level to the first node N1, the first node N1 is at a low level, and the second input transistor T4 transmits the first power supply signal VGL to the second node N2, the second node N2 is at a low level.

[0133] When the EM signal is high, both the first stabilizing transistor T1 and the second stabilizing transistor T2 are turned on. The low potential of the first node N1 is transmitted to the third node N3 through the first stabilizing transistor T1, and the third node N3 is now low. The low potential of the second node N2 is transmitted to the fourth node N4 through the second stabilizing transistor T2, and the fourth node N4 is now low. At this time, both the first output transistor T8 and the second output transistor T9 are turned on, transmitting the high potential of the second power supply signal VGH and the second clock signal SCK2 to the output terminal of the output module 300. Therefore, the scan signal Gout is high.

[0134] In stage ④, the first inter-control transistor T5 turns on in response to the low potential of the first node N1, and transmits the high potential of the first clock signal SCK1 to the second node N2.

[0135] When the EM signal is at a high potential, both the first stabilizing transistor T1 and the second stabilizing transistor T2 are turned on, the third node N3 is at a low potential, and the high potential of the second node N2 is transmitted to the fourth node N4 through the second stabilizing transistor T2, making the fourth node N4 high. At this time, the first output transistor T8 is turned on, transmitting the high potential of the second clock signal SCK2 to the output terminal of the output module 300, thus the scan signal Gout is at a high potential.

[0136] In stage ⑤, the state of each node remains unchanged, the second clock signal SCK2 changes from high potential to low potential, the first output transistor T8 transmits the low potential of the second clock signal SCK2 to the output terminal of the output module 300, so the scan signal Gout is at a low potential.

[0137] In stage ⑥, the first clock signal SCK1 is at a low level, the first input transistor T3 and the second input transistor T4 are turned on, the first input transistor T3 transmits the input signal SIN at a high level to the first node N1, the first node N1 is at a high level, and the second input transistor T4 transmits the first power supply signal VGL to the second node N2, the second node N2 is at a low level.

[0138] When the EM signal is at a high potential, both the first stabilizing transistor T1 and the second stabilizing transistor T2 are turned on. The high potential of the first node N1 is transmitted to the third node N3 through the first stabilizing transistor T1, making the third node N3 high. The low potential of the second node N2 is transmitted to the fourth node N4 through the second stabilizing transistor T2, making the fourth node N4 low. At this time, the second output transistor T9 is turned on, transmitting the second power supply signal VGH to the output terminal of the output module 300. Therefore, the scan signal Gout is at a high potential.

[0139] When the scan signal Gout needs to be output normally, the first stabilizing transistor T1 and the second stabilizing transistor T2 are turned on, allowing the scan signal Gout to be output normally. After the effective potential of the scan signal Gout is output, the first stabilizing transistor T1 and the second stabilizing transistor T2 are turned off. That is, during the operation of other stages of the scan circuit, the third node N3 and the fourth node N4 of this stage of the scan circuit are disconnected (the first capacitor C1 maintains the potential of the third node N3, and the second capacitor C2 maintains the potential of the fourth node N4). This avoids leakage of the second input transistor T4, the first inter-control transistor T5, and the second inter-control transistor T6 under the action of clock signal coupling, which would cause the potential of the fourth node N4 to drop; at the same time, it avoids leakage of the first input transistor T3 and the third inter-control transistor T7 under the action of clock signal coupling, which would cause the potential of the third node N3 to drop. Thus, the potentials of the third node N3 and the fourth node N4 can be maintained better, thereby improving the output stability of the first output transistor T8 and the second output transistor T9.

[0140] To verify the potential stabilization effect of the third node N3 and the fourth node N4 in the scanning circuit, the inventors based on Figure 1 The scanning circuit in the related technology shown, and Figure 7 The scanning circuit of the illustrated embodiment was simulated and compared; please refer to the following for details. Figures 9-13 .

[0141] Figure 9 This is a voltage diagram, with the horizontal axis representing time and the vertical axis representing voltage. Where 1 represents... Figure 7 The voltage waveform at the third node N3 of the scanning circuit shown is represented by 2. Figure 1 The voltage waveform at node B of the scanning circuit shown can be seen as follows: Figure 7 The average voltage of the third node N3 in the scanning circuit of the illustrated embodiment is significantly higher than the average voltage of node B in the related art. Specifically, please refer to... Figure 10 , Figure 10 for Figure 9 The enlarged schematic diagram of a portion of region 3 shows that the average voltage of the third node N3 has increased by more than 1.5V, which means that the average voltage of the gate of the first output transistor T8 has increased by more than 1.5V. The increased gate voltage makes the turn-off effect of the first output transistor T8 better, thus making the output more stable.

[0142] As can be seen, by setting the potential stabilization module 200, the voltage and current of the third node N3 and the fourth node N4 can be made more stable, improving the output stability of the output module 300 and thus improving the display quality of the display panel. At the same time, it can reduce the power consumption of the scanning circuit, which is conducive to the development of high resolution and high refresh rate of the display panel. Figure 11This is also a voltage diagram, with the horizontal axis representing time and the vertical axis representing voltage. The number 4 indicates... Figure 1 The voltage waveform at node A of the scanning circuit shown is represented by 5. Figure 7 The voltage waveform at the fourth node N4 of the scanning circuit shown is illustrated. It can be seen that in related technologies, the voltage drop at node A reaches approximately 2V. Figure 7 The voltage at the fourth node N4 of the scanning circuit shown is relatively stable, meaning the gate voltage of the second output transistor T9 is more stable. This improves the stability of the second output transistor T9, thereby enhancing output stability.

[0143] Figure 12 and Figure 13 This is a diagram illustrating current, with the horizontal axis representing time and the vertical axis representing current. The number 6 indicates... Figure 1 The current waveform at node B of the scanning circuit shown is represented by 7. Figure 7 The current waveform at the third node N3 of the scanning circuit shown. 8 represents... Figure 1 The current waveform at node A of the scanning circuit shown is represented by 9. Figure 7 The current waveform at the fourth node N4 of the scanning circuit is shown. It can be seen that, compared to related technologies, Figure 7 The currents at the third node N3 and the fourth node N4 of the scanning circuit shown are more stable.

[0144] In one embodiment, such as Figure 14 As shown, a gate driving circuit is provided, including multiple cascaded scanning circuits; wherein, the signal input terminal (which can receive the input signal SIN) of the first-stage scanning circuit is electrically connected to the start signal line, and the signal input terminal of the (i+1)th-stage scanning circuit is electrically connected to the output terminal (which can output the scanning signal) of the i-th-stage scanning circuit, where i is an integer greater than 0.

[0145] Specifically, the scanning circuit has n stages. The first stage scanning circuit receives the start signal as the input signal SIN. The structure of the scanning circuit can be set with reference to the above embodiments, and will not be repeated here.

[0146] In one embodiment, a display panel is provided, including a gate driving circuit, and the upper-level driving circuit can be configured as described in the above embodiment. The output stability of each scanning circuit in this gate driving circuit is higher, thus improving the display quality of the display panel and facilitating the development of high resolution and high refresh rate display panels.

[0147] In actual implementation, the display panel includes multiple pixel circuits and multiple cascaded light emission control signal generation circuits. The light emission control signal output by the light emission control signal generation circuit is provided to the corresponding pixel circuit, and the scan signal output by the scan circuit is provided to the corresponding pixel circuit, so that the pixel circuit controls the light emission of the light-emitting element according to the received light emission control signal and scan signal.

[0148] In one embodiment, the potential stabilization module in the scanning circuit is used to receive the scanning control signal and turn on / off according to the scanning control signal; the light emission control signal output by the light emission control signal generation circuit is used as the scanning control signal, or the signal output by the light emission control signal generation circuit that is opposite to the potential state of the light emission control signal is used as the scanning control signal.

[0149] Specifically, such as Figure 15 As shown, each scanning circuit is connected to a corresponding light emission control signal generation circuit, and the potential stabilization module 400 in each scanning circuit is controlled by the corresponding light emission control signal EM. In one embodiment, as... Figure 16 As shown, each scanning circuit is connected to a corresponding light-emitting control signal generation circuit. The potential stabilization module 400 in each scanning circuit is controlled by a signal EMB with a potential opposite to that of the light-emitting control signal EM. Therefore, the output stability of each scanning circuit can be improved without adding additional control signals, and the bezel of the display panel does not need to be increased.

[0150] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0151] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0152] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A scanning circuit, characterized in that, include: The input module is used to receive an input signal, a first power signal, and a first clock signal, and to transmit the input signal to a first node and the first power signal to a second node under the control of the first clock signal. A node potential control module is used to receive a second power signal, a first clock signal, and a second clock signal. The node potential control module is connected to the first node and the second node respectively. When the second node is at an effective potential, it responds to the effective potential of the second clock signal and controls the potential of the first node according to the second power signal. It is also used to respond to the valid potential of the first node and control the potential of the second node according to the first clock signal; The output module is used to receive the second clock signal and the second power signal. The output module is connected to the third node and the fourth node respectively, and is used to respond to the effective potential of the third node and output a scan signal according to the second clock signal. In response to the effective potential of the fourth node, a scanning signal is output according to the second power signal; wherein, the third node is used to connect to the first node, and the fourth node is used to connect to the second node; A potential stabilization module is disposed between the first node and the third node, and / or between the second node and the fourth node; the potential stabilization module switches to an on state before the input signal changes from an invalid potential to an effective potential; and switches to an off state after the scan signal changes from an effective potential to an invalid potential. The potential stabilization module is used to receive a scan control signal and turn on / off according to the scan control signal; the scan signal is used to output to the pixel circuit, and the timing of the scan control signal is matched with the timing of the light emission control stage of the pixel circuit; so that when the pixel circuit is in the non-light emission stage, the potential stabilization module is in the on state; when the pixel circuit is in the light emission stage, the potential stabilization module is in the off state, and the potential of the third node and / or the fourth node remains stable.

2. The scanning circuit according to claim 1, characterized in that, The scanning circuit includes a signal transmission circuit, which receives a transmission signal and outputs the scanning control signal according to the transmission signal.

3. The scanning circuit according to claim 2, characterized in that, The potential stabilization module includes a first stabilizing transistor and / or a second stabilizing transistor, and the scan control signal includes a first scan control signal and / or a second scan control signal; The control terminal of the first stable transistor is used to receive the first scan control signal. The first terminal of the first stable transistor is connected to the first node, and the second terminal of the first stable transistor is connected to the third node. The control terminal of the second stabilizing transistor is used to receive the second scan control signal. The first terminal of the second stabilizing transistor is connected to the second node, and the second terminal of the second stabilizing transistor is connected to the fourth node.

4. The scanning circuit according to claim 3, characterized in that, The first stable transistor is an N-type transistor.

5. The scanning circuit according to claim 4, characterized in that, The second stabilizing transistor is an N-type transistor, and both the first scan control signal and the second scan control signal are light emission control signals of the pixel circuit.

6. The scanning circuit according to claim 4, characterized in that, The second stabilizing transistor is a P-type transistor, the first scan control signal is the light emission control signal of the pixel circuit, and the potential state of the second scan control signal is opposite to the potential state of the first scan control signal.

7. The scanning circuit according to claim 3, characterized in that, The first stable transistor is a P-type transistor.

8. The scanning circuit according to claim 7, characterized in that, The width of the channel of the first stable transistor is less than or equal to its length.

9. The scanning circuit according to claim 7, characterized in that, The second stabilizing transistor is a P-type transistor. The potential state of the first scan control signal is opposite to the potential state of the light emission control signal of the pixel circuit. The potential state of the second scan control signal is synchronized with that of the first scan control signal.

10. The scanning circuit according to claim 9, characterized in that, The width of the channel of the second stable transistor of the P type is less than or equal to its length.

11. The scanning circuit according to claim 7, characterized in that, The second stabilizing transistor is an N-type transistor, the second scanning control signal is the light emission control signal of the pixel circuit, and the potential state of the first scanning control signal is opposite to the potential state of the second scanning control signal.

12. The scanning circuit according to claim 1, characterized in that, The input module includes: The first input unit is configured to receive the input signal and the first clock signal, and to transmit the input signal to the first node under the control of the first clock signal. The second input unit is used to receive the first power signal and the first clock signal, and to transmit the first power signal to the second node under the control of the first clock signal.

13. The scanning circuit according to claim 12, characterized in that, The first input unit includes a first input transistor, the control terminal of the first input transistor is used to receive the first clock signal, the first terminal of the first input transistor is used to receive the input signal, and the second terminal of the first input transistor is connected to the first node; The second input unit includes a second input transistor, the control terminal of the second input transistor is used to receive the first clock signal, the first terminal of the second input transistor is used to receive the first power signal, and the second terminal of the second input transistor is connected to the second node.

14. The scanning circuit according to claim 1, characterized in that, The node potential control module includes: The first mutual control unit is used to receive the first clock signal. The first mutual control unit is connected to the first node and the second node respectively. It is used to respond to the effective potential of the first node and control the potential of the second node according to the first clock signal. The second mutual control unit is used to receive the second clock signal and the second power signal. The second mutual control unit is connected to the first node and the second node respectively, and is used to respond to the effective potential of the second node and the effective potential of the second clock signal, and control the potential of the first node according to the second power signal.

15. The scanning circuit according to claim 14, characterized in that, The first mutual control unit includes a first mutual control transistor, the control terminal of the first mutual control transistor is connected to the first node, the first terminal of the first mutual control transistor is used to receive the first clock signal, and the second terminal of the first mutual control transistor is connected to the second node; The second mutual control unit includes a second mutual control transistor and a third mutual control transistor. The control terminal of the second mutual control transistor is connected to the second node. The first terminal of the second mutual control transistor is used to receive the second power signal. The second terminal of the second mutual control transistor is connected to the first terminal of the third mutual control transistor. The control terminal of the third mutual control transistor is used to receive the second clock signal. The second terminal of the third mutual control transistor is connected to the first node.

16. The scanning circuit according to claim 1, characterized in that, The output module includes a first output unit and a second output unit; The first output unit is used to receive the second clock signal. The first output unit is connected to the third node. The first output unit is used to respond to the effective potential of the third node and output a scan signal according to the second clock signal. The second output unit is used to receive the second power signal. The second output unit is connected to the fourth node and the first output unit respectively. The second output unit is used to respond to the effective potential of the fourth node and output a scan signal according to the second power signal.

17. The scanning circuit according to claim 16, characterized in that, The first output unit includes a first output transistor and a first capacitor. The control terminal of the first output transistor is connected to the third node. The first terminal of the first output transistor is used to receive the second clock signal, and the second terminal of the first output transistor is the output terminal of the first output unit. The first terminal of the first capacitor is connected to the control terminal of the first output transistor, and the second terminal of the first capacitor is connected to the second terminal of the first output transistor. The second output unit includes a second output transistor and a second capacitor. The control terminal of the second output transistor is connected to the fourth node. The first terminal of the second output transistor is used to receive the second power signal. The second terminal of the second output transistor is connected to the output terminal of the first output unit. The first terminal of the second capacitor is connected to the control terminal of the second output transistor. The second terminal of the second capacitor is connected to the first terminal of the second output transistor.

18. A gate driving circuit comprising a plurality of cascaded scanning circuits as described in any one of claims 1 to 17; wherein, The signal input terminal of the first-stage scanning circuit is electrically connected to the starting signal line, and the signal input terminal of the (i+1)th-stage scanning circuit is electrically connected to the output terminal of the ith-stage scanning circuit, where i is an integer greater than 0.

19. A display panel, characterized in that, Includes the gate drive circuit as described in claim 18.

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