Time synchronization method and apparatus, electronic device, and storage medium

Abstract

The present disclosure relates to a time synchronization method and device, electronic equipment and storage medium. The method comprises: obtaining a plurality of groups of transmission information calculated between a master device and a slave device; obtaining an average time deviation and an average network delay between the master device and the slave device based on the plurality of groups of transmission information; adjusting the system time of the slave device based on the average time deviation, obtaining the network delay between the adjusted master device and the slave device, and obtaining the time deviation between the master device and the slave device if the difference between the network delay and the average network delay is less than a first threshold; obtaining the deviation between the system time and the master clock, adjusting the system time based on the deviation, and synchronizing the system time of the slave device based on the time deviation if the time deviation between the master device and the slave device is less than a second threshold. By offsetting the predictable deviation introduced and the deviation in the link, the time synchronization accuracy can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a time synchronization method and device, electronic equipment and storage medium. BACKGROUND

[0002] In a communication network, normal operation of most telecommunication services requires that the time difference between devices in the whole network is maintained within a reasonable error level, i.e. time synchronization. However, due to the existence of certain precision of devices (for example + / - 20ns), in actual transmission network time synchronization applications, transmission devices mainly undertake the intermediate BC (Boundary Clock) unit, and there are usually 10 to 20 hop transmission devices. Therefore, for example, when the number of devices increases to 20 hops, the deviation will increase hop by hop, and the theoretical deviation may reach about 400ns. With the increase of the number of hops, the precision deviation value will gradually increase.

[0003] In the related art, if the precision of the device is improved, the time synchronization precision of the single-hop device is improved by improving the hardware capability, which requires higher hardware and has larger hardware cost; and cannot solve the problem of decreasing time synchronization precision with the increase of the number of devices. If the time synchronization application is actually deployed, the end-to-end time deviation is measured first, and the time deviation is compensated into the system to improve the time synchronization precision. In this way, when the number of devices increases, the length of the optical fiber changes, and various network configurations change, it is necessary to re-measure, which has large engineering implementation difficulty and cost. Therefore, the efficiency is low in solving the problem of decreasing time synchronization precision in the related art. SUMMARY

[0004] The present disclosure provides a time synchronization method, device, electronic equipment and storage medium.

[0005] According to a first aspect of the present disclosure, a time synchronization method is provided, the method comprising:

[0006] obtaining a plurality of sets of transmission information calculated between a master device and a slave device; wherein the transmission information comprises a time deviation and a network delay;

[0007] obtaining an average time deviation and an average network delay between the master device and the slave device based on the plurality of sets of transmission information;

[0008] adjusting the system time of the slave device based on the average time deviation, and obtaining the network delay between the master device and the slave device after adjustment; and obtaining the time deviation between the master device and the slave device in the case that the difference between the network delay and the average network delay is less than a first threshold value;

[0009] obtaining a deviation between the system time and a master clock, adjusting the system time based on the deviation, and synchronizing the system time of the slave device based on a time deviation between the master device and the slave device if the time deviation is less than a second threshold.

[0010] According to a second aspect of the present disclosure, there is provided a time synchronization apparatus, comprising:

[0011] a first information obtaining module configured to obtain a plurality of sets of transmission information calculated between a master device and a slave device, wherein the transmission information comprises a time deviation and a network delay;

[0012] a second information obtaining module configured to obtain an average time deviation and an average network delay between the master device and the slave device based on the plurality of sets of transmission information;

[0013] a third information obtaining module configured to adjust a system time of the slave device based on the average time deviation, and obtain a network delay between the master device and the slave device after the adjustment, and obtain a time deviation between the master device and the slave device if a difference between the network delay and the average network delay is less than a first threshold;

[0014] a time synchronization module configured to obtain a deviation between the system time and a master clock, adjust the system time based on the deviation, and synchronize the system time of the slave device based on a time deviation between the master device and the slave device if the time deviation is less than a second threshold.

[0015] According to a third aspect of the present disclosure, there is provided an electronic device. The electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the method as described above when executing the program.

[0016] According to a fourth aspect of the present disclosure, there is provided a computer readable storage medium, which stores a computer program, and the program is executed by a processor to implement the method as described above.

[0017] The time synchronization method, device, electronic device and storage medium provided by the embodiments of the present disclosure obtain the average time offset and the average network delay between the master device and the slave device based on the multiple sets of transmission information containing the time offset and the network delay between the master device and the slave device, adjust the system time of the slave device based on the average time offset, obtain the network delay between the master device and the slave device after the adjustment, and obtain the time offset between the master device and the slave device when the difference between the network delay and the average network delay is less than a first threshold. The offset between the system time and the master clock is obtained, the system time is adjusted based on the offset, and the system time of the slave device is synchronized based on the time offset when the time offset between the master device and the slave device is less than a second threshold. The introduced predictable offset and the offset in the link are offset, so that the time synchronization accuracy can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] In the following description of exemplary embodiments in conjunction with the accompanying drawings, more details, features and advantages of the present disclosure are disclosed, in which:

[0019] Figure 1 The interaction schematic diagram between the master device and the slave device provided by an exemplary embodiment of the present disclosure is provided.

[0020] Figure 2 The schematic diagram of the system time corrected by offset provided by an exemplary embodiment of the present disclosure is provided.

[0021] Figure 3 The schematic diagram of the offset value range in the multi-hop process provided by an exemplary embodiment of the present disclosure is provided.

[0022] Figure 4 The flowchart schematic block diagram of the time synchronization method provided by an exemplary embodiment of the present disclosure is provided.

[0023] Figure 5 The functional module schematic block diagram of the time synchronization device provided by an exemplary embodiment of the present disclosure is provided.

[0024] Figure 6 The structural block diagram of the electronic device provided by an exemplary embodiment of the present disclosure is provided.

[0025] Figure 7 The structural block diagram of the computer system provided by an exemplary embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0026] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so as to more completely and thoroughly understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for illustrative purposes and are not intended to limit the scope of protection of the present disclosure.

[0027] It should be understood that each of the steps recited in the method embodiments of the present disclosure can be performed in different orders and / or in parallel. In addition, the method embodiments can include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0028] The term "comprising" and variations thereof as used herein are open-ended, that is "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Related terms are defined in the following description. It should be noted that the concepts mentioned in the present disclosure are merely used to distinguish different devices, modules or units, and are not intended to limit the order or interdependence of the functions performed by these devices, modules or units.

[0029] It should be noted that the modification of "one" or "multiple" mentioned in the present disclosure is illustrative rather than limiting, and those skilled in the art should understand that, unless otherwise explicitly indicated in the context, it should be understood as "one or more".

[0030] The names of the messages or information exchanged between the devices in the embodiments of the present disclosure are only for illustrative purposes, and are not intended to limit the scope of the messages or information.

[0031] It can be understood that, before using the technical solutions disclosed in the embodiments of the present disclosure, the type, scope of use, use scenario, etc. of the personal information involved in the present disclosure should be informed to the user and the authorization of the user should be obtained in a proper manner according to relevant laws and regulations.

[0032] For example, when responding to the active request of the user, a prompt information is sent to the user to explicitly prompt the user that the operation requested to be performed will require the acquisition and use of the personal information of the user. Thus, the user can voluntarily choose whether to provide the personal information to the software or hardware such as electronic device, application program, server or storage medium, etc. performing the operation of the technical solutions of the present disclosure according to the prompt information.

[0033] As an optional but non-limiting implementation, in response to receiving the active request of the user, the manner of sending the prompt information to the user may be, for example, a pop-up window manner in which the prompt information may be presented in a text manner. In addition, the pop-up window may also carry a selection control for the user to select "agree" or "disagree" to provide the personal information to the electronic device. It can be understood that the above notification and the process of obtaining the authorization of the user are only illustrative and do not limit the implementation of the present disclosure, and other manners meeting the relevant laws and regulations can also be applied to the implementation of the present disclosure.

[0034] According to the basic principle of IEEE1588 synchronization, the device adjusts the time precision by a fixed step size. Taking the current mainstream precision Class B as an example, the device precision is + / -20ns per hop. Therefore, after adjusting the time precision of the device to + / -20ns, it will not be adjusted. Then when the device increases to 20 hops, the deviation increases hop by hop. The theoretical deviation should reach about 400ns. With the increase of the number of hops, the precision deviation value will gradually increase. Therefore, time synchronization is needed to reduce the precision deviation.

[0035] Among them, the 1588 protocol is defined by IEEE, and the full name is "Precision Clock Synchronization Protocol for Networked Measurement and Control Systems", which is abbreviated as PTP (Precision Time Protocol) protocol. 1588 is divided into 1588v1 and 1588v2 two versions, 1588v1 can only achieve sub-millisecond time synchronization precision, and 1588v2 can achieve sub-microsecond synchronization precision. 1588v2 is defined as a time synchronization protocol and can be used for high-precision time synchronization between devices.

[0036] The network that applies time synchronization can be referred to as a time synchronization network. The time synchronization network can be divided into two levels, the first level node can use a first level time synchronization device, the second level node can use a second level time synchronization device, and the devices below the second level node can include servers or clients that need time synchronization.

[0037] The embodiments of the present disclosure support 1588v2 (including derivative protocols such as ITU-T G.8275.1), which can improve the whole network time synchronization precision of the device, and solve the problem of gradual degradation of network clock precision in a multi-hop scenario. Moreover, according to the 1588V2 synchronization principle, the master-slave device deviation is automatically calculated and adjusted, so as to achieve the effect of mutual offset of the time deviation of the whole synchronization link.

[0038] According to whether the message carries a timestamp, the 1588v2 message can be divided into two categories: event message and general message. Among them, the event message is a time concept message, and the accurate timestamp is stamped when entering and exiting the device port, which is used to calculate the time offset and path delay between the master and slave clocks. The event message includes Sync, Delay_Req and Delay_Resp. In the embodiment, the event message can be used to more conveniently obtain the time corresponding to the timestamp, such as Figure 1 As shown in the figure, t1, t2, t3 and t4 can be obtained. Figure 1 In the formula, Master is the master device, and Slave is the slave device. The relationship between Master and Slave is master-slave.

[0039] As shown in the figure, Figure 1 The master device sends a Sync message at time t1. If the master device is in one-step mode, t1 is transmitted with the Sync message to the slave device, and the slave device receives the Sync message at time t2 and obtains t1 from the Sync message; the slave device sends a delay request message Delay_Req to the master device at time t3, and the master device receives the Delay_Req message at time t4. The master device then sends t4 to the slave device through a delay response message Delay_Resp.

[0040] The basic principle of 1588v2 time synchronization is that the master-slave devices transmit and receive time synchronization messages in both directions, and the round-trip total delay between the two devices is calculated according to the transmission and reception timestamps of the message. If the time delays in both directions are the same, the round-trip total delay divided by 2 is the one-way delay, and according to this, the time offset of Slave to Master can be obtained.

[0041] In the embodiment, offset represents the time offset of the master-slave devices, and delay represents the delay time caused by network transmission. If the transmission and reception path delays in Figure 1 are consistent, the following relationship exists:

[0042] delay = [(t2 - t1) + (t4 - t3)] / 2 (1)

[0043] offset = [(t2 - t1) - (t4 - t)] / 2 (2)

[0044] As shown in the figure, Figure 2 The device calculates the time offset offset of the local clock and the master clock source through the 1588v2 protocol, and then corrects the local clock. This continuous synchronization process ensures the time synchronization of Slave to Master.

[0045] If the path delay between Master and Slave is asymmetric, a synchronization error will be introduced, and the error size is half of the path delay difference in two directions. Therefore, the key of 1588v2 high-precision time synchronization is that the delay between two nodes is as stable as possible without jitter. The link delay can generally meet this condition, but the forwarding delay of the device has large jitter. Therefore, the delay correction field needs to be involved in the calculation of the Delay mode in the 1588v2 protocol of the IEEE standard, so as to obtain the correct average path delay Delay and time offset Offset. In the embodiment, it is assumed that Δ is the delay difference between the Tx path (transmission path) and the Rx path (reception path) of the Master, and the following relationships exist:

[0046] delay = ((t2 –t1) + (t4–t3)) / 2-△ / 2 (3)

[0047] offset = ((t2 –t1) - (t4–t3)) / 2 -△ / 2 (4)

[0048] Therefore, under the premise of frequency synchronization, the time deviation caused by link asymmetry is half of the link asymmetry delay, and as long as the deviation caused by link asymmetry is offset, the time precision of the entire network can be greatly improved, so that the ordinary-precision device can complete the effect of the high-precision network.

[0049] In the embodiment, the device does not accurately calculate the value of Δ at each hop, but can adjust a certain amount of offset in the positive direction or a certain amount of offset in the negative direction, so as to offset part of the Δ deviation at the end of the link. In the embodiment, Δ can refer to the deviation introduced by the asymmetry of the transmission and reception link. The larger the deviation, the worse the time precision of 1588. In the embodiment, the Δ of different devices is offset to each other, so that the Δ of the entire link tends to be 0, thereby providing the time precision of 1588 of the entire link.

[0050] In the embodiment, the way of obtaining Δ can include: being obtained by a dedicated instrument measurement; being obtained by conversion calculation of the fiber length of the transmission and reception paths. Different optical fibers, wavelengths, and refractive indexes cause slight differences in the delay per meter, but the deviation is not large; and being obtained by internal calculation of the device. The two time-synchronized devices (at this time, the offset is known to be 0) can be used to calculate Δ by using the offset formula.

[0051] In the embodiment, to offset the deviation caused by link asymmetry and improve the time precision of the device, the embodiment can include the following steps:

[0052] Step one: after the entire network is configured with 1588, the result is negotiated by BMC (Best Master Clock, Best Master Clock algorithm mobile communication network) algorithm, and the state decision is completed, the slave device starts to extract t1, t2, t3, t4, and calculates the offset and delay between the master and slave devices according to the above method, at this time, the system time of the slave end is not adjusted. Each group of t1, t2, t3, t4 can calculate the delay and offset once, and the value calculated by the first group of t1, t2, t3, t4 can be discarded in order to eliminate the error introduced by the first message negotiation, and the operation does not affect the calculation speed.

[0053] Step two: each group of t1, t2, t3, t4 can calculate the delay and offset once, and the calculation results delay and offset are cached. In the embodiment, after at least 3 times of calculation, the delay and offset of the last 3 times are compared. If the difference between the 3 results is within 5ns, that is, the difference between the delay obtained by the 3 times and the difference between the offset obtained by the 3 times is less than the threshold value, it is considered that the stable delay and offset are obtained, the average value of 3 times is calculated, and the average value of delay and offset is recorded as the result. Otherwise, discard the calculation of the last 3 groups and execute step two again. The threshold value depends on the system accuracy. The more stable the system clock is, the smaller the value can be set. The embodiment takes 5ns as an example to illustrate, and the embodiment is not limited thereto.

[0054] Step three: adjust the system time of the slave end according to the offset value calculated in the above step once, stop adjusting and calculate the delay and offset value according to step two again, compare the delay this time with the delay recorded in step two, if the difference is within 5ns, it is considered that the system is normal, record the offset value, otherwise it is considered that the system is abnormal, and calculate according to step three again.

[0055] Step four: according to the positive or negative of the offset value obtained in the above steps, the time deviation between the current system and the time corresponding to the master clock is determined. If the time deviation is positive, it means that the first offset adjustment is less, and needs to be adjusted positively. If the time deviation is negative, it means that the first offset adjustment is too much, and needs to be adjusted in the opposite direction. Step three is repeated until the offset calculation result is within 20ns and approaches 0, and a stable offset of the system is finally obtained. It should be noted that the final offset value can be obtained according to the empirical value. This value is the value of the time error adjustment. For example, a more reasonable value can be obtained according to the system measurement, and the embodiments are not limited thereto. After the above steps, some predictable deviations are introduced artificially, which roughly offset the deviations introduced by the link asymmetry, thereby automatically improving the time synchronization precision. Then, after spreading to the whole network, the whole precision controllable goal can be achieved.

[0056] Based on the above embodiments, in the embodiments provided in the present disclosure, in order to further control the whole network time synchronization precision, the step mechanism can also be used to synchronize the time of the whole network.

[0057] In the embodiments, the time synchronization can be specifically realized by the clock interface module and the clock processing module. The clock interface module is used to extract and insert the clock message and clock information downward while the service is accessed, such as t1, t2, t3 and t4 in the above embodiments. The clock processing module is responsible for analyzing the clock information extracted by the interface module and performing calculation, adjusting the clock of the device according to the calculation result, and transmitting the clock information downward.

[0058] In the embodiments, after the clock processing module receives the clock information extracted by the clock interface module, it is detected that the step value in the information is odd, and the offset positive direction is adjusted when the clock is adjusted. The stop adjustment interval is 0ns-20ns, and the offset value can be obtained by the above method. When it is detected that the step in the information is even, the offset negative direction is adjusted, that is, the stop adjustment interval is -20ns-0ns. After such calculation and adjustment, the clock tracking condition is as shown in Figure 3

[0059] ​In the embodiment, for the entire network, a plurality of nodes, such as node 1, node 2, node 3, and the like, can be included. In the process of time synchronization, the odd nodes are uniformly offset to positive, that is, offset takes a positive value; the even nodes are uniformly offset to negative, that is, offset takes a negative value; therefore, the end-to-end deviation is the sum of all odd nodes plus the sum of all even nodes, and the positive and negative deviations can cancel each other out most, so that the end-to-end time deviation remains normal, far lower than the average level of 20-hop network elements, and will not exceed the limit value 400ns in the related art, which can greatly improve the end-to-end time synchronization accuracy.

[0060] In this way, the deviations of the two devices before and after can be mostly canceled out, so that the deviation does not increase linearly regardless of the increase in the number of hops, but is controlled within a deviation of one-hop network element. Taking mainstream precision Class B as an example, the precision is about + / - 20ns, which is much higher than the actual business requirement of + / - 1us.

[0061] Based on the above embodiment, in another embodiment provided by the present disclosure, a time synchronization method is provided, as shown in the following table: Figure 4 The method can include the following steps:

[0062] In step S410, a plurality of sets of transmission information calculated between the master device and the slave device are obtained.

[0063] The transmission information includes time deviation and network delay.

[0064] In the embodiment, a plurality of sets of transmission information including time deviation and network delay can be obtained, and each set of transmission information can include one time deviation and one network delay.

[0065] In step S420, based on the plurality of sets of transmission information, an average time deviation and an average network delay between the master device and the slave device are obtained.

[0066] In the embodiment, the time deviation and the network delay between the master device and the slave device can be calculated according to the manner provided in the above embodiment. For example, a target message and a link delay difference value transmitted between the master device and the slave device can be obtained, and the time deviation and the network delay can be obtained based on the timestamp and the link delay difference value. The target message carries a timestamp. The target message can include the Sync, Delay_Req, and Delay_Resp messages in the above embodiment.

[0067] In the embodiment, offset and delay calculated from, for example, at least three sets of messages can be obtained, and the obtained three sets of offset and delay are averaged respectively to obtain an average time deviation and an average network delay, that is, an average offset and an average delay.

[0068] In step S430, the system time of the slave device is adjusted based on the average time deviation, the network delay between the master device and the slave device after adjustment is obtained, and the time deviation between the master device and the slave device is obtained when the difference between the network delay and the average network delay is less than the first threshold.

[0069] In the embodiment, the first threshold can be set to 5 ns, and can be set as required, and the embodiment is not limited thereto.

[0070] The time difference between the system time of the slave device and the time corresponding to the master clock can be obtained, the first time deviation is adjusted based on the time difference, the adjusted time deviation is obtained, and the system time of the slave device is adjusted based on the adjusted time deviation.

[0071] In step S440, the deviation between the system time and the master clock is obtained, the system time is adjusted based on the deviation, and the system time of the slave device is synchronized based on the time deviation when the time deviation between the master device and the slave device is less than the second threshold.

[0072] In the embodiment, the system time of the slave device can be adjusted according to the offset obtained above, and the offset and the delay between the master device and the slave device are recalculated after the adjustment is completed. Whether the absolute value of the difference between the delay and the delay is less than the second threshold can be compared. The second threshold can be 5 ns, and can be set as required. If the absolute value of the difference between the delay and the delay is less than the second threshold, it is confirmed that the system is normal, otherwise it is determined that the system is abnormal, and the delay and the offset can be recalculated.

[0073] In the embodiment, when the time deviation is not less than the threshold, the system time of the slave device is adjusted until the time deviation is less than the second threshold, so that the system time of the slave device can be synchronized based on the time deviation, and the time synchronization is realized.

[0074] In the time synchronization method provided in the embodiments of the present disclosure, a plurality of sets of transmission information containing time deviation and network delay between the master device and the slave device are obtained, and the average time deviation and the average network delay between the master device and the slave device are obtained based on the plurality of sets of transmission information. The system time of the slave device is adjusted based on the average time deviation, and the network delay between the master device and the slave device after adjustment is obtained. When the difference between the network delay and the average network delay is less than the first threshold, the time deviation between the master device and the slave device is obtained. The deviation between the system time and the master clock is obtained, the system time is adjusted based on the deviation, and the system time of the slave device is synchronized based on the time deviation when the time deviation between the master device and the slave device is less than the second threshold. By introducing some predictable deviations, the deviations introduced by the asymmetric link are offset, so that the time synchronization accuracy can be improved.

[0075] Based on the above embodiments, in yet another embodiment provided by the present disclosure, the target message includes at least N groups of messages, and the N groups of messages respectively carry timestamps; the step S410 can include the following steps:

[0076] In step S411, a plurality of groups of messages transmitted between the master device and the slave device are obtained.

[0077] The message carries a timestamp.

[0078] In step S412, a plurality of groups of transmission information between the master device and the slave device are obtained based on the timestamps respectively carried by the plurality of groups of messages, and a first group of transmission information in the plurality of groups of transmission information is discarded.

[0079] In the embodiment, a plurality of groups of time deviations and network delays transmitted between the master device and the slave device can be obtained, and a first group of time deviations and network delays can be discarded, and the remaining groups are taken as a plurality of groups of transmission information calculated between the master device and the slave device. Specifically, in the embodiment, a plurality of groups of time deviations and network delays can be obtained, each group of time deviations and network delays can obtain a group of time, for example, t1, t2, t3 and t4, and each group of time can calculate a time deviation offset and a network delay delay. Since the first message negotiation will introduce errors, the offset and delay calculated according to the first group t1, t2, t3 and t4 can be discarded, and a plurality of groups of transmission information including time deviations and network delays are obtained.

[0080] In the embodiment provided by the present disclosure, based on the above embodiments, the step S420 can further include the following steps:

[0081] In step S421, it is determined whether the difference between any two time deviations and the difference between any two network delays in the plurality of groups of transmission information are both less than a first threshold value.

[0082] In step S422, in the case that the difference between any two time deviations and the difference between any two network delays in the plurality of groups of transmission information are both less than the first threshold value, the average of the plurality of time deviations and the average of the plurality of network delays in the plurality of groups of transmission information are calculated to obtain an average time deviation and an average network delay, respectively.

[0083] And in the embodiments, if the difference between any two time deviations in the plurality of sets of transmission information and the difference between any two network delays are not less than the first threshold value, the plurality of sets of transmission information can be discarded, and the plurality of sets of transmission information between the master device and the slave device are recalculated until the difference between any two time deviations in the plurality of sets of transmission information and the difference between any two network delays are less than the first threshold value.

[0084] In the embodiments provided in the present disclosure, the above-mentioned each set of t1, t2, t3 and t4 can calculate a delay and an offset, after at least three times of calculation, the delay of the last three times and the offset of the last three times are compared, if the difference between the results of the three times is less than the first threshold value, for example, less than 5 ns, it is considered that the stable delay and offset are obtained, the average value of the three times of calculation is calculated, and the average value of the delay and the offset is recorded as the result, otherwise, the calculation of the three sets of this time is discarded, and the delay and the offset are recalculated. In this way, the offset obtained by averaging three times can be taken as the first time deviation, and the delay obtained by averaging three times can be taken as the first network delay, so that the delay and the offset obtained in this way are more accurate.

[0085] In the embodiments provided in the present disclosure, the method can further include the following steps:

[0086] In step S450, clock information is obtained, and the clock information includes a step value;

[0087] In step S460, when the step value is odd, the system time of the slave device is adjusted, and when the time deviation is within a first preset range, the adjustment of the system time is stopped; or when the step value is even, the system time of the slave device is adjusted, and when the time deviation is within a second preset range, the adjustment of the system time is stopped.

[0088] In the embodiments, the time synchronization can be specifically realized by a clock interface module and a clock processing module. The clock interface module is used to extract and insert a clock message and clock information at the same time of business access, for example, t1, t2, t3 and t4 in the above-mentioned embodiments; the clock processing module is responsible for analyzing the clock information extracted by the interface module and performing calculation, adjusting the clock of the device according to the calculation result, and transmitting the clock information downward. The above-mentioned embodiments can be combined with the above-mentioned embodiments. Figure 3 The corresponding embodiments are described, and details are not repeated here.

[0089] Based on the above-mentioned embodiments, in another embodiment provided in the present disclosure, the method can further include the following steps:

[0090] In step S470, the parity of the node number corresponding to the slave device is obtained.

[0091] In the embodiment, the delay and offset between different master-slave devices are calculated according to the above method, and the values of the delay and offset may be different. In order to offset the bias caused by the link asymmetry between different devices, the positive and negative of the offset of different slave devices need to be determined so as to offset in the positive network.

[0092] In step S480, the positive and negative values corresponding to the second time bias are determined based on the parity of the node number. Each slave device includes a corresponding node number, and the positive and negative values corresponding to the time bias of two slave devices with adjacent node numbers are different.

[0093] In the embodiment, the node number can be obtained, and the offset corresponding to the node number with an odd number is a positive value, and the offset corresponding to the node number with an even number is a negative value. For example, the values of the offset corresponding to node 1, node 2, node 3, … are 20 ns, -30 ns, 15 ns, …, respectively. In this way, the end-to-end bias is the sum of all odd nodes plus the sum of all even nodes, and the positive and negative biases can offset each other, the end-to-end bias remains normal, which is much lower than the average level of 20-hop network elements, and the limit value 400 ns will not appear, which can greatly improve the end-to-end time synchronization accuracy.

[0094] In the case of dividing each functional module according to each function, the embodiment of the present disclosure provides a time synchronization device, which can be a server or a chip applied to a server. Figure 5 The functional module schematic diagram of the time synchronization device provided by an exemplary embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the time synchronization device includes: Figure 5

[0095] The first information acquisition module 10 is configured to acquire a plurality of groups of transmission information calculated between the master device and the slave device; wherein the transmission information includes a time bias and a network delay;

[0096] The second information acquisition module 20 is configured to obtain an average time bias and an average network delay between the master device and the slave device based on the plurality of groups of transmission information;

[0097] The third information acquisition module 30 is configured to adjust the system time of the slave device based on the average time bias, acquire the network delay between the master device and the slave device after adjustment, and acquire the time bias between the master device and the slave device when the difference between the network delay and the average network delay is less than a first threshold value;

[0098] ​The time synchronization module 30 is used to obtain the deviation between the system time and the master clock, adjust the system time based on the deviation, and synchronize the system time of the slave device based on the time deviation when the time deviation between the master device and the slave device is less than a second threshold.

[0099] In another embodiment provided by the present disclosure, the first information acquisition module is specifically configured to:

[0100] Acquire multiple groups of messages transmitted between the master device and the slave device, the messages carrying timestamps;

[0101] Based on the timestamps respectively carried by the multiple groups of messages, multiple groups of transmission information between the master device and the slave device are obtained, and the first group of transmission information among the multiple groups of transmission information is discarded.

[0102] In another embodiment provided by the present disclosure, the second information acquisition module is specifically configured to:

[0103] Determining whether a difference between any two time offsets and a difference between any two network delays in the plurality of sets of transmission information are both less than a first threshold;

[0104] When the difference between any two time deviations and the difference between any two network delays in the multiple groups of transmission information are both less than the first threshold, the average value of multiple time deviations and the average value between multiple network delays in the multiple groups of transmission information are calculated to obtain the average time deviation and average network delay, respectively.

[0105] In another embodiment provided by the present disclosure, the apparatus further includes:

[0106] A processing module is used to discard the multiple groups of transmission information when the difference between any two time deviations and the difference between any two network delays in the multiple groups of transmission information are not both smaller than a first threshold, and recalculate the multiple groups of transmission information between the master device and the slave device until the difference between any two time deviations and the difference between any two network delays in the multiple groups of transmission information are both smaller than the first threshold.

[0107] In another embodiment provided by the present disclosure, the time synchronization module is specifically configured to:

[0108] When the deviation between the system time and the master clock is a positive number, adjusting the system time in a positive direction;

[0109] Alternatively, when the deviation between the system time and the master clock is negative, adjust the system time in the reverse direction;

[0110] stop adjusting the system time of the slave device in a case where the time deviation between the master device and the slave device is less than a second threshold.

[0111] In a further embodiment provided by the present disclosure, the apparatus further comprises:

[0112] a clock information obtaining module configured to obtain clock information, the clock information comprising a step value;

[0113] an adjusting module configured to adjust the system time of the slave device in a case where the step value is odd, and stop adjusting the system time in a case where the time deviation is within a first preset range; or adjust the system time of the slave device in a case where the step value is even, and stop adjusting the system time in a case where the time deviation is within a second preset range.

[0114] In a further embodiment provided by the present disclosure, the apparatus further comprises:

[0115] a number obtaining module configured to obtain the parity of the node number corresponding to the slave device;

[0116] a range determining module configured to determine the positive or negative value corresponding to the second time deviation based on the parity of the node number; wherein each slave device comprises a corresponding node number, and the positive or negative value corresponding to the time deviation of two slave devices with adjacent node numbers is different.

[0117] The time synchronization apparatus provided by the embodiments of the present disclosure obtains the average time deviation and the average network delay between the master device and the slave device based on the plurality of sets of transmission information comprising the time deviation and the network delay between the master device and the slave device, adjusts the system time of the slave device based on the average time deviation, and obtains the network delay between the master device and the slave device after the adjustment; and obtains the time deviation between the master device and the slave device in a case where the difference between the network delay and the average network delay is less than a first threshold. The time deviation between the system time and the master clock is obtained, the system time is adjusted based on the deviation, and the system time of the slave device is synchronized based on the time deviation in a case where the time deviation between the master device and the slave device is less than a second threshold. By introducing some predictable deviations, the deviations in the link are offset, so that the time synchronization precision can be improved.

[0118] The embodiments of the present disclosure further provide an electronic device, comprising: at least one processor; a memory for storing instructions executable by the at least one processor; wherein the at least one processor is configured to execute the instructions to implement the above-mentioned method disclosed by the embodiments of the present disclosure.

[0119] Figure 6 The structural schematic diagram of the electronic device provided by an exemplary embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the electronic device comprises a processor 101, a memory 102, a communication interface 103, and a bus 104. Figure 6As shown, the electronic device 1800 includes at least one processor 1801 and a memory 1802 coupled to the processor 1801, which can perform the corresponding steps of the above-described method disclosed by the embodiments of the present disclosure.

[0120] The processor 1801 described above can also be referred to as a central processing unit (CPU), which can be an integrated circuit chip with processing capability. Each step of the above-described method disclosed by the embodiments of the present disclosure can be completed by the integrated logic circuit of hardware or the instruction in the form of software in the processor 1801. The processor 1801 described above can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present disclosure can be directly embodied as a hardware coding processor to perform, or a combination of hardware and software modules in the coding processor to perform. The software module can be located in the memory 1802, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, and other mature storage media in the art. The processor 1801 reads the information in the memory 1802 and completes the steps of the above-described method in conjunction with its hardware.

[0121] In addition, various operations / processes according to the present disclosure are implemented by software and / or firmware, which can be loaded from a storage medium or a network to a computer system with a dedicated hardware structure, such as Figure 7 The computer system 1900 shown is installed with programs constituting the software, and the computer system, when various programs are installed, can perform various functions, including functions such as those described above, and the like. Figure 7 A structural block diagram of a computer system provided for an exemplary embodiment of the present disclosure is shown.

[0122] The computer system 1900 is intended to represent various forms of digital electronic computer devices, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown in the figures, their connections and relationships, and their functions, are merely examples, and are not intended to limit the implementations described and / or claimed in this document.

[0123] like Figure 7 As shown, computer system 1900 includes a computing unit 1901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1902 or a computer program loaded from a storage unit 1908 into a random access memory (RAM) 1903. Various programs and data required for the operation of computer system 1900 may also be stored in RAM 1903. Computing unit 1901, ROM 1902, and RAM 1903 are connected to each other via a bus 1904. An input / output (I / O) interface 1905 is also connected to bus 1904.

[0124] Several components within computer system 1900 are connected to I / O interface 1905, including an input unit 1906, an output unit 1907, a storage unit 1908, and a communication unit 1909. Input unit 1906 can be any type of device capable of inputting information into computer system 1900. Input unit 1906 can receive input numeric or character information and generate key input signals related to user settings and / or function control of an electronic device. Output unit 1907 can be any type of device capable of presenting information and may include, but is not limited to, a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. Storage unit 1908 may include, but is not limited to, a magnetic disk or an optical disk. Communication unit 1909 allows computer system 1900 to exchange information / data with other devices over a network, such as the Internet, and may include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver and / or chipset, such as a Bluetooth™ device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0125] The computing unit 1901 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 1901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, and the like. The computing unit 1901 performs various methods and processes described above. For example, in some embodiments, the above-described methods disclosed by the embodiments of the present disclosure can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as the storage unit 1908. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 1900 via the ROM 1902 and / or the communication unit 1909. In some embodiments, the computing unit 1901 can be configured to perform the above-described methods disclosed by the embodiments of the present disclosure by any other appropriate means (for example, by means of firmware).

[0126] The embodiments of the present disclosure also provide a computer-readable storage medium, wherein when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the above-described methods disclosed by the embodiments of the present disclosure.

[0127] The computer-readable storage medium in the embodiments of the present disclosure can be a tangible medium, which can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The above-described computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any appropriate combination thereof. More specifically, the above-described computer-readable storage medium can include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or a flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any appropriate combination thereof.

[0128] The above-described computer-readable medium can be contained in the above-described electronic device; or can exist separately without being assembled into the electronic device.

[0129] The embodiments of the present disclosure also provide a computer program product, which includes a computer program, wherein the computer program is executed by a processor to implement the above-described methods disclosed by the embodiments of the present disclosure.

[0130] Computer program code for carrying out operations of the present disclosure can be written in any one or more of a variety of programming languages or combinations of languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0131] The flow diagrams and the block diagrams in the drawings are meant only to illustrate possible architectures, functions and operations for a system, method and computer program product according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may

[0132] The modules, components or units described in the embodiments of the present disclosure can be implemented by software or by hardware. In some cases, the name of the module, component or unit does not imply the limitation of the module, component or unit itself.

[0133] The functions described above in the detailed description of embodiments of the present disclosure can be implemented in one or more hardware logic components or by using computer software, firmware, or any combination thereof. In some embodiments, the functions described above can be implemented in hardware logic components, which are designed to perform the functions described above. In some embodiments, the hardware logic components can include, for example, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SOC), a complex programmable logic device (CPLD), etc.

[0134] The above description is merely exemplary of some embodiments of the present disclosure and of the principles thereof. It is to be understood that the disclosure is not limited in scope to the particular embodiments described herein, which are intended as examples only, and that the scope of the disclosure is, instead, defined by the appended claims, along with the full range of equivalents to which such claims are entitled. For example, the features of the various embodiments described above can be combined with each other, unless expressly prohibited by the above description.

[0135] While some specific embodiments of the present disclosure have been described in detail, those skilled in the art should understand that the above examples are merely exemplary and are not intended to limit the scope of the present disclosure. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A time synchronization method, characterized by, The method comprises: obtaining a plurality of groups of transmission information calculated between a master device and a slave device; wherein the transmission information comprises a time offset and a network delay; obtaining an average time offset and an average network delay between the master device and the slave device based on the plurality of groups of transmission information; adjusting the system time of the slave device based on the average time offset, obtaining the network delay between the master device and the slave device after adjustment, and obtaining the time offset between the master device and the slave device if the difference between the network delay and the average network delay is less than a first threshold value; obtaining the offset between the system time and a master clock, adjusting the system time based on the offset, and synchronizing the system time of the slave device based on the time offset if the time offset between the master device and the slave device is less than a second threshold value; The method further comprises: obtaining the parity of the node number corresponding to the slave device; determining the positive or negative value corresponding to the time offset based on the parity of the node number; wherein each slave device comprises a corresponding node number, and the positive or negative value corresponding to the time offset of two slave devices with adjacent node numbers is different.

2. The method of claim 1, wherein, The method of obtaining a plurality of groups of transmission information calculated between a master device and a slave device comprises: obtaining a plurality of groups of messages transmitted between the master device and the slave device, wherein the messages carry timestamps; obtaining a plurality of groups of transmission information between the master device and the slave device based on the timestamps carried by the plurality of groups of messages, and discarding a first group of transmission information in the plurality of groups of transmission information.

3. The method of claim 2, wherein, The method of obtaining an average time offset and an average network delay between the master device and the slave device comprises: determining whether the difference between any two time offsets and the difference between any two network delays in the plurality of groups of transmission information are both less than a first threshold value; if the difference between any two time offsets and the difference between any two network delays in the plurality of groups of transmission information are both less than a first threshold value, calculating the average of a plurality of time offsets and the average of a plurality of network delays in the plurality of groups of transmission information to obtain the average time offset and the average network delay, respectively.

4. The method of claim 3, wherein, The method further comprises: if the difference between any two time offsets and the difference between any two network delays in the plurality of groups of transmission information are not both less than a first threshold value, discarding the plurality of groups of transmission information and recalculating a plurality of groups of transmission information between the master device and the slave device until the difference between any two time offsets and the difference between any two network delays in the plurality of groups of transmission information are both less than a first threshold value.

5. The method of claim 4, wherein, The method of adjusting the system time based on the offset comprises: if the offset between the system time and the master clock is positive, adjusting the system time in a positive direction; or, if the offset between the system time and the master clock is negative, adjusting the system time in a negative direction; if the time offset between the master device and the slave device is less than a second threshold value, stop adjusting the system time.

6. The method of claim 5, wherein, The method further comprises: obtaining clock information, wherein the clock information comprises a step value; When the step value is odd, adjusting the system time of the slave device, and stopping adjusting the system time when the time offset is within a first preset range; Or, when the step value is even, adjusting the system time of the slave device, and stopping adjusting the system time when the time offset is within a second preset range.

7. A time synchronization apparatus characterized by comprising: The apparatus comprises: A first information obtaining module configured to obtain a plurality of sets of transmission information calculated between a master device and a slave device; wherein the transmission information comprises a time offset and a network delay; A second information obtaining module configured to obtain an average time offset and an average network delay between the master device and the slave device based on the plurality of sets of transmission information; A third information obtaining module configured to adjust the system time of the slave device based on the average time offset, obtain a network delay between the master device and the slave device after the adjustment, and obtain a time offset between the master device and the slave device when a difference between the network delay and the average network delay is less than a first threshold value; A time synchronization module configured to obtain an offset between the system time and a master clock, adjust the system time based on the offset, and synchronize the system time of the slave device based on the time offset when a time offset between the master device and the slave device is less than a second threshold value; The apparatus further comprises: A number obtaining module configured to obtain the parity of a node number corresponding to the slave device; A range determining module configured to determine the positive or negative value of the time offset based on the parity of the node number; wherein each slave device comprises a corresponding node number, and the positive or negative value of the time offset of two slave devices with adjacent node numbers is different.

8. An electronic device, comprising: Comprise: At least one processor; A memory for storing instructions executable by the at least one processor; Wherein the at least one processor is configured to execute the instructions to implement the method of any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, When the instructions in the computer readable storage medium are executed by the processor of the electronic device, the electronic device can perform the method of any one of claims 1-6.

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