Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel, wherein the array substrate includes a substrate and a first conductive layer, a first insulating layer, a semiconductor layer and a third conductive layer arranged on the substrate, the first conductive layer includes a source electrode and a light-shielding electrode arranged at intervals, the semiconductor layer includes a channel portion and a source contact portion located on one side of the channel portion, part of the source contact portion is arranged in a first via hole of the first insulating layer and connected to the source electrode, the third conductive layer includes a first auxiliary electrode arranged corresponding to the source contact portion, the first auxiliary electrode is connected to at least the source contact portion located in the first via hole, and the orthographic projection of the source contact portion located in the first via hole on the substrate is located within the range of the orthographic projection of the first auxiliary electrode on the substrate, so that the first auxiliary electrode completely covers the source contact portion located in the first via hole, thereby improving the problem of poor overlap between the semiconductor layer and the source electrode.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In the field of display technology, thin-film transistor (TFT) array substrates are a crucial component of display panels. Their manufacture involves the use of multiple photomasks. The greater the number of photomasks used, the longer, more complex, and more expensive the overall manufacturing process for the TFT array substrate. To reduce the number of photomasks used, the source electrode of the TFT can be positioned beneath the semiconductor layer, with the semiconductor layer overlapping the underlying source electrode. However, poor overlap is common at the location where the semiconductor layer and source electrode overlap. Summary of the Invention

[0003] The present application provides an array substrate and a display panel to alleviate the technical problem of poor overlap between a semiconductor layer and a source electrode.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] A first conductive layer is provided on one side of the substrate, the first conductive layer comprising a source electrode and a light-shielding electrode that are spaced apart;

[0008] a first insulating layer, disposed on a side of the first conductive layer away from the substrate, the first insulating layer comprising a first via hole disposed corresponding to the source electrode;

[0009] a semiconductor layer disposed on a side of the first insulating layer away from the substrate, the semiconductor layer comprising a channel portion and a source contact portion located on one side of the channel portion, a portion of the source contact portion being disposed in the first via hole and connected to the source; the channel portion being disposed corresponding to the light-shielding electrode;

[0010] a second insulating layer disposed on the semiconductor layer and corresponding to the channel portion;

[0011] a second conductive layer disposed on the second insulating layer, wherein the second conductive layer includes a gate;

[0012] a planarization layer, disposed on a side of the second conductive layer away from the substrate, the planarization layer comprising a second via hole disposed corresponding to the source contact portion;

[0013] a third conductive layer, disposed on a side of the planarization layer away from the substrate, the third conductive layer comprising a first auxiliary electrode disposed corresponding to the source contact portion;

[0014] The first auxiliary electrode is at least connected to the source contact portion in the first via hole, and the orthographic projection of the source contact portion in the first via hole on the substrate is within the range of the orthographic projection of the first auxiliary electrode on the substrate.

[0015] In the array substrate provided by the embodiment of the present application, the first auxiliary electrode is disposed in the second via hole and the first via hole, and is connected to the source contact portion; the third conductive layer further includes a pixel electrode.

[0016] In the array substrate provided in the embodiment of the present application, the first auxiliary electrode is disposed in the second via hole and the first via hole, and is connected to the source contact portion; the third conductive layer further includes a common electrode.

[0017] In the array substrate provided in the embodiment of the present application, the array substrate further includes:

[0018] a third insulating layer, disposed on a side of the third conductive layer away from the substrate, the third insulating layer comprising a third via hole disposed corresponding to the source contact portion;

[0019] The fourth conductive layer is arranged on a side of the third insulating layer away from the substrate. The fourth conductive layer includes a second auxiliary electrode and a pixel electrode. The second auxiliary electrode is located in the second via hole and the third via hole and is connected to the first auxiliary electrode.

[0020] In the array substrate provided in the embodiment of the present application, the inner diameter of the second via hole is larger than the inner diameter of the third via hole, and the inner diameter of the third via hole is larger than the inner diameter of the first via hole.

[0021] In the array substrate provided in the embodiment of the present application, the array substrate further includes:

[0022] a fourth insulating layer, disposed on a side of the gate away from the substrate, the fourth insulating layer comprising a fourth via hole disposed corresponding to the source contact portion, and the first auxiliary electrode is further located in the fourth via hole;

[0023] The planarization layer is arranged on a side of the fourth insulating layer away from the substrate, and an inner diameter of the second via hole is larger than an inner diameter of the fourth via hole.

[0024] In the array substrate provided in the embodiment of the present application, the first conductive layer further includes a first bridging electrode, and the first insulating layer further includes a fifth via hole and a sixth via hole provided corresponding to the first bridging electrode;

[0025] The semiconductor layer further includes a drain contact portion located on a side of the channel portion away from the source contact portion, and a portion of the drain contact portion is disposed in the fifth via hole and connected to the first bridging electrode;

[0026] The planarization layer further includes a seventh via hole provided corresponding to the first bridging electrode. The pixel electrode is located in the seventh via hole and the sixth via hole and is connected to the first bridging electrode.

[0027] In the array substrate provided in an embodiment of the present application, the third conductive layer also includes a third auxiliary electrode, the planarization layer also includes an eighth via hole arranged corresponding to the drain contact portion, the third auxiliary electrode is arranged in the eighth via hole and connected to the drain contact portion, and the orthographic projection of the drain contact portion located in the fifth via hole on the substrate is located within the range of the orthographic projection of the third auxiliary electrode on the substrate.

[0028] In the array substrate provided in the embodiment of the present application, the first conductive layer further includes a first signal line, and the second conductive layer further includes a second signal line;

[0029] The planarization layer further includes a ninth via hole provided corresponding to the first signal line and a tenth via hole provided corresponding to the second signal line;

[0030] The array substrate also includes a second bridging electrode arranged in the same layer as the first auxiliary electrode, a portion of the second bridging electrode is arranged in the ninth via hole and connected to the first signal line; another portion of the second bridging electrode is arranged in the tenth via hole and connected to the second signal line.

[0031] In the array substrate provided in the embodiment of the present application, the array substrate further includes a fourth auxiliary electrode, the fourth auxiliary electrode is connected to the first signal line, the second bridging electrode is connected to the fourth auxiliary electrode, and the fourth auxiliary electrode is arranged in the same layer as the semiconductor layer.

[0032] In the array substrate provided in the embodiment of the present application, the array substrate further includes an anti-oxidation layer, and the anti-oxidation layer is provided at least at the connection between the semiconductor layer and the first conductive layer.

[0033] An embodiment of the present application further provides a display panel, which includes the array substrate of one of the aforementioned embodiments.

[0034] The beneficial effects of the present application are as follows: in the array substrate and display panel provided by the present application, the array substrate includes a substrate and a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a planarization layer and a third conductive layer arranged on the substrate, the first conductive layer includes a source electrode and a light-shielding electrode arranged at intervals, the semiconductor layer includes a channel portion and a source contact portion located on one side of the channel portion, part of the source contact portion is arranged in a first via hole in the first insulating layer and is connected to the source electrode, the third conductive layer includes a first auxiliary electrode arranged corresponding to the source contact portion, and the first auxiliary electrode The electrode is at least connected to the source contact portion located in the first via hole, and the positive projection of the source contact portion located in the first via hole on the substrate is located within the range of the positive projection of the first auxiliary electrode on the substrate, so that the first auxiliary electrode completely covers the source contact portion located in the first via hole. In this way, when the source contact portion climbs and breaks in the first via hole, the first auxiliary electrode can fill the position of the broken source contact portion, so that the source contact portion is continuous in the first via hole, so as to enhance the reliability of the overlap between the source contact portion and the source, and improve the problem of poor overlap between the semiconductor layer and the source. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 As a preface to the embodiments of the present application, an array substrate is provided.

[0037] Figure 2 This is a schematic diagram of the first cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0038] Figure 3 This is a schematic diagram of a second cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0039] Figure 4 This is a schematic diagram of a third cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0040] Figure 5 This is a schematic diagram of the fourth cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0041] Figure 6 This is a schematic diagram of the fifth cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0042] Figure 7This is a schematic diagram of the sixth cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0043] Figure 8 This is a schematic diagram of the seventh cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0044] Figure 9 This is a schematic diagram of the eighth cross-sectional structure of the array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0046] In order to solve the problem of poor connection between the semiconductor layer and the source electrode, the inventors of this application found in their research that: Figure 1 , Figure 1 As a preface to an embodiment of the present application, an array substrate is provided, comprising a substrate 10' and a first insulating layer 11', a source electrode 21', and a semiconductor layer 31' disposed on the substrate 10'. The first insulating layer 11' is provided with a first via 111' at a position corresponding to the source electrode 21'. A portion of the semiconductor layer 31' is disposed within the first via 111' and overlaps the source electrode 21'. The film thickness of the semiconductor layer 31' is less than the film thickness of the first insulating layer 11'. For example, the film thickness of the semiconductor layer 31' ranges from 200 angstroms to 400 angstroms, while the film thickness of the first insulating layer 11' ranges from 3000 angstroms to 5000 angstroms. When the inner diameter of the first via hole 111' is small, due to the large film thickness of the first insulating layer 11', the taper angle of the first via hole 111' is large. When the semiconductor layer 31' with a thin film thickness climbs in the first via hole 111', problems such as disconnection are likely to occur, thereby resulting in poor overlap between the semiconductor layer 31' in the first via hole 111' and the source electrode 21'.

[0047] To this end, the present application provides an array substrate and a display panel. Figure 2 , Figure 2A schematic diagram of a first cross-sectional structure of an array substrate provided in an embodiment of the present application. The array substrate 100 includes a substrate 10 and a first transistor disposed on the substrate 10, wherein the first transistor includes a source 21, a semiconductor layer 31, and a gate 41. The array substrate 100 also includes a first conductive layer 20, a first insulating layer 11, a semiconductor layer 31, a second insulating layer 12, a second conductive layer 40, a planarization layer 13, and a third conductive layer 50. The first conductive layer 20 is disposed on a side of the substrate 10 away from the substrate 10 and includes a source 21 and a light-shielding electrode 22 of the first transistor disposed at intervals. The first insulating layer 11 is disposed on a side of the first conductive layer 20 away from the substrate 10 and includes a first via 111 disposed corresponding to the source 21. The semiconductor layer 31 is disposed on a side of the first insulating layer 11 away from the substrate 10. The semiconductor layer 31 includes a channel portion 311 and a source contact portion 312 located on one side of the channel portion 311. The gate 41 is disposed corresponding to the channel portion 311. A portion of the source contact portion 312 is disposed within the first via 111 and connected to the source electrode 21. The channel portion 311 is disposed corresponding to the light-shielding electrode 22. The second insulating layer 12 is disposed on a side of the semiconductor layer 31 away from the substrate 10 and corresponds to the channel portion 311. A second conductive layer 40 is disposed on the second insulating layer 12 and includes a gate 41. The planarization layer 13 is disposed on a side of the second conductive layer 40 away from the substrate 10 and includes a second via 131 disposed corresponding to the source contact portion 312. The third conductive layer 50 is disposed on a side of the planarization layer 13 away from the substrate 10 and includes a first auxiliary electrode 51 disposed corresponding to the source contact 312. The first auxiliary electrode 51 is connected to at least the source contact 312 located within the first via 111, and the orthographic projection of the source contact 312 located within the first via 111 on the substrate 10 is within the range of the orthographic projection of the first auxiliary electrode 51 on the substrate 10, so that the first auxiliary electrode 51 completely covers the source contact 312 located within the first via 111. In this way, when the source contact 312 breaks while climbing up the slope within the first via 111, the first auxiliary electrode 51 can fill the position of the broken source contact 312, making the source contact 312 continuous within the first via 111, thereby enhancing the reliability of the overlap between the source contact 312 and the source 21 and improving the problem of poor overlap between the semiconductor layer 31 and the source 21.

[0048] Optionally, the substrate 10 can be a rigid substrate or a flexible substrate. When the substrate 10 is a rigid substrate, it can include a rigid substrate such as a glass substrate, a quartz substrate, or a silicon wafer. When the substrate 10 is a flexible substrate, it can include a flexible substrate such as a polyimide (PI) film or an ultra-thin glass film. When the substrate 10 is a polyimide substrate, moisture or oxygen can more easily penetrate the substrate 10 than when it is a glass substrate. To prevent this, a single-layer or multi-layer buffer layer comprising silicon oxide or silicon nitride can be provided on the substrate 10.

[0049] The first transistor is disposed on the substrate 10. The first transistor may be a thin film transistor. The first transistor includes a source 21, a semiconductor layer 31, and a gate 41. The semiconductor layer 31 is disposed on a side of the source 21 away from the substrate 10, and the gate 41 is disposed on a side of the semiconductor layer 31 away from the substrate 10. In other words, the semiconductor layer 31 is disposed on a side of the source 21 away from the substrate 10, and the gate 41 is disposed on a side of the semiconductor layer 31 away from the substrate 10. The semiconductor layer 31 includes a channel portion 311 and a source contact portion 312 located on one side of the channel portion 311. Of course, the semiconductor layer 31 also includes a drain contact portion 313 located on a side of the channel portion 311 away from the source contact portion 312. In other words, the drain contact portion 313 and the source contact portion 312 are located on opposite sides of the channel portion 311. The gate 41 is disposed opposite to the channel portion 311 , and an orthographic projection of the gate 41 on the substrate 10 coincides with an orthographic projection of the channel portion 311 on the substrate 10 .

[0050] The first conductive layer 20 is arranged on the substrate 10. The first conductive layer 20 includes the source 21 of the first transistor. Optionally, the first conductive layer 20 also includes a light-shielding electrode 22, and the light-shielding electrode 22 is spaced apart from and insulated from the source 21. The light-shielding electrode 22 is arranged at least corresponding to the channel portion 311 to shield the channel portion 311 and reduce the photogenerated leakage current of the first transistor. The first conductive layer 20 can be formed into multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high corrosion resistance. For example, the first conductive layer 20 can be a triple stack of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti or Mo / Al / Mo, and others.

[0051] The first insulating layer 11 covers the first conductive layer 20 and the substrate 10. The first insulating layer 11 has a first via 111 formed at a position corresponding to the source electrode 21. The first via 111 penetrates the first insulating layer 11 to expose at least a portion of the source electrode 21. The thickness of the first insulating layer 11 ranges from 3000 angstroms to 5000 angstroms. The depth of the first via 111 is equal to the thickness of the first insulating layer 11, that is, the depth of the first via 111 ranges from 3000 angstroms to 5000 angstroms, such as 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, etc. The material of the first insulating layer 11 includes an inorganic material. For example, the first insulating layer 11 can be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0052] The semiconductor layer 31 is disposed on a side of the first insulating layer 11 away from the substrate 10. The source contact 312 and drain contact 313 of the semiconductor layer 31 are formed by conductively converting the semiconductor layer 31, forming conductive regions. The source contact 312 is located on a portion of the first insulating layer 11 and within the first via 111. The source contact 312 within the first via 111 covers the wall of the first via 111 and the source electrode 21 exposed by the first via 111, thereby connecting to the source electrode 21. The thickness of the semiconductor layer 31 ranges from 200 angstroms to 400 angstroms, such as 200 angstroms, 220 angstroms, 250 angstroms, 280 angstroms, 300 angstroms, 350 angstroms, 380 angstroms, or 400 angstroms. In other words, the thickness of the semiconductor layer 31 ranges from 200 angstroms to 400 angstroms. The material of the semiconductor layer 31 includes semiconductor materials such as polysilicon and metal oxide.

[0053] The array substrate 100 also includes a second insulating layer 12 and a second conductive layer 40. The second insulating layer 12 is disposed on a side of the semiconductor layer 31 away from the substrate 10 and corresponds to the channel portion 311. The second insulating layer 12 is made of an inorganic material. For example, the second insulating layer 12 may be a plurality of layers or a single layer comprising at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide. The second conductive layer 40 is disposed on a side of the second insulating layer 12 away from the substrate 10. The second conductive layer 40 includes a gate electrode 41 of the first transistor, which is disposed corresponding to the second insulating layer 12. The second conductive layer 40 may be formed of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance, or a plurality of layers or a single layer. For example, the second conductive layer 40 may be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, among others.

[0054] The array substrate 100 also includes a planarization layer 13, which is disposed on a side of the semiconductor layer 31 away from the substrate 10. The planarization layer 13 includes a second via 131 corresponding to the source contact 312, and the second via 131 extends through the planarization layer 13. The second via 131 is disposed corresponding to the first via 111 and extends through the planarization layer 13. The planarization layer 13 is made of an organic material. For example, the planarization layer 13 can be formed of a resin such as polyacrylate, polyimide, or a silica-based organic material. The third conductive layer 50 is disposed on a side of the planarization layer 13 away from the substrate 10. The first auxiliary electrode 51 formed by the third conductive layer 50 is disposed within the second via 131 and the first via 111, and is connected to the source contact 312. The third conductive layer 50 can be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0055] Specifically, the first auxiliary electrode 51 covers a portion of the planarization layer 13, the wall of the second via hole 131, a portion of the source contact portion 312, and the source contact portion 312 located in the first via hole 111, so as to be connected to at least the source contact portion 312 located in the first via hole 111. Moreover, the orthographic projection of the source contact portion 312 located in the first via hole 111 on the substrate 10 is located within the range of the orthographic projection of the first auxiliary electrode 51 on the substrate 10, so that the first auxiliary electrode 51 completely covers the source contact portion 312 located in the first via hole 111. In this way, there is no need to increase the film thickness of the semiconductor layer 31 and / or reduce the film thickness of the first insulating layer 11, nor is there any need to increase the inner diameter of the first via hole 111. Even if the source contact portion 312 breaks while climbing in the first via hole 111, the first auxiliary electrode 51 can fill the position of the broken source contact portion 312, so that the source contact portion 312 is continuous in the first via hole 111, so as to enhance the reliability of the overlap between the source contact portion 312 and the source 21, and improve the problem of poor overlap between the semiconductor layer 31 and the source 21.

[0056] Optionally, the inner diameter of the second via 131 is larger than the inner diameter of the first via 111. For example, the opening of the second via 131 on the side close to the first insulating layer 11 is larger than the opening of the first via 111 on the side close to the planarization layer 13. This allows the orthographic projection of the second via 131 on the substrate 10 to completely cover the orthographic projection of the first via 111 on the substrate 10. This allows the second via 131 and the first via 111 to form a stepped structure, thereby improving the stability of the first auxiliary electrode 51 climbing within the second via 131 and the first via 111. The longitudinal cross-sections of the second via 131 and the first via 111 are both inverted trapezoidal.

[0057] The third conductive layer 50 also includes a pixel electrode 52, which is connected to the drain contact portion 313 of the semiconductor layer 31. Specifically, the planarization layer 13 has a first additional via hole 132 formed in a region corresponding to the drain contact portion 313 of the semiconductor layer 31. The first additional via hole 132 penetrates the planarization layer 13 and exposes a portion of the drain contact portion 313. A portion of the pixel electrode 52 is located within the first additional via hole 132 and connected to the drain contact portion 313.

[0058] Optionally, the array substrate 100 further includes a fourth insulating layer 14, which is disposed on a side of the gate electrode 41 away from the substrate 10. For example, the fourth insulating layer 14 covers the gate electrode 41, a portion of the source contact portion 312, a portion of the drain contact portion 313, and a portion of the first insulating layer 11. The fourth insulating layer 14 includes a fourth via hole 141 corresponding to the source contact portion 312, and the first auxiliary electrode 51 is further located within the fourth via hole 141. The material of the fourth insulating layer 14 includes an inorganic material. For example, the fourth insulating layer 14 may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide. The planarization layer 13 is disposed on a side of the fourth insulating layer 14 away from the substrate 10. For example, the planarization layer 13 covers the fourth insulating layer 14. The inner diameter of the second via hole 131 on the planarization layer 13 is larger than the inner diameter of the fourth via hole 141 on the fourth insulating layer 14, and the inner diameter of the fourth via hole 141 is larger than the inner diameter of the first via hole 111, so that the second via hole 131, the fourth via hole 141 and the first via hole 111 form a stepped structure together, thereby improving the stability of the first auxiliary electrode 51 climbing in the second via hole 131, the fourth via hole 141 and the first via hole 111.

[0059] The fourth insulating layer 14 has a second other via hole 142 formed at a position corresponding to the drain contact portion 313. The second other via hole 142 is provided corresponding to the first other via hole 132 and intersects the first other via hole 132. The inner diameter of the second other via hole 142 is smaller than the inner diameter of the first other via hole 132. A portion of the pixel electrode 52 is located within the first other via hole 132 and the second other via hole 142 and is connected to the drain contact portion 313.

[0060] In one embodiment, please refer to Figures 1 to 3 , Figure 3 This is a schematic diagram of a second cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 3Unlike the above embodiment, the array substrate 100 further includes an anti-oxidation layer 60. The anti-oxidation layer 60 is provided at least at the connection between the semiconductor layer 31 and the first conductive layer 20 to improve the reliability of the connection between the semiconductor layer 31 and the first conductive layer 20. It should be noted that when the first conductive layer 20 is formed using a low-resistance material such as Al or Cu, oxygen is present during the formation of the semiconductor layer 31. Oxygen can cause oxidation of the first conductive layer 20, thereby resulting in poor overlap between the semiconductor layer 31 and the first conductive layer 20. In this embodiment, the anti-oxidation layer 60 is provided at the location where the semiconductor layer 31 and the first conductive layer 20 overlap. The semiconductor layer 31 overlaps the first conductive layer 20 through the anti-oxidation layer 60. The anti-oxidation layer 60 can protect the first conductive layer 20, preventing oxidation of the first conductive layer 20, which could result in poor overlap between the semiconductor layer 31 and the first conductive layer 20. The material of the anti-oxidation layer 60 includes titanium-molybdenum alloy, etc.

[0061] Specifically, refer to Figure 3 Taking the connection between the source contact portion 312 of the semiconductor layer 31 and the source electrode 21 of the first conductive layer 20 as an example, the anti-oxidation layer 60 is disposed on the side of the source electrode 21 away from the substrate 10 and covers the surface of the source electrode 21. A portion of the source contact portion 312 covers the anti-oxidation layer 60 and is connected to the source electrode 21 through the anti-oxidation layer 60. The anti-oxidation layer 60 serves as a protective layer for the source electrode 21 to prevent oxidation of the source electrode 21, which could result in poor connection between the source contact portion 312 and the source electrode 21. For other explanations, please refer to the above embodiment and will not be repeated here.

[0062] In one embodiment, please refer to Figures 1 to 4 , Figure 4 This is a schematic diagram of a third cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 4Unlike the above embodiment, the array substrate 100 further includes a third insulating layer 15 and a fourth conductive layer 70. The fourth conductive layer 70 is disposed on a side of the third insulating layer 15 away from the substrate 10. The first auxiliary electrode 51 and the common electrode 53 are formed on the third conductive layer 50, and the pixel electrode 52 opposite the common electrode 53 is formed on the fourth conductive layer 70. The pixel electrode 52 is connected to the drain contact 313 of the semiconductor layer 31. The first auxiliary electrode 51 is located within the second via 131, the fourth via 141, and the first via 111, and is connected to the source contact 312. A portion of the third insulating layer 15 covers the first auxiliary electrode 51. Optionally, the material of the third insulating layer 15 includes an inorganic material. For example, the third insulating layer 15 may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide. The fourth conductive layer 70 may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In2O3).

[0063] In one embodiment, please refer to Figures 1 to 5 , Figure 5 This is a schematic diagram of a fourth cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 5 Unlike the above embodiment, the third insulating layer 15 is disposed on the side of the third conductive layer 50 away from the substrate 10 and includes a third via 151 corresponding to the source contact 312. The inner diameter of the second via 131 is larger than that of the third via 151, which in turn is larger than that of the first via 111. The fourth conductive layer 70 includes a second auxiliary electrode 71 and a pixel electrode 52. The second auxiliary electrode 71 is located within the second and third vias 131 and 151 and is connected to the first auxiliary electrode 51. By disposing the second auxiliary electrode 71 on the side of the first auxiliary electrode 51 away from the source contact 312 and covering the first auxiliary electrode 51 within the third via 151, the reliability of the connection between the first auxiliary electrode 51 and the source 21 is improved, thereby further enhancing the reliability of the connection between the source contact 312 and the source 21, and further improving the problem of poor connection between the semiconductor layer 31 and the source 21. For other explanations, please refer to the above embodiments and will not be repeated here.

[0064] In one embodiment, please refer to Figures 1 to 6 , Figure 6 This is a schematic diagram of the fifth cross-sectional structure of the array substrate 100 provided in the embodiment of the present application. Figure 6 Unlike the above embodiment, the first conductive layer 20 further includes a first bridging electrode 23, and the first insulating layer 11 further includes a fifth via 112 and a sixth via 113 corresponding to the first bridging electrode 23. The semiconductor layer 31 further includes a drain contact portion 313 located on the side of the channel portion 311 away from the source contact portion 312. A portion of the drain contact portion 313 is disposed within the fifth via 112 and connected to the first bridging electrode 23. The planarization layer 13 further includes a seventh via 133 corresponding to the first bridging electrode 23. The seventh via 133 corresponds to the sixth via 113 and extends through it. The inner diameter of the seventh via 133 is larger than that of the sixth via 113. The pixel electrode 52 is located within the seventh via 133 and the sixth via 113 and connected to the first bridging electrode 23.

[0065] It should be noted that when the pixel electrode 52 and / or the semiconductor layer 31 are formed of a metal oxide, for example, when the pixel electrode 52 is formed of indium tin oxide and the semiconductor layer 31 is formed of indium gallium zinc oxide, the metal oxide itself has a relatively high impedance, resulting in a relatively high impedance when the pixel electrode 52 is directly connected to the drain contact 313 of the semiconductor layer 31. In this embodiment, by providing the first bridging electrode 23, the pixel electrode 52 is connected to the drain contact 313 of the semiconductor layer 31 via the first bridging electrode 23, thereby improving the problem of high impedance when the pixel electrode 52 is directly connected to the drain contact 313. For other explanations, please refer to the above embodiment and will not be repeated here.

[0066] In one embodiment, please refer to Figures 1 to 7 , Figure 7 This is a sixth cross-sectional structural diagram of the array substrate 100 provided in an embodiment of the present application. Figure 7Different from the above embodiment, the array substrate 100 further includes a third auxiliary electrode 54 provided on the same layer as the first auxiliary electrode 51 , that is, the third conductive layer 50 further includes a third auxiliary electrode 54 . The planarization layer 13 further includes an eighth via 134 corresponding to the drain contact 313. The third auxiliary electrode 54 is disposed within the eighth via 134 and connected to the drain contact 313. Furthermore, the orthographic projection of the drain contact 313 within the fifth via 112 on the substrate 10 is within the range of the orthographic projection of the third auxiliary electrode 54 on the substrate 10, so that the third auxiliary electrode 54 completely covers the drain contact 313 within the fifth via 112. In this way, if the drain contact 313 breaks while climbing up the slope within the fifth via 112, the third auxiliary electrode 54 can fill the gap in the broken drain contact 313, ensuring that the drain contact 313 is continuous within the fifth via 112. This enhances the reliability of the overlap between the drain contact 313 and the first bridging electrode 23, thereby improving the problem of poor overlap between the drain contact 313 and the first bridging electrode 23 of the semiconductor layer 31. For other explanations, please refer to the above embodiment and will not be repeated here.

[0067] In one embodiment, please refer to Figures 1 to 8 , Figure 8 This is a seventh cross-sectional structural diagram of the array substrate 100 provided in an embodiment of the present application. Figure 8 Unlike the above embodiment, the array substrate 100 further includes a fifth auxiliary electrode 32. Optionally, the fifth auxiliary electrode 32 is disposed in the same layer as the semiconductor layer 31. The fifth auxiliary electrode 32 can be formed by converting a semiconductor thin film into a conductor. At least a portion of the fifth auxiliary electrode 32 is disposed within the sixth via hole 113 and connected to the first bridging electrode 23. The pixel electrode 52 is connected to the fifth auxiliary electrode 32 within the sixth via hole 113 to improve the reliability of the overlap between the pixel electrode 52 and the first bridging electrode 23.

[0068] It should be noted that in the process of directly overlapping the pixel electrode 52 and the first bridging electrode 23, the sixth via hole 113 must first be formed in the first insulating layer 11. The sixth via hole 113 exposes at least a portion of the first bridging electrode 23. Then, a semiconductor film is formed on the first insulating layer 11 and etched to form the semiconductor layer 31. However, during the etching process of the semiconductor film, the etching solution may damage the first bridging electrode 23 exposed by the damaged sixth via hole 113. As a result, poor overlap may occur when the pixel electrode 52 and the first bridging electrode 23 are subsequently directly overlapped. In this embodiment, by simultaneously etching the semiconductor film to form the semiconductor layer 31, the fifth auxiliary electrode 32 is also formed in the semiconductor film. This allows the pixel electrode 52 to be connected to the first bridging electrode 23 via the fifth auxiliary electrode 32, thereby improving the poor overlap problem that may occur when the pixel electrode 52 and the first bridging electrode 23 are directly overlapped, and enhancing the reliability of the overlap between the pixel electrode 52 and the first bridging electrode 23. Moreover, in this embodiment, the fifth auxiliary electrode 32 is disposed in the sixth via hole 113 formed in the first insulating layer 11, and the pixel electrode 52 is connected to the fifth auxiliary electrode 32 in the sixth via hole 113. Figure 2 The pixel electrode 52 shown is connected to the drain contact portion 313 directly disposed on the horizontal surface of the first insulating layer 11, which can increase the contact area between the pixel electrode 52 and the fifth auxiliary electrode 32, thereby reducing the contact resistance between the pixel electrode 52 and the fifth auxiliary electrode 32. In other words, the provision of the fifth auxiliary electrode 32 in this embodiment improves the poor overlap between the pixel electrode 52 and the first bridging electrode 23 while not affecting the effect of the provision of the first bridging electrode 23 on improving the high impedance of the direct overlap between the pixel electrode 52 and the drain contact portion 313. For other explanations, please refer to the above embodiment and will not be repeated here.

[0069] In one embodiment, please refer to Figures 1 to 9 , Figure 9 This is a schematic diagram of the eighth cross-sectional structure of the array substrate 100 provided in the embodiment of the present application. Figure 9Unlike the above embodiment, the first conductive layer 20 further includes a first signal line 24, and the second conductive layer 40 further includes a second signal line 42. The planarization layer 13 further includes a ninth via hole 135 corresponding to the first signal line 24 and a tenth via hole 136 corresponding to the second signal line 42. The first insulating layer 11 further includes a third additional via hole 114 corresponding to the first signal line 24. The third additional via hole 114 and the ninth via hole 135 are disposed opposite and interpenetrate each other. The inner diameter of the ninth via hole 135 is larger than that of the third additional via hole 114. The array substrate 100 further includes a second bridging electrode 55 disposed on the same layer as the first auxiliary electrode 51. A portion of the second bridging electrode 55 is disposed within the ninth via hole 135 and connected to the first signal line 24; another portion of the second bridging electrode 55 is disposed within the tenth via hole 136 and connected to the second signal line 42, thereby connecting the first signal line 24 to the second signal line 42 via the second bridging electrode 55.

[0070] Optionally, the array substrate 100 further includes a fourth auxiliary electrode 33. Optionally, the fourth auxiliary electrode 33 is disposed in the same layer as the semiconductor layer 31 and can be formed by converting the semiconductor thin film into a conductor. At least a portion of the fourth auxiliary electrode 33 is disposed within the third other via 114 and connected to the first signal line 24. The second bridging electrode 55 is connected to the fourth auxiliary electrode 33 within the third other via 114 to improve the reliability of the connection between the fourth auxiliary electrode 33 and the first signal line 24. For other details, please refer to the above embodiment and will not be repeated here.

[0071] Based on the same inventive concept, the present application further provides a display panel, which includes the array substrate 100 of one of the aforementioned embodiments. The display panel includes a liquid crystal display panel, an organic light emitting diode display panel, or other types of display panels.

[0072] According to the above embodiments, it can be seen that:

[0073] The present application provides an array substrate and a display panel, wherein the array substrate includes a substrate and a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a planarization layer, and a third conductive layer disposed on the substrate. The first conductive layer includes a source electrode and a light-shielding electrode disposed at intervals. The semiconductor layer includes a channel portion and a source contact portion located on one side of the channel portion. Part of the source contact portion is disposed in a first via hole of the first insulating layer and connected to the source electrode. The third conductive layer includes a first auxiliary electrode disposed corresponding to the source contact portion. The first auxiliary electrode is connected to at least the source contact portion located in the first via hole, and an orthographic projection of the source contact portion located in the first via hole on the substrate is located within the range of an orthographic projection of the first auxiliary electrode on the substrate, such that the first auxiliary electrode completely covers the source contact portion located in the first via hole. In this way, when the source contact portion breaks while climbing in the first via hole, the first auxiliary electrode can fill the position of the broken source contact portion, making the source contact portion continuous in the first via hole, thereby enhancing the reliability of the overlap between the source contact portion and the source electrode and improving the problem of poor overlap between the semiconductor layer and the source electrode.

[0074] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0075] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes: substrate; A first conductive layer is provided on one side of the substrate, the first conductive layer comprising a source electrode and a light-shielding electrode that are spaced apart; a first insulating layer, disposed on a side of the first conductive layer away from the substrate, the first insulating layer comprising a first via hole disposed corresponding to the source electrode; a semiconductor layer disposed on a side of the first insulating layer away from the substrate, the semiconductor layer comprising a channel portion and a source contact portion located on one side of the channel portion, a portion of the source contact portion being disposed in the first via hole and connected to the source; the channel portion being disposed corresponding to the light-shielding electrode; a second insulating layer disposed on the semiconductor layer and corresponding to the channel portion; a second conductive layer disposed on the second insulating layer, wherein the second conductive layer includes a gate; a planarization layer, disposed on a side of the second conductive layer away from the substrate, the planarization layer comprising a second via hole disposed corresponding to the source contact portion; a third conductive layer, disposed on a side of the planarization layer away from the substrate, the third conductive layer comprising a first auxiliary electrode and a common electrode disposed corresponding to the source contact portion, the first auxiliary electrode being disposed in the second via hole and the first via hole and connected to the source contact portion; a third insulating layer, disposed on a side of the third conductive layer away from the substrate, the third insulating layer comprising a third via hole disposed corresponding to the source contact portion; a fourth conductive layer, disposed on a side of the third insulating layer away from the substrate, the fourth conductive layer comprising a second auxiliary electrode and a pixel electrode, the second auxiliary electrode being located in the second via hole and the third via hole and connected to the first auxiliary electrode; The first auxiliary electrode is at least connected to the source contact portion in the first via hole, and the orthographic projection of the source contact portion in the first via hole on the substrate is within the range of the orthographic projection of the first auxiliary electrode on the substrate.

2. The array substrate according to claim 1, wherein: The inner diameter of the second via hole is larger than the inner diameter of the third via hole, and the inner diameter of the third via hole is larger than the inner diameter of the first via hole.

3. The array substrate according to claim 1, wherein: The array substrate further includes: a fourth insulating layer, disposed on a side of the gate away from the substrate, the fourth insulating layer comprising a fourth via hole disposed corresponding to the source contact portion, and the first auxiliary electrode is further located in the fourth via hole; The planarization layer is arranged on a side of the fourth insulating layer away from the substrate, and an inner diameter of the second via hole is larger than an inner diameter of the fourth via hole.

4. The array substrate according to claim 3, wherein: The first conductive layer further includes a first bridging electrode, and the first insulating layer further includes a fifth via hole and a sixth via hole provided corresponding to the first bridging electrode; The semiconductor layer further includes a drain contact portion located on a side of the channel portion away from the source contact portion, and a portion of the drain contact portion is disposed in the fifth via hole and connected to the first bridging electrode; The planarization layer further includes a seventh via hole provided corresponding to the first bridging electrode. The pixel electrode is located in the seventh via hole and the sixth via hole and is connected to the first bridging electrode.

5. The array substrate according to claim 4, wherein: The third conductive layer also includes a third auxiliary electrode, and the planarization layer also includes an eighth via hole arranged corresponding to the drain contact portion. The third auxiliary electrode is arranged in the eighth via hole and connected to the drain contact portion, and the orthographic projection of the drain contact portion located in the fifth via hole on the substrate is located within the range of the orthographic projection of the third auxiliary electrode on the substrate.

6. The array substrate according to claim 3, wherein: The first conductive layer further includes a first signal line, and the second conductive layer further includes a second signal line; The planarization layer further includes a ninth via hole provided corresponding to the first signal line and a tenth via hole provided corresponding to the second signal line; The array substrate also includes a second bridging electrode arranged in the same layer as the first auxiliary electrode, a portion of the second bridging electrode is arranged in the ninth via hole and connected to the first signal line; another portion of the second bridging electrode is arranged in the tenth via hole and connected to the second signal line.

7. The array substrate according to claim 6, wherein: The array substrate further includes a fourth auxiliary electrode, the fourth auxiliary electrode is connected to the first signal line, the second bridging electrode is connected to the fourth auxiliary electrode, and the fourth auxiliary electrode is provided in the same layer as the semiconductor layer.

8. The array substrate according to claim 3, wherein: The array substrate further includes an anti-oxidation layer, and the anti-oxidation layer is at least arranged at a connection between the semiconductor layer and the first conductive layer.

9. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 8.

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