A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a display area and a non-display area arranged adjacently. The display panel comprises a first metal layer, a second metal layer and an electrode layer. The first metal layer comprises a plurality of data lines located in the display area. The second metal layer comprises a plurality of fan-out wires located in the display area and electrically connected with the plurality of data lines one by one. The electrode layer comprises a plurality of first pixel electrodes arranged adjacently with the plurality of fan-out wires. The first pixel electrode comprises a first pixel area and a first non-pixel area arranged adjacently. The fan-out wire comprises a winding part arranged correspondingly with the adjacent first pixel electrode. Each first pixel electrode is arranged correspondingly with at least one winding part, and the winding part is located at the periphery of the corresponding first pixel area. At least one winding part arranged correspondingly with the same first pixel electrode is arranged centrally symmetrically. The application can improve the problems of green and pink emission, color separation and diffraction under a large viewing angle.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the increasing demand for OLED panel display, various new technologies need to be introduced at the same time, such as FIAA (Fanout In AA, fanout wiring is arranged in the effective display area) technology and PLP (POL-less, polarization-free) technology.

[0003] Generally, in the FIAA technology, each fanout wiring located in the AA area is divided into a transverse wiring and a longitudinal wiring connected to each other; wherein the transverse wiring is connected with a corresponding data line, and the longitudinal wiring is connected with a driving chip. The FIAA technology can effectively narrow the lower frame of the display panel. In the PLP technology, a color filter is used to replace a polarizing plate, which not only can reduce the thickness of the functional layer, but also can effectively improve the light output rate. However, when the FIAA technology and the PLP technology are combined and introduced into the display panel, the display panel often has problems such as cyan and pink emission, color separation, and diffraction at large viewing angles. SUMMARY

[0004] The present application provides a display panel and a display device, by winding design of the fanout wiring in the display area, the flatness of the pixel electrode can be effectively improved, thereby improving the problems such as cyan and pink emission, color separation, and diffraction at large viewing angles.

[0005] The present application provides a display panel, comprising a display area and a non-display area arranged adjacent to each other; the display panel comprises:

[0006] a substrate, located in the display area and the non-display area;

[0007] a first metal layer, located on one side of the substrate, and comprising a plurality of data lines located in the display area;

[0008] a first flat layer, located on the side of the first metal layer away from the substrate;

[0009] a second metal layer, located on the side of the first flat layer away from the substrate, and comprising a plurality of fanout wirings located in the display area and electrically connected one by one with the plurality of data lines;

[0010] a second flat layer, located on the side of the second metal layer away from the substrate;

[0011] an electrode layer located on a side of the second planar layer away from the substrate and in the display area; the electrode layer comprises a plurality of first pixel electrodes arranged adjacent to the plurality of fan-out wires; the first pixel electrodes comprise first pixel regions and first non-pixel regions arranged around the first pixel regions;

[0012] Each of the fan-out wires comprises a winding portion arranged corresponding to an adjacent first pixel electrode; each of the first pixel electrodes is arranged corresponding to at least one winding portion, and the winding portion is located at a periphery of the corresponding first pixel region; the at least one winding portion arranged corresponding to the same first pixel electrode is arranged in a central symmetry.

[0013] Optionally, the winding portion is located at a periphery of the corresponding first pixel electrode; or the winding portion is arranged at least partially overlapping the first non-pixel region of the corresponding first pixel electrode.

[0014] Optionally, the winding portion comprises a first winding portion arranged in a central symmetry and in a ring shape; the fan-out wire comprises at least one first winding portion; at least part of the first pixel electrodes are arranged corresponding to only one second winding portion, and the first winding portion is arranged surrounding the corresponding first pixel region.

[0015] Optionally, the winding portion further comprises a second winding portion, and at least one first pixel electrode is arranged corresponding to two second winding portions; the extension direction of the second winding portion is consistent with the extension direction of the edge of the corresponding first pixel region; the two second winding portions arranged corresponding to the same first pixel electrode are arranged in a central symmetry and are respectively located in two adjacent fan-out wires.

[0016] Optionally, the display panel further comprises a light-emitting functional layer and a color filter layer; the light-emitting functional layer is located on a side of the electrode layer away from the substrate, and the color filter layer is located on a side of the light-emitting functional layer away from the substrate; the light-emitting functional layer comprises a plurality of light-emitting units arranged one-to-one corresponding to the plurality of first pixel electrodes; the light-emitting units are located in the first pixel regions of the corresponding first pixel electrodes; the color filter layer comprises a plurality of color resistance units arranged one-to-one corresponding to the plurality of light-emitting units.

[0017] The shapes of the edges of the orthographic projections of the first pixel regions and the first pixel electrodes on the substrate are circular; and the shape of the edge of the orthographic projection of any one winding portion on the substrate is circular or circular arc.

[0018] Optionally, the data lines extend along a first direction; each of the fan-out wires comprises a first wire part extending along the first direction and a second wire part extending along a second direction; the second direction is perpendicular to the first direction;

[0019] The first wire part extends to the non-display area; one end of the second wire part is connected to one end of the first wire part away from the non-display area, and the other end of the second wire part is connected to the corresponding data line; the first wire part and / or the second wire part comprises at least one winding part;

[0020] The fan-out wire further comprises a plurality of connecting parts, and any two adjacent winding parts are connected by the connecting part.

[0021] Optionally, the plurality of first pixel electrodes are arranged in a plurality of rows and a plurality of columns in the first direction and the second direction; each column of the first pixel electrodes is arranged along the first direction, and each row of the second pixel electrodes is arranged along the second direction;

[0022] The first wire part is arranged adjacent to at least one column of the first pixel electrodes, and the first wire part comprises a plurality of winding parts arranged corresponding to the at least one column of the first pixel electrodes; the second wire part is arranged adjacent to at least one row of the first pixel electrodes, and the second wire part comprises a plurality of winding parts arranged corresponding to the at least one row of the first pixel electrodes.

[0023] Optionally, the display area comprises a fan-out area and a non-fan-out area arranged adjacent to each other; the fan-out wires and the first pixel electrodes are located in the fan-out area; the second metal layer further comprises a plurality of virtual wires located in the non-fan-out area and arranged spaced apart from the plurality of fan-out wires; the virtual wires are used to access a preset potential;

[0024] The electrode layer further comprises a plurality of second pixel electrodes located in the non-fan-out area and arranged adjacent to the plurality of virtual wires; the second pixel electrode comprises a second pixel area and a second non-pixel area arranged around the second pixel area; each of the virtual wires comprises a virtual winding part arranged corresponding to the adjacent second pixel electrode, and each of the second pixel electrodes is arranged corresponding to at least one virtual winding part, and the extension direction of the virtual winding part is consistent with the extension direction of the corresponding second pixel area; the at least one virtual winding part corresponding to the same second pixel electrode is arranged in a central symmetry.

[0025] Optionally, the plurality of first pixel electrodes in the fan-out area are arranged in multiple rows and multiple columns, and the plurality of second pixel electrodes in the non-fan-out area are arranged in multiple rows and multiple columns; a portion of the second pixel electrodes are arranged in the same row as the first pixel electrodes, and another portion of the second pixel electrodes are arranged in the same column as the second pixel electrodes; the first pixel electrodes and second pixel electrodes arranged in the same row have the same shape and size, and the first pixel electrodes and second pixel electrodes arranged in the same column have the same size and shape;

[0026] The multiple winding portions in the fan-out area are arranged in multiple rows and columns, and the multiple virtual winding portions in the non-fan-out area are arranged in multiple rows and columns; a portion of the virtual winding portions are arranged in the same row as the winding portions, and another portion of the virtual winding portions are arranged in the same column as the winding portions; the virtual winding portions arranged in the same row and the winding portions have the same shape and size, and the virtual winding portions arranged in the same column and the winding portions have the same size and shape.

[0027] This application also provides a display device, including the display panel described above.

[0028] The display panel and display device provided in this application employ a winding design for the fan-out traces within the display area. This design ensures that the fan-out traces, when passing below the first pixel electrode, are wound according to the shape of the first pixel area of ​​the first pixel electrode, forming a winding portion located on the periphery of the first pixel area. This avoids overlap between the fan-out traces and the first pixel area, thus improving the flatness of the first pixel area of ​​the first pixel electrode. Furthermore, at least one winding portion located below each first pixel electrode is centrally symmetrically arranged, further enhancing the flatness of the first pixel area. Therefore, when FIAA and PLP technologies are combined and introduced into the display panel, this application can effectively improve the flatness of the first pixel area of ​​the first pixel electrode, thereby effectively mitigating problems such as bluish-pink tint, color separation, and diffraction in the display panel at wide viewing angles. Attached Figure Description

[0029] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the distribution of fan-out traces of a display panel provided in an embodiment of this application.

[0031] Figure 2 This is a partial cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0032] Figure 3 This is a top view of a second metal layer provided in an embodiment of this application.

[0033] Figure 4 FIG. 1 is a schematic view of a local structure of a first fan-out wire, a second fan-out wire and a third fan-out wire in the display panel. Figure 3

[0034] Figure 5 FIG. 2 is a schematic view of a top structure of a second metal layer and a data line provided by an embodiment of the present application.

[0035] Figure 6 FIG. 3 is a schematic view of a top structure of a second metal layer and an electrode layer provided by an embodiment of the present application.

[0036] Figure 7 FIG. 4 is a schematic view of a top structure of a second metal layer, a data line and an electrode layer provided by an embodiment of the present application.

[0037] Figure 8 FIG. 5 is a schematic view of a local structure of a B region in the display panel. Figure 7 DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative labor fall within the scope of protection of the present application.

[0039] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0040] ​​In the description of the application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection or can communicate with each other; can be directly connected, can also be indirectly connected through intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0041] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the "upper", "above" and "on" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The "below", "under" and "under" of the first feature to the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0042] The following disclosure provides many different embodiments or examples for implementing different structures of the application. In order to simplify the disclosure of the application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the application. In addition, the application can repeatedly refer to numbers and / or letters in different examples. Such repetition is for the purpose of simplification and clarity, and in itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0043] In view of the problems of green and pink emission, color separation and diffraction at large viewing angles when the FIAA and PLP combined technology is introduced into the display panel, the inventors find through analysis of various factors and experimental research that the existing FIAA technology needs to distribute multiple fan-out wires in a pixel area, and the multiple fan-out wires in the pixel area are asymmetrically arranged, so that the introduction of the FIAA technology will cause the pixel electrode (for example, the anode ANO) to be uneven, especially the pixel area of the pixel electrode, thereby causing the display panel to have problems of green and pink emission, color separation and more serious diffraction at large viewing angles when displaying; and the PLP technology has a higher requirement for the flatness of the pixel electrode, so that the introduction of the FIAA and PLP combined technology will often cause the problems of green and pink emission, color separation and diffraction at large viewing angles to be more serious. Therefore, the inventors improve the structure of the fan-out wires in the display area of the display panel, so that the fan-out wires under the pixel electrode are centrally symmetrically arranged and do not overlap the pixel area, effectively improving the flatness of the pixel area of the pixel electrode, so that the FIAA technology and the PLP technology can effectively improve the problems of green and pink emission, color separation and more serious diffraction at large viewing angles when combined.

[0044] As shown in Figure 1 , the embodiment of the present application provides a display panel 1, which comprises a display area 2 and a non-display area 3 arranged adjacent to each other.

[0045] Specifically, as shown in Figure 2 , the display panel 1 comprises, from bottom to top, a substrate 4, a first metal layer 5, a first flat layer 6, a second metal layer 7, a second flat layer 8, an electrode layer 9, a light-emitting functional layer 10 and a color filter layer 11.

[0046] Specifically, the substrate 4 is located in the display area 2 and the non-display area 3.

[0047] Specifically, the substrate 4 is an array substrate, which comprises a substrate layer 12 and an array layer on the substrate layer 12. The substrate layer 12 can be a flexible substrate layer or a rigid substrate layer, which is not limited here; the array layer comprises a plurality of driving units, each of which comprises a plurality of thin film transistors, for example, the thin film transistors T1 and T2 which are electrically connected to each other, but not limited thereto.

[0048] In a specific embodiment, the substrate layer 12 is composed of a double-layer polyimide (PI) layer, as shown in Figure 2As shown, the array layer includes at least one barrier layer (Barrier) 13 on the substrate layer 12, a bottom shield metal layer (BSM) 14 disposed wrapped by the barrier layer 13, a buffer layer (Buffer) 15 on the barrier layer 13, a first active layer 16 on the buffer layer 15, a first gate insulating layer (GI1) 17 covering the first active layer 16 and the buffer layer 15, a first gate layer 18 on the first gate insulating layer 17, a second gate insulating layer (GI2) 19 covering the first gate layer 18 and the first gate insulating layer 17, a second gate layer 20 on the second gate insulating layer 19, a first interlayer dielectric layer (ILD1) 21 covering the second gate layer 20 and the second gate insulating layer 19, a second active layer 22 on the first interlayer dielectric layer 21, a third gate insulating layer (GI3) 23 covering the second active layer 22 and the first interlayer dielectric layer 21, a third gate layer 24 on the third gate insulating layer 23, and a second interlayer dielectric layer (ILD2) 25 covering the third gate layer 24 and the third gate insulating layer 23.

[0049] Specifically, the first active layer 16 includes a first channel region 16a and first ohmic contact regions 16b on both sides of the first channel region 16a; the second active layer 22 includes a second channel region 22a and second ohmic contact regions 22b on both sides of the second channel region 22a. The first gate layer 18 includes a first gate corresponding to the first channel region 16a; the second gate layer 20 includes a second gate corresponding to the first gate and a third gate corresponding to the second channel region 22a; the third gate layer 24 includes a fourth gate corresponding to the second channel region 22a.

[0050] Specifically, the material of the first channel region 16a of the first active layer 16 includes polycrystalline silicon, but is not limited thereto; the material of the second channel region 22a of the second active layer 22 includes indium gallium zinc oxide (IGZO), but is not limited thereto.

[0051] In a specific embodiment, as shown in FIG. 2, the array layer includes at least one barrier layer (Barrier) 13 on the substrate layer 12, a bottom shield metal layer (BSM) 14 disposed wrapped by the barrier layer 13, a buffer layer (Buffer) 15 on the barrier layer 13, a first active layer 16 on the buffer layer 15, a first gate insulating layer (GI1) 17 covering the first active layer 16 and the buffer layer 15, a first gate layer 18 on the first gate insulating layer 17, a second gate insulating layer (GI2) 19 covering the first gate layer 18 and the first gate insulating layer 17, a second gate layer 20 on the second gate insulating layer 19, a first interlayer dielectric layer (ILD1) 21 covering the second gate layer 20 and the second gate insulating layer 19, a second active layer 22 on the first interlayer dielectric layer 21, a third gate insulating layer (GI3) 23 covering the second active layer 22 and the first interlayer dielectric layer 21, a third gate layer 24 on the third gate insulating layer 23, and a second interlayer dielectric layer (ILD2) 25 covering the third gate layer 24 and the third gate insulating layer 23. Figure 2As shown, the array layer further comprises a third metal layer (SD1) 26 on the second interlayer insulating layer 25, and a third planar layer 27 covering the third metal layer 26 and the second interlayer insulating layer 25, and the first metal layer (SD2) 5 is on the third planar layer 27. The third metal layer 26 comprises the first source S1, the first drain D1, the second source S2 and the second drain D2 in the display area 2; the third metal layer 26 further comprises a shielding signal line 28 in the non-display area 3, and the shielding signal line 28 is connected with the bottom shielding metal layer 14 through the second contact hole penetrating through the barrier layer 13, the buffer layer 15, the first gate insulating layer 17, the second gate insulating layer 19, the first interlayer insulating layer 21, the third gate insulating layer 23 and the second interlayer insulating layer 25. The first metal layer 5 comprises a plurality of data lines 29. The power signal line (such as VDD) can be on the first metal layer 5 or on the third metal layer 26. It can be understood that the second metal layer 7 is SD3 at this time.

[0052] In another specific embodiment, the first metal layer (SD1) is on the second interlayer insulating layer; the first metal layer comprises the first source, the first drain, the second source, the second drain and a plurality of data lines in the display area; the first metal layer further comprises a shielding signal line in the non-display area, and the shielding signal line is connected with the bottom shielding metal layer through the second contact hole penetrating through the barrier layer, the buffer layer, the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer. In the above-mentioned embodiment, the first metal layer can further comprise a power signal line, a film layer exchange line and other signal lines; of course, for high PPI panel products (such as LTPO panel products), a third metal layer (SD2) can be arranged between the first metal layer and the second metal layer for configuring the power signal line, the film layer exchange line and other signal lines. It can be understood that the second metal layer is SD3 at this time.

[0053] It should be noted that the first metal layer 5 is taken as the SD2 layer, the second metal layer is taken as the SD3 layer, and the third metal layer 26 is taken as the SD1 layer in the embodiments of the present application, but the present application is not limited thereto.

[0054] Specifically, the first source S1 and the first drain D1 are connected with the corresponding first ohmic contact area 16b through the first gate insulating layer 17, the second gate insulating layer 19, the first interlayer insulating layer 21, the third gate insulating layer 23 and the second interlayer insulating layer 25; the second source S2 and the second drain D2 are connected with the corresponding second ohmic contact area 22b through the third gate insulating layer 23 and the second interlayer insulating layer 25.

[0055] Specifically, the first active layer, the first gate, the second gate, the first source, and the first drain constitute the thin film transistor T1, and the third gate, the second active layer, the fourth gate, the second source, and the second drain constitute the thin film transistor T2. The first drain of the thin film transistor T1 is electrically connected to the second source of the thin film transistor T2 through the first ohmic contact region. Of course, the connection mode of the thin film transistor T1 and the thin film transistor T2 is not limited to this.

[0056] Specifically, the second source S2 is connected to the first ohmic contact region 16b through the first contact hole penetrating through the first gate insulating layer 17, the second gate insulating layer 19, the first interlayer insulating layer 21, the third gate insulating layer 23, and the second interlayer insulating layer 25.

[0057] It should be noted that the number and type of the thin film transistors in the driving unit of the array layer are not limited in the embodiments of the present application, and the structure of the array layer described above is only an example.

[0058] In the embodiments of the present application, the first metal layer 5 includes a plurality of data lines 29 located in the display area 2, and the data lines 29 extend along a first direction (for example, a vertical direction).

[0059] Specifically, the first planar layer 6 is located on the side of the first metal layer 5 away from the substrate 4.

[0060] Specifically, the second metal layer 7 is located on the side of the first planar layer 6 away from the substrate 4; the second metal layer 7 includes a plurality of fan-out wires 30 located in the display area 2 and electrically connected to the plurality of data lines 29 one by one.

[0061] Specifically, as shown in FIG. 1, each fan-out wire 30 includes a first wire part 31 extending along a first direction (for example, a vertical direction) and a second wire part 32 extending along a second direction (for example, a horizontal direction); the second direction is perpendicular to the first direction. The first wire part 31 extends to the non-display area 3; one end of the second wire part 32 is connected to the end of the first wire part 31 away from the non-display area 3, and the other end of the second wire part 32 is connected to the corresponding data line 29.

[0062] Specifically, as shown in FIG. 1, each fan-out wire 30 includes a first wire part 31 extending along a first direction (for example, a vertical direction) and a second wire part 32 extending along a second direction (for example, a horizontal direction); the second direction is perpendicular to the first direction. The first wire part 31 extends to the non-display area 3; one end of the second wire part 32 is connected to the end of the first wire part 31 away from the non-display area 3, and the other end of the second wire part 32 is connected to the corresponding data line 29. Figure 1 Specifically, as shown in FIG. 1, the display panel 1 further includes a binding area 33 located in the non-display area 3, for binding a driving chip; the first wire part 31 extends from the display area 2 to the binding area 33, and is electrically connected to the driving chip in the binding area 33 through a connection line located in the non-display area 3. It can be understood that the driving chip transmits electrical signals to the data line 29 through the first wire part 31 and the second wire part 32.

[0063] Figure 5 It can be understood that the fan-out wire 30 and the corresponding data line 29 are electrically connected through a via hole penetrating through the first planar layer 6. As shown in FIG. 1, the via hole is located in the display area 2.​Figure 5 As shown, the fan-out wires 30 are electrically connected to the corresponding data lines 29 in the A area through vias.

[0064] Specifically, the second planar layer 8 is located on the side of the second metal layer 7 away from the substrate 4.

[0065] Specifically, as shown in FIG. 1, Figure 2 As shown, the electrode layer 9 is located on the side of the second planar layer 8 away from the substrate 4 and in the display area 2. The electrode layer 9 includes pixel electrodes (e.g., ANOs) 34 arranged in multiple rows and multiple columns in the first direction and the second direction; each pixel electrode 34 includes a pixel area 35 and a non-pixel area 36 arranged around the pixel area 35.

[0066] In a specific embodiment, as shown in FIG. 1, Figure 2 As shown, the first metal layer 5 further includes first metal blocks 37, and the second metal layer 7 further includes second metal blocks 38; each pixel electrode 34 is electrically connected to the corresponding second metal block 38 through a via penetrating the second planar layer 8, then connected to the corresponding first metal block 37 through a via penetrating the first planar layer 6, and finally connected to the drain (e.g., the first drain D1 of the thin film transistor T1) of the corresponding thin film transistor through a via penetrating the third planar layer 27. Of course, in other embodiments, the pixel electrode 34 can also be electrically connected to the drain of the corresponding thin film transistor in other ways.

[0067] Specifically, as shown in FIG. 1, Figure 2 As shown, the display panel 1 further includes a pixel defining layer 39 located on the side of the electrode layer 9 away from the substrate 4, and the pixel defining layer 39 is provided with pixel openings 40 corresponding to the pixel areas 35, for exposing the pixel areas 35 of the corresponding pixel electrodes 34. It can be understood that the shape and size of the pixel openings 40 are consistent with those of the pixel areas 35.

[0068] Specifically, as shown in FIG. 1, Figure 2 As shown, the light-emitting functional layer 10 is located on the side of the electrode layer 9 away from the substrate 4, and the light-emitting functional layer 10 includes a plurality of light-emitting units 41 corresponding to the plurality of pixel electrodes 34. The light-emitting unit 41 is located in the pixel area 35 of the corresponding pixel electrode 34, for emitting light of a specific color.

[0069] Specifically, each light-emitting unit 41 includes any one of a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit. In a specific embodiment, the plurality of light-emitting units 41 on the two adjacent rows of pixel electrodes 34 are arranged in an RGBG array or a BGRG array, but are not limited thereto.

[0070] In an embodiment, the display panel 1 is a PLP type display panel, that is, no polarizer (POL) is arranged in the display panel 1, and a color filter layer is used instead of the polarizer. Specifically, as shown in Figure 2 The display panel 1 further includes a color filter layer 11 located on the side of the light-emitting functional layer 10 away from the substrate 4, and the color filter layer 11 includes a plurality of color-resistance units 42 arranged one-to-one corresponding to the plurality of light-emitting units 41 and a light-blocking unit 43 located between two adjacent color-resistance units 42.

[0071] For the PLP type display panel, as shown in Figure 7 The orthographic projection of the light-emitting unit (for example, the red light-emitting unit 41a, the green light-emitting unit 41b and the blue light-emitting unit 41c) on the substrate is generally circular, and the orthographic projection of the corresponding pixel electrode (for example, the first pixel electrode 34a and the second pixel electrode 34b) on the substrate is also circular. That is, the orthographic projection of the pixel region on the pixel electrode on the substrate is also circular. Of course, the shape of the orthographic projection of the light-emitting unit and the pixel electrode on the substrate is not limited in the embodiments of the present application.

[0072] Specifically, as shown in Figure 1 The display area 2 can be divided into an adjacent fan-out area 2a and a non-fan-out area 2b; the fan-out wire 30 is located in the fan-out area 2a, and each pixel electrode 34 in the fan-out area 2a is arranged adjacent to at least one fan-out wire 30.

[0073] For the convenience of description, as shown in Figures 6 to 8 The pixel electrode located in the fan-out area 2a is referred to as the first pixel electrode 34a in the embodiments of the present application, the pixel region of the first pixel electrode 34a is referred to as the first pixel region 35a, and the non-pixel region of the first pixel electrode 34a is referred to as the first non-pixel region 36a; correspondingly, the pixel electrode located in the non-fan-out area 2b is referred to as the second pixel electrode 34b, the pixel region of the second pixel electrode 34b is referred to as the second pixel region 35b, and the non-pixel region of the second pixel electrode 34b is referred to as the second non-pixel region 36b.

[0074] As can be understood, as shown in Figure 7 and Figure 8 The electrode layer 9 includes a plurality of first pixel electrodes 34a arranged adjacent to a plurality of fan-out wires; the first pixel electrode 34a includes a first pixel region 35a and a first non-pixel region 36a arranged around the first pixel region 35a.

[0075] Specifically, in combination with Figure 3 and Figure 6As shown, each fan-out wire 30 includes a winding portion 44 arranged corresponding to an adjacent first pixel electrode 34a; each first pixel electrode 34a is arranged corresponding to at least one winding portion 44, and the winding portion 44 is located at the periphery of the corresponding first pixel region 35a; at least one winding portion 44 arranged corresponding to the same first pixel electrode 34a is arranged in a central symmetry.

[0076] It can be understood that the winding portion 44 is arranged non-overlappingly with the first pixel region 35a of the corresponding first pixel electrode 34a, that is, the winding portion 44 is designed by winding to avoid being directly arranged below the first pixel region 35a, which is beneficial to improve the flatness of the first pixel region 35a; in addition, one or more winding portions 44 located below the first pixel electrode 34a are arranged in a central symmetry, which is beneficial to further improve the flatness of the first pixel electrode 34a; therefore, the embodiments of the present application are beneficial to ensure that the visual effects are consistent under each large viewing angle, and can improve the color separation problem to a certain extent.

[0077] Specifically, the winding portion 44 is located at the periphery of the corresponding first pixel electrode 34a; or, the winding portion 44 is arranged at least partially overlappingly with the first non-pixel region 36a of the corresponding first pixel electrode 34a. For example, Figure 6 In the middle, the winding portion 44 arranged corresponding to the first pixel electrode 34a with a larger area is located at the periphery of the corresponding first pixel electrode 34a, and the winding portion 44 arranged corresponding to the first pixel electrode 34a with a smaller area is located at the first non-pixel region 36a of the corresponding first pixel electrode 34a. Of course, the winding portion 44 arranged corresponding to the first pixel electrode 34a with a larger area can also be located at the first non-pixel region 36a of the corresponding first pixel electrode 34a, and the winding portion 44 arranged corresponding to the first pixel electrode 34a with a smaller area can also be located at the periphery of the corresponding first pixel electrode 34a.

[0078] It should be noted that the winding portion 44 is located at the periphery of the corresponding first pixel electrode 34a, which can be understood as that the spacing between the orthographic projection of the winding portion 44 on the substrate 4 and the orthographic projection of the first pixel electrode 34a on the substrate 4 can be greater than or equal to 0; the winding portion 44 is arranged at least partially overlappingly with the first non-pixel region 36a of the corresponding first pixel electrode 34a, which can be understood as that the orthographic projection of the winding portion 44 on the substrate 4 and the orthographic projection of the first non-pixel region 36a of the first pixel electrode 34a on the substrate 4 at least partially overlap.

[0079] Specifically, when the interval between the orthographic projection of the winding portion 44 on the substrate 4 and the orthographic projection of the corresponding first pixel electrode 34a on the substrate 4 can be greater than or equal to 0, the winding portion 44 is not arranged to coincide with the corresponding first pixel electrode 34a, so that the entire first pixel electrode 34a is in a flat shape. When the orthographic projection of the winding portion 44 on the substrate 4 and the orthographic projection of the corresponding first pixel electrode 34a on the substrate 4 are at least partially overlapped, the winding portion 44 is arranged to coincide with only the edge of the corresponding first pixel electrode 34a, so that at least the first pixel area 35a of the first pixel electrode 34a is in a flat shape. That is, the surface of the light emitting unit 41 on the first pixel electrode 34a in the embodiment of the present application is flat, which is beneficial to improve the problems of green and pink emission, color separation and diffraction under large viewing angle.

[0080] Specifically, in combination with the first pixel electrode 34a and the second pixel electrode 34b shown in Figure 3 and Figure 4 , each first wiring portion 31 and / or second wiring portion 32 of each fan-out wiring 30 includes at least one winding portion 44; the fan-out wiring 30 further includes a plurality of connecting portions 45, and any two adjacent winding portions 44 are connected by the connecting portion 45.

[0081] It can be understood that when the first wiring portion 31 or the second wiring portion 32 does not need to pass through the first pixel electrode 34a, the winding portion 44 does not need to be arranged. However, considering that the distribution of the first pixel electrode 34a is relatively dense, the first wiring portion 31 and the second wiring portion 32 will inevitably pass through the area where the first pixel electrode 34a is located, so the first wiring portion 31 and the second wiring portion 32 can be composed of a plurality of winding portions 44 and connecting portions 45 for connecting the winding portions 44.

[0082] Specifically, the connecting portion 45 is located between the two adjacent winding portions 44, i.e., between the two adjacent first pixel electrodes 34a.

[0083] Specifically, as shown in Figure 6 , the plurality of first pixel electrodes 34a are arranged in multiple rows and multiple columns in the first direction and the second direction; each column of first pixel electrodes 34a is arranged along the first direction, and each row of first pixel electrodes 34a is arranged along the second direction. The first wiring portion 31 is arranged adjacent to at least one column of first pixel electrodes 34a, and the first wiring portion 31 includes a plurality of winding portions 44 arranged corresponding to at least one column of first pixel electrodes 34a; the second wiring portion 32 is arranged adjacent to at least one row of first pixel electrodes 34a, and the second wiring portion 32 includes a plurality of winding portions 44 arranged corresponding to at least one row of first pixel electrodes 34a.

[0084] It can be understood that the plurality of winding portions 44 in the first wiring portion 31 are arranged in at least one column, and the plurality of winding portions 44 in the second wiring portion 32 are arranged in at least one row.

[0085] Specifically, the connection portions 45 in the first wiring portion 31 extend along the first direction, and the connection portions 45 in the second wiring portion 32 extend along the second direction, but are not limited thereto.

[0086] When the first wiring portion 31 is arranged adjacent to only one column of the first pixel electrodes 34a, the plurality of winding portions 44 in the first wiring portion 31 are arranged in a single column, and the connection portion 45 in the first wiring portion 31 is located between the two adjacent winding portions 44 (the first pixel electrode 34a) arranged in the same column and extends along the first direction; when the first wiring portion 31 is arranged adjacent to two columns of the first pixel electrodes 34a, the plurality of winding portions 44 in the first wiring portion 31 are arranged in two columns, and the connection portion 45 in the first wiring portion 31 is located between the two adjacent columns of winding portions 44 and extends along the first direction, at this time, the plurality of connection portions 45 can be connected to each other, and the two columns of winding portions 44 are located on opposite sides of the connection portion 45, respectively.

[0087] Similarly, when the second wiring portion 32 is arranged adjacent to only one row of the first pixel electrodes 34a, the plurality of winding portions 44 in the second wiring portion 32 are arranged in a single row, and the connection portion 45 in the second wiring portion 32 is located between the two adjacent winding portions 44 arranged in the same row and extends along the second direction; when the second wiring portion 32 is arranged adjacent to two rows of the first pixel electrodes 34a, the plurality of winding portions 44 in the second wiring portion 32 are arranged in two rows, and the connection portion 45 in the second wiring portion 32 is located between the two adjacent rows of winding portions 44 and extends along the second direction, at this time, the plurality of connection portions 45 can be connected to each other, and the two rows of winding portions 44 are located on opposite sides of the connection portion 45, respectively.

[0088] Specifically, in combination with the first winding portion 44a and the second winding portion 44b shown in FIGS. 1 and 2, the winding portion 44 can be the first winding portion 44a arranged in a central symmetry and in a ring shape; each fan-out wiring 30 includes at least one first winding portion 44a; at least part of the first pixel electrodes 34a are arranged corresponding to only one second winding portion 44b, and the first winding portion 44a is arranged surrounding the corresponding first pixel area 35a. Figure 3 Figure 4 Of course, the winding portion 44 can also be the second winding portion 44b, and at least one first pixel electrode 34a is arranged corresponding to two second winding portions 44b; the extension direction of the second winding portion 44b is consistent with the extension direction of the edge of the corresponding first pixel area 35a; the two second winding portions 44b arranged corresponding to the same first pixel electrode 34a are arranged in a central symmetry and are located in the adjacent two fan-out wirings 30, respectively.

[0089] Of course, the winding portion 44 can also be the second winding portion 44b, and at least one first pixel electrode 34a is arranged corresponding to two second winding portions 44b; the extension direction of the second winding portion 44b is consistent with the extension direction of the edge of the corresponding first pixel area 35a; the two second winding portions 44b arranged corresponding to the same first pixel electrode 34a are arranged in a central symmetry and are located in the adjacent two fan-out wirings 30, respectively.

[0090] ​Specifically, the winding portions 44 in the fan-out wires 30 can all be the first winding portions 44a, can be partially the first winding portions 44a and partially the second winding portions 44b, or all be the second winding portions 44b. It can be understood that different fan-out wires 30 can selectively set the winding portions 44 at different positions as the first winding portions 44a or the second winding portions 44b according to different distribution positions, so that the winding portions 44 under each first pixel electrode 34a are finally arranged in a central symmetry.

[0091] For example, as shown in Figure 3 , the plurality of fan-out wires 30 includes a first fan-out wire 30a, a second fan-out wire 30b and a third fan-out wire 30c arranged in sequence.

[0092] In combination with Figure 3 , Figure 4 and Figure 6 , the first wire portion 31 of the first fan-out wire 30a is arranged adjacent to the plurality of first pixel electrodes 34a arranged in the same column, and the second wire portion 32 of the first fan-out wire 30a is arranged adjacent to the two rows of first pixel electrodes 34a; correspondingly, the first wire portion 31 of the first fan-out wire 30a includes a plurality of second winding portions 44b arranged in the same column, and the second winding portion 44b of the first fan-out wire 30a includes a plurality of first winding portions 44a arranged in two rows. The first wire portion 31 of the second fan-out wire 30b and the first wire portion 31 of the first fan-out wire 30a are arranged adjacent to the same column of first pixel electrodes 34a, and the second wire portion 32 of the second fan-out wire 30b is arranged adjacent to the two rows of first pixel electrodes 34a; correspondingly, the first wire portion 31 of the second fan-out wire 30b includes a plurality of second winding portions 44b arranged in the same column, and the second wire portion 32 of the second fan-out wire 30b includes a plurality of first winding portions 44a arranged in two rows. The first wire portion 31 of the third fan-out wire 30c is arranged corresponding to the plurality of first pixel electrodes 34a arranged in the same column, and the second wire portion 32 of the third fan-out wire 30c is arranged corresponding to the two rows of first pixel electrodes 34a; correspondingly, the first wire portion 31 of the third fan-out wire 30c includes a plurality of first winding portions 44a arranged in the same column, and the second wire portion 32 of the second fan-out wire 30b includes a plurality of first winding portions 44a arranged in two rows.

[0093] It can be understood that when the first wire part 31 of the first fan-out wire 30a and the second wire part 32 of the second fan-out wire 30b are arranged adjacent to the same column of the first pixel electrodes 34a, each of the first pixel electrodes 34a in the column is arranged corresponding to two second winding parts 44b, and the two second winding parts 44b are arranged in a central symmetry. This design makes the fan-out wires 30 under all the first pixel electrodes 34a uniformly and symmetrically distributed, which is beneficial to improve the flatness of all the first pixel areas 35a and avoid display problems caused by uneven and asymmetric distribution of the fan-out wires 30.

[0094] Specifically, when one first pixel electrode 34a is arranged corresponding to two second winding parts 44b, the pattern formed by the two winding parts 44 is similar to the pattern of the first winding part 44a, so that the overall pattern of the winding parts 44 under different first pixel electrodes 34a is consistent or similar, which is beneficial to improve the uniformity of the metal pattern under the first pixel electrode 34a, thereby reducing display problems such as visible lines.

[0095] In a specific embodiment, as shown in Figures 3 to 8 the edge shape of the orthographic projection of the first pixel area 35a and the first pixel electrode 34a on the substrate 4 is circular; and the edge shape of the orthographic projection of any one winding part 44 on the substrate 4 is circular or circular arc. That is, when the edge shape of the orthographic projection of the first pixel area 35a and the first pixel electrode 34a on the substrate 4 is circular, the first winding part 44a is circular ring-shaped, and the second winding part 44b is circular arc-shaped. This design is beneficial to effectively improve the uniformity and symmetry of the fan-out wires 30 under the first pixel electrode 34a when the FIAA technology and the PLP technology are combined and applied, thereby effectively improving the flatness of the first pixel area 35a of the first pixel electrode 34a, and further improving problems such as bluish and pinkish, color separation and diffraction at large viewing angles caused by uneven and asymmetric metal wires.

[0096] In a specific embodiment, as shown in Figures 3 to 6As shown, the shapes and sizes of the multiple first pixel electrodes 34a arranged in the same row are the same, and the sizes of the two adjacent first pixel electrodes 34a arranged in the same row are different and staggered. The shapes and sizes of the multiple first pixel electrodes 34a arranged in the same column are the same, and the sizes of the two adjacent first pixel electrodes 34a arranged in the same column are different and staggered. Correspondingly, the shapes and sizes of the multiple winding portions 44 arranged in the same row are the same, and the size of each row of winding portions 44 is positively correlated with the size of the corresponding row of first pixel electrodes 34a. The shapes and sizes of the multiple winding portions 44 arranged in the same column are the same, and the size of each column of winding portions 44 is positively correlated with the size of the corresponding column of first pixel electrodes 34a. This design makes the distribution of each row of winding portions 44 and each column of winding portions 44 uniform and regular, which is beneficial to reducing display problems such as visible lines caused by uneven distribution of winding portions 44.

[0097] Based on the above specific embodiments, as Figure 7 shown, the multiple light emitting units (for example, red light emitting units 41a, green light emitting units 41b, and blue light emitting units 41c) are arranged in multiple rows and multiple columns, and each two adjacent rows of light emitting units 41 are arranged in an RGBG array or a BGRG array. That is, the red light emitting units 41a and the blue light emitting units 41c are alternately arranged in the same row, and the green light emitting units 41b are arranged in a single row. In addition, the area of the orthographic projection of the red light emitting unit 41a and the green light emitting unit 41b on the substrate 4 is smaller than the area of the orthographic projection of the blue light emitting unit 41c on the substrate 4. Since the red light emitting units 41a and the blue light emitting units 41c are arranged in the same row, the shapes and sizes of the two first pixel electrodes 34a corresponding to the red light emitting units 41a and the blue light emitting units 41c are the same. In addition, the shapes of the two first pixel electrodes 34a corresponding to the green light emitting units 41b and the blue light emitting units 41c are the same, but the sizes are different. Specifically, the area of the first pixel electrode 34a corresponding to the green light emitting unit 41b is smaller than the area of the first pixel electrode 34a corresponding to the blue light emitting unit 41c.

[0098] It can be understood that the area of the red light emitting unit 41a is smaller than the area of the blue light emitting unit 41c arranged in the same row, that is, the area of the first pixel area 35a corresponding to the red light emitting unit 41a is smaller than the area of the first pixel area 35a corresponding to the blue light emitting unit 41c. Here, the area can be understood as the area of the orthographic projection on the substrate.

[0099] Specifically, the shape and size of the first pixel electrode 34a in the same row are the same, and the shape and size of the two winding parts 44 arranged respectively corresponding to the red light emitting unit 41a and the blue light emitting unit 41c are consistent. This design is conducive to improving the uniformity and regularity of the winding part 44 under the first pixel electrode 34a in the same row, which is conducive to improving the production efficiency and the flatness and uniformity of the first pixel electrode 34a in the same row.

[0100] Specifically, the area of the first pixel electrode 34a arranged corresponding to the green light emitting unit 41b is smaller than the area of the first pixel electrode 34a arranged corresponding to the red light emitting unit 41a (or the blue light emitting unit 41c), and the area of the winding part 44 arranged corresponding to the green light emitting unit 41b is smaller than the area of the winding part 44 arranged corresponding to the red light emitting unit 41a (or the blue light emitting unit 41c). That is, the size (such as radius or area) of the winding part 44 can be positively correlated with the size of the corresponding first pixel electrode 34a, which is conducive to avoiding the winding part 44 occupying too much wiring space on the basis of improving the flatness of the first pixel electrode 34a.

[0101] Of course, the size of the winding part 44 can also be adjusted according to the size of the different light emitting units 41 (the first pixel area 35a), for example, the size of the winding part 44 is positively correlated with the size of the corresponding light emitting unit 41 (the first pixel area 35a). This design makes the consistency of the influence of the winding part 44 on the first pixel area 35a of different areas.

[0102] It should be noted that the arrangement mode of the light emitting unit and the pixel electrode in the embodiment of the present application is not limited, and the above-mentioned setting rule of the winding part is also applicable to the light emitting unit and the pixel electrode arranged in other modes.

[0103] In the above-mentioned embodiment, by winding design of the fan-out wire 30 in the fan-out area 2a of the display area 2, the fan-out wire 30 is wound according to the shape of the first pixel area 35a when passing under the first pixel electrode 34a, forming the winding part 44 located at the periphery of the first pixel area 35a, avoiding the fan-out wire 30 and the first pixel area 35a from being arranged in overlap, which is conducive to improving the flatness of the first pixel area 35a of the first pixel electrode 34a; and at least one winding part 44 under each first pixel electrode 34a is arranged in central symmetry, which is conducive to further improving the flatness of the first pixel area 35a of the first pixel electrode 34a; therefore, when the FIAA technology and the PLP technology are combined and applied, the flatness of the first pixel area 35a of the first pixel electrode 34a can be effectively improved, thereby effectively improving the problems of green and pink emission, color separation and diffraction of the display panel 1 under large viewing angle.

[0104] However, in FIAA technology, the fan-out traces are only formed in the fan-out area, resulting in uneven distribution of metal patterns in both the fan-out and non-fan-out areas. This leads to uneven screen-off display issues in the cell or module assembly state after panel production due to the uneven distribution of metal patterns. To solve the screen-off problem, this application also improves the structure in the non-fan-out area, as described below.

[0105] like Figures 3 to 7 As shown, based on the aforementioned embodiment, the second metal layer 7 further includes multiple virtual traces 46 located in the non-fan-out region 2b and spaced apart from the multiple fan-out traces 30; the multiple virtual traces 46 are arranged adjacent to multiple second pixel electrodes 34b in the non-fan-out region 2b. Each virtual trace 46 includes a virtual winding portion 47 corresponding to an adjacent second pixel electrode 34b, and each second pixel electrode 34b corresponds to at least one virtual winding portion 47. The extension direction of the virtual winding portion 47 is consistent with the extension direction of the corresponding second pixel region 35b; at least one virtual winding portion 47 corresponding to the same second pixel electrode 34b is centrally symmetrically arranged.

[0106] Understandably, the virtual trace 46 and the fan-out trace 30 are located on the same metal layer and are disconnected from each other.

[0107] Specifically, virtual trace 46 is used to connect to a preset potential, such as VDD or VSS.

[0108] Specifically, the multiple first pixel electrodes 34a in the fan-out area 2a are arranged in multiple rows and columns, and the multiple second pixel electrodes 34b in the non-fan-out area 2b are arranged in multiple rows and columns; a portion of the second pixel electrodes 34b are arranged in the same row as the first pixel electrodes 34a, and another portion of the second pixel electrodes 34b are arranged in the same column as the second pixel electrodes 34b; the first pixel electrodes 34a and second pixel electrodes 34b arranged in the same row have the same shape and size, and the first pixel electrodes 34a and second pixel electrodes 34b arranged in the same column have the same size and shape.

[0109] Correspondingly, the multiple winding portions 44 in the fan-out area 2a are arranged in multiple rows and columns, and the multiple virtual winding portions 47 in the non-fan-out area 2b are arranged in multiple rows and columns; some virtual winding portions 47 are arranged in the same row as the winding portions 44, and other virtual winding portions 47 are arranged in the same column as the winding portions 44; the virtual winding portions 47 and winding portions 44 arranged in the same row have the same shape and size, and the virtual winding portions 47 and winding portions 44 arranged in the same column have the same size and shape.

[0110] It can be seen that the distribution of the virtual winding part 47 in the virtual trace 46 is consistent with the distribution of the winding part 44 in the fan-out trace 30, and the pattern of the virtual winding part 47 is consistent with the pattern of the winding part 44, so that the distribution of the second metal layer 7 in the entire display area 2 is uniform, and the metal trace distribution under each pixel electrode 34 (including the first pixel electrode 34a and the second pixel electrode 34b) in the display area 2 is uniform and symmetrical, which is beneficial to effectively improve the screen-out problem caused by uneven metal pattern distribution on the basis of ensuring the flatness of the pixel area 35.

[0111] It should be noted that, as shown in FIG. 1, when the disconnection positions of the fan-out traces 30 and the virtual traces 46 arranged in the same row (or column) correspond to the same pixel electrode, the pixel electrode is provided with one winding part 44 and one virtual winding part 47, and the winding part 44 and the virtual winding part 47 corresponding to the same pixel electrode 34 are arranged in central symmetry. Figure 3

[0112] Specifically, since the virtual trace 46 in the non-fan-out area 2b is only used to realize the uniformity of the metal pattern of the fan-out area 2a and the non-fan-out area 2b, any two virtual winding parts 47 in the non-fan-out area 2b can be disconnected or connected to each other, which is not limited here.

[0113] In summary, the embodiments of the present application can not only effectively improve the problems of green and pink emission, color separation and diffraction of the display panel 1 at a large viewing angle when the FIAA and PLP technologies are combined, but also effectively improve the screen-out problem caused by uneven metal pattern distribution.

[0114] The embodiments of the present application also provide a display device, which comprises the display panel described in the above embodiments.

[0115] Specifically, the display device further comprises a housing located at least at the back and the side of the display panel.

[0116] The embodiments of the present application have the advantages described in the above embodiments, which will not be repeated here.

[0117] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0118] ​The above has carried out the detailed introduction to the display panel and the display device provided by the embodiment of the application, the principle and the implementation mode of the application are described in the text by applying specific examples, the above embodiment is only used for helping understanding the technical scheme of the application and its core idea; the ordinary skilled in the art should understand that: it can still modify the technical scheme recorded by the foregoing each embodiment, or equivalent replacement is carried out to part of technical features; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of the embodiments of the application.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a non-display area arranged adjacently, and the display panel comprises: a substrate, located in the display area and the non-display area; a first metal layer, located on one side of the substrate and comprising a plurality of data lines located in the display area; a first planar layer, located on a side of the first metal layer away from the substrate; a second metal layer, located on a side of the first planar layer away from the substrate and comprising a plurality of fan-out wires located in the display area and electrically connected to the plurality of data lines one by one; a second planar layer, located on a side of the second metal layer away from the substrate; an electrode layer, located on a side of the second planar layer away from the substrate and in the display area; the electrode layer comprises a plurality of first pixel electrodes arranged adjacently to the plurality of fan-out wires; the first pixel electrode comprises a first pixel area and a first non-pixel area arranged around the first pixel area; wherein each of the fan-out wires comprises a wire winding part arranged corresponding to the adjacent first pixel electrode; each of the first pixel electrodes corresponds to at least one wire winding part, and the wire winding part is located at the periphery of the corresponding first pixel area; the at least one wire winding part corresponding to the same first pixel electrode is arranged in a central symmetry; the wire winding part is located at the periphery of the corresponding first pixel electrode; or the wire winding part at least partially overlaps with the first non-pixel area of the corresponding first pixel electrode; the wire winding part comprises a first wire winding part arranged in a central symmetry and in a ring shape; the fan-out wire comprises at least one first wire winding part; at least part of the first pixel electrode is arranged corresponding to only one first wire winding part, and the first wire winding part surrounds the corresponding first pixel area.

2. The display panel of claim 1, wherein, The wire winding part further comprises a second wire winding part, and at least one first pixel electrode corresponds to two second wire winding parts; the extension direction of the second wire winding part is consistent with the extension direction of the edge of the corresponding first pixel area; the two second wire winding parts corresponding to the same first pixel electrode are arranged in a central symmetry and are located in two adjacent fan-out wires respectively.

3. The display panel of claim 1, wherein, The display panel further comprises a light-emitting functional layer and a color filter layer; the light-emitting functional layer is located on a side of the electrode layer away from the substrate, and the color filter layer is located on a side of the light-emitting functional layer away from the substrate; the light-emitting functional layer comprises a plurality of light-emitting units arranged corresponding to the plurality of first pixel electrodes one by one; the light-emitting unit is located in the first pixel area of the corresponding first pixel electrode; the color filter layer comprises a plurality of color resistance units arranged corresponding to the plurality of light-emitting units one by one; the shape of the edge of the orthographic projection of the first pixel area and the first pixel electrode on the substrate is circular; the shape of the edge of the orthographic projection of any one wire winding part on the substrate is circular or circular arc.

4. The display panel of claim 1, wherein, The data lines extend along a first direction; each of the fan-out wires comprises a first wire part extending along the first direction and a second wire part extending along a second direction; the second direction is perpendicular to the first direction; The first wire part extends to the non-display area; one end of the second wire part is connected to one end of the first wire part away from the non-display area, and the other end of the second wire part is connected to the corresponding data line; the first wire part and / or the second wire part comprises at least one winding part; The fan-out wire further comprises a plurality of connecting parts, and any two adjacent winding parts are connected through the connecting part.

5. The display panel of claim 4, wherein, The plurality of first pixel electrodes are arranged in a plurality of rows and a plurality of columns in the first direction and the second direction; each column of the first pixel electrodes is arranged along the first direction, and each row of the first pixel electrodes is arranged along the second direction; The first wire part is arranged adjacent to at least one column of the first pixel electrodes, and the first wire part comprises a plurality of winding parts arranged corresponding to the at least one column of the first pixel electrodes; the second wire part is arranged adjacent to at least one row of the first pixel electrodes, and the second wire part comprises a plurality of winding parts arranged corresponding to the at least one row of the first pixel electrodes.

6. The display panel of claim 1, wherein, The display area comprises a fan-out area and a non-fan-out area arranged adjacent to each other; the fan-out wires and the first pixel electrodes are located in the fan-out area; the second metal layer further comprises a plurality of virtual wires located in the non-fan-out area and arranged spaced apart from the plurality of fan-out wires; the virtual wires are used to access a preset potential; The electrode layer further comprises a plurality of second pixel electrodes located in the non-fan-out area and arranged adjacent to the plurality of virtual wires; the second pixel electrode comprises a second pixel area and a second non-pixel area arranged around the second pixel area; each of the virtual wires comprises a virtual winding part arranged corresponding to the adjacent second pixel electrode, and each of the second pixel electrodes is arranged corresponding to at least one virtual winding part; the extension direction of the virtual winding part is consistent with the extension direction of the corresponding second pixel area; the at least one virtual winding part corresponding to the same second pixel electrode is arranged in a central symmetry.

7. The display panel of claim 6, wherein, The plurality of first pixel electrodes in the fan-out area are arranged in a plurality of rows and a plurality of columns, and the plurality of second pixel electrodes in the non-fan-out area are arranged in a plurality of rows and a plurality of columns; a part of the second pixel electrodes are arranged in the same row as the first pixel electrodes, and another part of the second pixel electrodes are arranged in the same column as the second pixel electrodes; the first pixel electrodes and the second pixel electrodes arranged in the same row have the same shape and size, and the first pixel electrodes and the second pixel electrodes arranged in the same column have the same size and shape. The multiple winding parts in the fan-out area are arranged in multiple rows and multiple columns, and the multiple virtual winding parts in the non-fan-out area are arranged in multiple rows and multiple columns; a part of the virtual winding parts are arranged in the same row as the winding parts, and another part of the virtual winding parts are arranged in the same column as the winding parts; the virtual winding parts arranged in the same row as the winding parts are the same in shape and size, and the virtual winding parts arranged in the same column as the winding parts are the same in size and shape.

8. A display device, characterized by comprising: The display panel comprises any one of claims 1 to 7.

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