Shift register, drive circuit, drive method, and display device

Abstract

This disclosure provides a shift register, a driving circuit, a driving method, and a display device, relating to the field of display technology. The shift register includes a first control circuit configured to provide a first clock signal to control a first node under the control of a first clock signal from a first clock terminal, or to provide a first power supply voltage to the first node under the control of a first power supply voltage from a first power supply; a second control circuit configured to control the potential of a second node using a second power supply voltage from a second power supply under the control of the potential of the first node; a gating circuit configured to control the potential of the second node using the first power supply voltage from a first power supply under the control of multiple gating signals from multiple gating terminals; and an output circuit configured to provide a second power supply voltage or a second clock signal from a second clock terminal to an output terminal as an output signal under the control of the potentials of the first and second nodes.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method, and a display device. Background Technology

[0002] To achieve a good balance between power consumption and high refresh rates, displays typically employ local high refresh rate (DRPR) technology. This technology requires the driver circuitry to have flexible activation capabilities. Common shift register driver circuits offer limited driving capabilities for displays and cannot adjust in real time according to the image, thus failing to meet the more flexible high refresh rate requirements of displays. Summary of the Invention

[0003] This disclosure provides a shift register, a driving circuit, a driving method, and a display device.

[0004] According to a first aspect, this disclosure provides a shift register, including a first control circuit configured to provide a first clock signal to control a first node under the control of a first clock signal from a first clock terminal, or to provide a first power supply voltage to the first node under the control of a first power supply voltage; a second control circuit configured to control the potential of a second node using a second power supply voltage from a second power supply under the control of the potential of the first node; a gating circuit configured to control the potential of the second node using the first power supply voltage from a first power supply under the control of multiple gating signals from multiple gating terminals; and an output circuit configured to provide a second power supply voltage or a second clock signal from a second clock terminal to an output terminal as an output signal under the control of the potentials of the first and second nodes, wherein the multiple gating signals control the output of the output signal.

[0005] According to a second aspect, this disclosure provides a driving circuit including M shift registers as provided in any embodiment of this disclosure; wherein the m-th shift register is electrically connected to a first strobe terminal, the (m+1)-th shift register is electrically connected to a second strobe terminal, the first strobe signal output from the first strobe terminal and the second strobe signal output from the second strobe terminal are not simultaneously active, 1 ≤ m < M, and M is a positive integer greater than 1.

[0006] According to a third aspect, this disclosure provides a display device, including a display panel; and a driving circuit as provided in the embodiments of this disclosure; wherein the display panel includes M pixel rows arranged in an array, and the driving circuit includes M shift registers for driving the M pixel rows in the display panel respectively.

[0007] According to the fourth aspect, this disclosure provides a driving method applied to a shift register provided in the embodiments of this disclosure, comprising: in a gating phase, controlling a designated gating signal among a plurality of gating signals to be at a second level, and all gating signals other than the designated gating signal among the plurality of gating signals being at a first level; and in a non-gating phase, controlling at least one gating signal among the gating signals other than the designated gating signal among the plurality of gating signals to be at a second level. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure;

[0009] Figure 2A This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0010] Figure 2B This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0011] Figure 3 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0012] Figure 4 This is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0013] Figure 5 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0014] Figure 6 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0015] Figure 7 This is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0016] Figure 8 This is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure; and

[0017] Figure 9 This is a flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0019] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0020] Furthermore, in the description of the embodiments disclosed herein, the terms "connected" or "connected to" can refer to two components being directly connected, or to two components being connected via one or more other components. Additionally, these two components can be connected or coupled via wired or wireless means.

[0021] The source and drain of the switching transistor used in this embodiment are symmetrical, so their source and drain can be interchanged. In this embodiment, according to its function, the control electrode can be called the control electrode, one of the source and drain is called the first electrode, and the other of the source and drain is called the second electrode.

[0022] It should be noted that in the description of the embodiments of this disclosure, the symbol OUT can represent either an output signal or an output terminal. Similarly, the symbol CKLE1 can represent either a first clock terminal or a first clock signal provided by the first clock terminal, the symbol VGH can represent either a first power supply or a first power supply voltage provided by the first power supply, and the symbol VGL can represent either a second power supply or a second power supply voltage provided by the second power supply. For example, power supplies VGL and LVGL can provide low voltages, while power supplies VGH and GVDD can provide high levels. The following embodiments are the same, and similar parts will not be described again.

[0023] Figure 1 This is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0024] like Figure 1 As shown, the shift register 100 includes a first control circuit 110, a second control circuit 120, a gating circuit 130, and an output circuit 140.

[0025] In this embodiment, the first control circuit 110 is electrically connected to either the first clock terminal CLKE1 or the second power supply VGL, or the first control circuit 110 is electrically connected to the first power supply VGH and the second power supply VGL. Under the control of the first clock signal CLKE1 from the first clock terminal CLKE1, the first control circuit 110 provides the first clock signal CLKE1 to control the first node QB. Alternatively, under the control of the first power supply voltage VGH of the first power supply VGH, the first control circuit 110 provides the first power supply voltage VGH to the first node QB.

[0026] For example, the first clock signal CLKE1 or the first power supply voltage VGH can control the first control circuit 110 to switch between on and off states. For instance, when the first clock signal CLKE1 controls the first control circuit 110 to be in the on state, the first clock signal CLKE1 and the first node QB are in a conducting state, and the first clock terminal CLKE1 is written to the first node QB. When the first power supply voltage VGH controls the first control circuit 110 to be in the on state, the first power supply VGH and the first node QB are in a conducting state, and the first power supply voltage VGH is written to the first node QB.

[0027] In this embodiment, the second control circuit 120 is electrically connected to the second power supply VGL, the first node QB, and the second node Q. Under the control of the potential of the first node QB, the second control circuit 120 uses the second power supply voltage VGL of the second power supply VGL to control the potential of the second node Q.

[0028] For example, the potential of the first node QB can control whether the second power supply VGL and the second node Q are in a conducting or cut-off state. When the second power supply VGL and the second node Q are in a conducting state, the second control circuit 120 can write the second power supply voltage VGL to the second node Q to control the potential of the second node Q.

[0029] In this embodiment, the gating circuit 130 is electrically connected to a plurality of gating terminals D0, D0', D1', ..., Dn', a first power supply VGH, and a second node Q. Under the control of a plurality of gating signals D0, D0', D1', ..., Dn' from the plurality of gating terminals D0, D0', D1', ..., Dn', the gating circuit 130 controls the potential of the second node Q using the first power supply voltage VGH of the first power supply VGH.

[0030] For example, multiple gating signals D0, D0', D1', ..., Dn' can control the connection between the first power supply VGH and the second node Q to be in a conducting or cut-off state. When the first power supply VGH and the second node Q are in a conducting state, the gating circuit 130 can write the first power supply voltage VGH to the second node Q to control the potential of the second node Q.

[0031] In this embodiment of the disclosure, the second control circuit 120 can pull down the potential of the second node Q based on the second power supply voltage VGL. The gating circuit 130 can pull up the potential of the second node Q based on the first power supply voltage VGH.

[0032] In this embodiment, the output circuit 140 is electrically connected to the output terminal OUT, the first node QB, the second node Q, the second power supply VGL, and the second clock terminal CLKE2. Under the control of the potentials of the first node QB and the second node Q, the second power supply voltage VGL or the second clock signal CLKE2 from the second clock terminal CLKE2 is provided to the output terminal OUT as the output signal OUT.

[0033] For example, the potential of the first node QB can control whether the second power supply VGL and the output terminal OUT1 are in a conducting or cut-off state. When the second power supply VGL and the output terminal OUT1 are in a conducting state, the output circuit 140 provides the second power supply voltage VGL to the output terminal OUT, and the output terminal OUT outputs a low-level signal.

[0034] For example, the potential of the second node Q can control whether the second clock terminal CLKE2 and the output terminal OUT are in a conducting or cut-off state. When the second clock terminal CLKE2 and the output terminal OUT are in a conducting state, the output circuit 140 provides the second clock signal CLKE2 to the output terminal OUT, and the output terminal OUT outputs the second clock signal CLKE2.

[0035] In this embodiment, the output signal OUT can be used to drive the N-type transistor in the pixel circuit. For example, when the input signal OUT is high, the N-type transistor is turned on, and data signals can be written, thereby refreshing the screen. When the input signal OUT is low, the N-type transistor is turned off, and data signals cannot be written, thus preventing screen refresh and keeping the screen unchanged.

[0036] For example, the levels of the strobe signals D0, D1', ..., Dn' can indicate whether the transistors in the pixel circuit electrically connected to the shift register 100 are turned on. For instance, when all strobe signals D0, D1', ..., Dn' are high, the first power supply voltage VGH is written to the second node Q, the voltage of the first node Q is pulled high, and the output terminal OUT outputs the second clock signal CLKE2 as the output signal OUT. At this time, the N-type transistors in the pixel circuit can switch to the on state, and the corresponding display screen refreshes. When any one of the strobe signals D0, D1', ..., Dn' is low, the first power supply VGH and the second node Q are in a cutoff state, the second power supply voltage VGH cannot be written to the second node Q, and the level of the output signal OUT from the output terminal OUT remains low. At this time, the N-type transistors in the pixel circuit remain in the off state based on the low-level output signal OUT, and the corresponding display screen does not refresh.

[0037] According to embodiments of this disclosure, by controlling the potentials of the first node QB and the second node Q based on a gating signal, it can be determined whether the shift register 100 is in the gating stage, thereby controlling whether a pixel row electrically connected to the shift register 100 is refreshed. In a driving circuit including multiple shift registers, any shift register can be selected for gating by a gating signal, thereby enabling each pixel row in the pixel circuit to have the ability to be flexibly turned on, realizing control over whether a single pixel row is refreshed.

[0038] In some embodiments, under the control of a first level of a designated gating signal D0 from a designated gating terminal D0 among a plurality of gating terminals D0, D0', D1', ..., Dn', the gating circuit 130 provides a second power supply voltage VGL to the second node Q. Under the control of a first level of multiple gating signals from a plurality of gating terminals other than the designated gating terminal, the gating circuit 130 provides a first power supply voltage VGH to the second node Q.

[0039] In this embodiment of the disclosure, among the plurality of gating signals D0, D0', D1', ..., Dn', gating signal D0' is a designated gating signal. The first level is a high level, and the second level is a low level.

[0040] When the gating signals D0', D1', ..., Dn' are all high and the gating signal D0 is low, the shift register 100 is in the gating stage. Under the control of the high levels of the gating signals D0', D1', ..., Dn' and the low level of the gating signal D0, the gating circuit 130 controls the first power supply voltage VGH to be written to the second node Q, at which time the potential of the second node Q is high. Under the control of the second node Q, the first control circuit 110 controls the first node QB to be low.

[0041] In this case, the output terminal OUT and the second clock terminal CLKE2 are in a conducting state, and the output terminal OUT outputs the second clock signal CLKE2 as the output signal OUT.

[0042] In this embodiment of the disclosure, when any one of the strobe signals D0', D1', ..., Dn' is at a low level, the shift register 100 is in the non-strobe stage.

[0043] For example, when any of the strobe signals D0', D1', ..., Dn' is low, the first power supply voltage VGH is in a cutoff state with respect to the second node Q, and the first power supply voltage VGH cannot pull the potential of the second node Q high. In this case, the output terminal OUT is in a cutoff state with respect to the second clock terminal CLKE2, and the output terminal OUT cannot output the second clock signal CLKE2 as the output signal OUT.

[0044] When the first clock signal CLKE1 or the first power supply voltage VGH is written to the first node QB, the output terminal OUT is in a conducting state with the second power supply VGL, and the output terminal OUT outputs the second power supply voltage VGL as the output signal OUT.

[0045] Figure 2A This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0046] like Figure 2A As shown, the shift register 200a includes a first control circuit 210, a second control circuit 220, a gating circuit 230, and an output circuit 240.

[0047] In this embodiment, the second control circuit 220 is electrically connected to the first node QB, the output terminal OUT, and the second power supply VGL. Under the control of the output signal OUT, the second control circuit 220 provides the second power supply voltage VGL to the first node QB.

[0048] For example, the output signal OUT can control the connection between the first node QB and the second power supply VGL to be in an on or off state. When the output signal OUT controls the first node QB to be in an on state with the second power supply VGL, the second power supply voltage VGL is written to the first node QB to pull down the potential of the first node QB.

[0049] In some embodiments, the first control circuit 210 is also electrically connected to the first node QB, the second node Q, and the second power supply VGL. Under the control of the potential of the second node Q, the first control circuit 210 provides the second power supply voltage VGL to the first node.

[0050] For example, the potential of the second node Q can control the conduction and cutoff states between the first node QB and the second power supply VGL. When the potential of the second node Q controls the conduction state between the first node QB and the second power supply VGL, the second power supply voltage VGL is written to the first node QB to pull down the potential of the first node QB.

[0051] In this embodiment, during the non-gating phase, when the first control circuit 210 controls the potential of the first node QB to be high, the second power supply voltage VGL is pulled down by the second control circuit 220 under the control of the high level of the first node QB. During the gating phase, when the gating circuit 230 controls the potential of the second node Q to be high, the second power supply voltage VGL is pulled down by the first control circuit 210 under the control of the high level of the second node QB.

[0052] In this embodiment of the present disclosure, the first control circuit 210 and the second control circuit 220 can control the potentials of the first node QB and the second node Q to be reversed, which enables the output circuit 240 of the shift register 100 to output the output signal OUT normally.

[0053] Figure 2B This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0054] like Figure 2B As shown, the shift register 200b includes a first control circuit 210, a second control circuit 220, a gating circuit 230, an output circuit 240, and a third control circuit 250.

[0055] In this embodiment, the first control circuit 210, the second control circuit 220, the gating circuit 230, and the output circuit 240 are similar in structure to the first control circuit 110, the second control circuit 120, the gating circuit 130, and the output circuit 140 described above, and will not be repeated for the sake of brevity.

[0056] In this embodiment, the third control circuit 250 is electrically connected to the first node QB, the first power supply VGH, and the third node P. The gating circuit 230 is electrically connected to the third node P. Under the control of multiple gating signals D0', D1', ..., Dn', the potential of the third node P is controlled by the first power supply voltage VGH. Under the control of the potential of the third node P, the third control circuit 250 provides the first power supply voltage VGH to the potential of the first node QB.

[0057] For example, multiple strobe signals D0', D1', ..., Dn' can control the conduction and cutoff states between the third node P and the first power supply VGH. When the third node P and the first power supply VGH are in the conduction state, the first power supply voltage VGH is written to the third node P to pull up the potential of the third node P.

[0058] The third node P can control the conduction and cutoff states between the second node Q and the first power supply VGH. When the second node Q is in the conduction state with the first power supply VGH, the first power supply voltage VGH is written to the second node Q to pull up the potential of the second node Q.

[0059] In this embodiment, since the gating circuit 230 has a weak ability to write the first power supply voltage VGH into the second node Q, in order to ensure that the potential of the second node Q can be stably maintained at a high level during the gating phase, the third control unit 250 writes the first power supply voltage VGH into the second node Q to enhance the ability to pull the potential of the second node Q high.

[0060] In some embodiments, the third control circuit 250 is also electrically connected to the designated strobe terminal D0 and the second power supply VGL.

[0061] In the embodiments of this disclosure, under the control of the high level of the designated strobe signal D0, the third control circuit 250 provides the second power supply voltage VGL to the third node P to pull down the potential of the third node P, thereby resetting the potential of the third node P.

[0062] For example, a high level of the specified strobe signal D0 controls the second power supply VGL to be in a conducting state with the third node P. The third control circuit 250 writes the second power supply voltage VGL into the third node P.

[0063] In this embodiment, the first control circuit 210 is electrically connected to the third node P, the first node QB, the second node Q, and the second power supply VGL. Under the control of the potential of the third node P, the first control circuit 210 provides the second power supply voltage VGL to the first node QB.

[0064] For example, the potential of the third node P controls the second power supply VGL to be in a conducting state with the first node QB. The third control circuit 250 writes the second power supply voltage VGL into the first node QB, pulling down the potential of the first node QB.

[0065] For example, during the selection phase, when the potential of the third node P is high, the first power supply VGH and the second node Q are in a conducting state, and the potential of the second node Q is also high. Under the control of the high level of the second node Q, the second control circuit 220 pulls down the potential of the first node QB, thereby preventing the second node QB from coupling to a high potential. The low potential of the first node QB ensures that the second power supply VGL and the output terminal OUT are in a cutoff state, thus preventing the second power supply voltage VGL from pulling down the output signal OUT, causing the output signal OUT to have noise.

[0066] Figure 3 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0067] like Figure 3 As shown, the shift register 300 includes a first control circuit 310, a second control circuit 30, a gating circuit 330, and an output circuit 340.

[0068] In this embodiment of the disclosure, the gating circuit 330 includes a first transistor T1 to a ninth transistor T9. The first transistor T1 to the ninth transistor T9 are gating transistors. The control terminals of the first transistor T1 to the ninth transistor T9 are electrically connected to a plurality of gating terminals D0, D1', ..., D7', D0', respectively. The control terminal of the ninth transistor T9 is electrically connected to a designated gating terminal D0'.

[0069] The first terminal of the first transistor T1 is electrically connected to the first power supply VGH. The second terminal of the first transistor T1 is electrically connected to the first terminal of the second transistor T2. The second terminal of the second transistor T2 is electrically connected to the first terminal of the third transistor T3. The second terminal of the third transistor T3 is electrically connected to the first terminal of the fourth transistor T4. The second terminal of the fourth transistor T4 is electrically connected to the first terminal of the fifth transistor T5. The second terminal of the fifth transistor T5 is electrically connected to the first terminal of the sixth transistor T6. The second terminal of the sixth transistor T6 is electrically connected to the first terminal of the seventh transistor T7. The second terminal of the seventh transistor T7 is electrically connected to the first terminal of the eighth transistor T8. The second terminal of the eighth transistor T8 is electrically connected to the second node Q.

[0070] The first terminal of the ninth transistor T9 is electrically connected to the second node Q, and the second terminal of the ninth transistor T9 is electrically connected to the second power supply VGL.

[0071] In this embodiment of the disclosure, the first control circuit 310 includes a tenth transistor T10 and an eleventh transistor T11.

[0072] The control electrode and first electrode of the tenth transistor T10 are electrically connected to the first clock terminal CLKE1, and the second electrode of the tenth transistor T10 is electrically connected to the first node QB.

[0073] The control electrode of the eleventh transistor T11 is electrically connected to the second node Q, the first electrode of the eleventh transistor T11 is electrically connected to the first node QB, and the second electrode of the eleventh transistor T11 is electrically connected to the second power supply VGL.

[0074] In this embodiment of the disclosure, the second control circuit 320 includes a twelfth transistor T12 and a thirteenth transistor T13.

[0075] The control electrode of the twelfth transistor T12 is electrically connected to the first node QB, the first electrode of the twelfth transistor T12 is electrically connected to the second node Q, and the second electrode of the twelfth transistor T12 is electrically connected to the second power supply VGL.

[0076] The control electrode of the thirteenth transistor T13 is connected to the output terminal OUT, the first electrode of the thirteenth transistor T13 is connected to the first node QB, and the second electrode of the thirteenth transistor T13 is connected to the second power supply VGL.

[0077] In this embodiment of the disclosure, the output circuit 340 includes a fourteenth transistor T14, a fifteenth transistor T15, and a first capacitor C1.

[0078] The control electrode of the fourteenth transistor T14 is connected to the second node Q, the first electrode of the fourteenth transistor T14 is connected to the second clock terminal CLKE2, and the second electrode of the fourteenth transistor T14 is connected to the output terminal OUT.

[0079] The control electrode of the fifteenth transistor T15 is electrically connected to the first node QB, the first electrode of the fifteenth transistor T15 is electrically connected to the output terminal OUT, and the second electrode of the fifteenth transistor T15 is electrically connected to the second power supply VGL.

[0080] The first terminal of the first capacitor C1 is electrically connected to the second node Q, and the second terminal of the first capacitor C1 is electrically connected to the output terminal OUT.

[0081] In the embodiments of this disclosure, the first transistor T1 to the fifteenth transistor T15 are N-type TFT transistors, such as thin-film transistors with an active layer of indium gallium zinc oxide (IGZO). As those skilled in the art will understand, the first transistor T1 to the fifteenth transistor T15 in this disclosure can also be P-type TFT transistors, such as thin-film transistors with an active layer of low-temperature doped polysilicon (LTPS). The gate conduction signal level of each transistor can be changed accordingly.

[0082] Furthermore, those skilled in the art will understand that capacitors can be implemented as single capacitors or multiple capacitor units connected in parallel or series, as long as they can achieve their respective functions.

[0083] In the description of the embodiments of this disclosure, the first node QB and the second node Q do not represent actual existing components, but rather represent the junction points of related circuit connections in the circuit diagram.

[0084] Figure 4 yes Figure 3 The signal timing diagram of the intermediate shift register. The following is an example. Figure 3 Taking the structure of the shift register 300 shown as an example, combined with... Figure 4 The signal timing diagram shown describes the operation of the shift register provided in the embodiments of this disclosure. Figure 4 The signal timing of shift register 300 during the five stages S1-S5 of the process is shown.

[0085] In this embodiment of the disclosure, the gating signals received by gating terminals D0', D1', ..., D7' are gating signals D0, D1', ..., D7', respectively, and the gating signal received by gating terminal D0 is designated as gating signal D0'.

[0086] In the first stage S1, the levels of the strobe signals D0, D0', D1', ..., D7' are high, high, low, low, low, low, low, low, and low, respectively. The first clock signal CLKE1 and the second clock signal CLKE2 both transition from low to high.

[0087] The first transistor T1, the tenth transistor T10, and the ninth transistor T9 are turned on, while the second transistor T2 through the eighth transistor T8 are turned off.

[0088] The first clock signal CLKE1 is written to the first node QB through the tenth transistor T10. When the first clock signal CLKE1 changes from low to high, the potential of the first node QB also changes from low to high.

[0089] Under the control of the high level of the first node QB, the twelfth transistor T12 is turned on. The second power supply voltage VGL is written to the second node Q through the twelfth transistor T12, and the potential of the second node Q is low.

[0090] Under the control of the high level of the first node QB, the fifteenth transistor T15 is turned on. Under the control of the low level of the second node Q, the fourteenth transistor T14 is turned off. At this time, the first power supply voltage VGL is output to the output terminal OUT through the fifteenth transistor T15, and the output terminal OUT outputs a low-level signal.

[0091] In the second stage S2, the levels of the strobe signals D0, D0', D1', ..., D7' are high, low, high, high, high, high, high, high, and high, respectively. The first clock signal CLKE1 and the second clock signal CLKE2 are both low.

[0092] The tenth transistor T10 and the ninth transistor T9 are turned off, while the first transistor T1 through the eighth transistor T8 are turned on.

[0093] The first power supply voltage VGH is written to the second node Q through the first transistor T1 to the eighth transistor T8, raising the potential of the second node Q and charging the first terminal of the first capacitor C1. Under the control of the high level of the second node Q, the eleventh transistor T11 is turned on. The second power supply voltage VGL is written to the first node QB through the eleventh transistor T11, lowering the potential of the first node QB.

[0094] Under the control of the low level of the first node QB, the fifteenth transistor T15 is turned off. Under the control of the high level of the second node Q, the fourteenth transistor T14 is turned on. At this time, the low level of the second clock signal CLKE2 is output to the output terminal OUT through the fourteenth transistor T14, and the output terminal OUT outputs a low level signal.

[0095] In the third stage S3, the levels of the strobe signals D0, D0', D1', ..., D7' are high, low, high, high, high, high, high, high, and high, respectively. The first clock signal CLKE1 is low, and the second clock signal CLKE2 is high.

[0096] The states of transistors T1 through T15 are the same as in stage S2. The first power supply voltage VGH continues to charge node Q. Under the bootstrap effect of the first capacitor C1, the potential of node Q is pulled up again.

[0097] Under the control of the low level of the first node QB, the fifteenth transistor T15 is turned off. Under the control of the high level of the second node Q, the fourteenth transistor T14 is turned on. At this time, the high level of the second clock signal CLKE2 is output to the output terminal OUT through the fourteenth transistor T14, and the output terminal OUT outputs a high-level signal.

[0098] Under the control of the high level of the output signal OUT, the thirteenth transistor T13 is turned on. The second power supply voltage VGL is written to the first node QB through the thirteenth transistor T13, and the potential of the first node QB remains low. At this time, the fifteenth transistor T15 is completely turned off, which can prevent the fifteenth transistor T15 from generating noise for the high-level signal output at the output terminal OUT.

[0099] In the fourth stage S4, the levels of the strobe signals D0, D0', D1', ..., D7' are low, high, low, high, high, high, high, and high, respectively. The first clock signal CLKE1 and the second clock signal CLKE2 are both at a low level.

[0100] Transistors T3 through T9 are turned on, while transistors T1 and T2 are turned off. The second power supply voltage VGL is written to node Q via transistor T9, causing the potential of node Q to jump from high to low. Under the influence of capacitor C1, the potential of output terminal OUT is also low. The potential of node QB remains low as in the previous stage.

[0101] In the fifth stage S5, the levels of the strobe signals D0, D0', D1', ..., D7' are low, high, low, high, high, high, high, high, and high, respectively. The first clock signal CLKE1 is high, and the second clock signal CLKE2 is low.

[0102] The first transistor T1, the third transistor T3 to the ninth transistor T9 are turned on, and the second transistor T2 is turned off.

[0103] The high level of the first clock signal CLKE1 is written to the first node QB through the tenth transistor T10, pulling the potential of the first node QB high. Under the control of the high level of the first node QB, the potential of the second node Q is pulled low by the second power supply voltage VGL.

[0104] Under the control of the high level of the first node QB, the fifteenth transistor T15 is turned on. Under the control of the low level of the second node Q, the fourteenth transistor T14 is turned off. At this time, the first power supply voltage VGL is output to the output terminal OUT through the fifteenth transistor T15, and the output terminal OUT outputs a low-level signal.

[0105] In this embodiment of the disclosure, multiple gating signals can support gating display of multiple pixel rows. For example, the number of gating signals is 2^n, the decoding bit depth of the gating signals is n, and the maximum number of supported rows is 2^n. n For example, with a 14-bit decoding bit, the maximum number of supported rows reaches 16,384. Alternatively, with strobe signals D0~D7 and D0'~D7' implementing an 8-bit decoding bit, it can support 256 rows of strobes. If the number of rows needs to be increased, each additional strobe signal can support double the number of rows.

[0106] Figure 5 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0107] like Figure 5 As shown, the shift register 500 includes a first control circuit 510, a second control circuit 520, a gating circuit 530, an output circuit 540, and a third control circuit 550.

[0108] In this embodiment, the first control circuit 510, the second control circuit 520, the gating circuit 530, and the output circuit 540 are similar in structure to the first control circuit 410, the second control circuit 420, the gating circuit 430, and the output circuit 440 described above, and will not be repeated for the sake of brevity.

[0109] In this embodiment of the disclosure, the third control circuit 550 includes a sixteenth transistor T16, a seventeenth transistor T17, and a second capacitor C2.

[0110] The control electrode of the sixteenth transistor T16 is connected to the third node P, the first electrode of the sixteenth transistor T16 is connected to the first power supply VGH, and the second electrode of the sixteenth transistor T16 is connected to the second node Q.

[0111] The control electrode of the seventeenth transistor T17 is electrically connected to the designated strobe terminal D0', the first electrode of the seventeenth transistor T17 is electrically connected to the third node P, and the second electrode of the seventeenth transistor T17 is electrically connected to the second power supply VGL.

[0112] The first terminal of the second capacitor C2 is electrically connected to the third node P, and the second terminal of the second capacitor C2 is electrically connected to the second node Q.

[0113] In this embodiment of the disclosure, since the gating circuit 530 includes a large number of transistors, the ability of the first power supply voltage VGH to be written into the second node Q through the first transistor T1 to the eighth transistor T8 is relatively weak. Therefore, the third control circuit 550 is added to charge the potential of the first node Q.

[0114] Under the control of the high level at the third node P, the sixteenth transistor T16 is turned on, and the first power supply voltage VGH is written to the second node Q through the sixteenth transistor T16. While being written to the third node P, the first power supply voltage VGH also charges the second capacitor C2. The high level at the third node P is maintained through the second capacitor C2.

[0115] The third control circuit 530 can enhance the write capability of the first power supply voltage VGH to the second node QB.

[0116] In this embodiment, when the strobe signal D0 is high, the seventeenth transistor T17 and the ninth transistor T9 are simultaneously turned on. The seventeenth transistor T17 discharges to the third node P, pulling down the potential of the third node P. The ninth transistor T9 discharges to the second node Q, pulling down the potential of the second node Q, thereby resetting the second node Q and the third node P.

[0117] Figure 6 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0118] like Figure 6 As shown, the shift register 600 includes a first control circuit 610, a second control circuit 620, a gating circuit 630, an output circuit 640, and a third control circuit 650.

[0119] In the embodiments of this disclosure, the second control circuit 620, the gating circuit 630, the output circuit 640 and the third control circuit 650 are structurally similar to the first control circuit 510, the gating circuit 530, the output circuit 540 and the third control circuit 550 described above, and will not be repeated for the sake of brevity.

[0120] In this embodiment of the disclosure, the first control circuit 610 includes a tenth transistor T10, an eleventh transistor T11, an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20.

[0121] The control electrode and first electrode of the tenth transistor T10 are electrically connected to the first power supply VGH, and the second electrode of the tenth transistor T10 is electrically connected to the fifth node H.

[0122] The control electrode of the eleventh transistor T11 is connected to the second node Q, the first electrode of the eleventh transistor T11 is connected to the fifth node H, and the second electrode of the eleventh transistor T11 is connected to the second power supply.

[0123] The control electrode of the eighteenth transistor T18 is electrically connected to the third node P, the first electrode of the eighteenth transistor T18 is electrically connected to the first node QB, and the second electrode of the eighteenth transistor T18 is electrically connected to the second power supply.

[0124] The control electrode of the nineteenth transistor T19 is connected to the fifth node H, the first electrode of the nineteenth transistor T19 is connected to the first power supply VGH, and the second electrode of the nineteenth transistor T19 is connected to the first node QB.

[0125] The control electrode of the twentieth transistor T20 is electrically connected to the second node Q, the first electrode of the twentieth transistor T20 is electrically connected to the first node QB, and the second electrode of the twentieth transistor T20 is electrically connected to the second power supply VGLQ.

[0126] In this embodiment of the present disclosure, when the second node Q is at a low level, under the action of the tenth transistor T10, the eleventh transistor T11, the nineteenth transistor T19, and the twentieth transistor T20, the first power supply voltage VGH continuously pulls the potential of the first node QB high, thereby providing continuous noise reduction for the shift register 600.

[0127] When the second node Q is high, the third node P is also high. Under the influence of the high level of the third node P, the eighteenth transistor T18 is turned on. The eighteenth transistor T18 can pull the potential of the first node QB low in advance, thereby turning off the twelfth transistor T12 in advance, ensuring the charging capability of the second node Q, and keeping the potential of the second node Q stably at a high level.

[0128] Figure 7 This is a schematic diagram of the structure of a driving circuit according to an embodiment of the present disclosure.

[0129] like Figure 7 As shown, the drive circuit 700 includes M shift registers. For example, M=254. Shift registers GOA1, GOA2, GOA3, ..., GOA254 can be any one of the shift registers 100, 200, 300, 500, and 600 described above.

[0130] In this embodiment of the disclosure, the m-th shift register is electrically connected to the first strobe signal line, and the (m+1)-th shift register is electrically connected to the second strobe signal line. The first strobe signal output from the first strobe signal line and the second strobe signal output from the second strobe signal line are not simultaneously active. 1 ≤ m < M, where M is a positive integer greater than 1.

[0131] For example, the first strobe signal line can be strobe signal line d0', and the second strobe signal line can be strobe signal line d0. The designated strobe terminal D0 of the first shift register is electrically connected to strobe signal line d0', and the designated strobe terminal D0 of the second shift register is electrically connected to strobe signal line d0. The strobe signals provided by strobe signal lines d0' and d0 are not simultaneously active.

[0132] For example, the timing variations of the gating signal provided by gating signal line d0' and gating signal line d0 can be referenced. Figure 4 The diagram shows the strobe signal D0' and the strobe signal D0. When the strobe signal D0' is high, the strobe signal D0 is low. When the strobe signal D0 is high, the strobe signal D0' is low.

[0133] In this embodiment of the disclosure, the driving circuit 700 further includes a first clock line clke1 and a second clock line clke2.

[0134] The first clock input CLKE1 of the m-th shift register is connected to the first clock line clke1, and the second clock input CLKE2 of the m-th shift register is connected to the second clock line clke2. The first clock input CLKE1 of the (m+1)-th shift register is connected to the second clock line clke2, and the second clock input CLKE2 of the (m+1)-th shift register is connected to the first clock line clke1.

[0135] For example, the first clock input CLKE1 of the first shift register is connected to the first clock line clke1, and the second clock input CLKE2 of the first shift register is connected to the second clock line clke2. The first clock input CLKE1 of the second shift register is connected to the second clock line clke2, and the second clock input CLKE2 of the second shift register is connected to the first clock line clke1.

[0136] The timing variations of the clock signals provided by the first clock line clk1 and the second clock line clk2 can be referenced. Figure 4 The first clock signal CLKE1 and the second clock signal CLKE12 are shown.

[0137] In this embodiment, the driving circuit 700 includes 16 gating signal lines d0~D7, d0'~d7' and 2 clock signal lines. The 16 gating signals provided by the 16 gating signal lines d0~d7, d0'~d7' can be divided into two groups of gating signals, each group including 8 gating signals. For example, gating signals d0~d7 form a positive gating group, and gating signals d0'~d7' form a negative gating group. The timing variations of the gating signals d0~d7, d0'~d7' can be referenced. Figure 4 The gating signals d0~d7 and d0'~d7' are shown.

[0138] The effective level is when the levels of the gating signal in the positive gating group and the corresponding gating signal in the negative gating group are not both simultaneously. For example, gating signal d1 and gating signal d1' are not both effective levels, and gating signal d7 and gating signal d7' are both effective levels.

[0139] The drive circuit 700 includes a shift register in which the first transistor T1 to the eighth transistor T8 are electrically connected to eight gating signal lines d0~d7 and d0'~d7', respectively. Specifically, the first transistor T1 is electrically connected to one of the gating signal lines d0 and d0', the second transistor T2 is electrically connected to one of the gating signal lines d1 and d1', the third transistor T3 is electrically connected to one of the gating signal lines d3 and d3', ..., and the eighth transistor T8 is electrically connected to one of the gating signal lines d7 and d7'.

[0140] For example, a shift register can record the strobe signal as 1 when receiving a strobe signal from a positive strobe group, and as 0 when receiving a strobe signal from a negative strobe group. The strobe signals received by D7' to D0' of shift register GOA1 are 00000001, those received by D7' to D0' of shift register GOA2 are 00000010, those received by D7' to D0' of shift register GOA3 are 00000011, ..., and those received by D7' to D0' of shift register GOA255 are 11111110.

[0141] Based on the 8 gating signals in each group, 2 8 =256 rows of pixels are selected. However, the strobe signals 00000000 and 11111111 are used to reset all the second nodes Q in the driver circuit 700. Therefore, the driver circuit 700 only outputs 254 output signals to select (256-2) rows of pixels. For example, the levels of the strobe signals d0'~d7' are all high, and all the second nodes Q in the driver circuit 700 are reset based on the strobe signals d0'~d7'.

[0142] In this embodiment of the disclosure, the first control circuit of the shift register in the driving circuit 700 can be disposed in the back panel of the display device to reduce the number of signal lines in the display device.

[0143] Figure 8 This is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0144] like Figure 8 As shown, the display device 800 includes a display panel 810 and a driving circuit 820.

[0145] In this embodiment of the disclosure, the display panel 810 includes a plurality of sub-pixel units arranged in an array, and a driving circuit is used to drive the sub-pixel units. Each row of pixel units Piexl in the display panel 810 forms a pixel row 811.

[0146] In this embodiment, the driving circuit 820 can be the driving circuit 700 described above, and will not be repeated here. A shift register 821 in the driving circuit 820 can drive a pixel row 811, thereby controlling whether a single pixel row is selected.

[0147] It should be noted that the number of subpixel units included in the display panel 810 is for illustrative purposes only, and this disclosure does not limit the number of subpixel units.

[0148] The driver circuit 820 includes multiple shift registers that support gating, each shift register being connected to sub-pixel units in a different row. When it is necessary to refresh the sub-pixel units in a certain row, the driver circuit can select the corresponding shift register to refresh the specified row of sub-pixel units.

[0149] Figure 9 This is a flowchart of a driving method according to an embodiment of the present disclosure.

[0150] like Figure 9 As shown, the driving method may include operations S910-S920.

[0151] In the embodiments of this disclosure, the driving method can be applied to the shift registers 100, 200, 300, 500 and 600 described above.

[0152] During operation S910, in the gating phase, a designated gating signal among multiple gating signals is controlled to be at the second level, while all other gating signals among the multiple gating signals except the designated gating signal are at the first level.

[0153] During operation S920, in the non-gating phase, at least one of the gating signals other than the specified gating signal is controlled to be at the second level.

[0154] In the embodiments disclosed herein, operations S910-S920 are similar to those performed by shift registers 300, 500 and 600 as described above, and will not be repeated here.

[0155] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0156] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0157] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A shift register comprising: a first control circuit configured to provide a first clock signal from a first clock terminal to a first node under control of the first clock signal or to provide a first power supply voltage of a first power supply to the first node under control of the first power supply voltage; a second control circuit configured to control a potential of a second node with a second power supply voltage of a second power supply under control of a potential of the first node; a gating circuit configured to control the potential of the second node with the first power supply voltage of a first power supply under control of a plurality of gate signals from a plurality of gate terminals; an output circuit configured to provide the second power supply voltage or a second clock signal from a second clock terminal to an output terminal as an output signal under control of the potentials of the first node and the second node, wherein the plurality of gate signals control output of the output signal; wherein the gating circuit is electrically connected with the second node, the plurality of gate terminals, the first power supply, and the second power supply, and the gating circuit is configured to: provide the second power supply voltage to the second node under control of a first level of a specified gate signal from a specified gate terminal of the plurality of gate terminals; and provide the first power supply voltage to the second node under control of a first level of the plurality of gate signals from the plurality of gate terminals other than the specified gate terminal.

2. The shift register of claim 1, further comprising: a third control circuit electrically connected with the second node, the first power supply, and a third node; the third control circuit configured to provide the first power supply voltage to the potential of the second node under control of a potential of the third node; wherein the gating circuit is configured to control the potential of the third node with the first power supply voltage under control of the plurality of gate signals. the third control circuit is further electrically connected with the specified gate terminal and the second power supply; 3. The shift register of claim 2, wherein, the third control circuit is further configured to provide the second power supply voltage to the third node under control of the first level of the specified gate signal. the second control circuit is electrically connected with the first node, the output terminal, and the second power supply; 4. The shift register of claim 1, wherein, the second control circuit is configured to provide the second power supply voltage to the first node under control of the output signal. the first control circuit is electrically connected with the first node, the second node, and the second power supply; 5. The shift register of claim 1, wherein, the first control circuit is further configured to provide the second power supply voltage to the first node under control of the second node. the first control circuit is electrically connected with the third node, the first node, and the second power supply; 6. The shift register of claim 2, wherein, the first control circuit is further configured to provide the second power supply voltage to the first node under control of the potential of the third node. the gating circuit comprises a first transistor to a ninth transistor; 7. The shift register of claim 1, wherein, wherein control electrodes of the first transistor to the ninth transistor are electrically connected to the plurality of gate terminals, and a control electrode of the ninth transistor is electrically connected to the specified gate terminal. ​ A first electrode of the first transistor is electrically connected to the first power supply, a second electrode of the first transistor is electrically connected to a first electrode of the second transistor, a second electrode of the second transistor is electrically connected to a first electrode of the third transistor, a second electrode of the third transistor is electrically connected to a first electrode of the fourth transistor, a second electrode of the fourth transistor is electrically connected to a first electrode of the fifth transistor, a second electrode of the fifth transistor is electrically connected to a first electrode of the sixth transistor, a second electrode of the sixth transistor is electrically connected to a first electrode of the seventh transistor, a second electrode of the seventh transistor is electrically connected to a first electrode of the eighth transistor, and a second electrode of the eighth transistor is electrically connected to the second node; A first electrode of the ninth transistor is electrically connected to the second node, and a second electrode of the ninth transistor is electrically connected to the second power supply.

8. The shift register of claim 1, wherein, The first control circuit includes a tenth transistor and an eleventh transistor; A control electrode and a first electrode of the tenth transistor are electrically connected to the first clock terminal, and a second electrode of the tenth transistor is electrically connected to the first node; A control electrode of the eleventh transistor is electrically connected to the second node, a first electrode of the eleventh transistor is electrically connected to the first node, and a second electrode of the eleventh transistor is electrically connected to the second power supply.

9. The shift register of claim 1, wherein, The second control circuit includes a twelfth transistor and a thirteenth transistor; A control electrode of the twelfth transistor is electrically connected to the first node, a first electrode of the twelfth transistor is electrically connected to the second node, and a second electrode of the twelfth transistor is electrically connected to the second power supply; A control electrode of the thirteenth transistor is electrically connected to the output terminal, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the second power supply.

10. The shift register of claim 1, wherein, The output circuit includes a fourteenth transistor, a fifteenth transistor, and a first capacitor; A control electrode of the fourteenth transistor is electrically connected to the second node, a first electrode of the fourteenth transistor is electrically connected to the second clock terminal, and a second electrode of the fourteenth transistor is electrically connected to the output terminal; A control electrode of the fifteenth transistor is electrically connected to the first node, a first electrode of the fifteenth transistor is electrically connected to the output terminal, and a second electrode of the fifteenth transistor is electrically connected to the second power supply; A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the output terminal.

11. The shift register of claim 2, wherein, The third control circuit includes a sixteenth transistor, a seventeenth transistor, and a second capacitor; A control electrode of the sixteenth transistor is electrically connected to the third node, a first electrode of the sixteenth transistor is electrically connected to the first power supply, and a second electrode of the sixteenth transistor is electrically connected to the second node; A control electrode of the seventeenth transistor is electrically connected to a designated gate terminal, a first electrode of the seventeenth transistor is electrically connected to the third node, and a second electrode of the seventeenth transistor is electrically connected to the second power supply; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the second node.

12. The shift register of claim 1, wherein, The first control circuit comprises a tenth transistor, an eleventh transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor; The control electrode and the first electrode of the tenth transistor are electrically connected to the first power supply, and the second electrode of the tenth transistor is electrically connected to a fifth node; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the fifth node, and the second electrode of the eleventh transistor is electrically connected to the second power supply; The control electrode of the eighteenth transistor is electrically connected to a third node, the first electrode of the eighteenth transistor is electrically connected to the first node, and the second electrode of the eighteenth transistor is electrically connected to the second power supply; The control electrode of the nineteenth transistor is electrically connected to the fifth node, the first electrode of the nineteenth transistor is electrically connected to the first power supply, and the second electrode of the nineteenth transistor is electrically connected to the first node; The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the first node, and the second electrode of the twentieth transistor is electrically connected to the second power supply.

13. A driving circuit comprising M shift registers according to any one of claims 1-12. wherein The mth shift register is electrically connected to a first gate signal line, the m+1th shift register is electrically connected to a second gate signal line, the first gate signal output by the first gate signal line and the second gate signal output by the second gate signal line are not simultaneously at an effective level, 1≤m 14. The driving circuit according to claim 13, further comprising a first clock line and a second clock line; wherein The first clock terminal of the mth shift register is connected to the first clock line, and the second clock terminal of the mth shift register is connected to the second clock line; The first clock terminal of the m+1th shift register is connected to the second clock line, and the second clock terminal of the m+1th shift register is connected to the first clock line.

15. A display device, comprising: a display panel; and the driving circuit according to claim 13 or 14; The display panel comprises M pixel rows arranged in an array, and the driving circuit comprises M shift registers for driving the M pixel rows in the display panel respectively.

16. A driving method applied to the shift register according to any one of claims 1-12, comprising: in a gate-on phase, controlling a specified gate signal in the plurality of gate signals to be at a second level, and controlling the gate signals other than the specified gate signal in the plurality of gate signals to be at a first level; in a gate-off phase, controlling at least one gate signal in the gate signals other than the specified gate signal to be at the second level.

Images