Liquid crystal pixel control circuit and control method

Abstract

This invention discloses a liquid crystal pixel control circuit and method, comprising: a threshold voltage compensation unit and a pixel unit; the threshold voltage compensation unit includes a first transistor, a second transistor, and a pre-storage capacitor; the first source-drain of the first transistor is coupled to a data signal line, the second source-drain of the first transistor is coupled to the second source-drain of the second transistor; the first gate of the first transistor is coupled to the first source-drain of the second transistor; the pixel unit includes a third transistor and a pixel capacitor, the gate of the third transistor is coupled to a transfer signal line, the second source-drain of the third transistor is coupled to one end of the pixel capacitor; the other end of the pixel capacitor is coupled to a common signal line. The beneficial effects of this invention are: it can accurately compensate the threshold voltage for each frame in real time, and it improves the aperture ratio, reduces the difficulty of pre-charging the pre-storage capacitor, and facilitates the realization of high refresh rates and high resolutions.

Description

Technical Field

[0001] This invention relates to the field of pixel display technology, and in particular to a liquid crystal pixel control circuit and control method. Background Technology

[0002] In traditional field sequential or color sequential display driving technologies, the 1T2C pixel driving circuit design requires all screen data to be written and the backlight to be turned on only after the liquid crystal has deflected to a stable state. Otherwise, screen chaos will occur. Therefore, the data writing and liquid crystal deflection time greatly compresses the backlight turn-on time, making it difficult to improve the brightness of the display, as well as the refresh rate and resolution, increase power consumption, and increase the cost of backlight materials.

[0003] Therefore, this invention proposes a liquid crystal pixel control circuit and control method to solve the problem of short light emission time in traditional color sequence display driving circuits, which leads to screen chaos; and to improve the aperture ratio and reduce the difficulty of pre-charging the pre-storage capacitor, which is beneficial to the realization of high refresh rate and high resolution. Summary of the Invention

[0004] The purpose of this invention is to propose a liquid crystal pixel control circuit and control method to solve the problems of short light emission time and abnormal image during discharge caused by threshold voltage drift in traditional color sequence display driving circuits; and to improve the aperture ratio and reduce the difficulty of pre-charging the pre-storage capacitor, which is beneficial to the realization of high refresh rate and high resolution.

[0005] The present invention aims to achieve a liquid crystal pixel control circuit through the following technical solution, comprising: a threshold voltage compensation unit and a pixel unit;

[0006] The threshold voltage compensation unit includes a first transistor, a second transistor, and a pre-storage capacitor; the first source and drain of the first transistor are coupled to a data signal line, the second source and drain of the first transistor are coupled to the second source and drain of the second transistor; the first gate of the first transistor is coupled to the first source and drain of the second transistor.

[0007] The first source and drain of the second transistor are coupled to one end of the pre-storage capacitor, and the gate of the second transistor is coupled to the Scan signal line;

[0008] The pixel unit includes a third transistor and a pixel capacitor. The first source and drain of the third transistor are coupled to the second source and drain of the first transistor and the second source and drain of the second transistor. The gate of the third transistor is coupled to a transfer signal line. The second source and drain of the third transistor are coupled to one end of the pixel capacitor. The other end of the pixel capacitor is coupled to a common signal line.

[0009] Furthermore, the pixel unit also includes a holding capacitor, one end of which is coupled to the second source-drain of the third transistor, and the other end is coupled to a common signal line.

[0010] Furthermore, the liquid crystal pixel control circuit also includes a pre-storage capacitor, the other end of which is coupled to a coupling signal line.

[0011] Furthermore, when the first transistor is a dual-gate transistor, the first gate of the first transistor is coupled to the first source and drain of the second transistor, and the second gate of the first transistor is coupled to the coupling signal line.

[0012] Furthermore, the other end of the pre-stored capacitor is coupled to a common signal line.

[0013] The present invention also proposes a liquid crystal pixel control method, comprising: a first programming stage, a second programming stage, and a discharge stage;

[0014] S1, First programming stage: By controlling the potential changes of the data signal line, coupling signal line and Scan signal line, the data signal line is pre-charged to the pre-storage capacitor in the threshold voltage compensation unit through the first transistor and the second transistor, and a preset potential is written.

[0015] S2, Second programming stage: By controlling the potential changes of the data signal line, coupling signal line and transfer signal line, the data signal line writes the reset level to the pixel capacitor and holding capacitor in the pixel unit through the first transistor and the third transistor;

[0016] S3, Discharge stage: By controlling the level changes of the data signal line and the coupling signal line, the pixel capacitor and the holding capacitor discharge to the data signal line through the first transistor and the third transistor.

[0017] Furthermore, the specific steps of the first programming stage include:

[0018] When the coupling signal line and the Scan signal line switch to a first high level, the first transistor and the second transistor are turned on.

[0019] This allows the data signal line to write a potential into the pre-storage capacitor through the first and second transistors;

[0020] When the voltage difference between the first gate and the first source and drain of the first transistor is equal to the threshold voltage Vth of the first transistor, the first transistor operates in the cutoff region. At this time, the upper plate potential of the pre-storage capacitor reaches the preset potential, that is, the upper plate potential Vx of the pre-storage capacitor is the sum of the voltage of the data signal line and the threshold voltage of the first transistor.

[0021] The coupled signal line and Scan signal line switch to a low potential.

[0022] Furthermore, the specific steps of the second programming stage include:

[0023] The coupling signal line switches to a second high level, and the first transistor is turned on;

[0024] When the transfer signal line jumps to a high level, the third transistor is turned on;

[0025] This allows the data signal line to write a reset potential into the pixel capacitor and the holding capacitor through the first transistor and the third transistor.

[0026] Furthermore, the specific steps of the discharge stage include:

[0027] The transfer signal line remains at a high level, and the third transistor remains on.

[0028] The coupling signal line switches to the first high level, keeping the upper plate potential Vx of the pre-storage capacitor at a preset potential; the data signal line switches to the third level, and the first transistor is turned on.

[0029] The pixel capacitor and the holding capacitor discharge to the data signal line through the third transistor and the first transistor;

[0030] The transfer signal line jumps to a low potential.

[0031] The present invention has the following advantages:

[0032] (1) The present invention uses a pre-storage node to write a preset level into a pre-storage capacitor; in the first programming stage, the data signal line charges the pre-storage capacitor through the first transistor and the second transistor, so that the potential Vx of the upper plate of the pre-storage capacitor reaches the preset potential (Vdata+Vth).

[0033] On the one hand, conventional threshold voltage compensation involves writing a fixed threshold voltage value to the data signal line via T-con. However, the threshold voltage value can change due to temperature or operating frequency. In contrast, this invention utilizes the cutoff characteristics of the first transistor during the charging process of the first transistor, second transistor, and pre-storage capacitor via the data signal line. This allows the pre-storage node (i.e., the upper-level board Vx node) to be written with the threshold voltage Vth regardless of whether the first transistor changes in each frame, thus achieving accurate Vth compensation. This ensures accurate discharge rate during the discharge phase, thereby resolving the issue of abnormal image quality.

[0034] On the other hand, because it adopts a non-charge-sharing method, it has lower requirements for the output voltage range of the source driver chip compared to conventional pixel driving circuits; at the same time, it reduces the requirements for the size of the pre-storage capacitor, which is conducive to improving the aperture ratio and reducing the difficulty of pre-charging the pre-storage capacitor. It is more conducive to the driving implementation of high refresh rate and high resolution display products, and has great application value.

[0035] (2) The present invention forms a reset path for the pixel electrode in the second programming stage by adjusting the level of the coupling signal line in conjunction with the on / off state of the first transistor and the third transistor, thereby realizing the reuse of transistor functions; compared with conventional pixel driving circuits, it reduces the use of one transistor and one reset signal line, thereby increasing the aperture ratio of the circuit. Attached Figure Description

[0036] Figure 1 This is a circuit diagram of the liquid crystal pixel control circuit of the present invention (Embodiment 1);

[0037] Figure 2 This is a circuit diagram of the liquid crystal pixel control circuit of the present invention (Embodiment 2);

[0038] Figure 3 This is a circuit diagram of the liquid crystal pixel control circuit of the present invention (Embodiment 3);

[0039] Figure 4 This is a timing diagram of the liquid crystal pixel control method of the present invention (Example 4);

[0040] Figure 5 This is a timing diagram of the liquid crystal pixel control method of the present invention (Example 5). Detailed Implementation

[0041] The present invention will be further described below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0042] It should be noted that the orientation or positional relationship indicated by terms such as "left" and "right" is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, or the orientation or positional relationship in which those skilled in the art would conventionally understand it. Such terms are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0043] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other. Example

[0044] like Figure 1As shown, the liquid crystal pixel control circuit proposed in this embodiment includes a threshold voltage compensation unit and a pixel unit.

[0045] The threshold voltage compensation unit includes a first transistor T1, a second transistor T2, and a pre-storage capacitor Cs1; the first source and drain of the first transistor T1 are coupled to the data signal line (Data), and the second source and drain of the first transistor T1 are coupled to the second source and drain of the second transistor T2; the first gate of the first transistor T1 is coupled to the first source and drain of the second transistor T2; the other end of the pre-storage capacitor Cs1 is coupled to the coupling signal line (Couple).

[0046] The first source and drain of the second transistor T2 are coupled to one end of the pre-storage capacitor Cs1, and the gate of the second transistor T2 is coupled to the Scan signal line.

[0047] The pixel unit includes a third transistor T3, a pixel capacitor Clc, and a holding capacitor Cs2. The first source and drain of the third transistor T3 are coupled to the second source and drain of the first transistor T1 and the second source and drain of the second transistor T2. The gate of the third transistor T3 is coupled to the transfer signal line (Tran), and the second source and drain of the third transistor T3 are coupled to one end of the pixel capacitor Clc. The other end of the pixel capacitor Clc is coupled to the common signal line (Com). One end of the holding capacitor Cs2 is coupled to the second source and drain of the third transistor T3, and the other end is coupled to the common signal line (Com).

[0048] During operation, it is divided into three stages: the first programming stage, the second programming stage, and the discharge stage;

[0049] S1, First programming stage: The Couple signal line and Scan signal line switch to the first high level. In some specific embodiments, the first high level is the turn-on voltage Vgh of the first transistor T1, and the first transistor T1 and the second transistor T2 are turned on synchronously.

[0050] When the coupling signal line (Couple) switches to the first high level, the potential of the upper plate of the pre-storage capacitor Cs1 is raised through the pre-storage capacitor Cs1. The first gate of the first transistor T1 is at the same potential as the upper plate of the pre-storage capacitor Cs1. The potential of the first gate of the first transistor T1 becomes high, thereby turning on the first transistor T1.

[0051] This causes the data signal line (Data) to write a potential into the pre-storage capacitor Cs1 through the first transistor T1 and the second transistor T2;

[0052] When the voltage difference between the first gate and the first source-drain of the first transistor T1 is equal to the threshold voltage Vth of the first transistor T1, the first transistor T1 operates in the cutoff region. At this time, the upper plate potential Vx of the pre-storage capacitor Cs1 is the sum of the voltage of the data signal line (Data) and the threshold voltage of the first transistor T1. After the pre-storage capacitor Cs1 is pre-charged, the coupling signal line (Couple) and the Scan signal line jump to a low potential.

[0053] S2, Second Programming Stage: By controlling the potential changes of the data signal line (Data), the coupling signal line (Couple), and the transfer signal line (Tran), the data signal line (Data) writes a reset level to the pixel capacitor Clc and the holding capacitor Cs2 in the pixel unit through the first transistor T1 and the third transistor T3;

[0054] When the coupling signal line (Couple) transitions to a second high level, which is greater than the first high level, the first transistor T1 is turned on and remains on. In some specific embodiments, the second high level is twice the turn-on voltage of the first transistor T1, i.e., 2*Vgh.

[0055] When the transfer signal line (Tran) jumps to a high level, the third transistor T3 is turned on; this causes the data signal line (Data) to write a reset level to the pixel capacitor Clc and the holding capacitor Cs2 through the first transistor T1 and the third transistor T3, so that the pixel node potential is written to Vpixel=Vdata+Vcom, or the pixel node potential is written to Vpixel=Vcom; Vcom is the potential of the common signal line.

[0056] S3, Discharge stage: By controlling the level changes of the data signal line (Data) and the coupling signal line (Couple), the pixel capacitor Clc and the holding capacitor Cs2 are discharged to the data signal line (Data) through the first transistor T1 and the third transistor T3.

[0057] The transfer signal line remains high, and the third transistor T3 remains on.

[0058] The coupling signal line (Couple) switches to the first high level (from 2*Vgh to Vgh), keeping the upper plate potential Vx of the pre-storage capacitor Cs1 at the preset potential; the data signal line (Data signal line) switches to the third level, and the first transistor T1 is turned on;

[0059] When the pixel node potential is written as Vpixel = Vdata + Vcom, the third level is the level of the common signal line Vcom, and the data signal line (Data) Vdata jumps to the potential of the common signal line (Com) Vcom.

[0060] When the pixel node potential is written as Vpixel=Vcom, the third level is Vcom-Vop_max, and the level of the data signal line (Data) Vdata is restored to Vcom-Vop_max. Vop_max is the potential of the data signal line (Data) when the maximum gray level is written.

[0061] The pixel capacitor Clc and the holding capacitor Cs2 discharge to the data signal line (Data) through the third transistor T3 and the first transistor T1; the discharge at this time satisfies the following formula:

[0062] ;

[0063] In the formula:

[0064] Pixel voltage;

[0065] Discharge time;

[0066] : This refers to the discharge characteristic time of the pixel capacitor and the holding capacitor; (discharge time);

[0067] The formula for calculating the characteristic discharge time is as follows:

[0068] ;

[0069] In the formula:

[0070] Req: Equivalent impedance of the first transistor T1;

[0071] The formula for calculating the equivalent impedance of the first transistor T1 is as follows:

[0072]

[0073] In the formula

[0074] : Channel length of the first transistor T1;

[0075] The channel bandwidth of the first transistor T1;

[0076] Electron mobility;

[0077] : Gate dielectric layer capacitance per unit area of ​​the first transistor T1;

[0078] The first gate voltage of the first transistor T1;

[0079] The threshold voltage of the first transistor T1;

[0080] When the first gate of the first transistor T1 is written with Vdata+Vth, that is... Therefore, the following formula can be further derived:

[0081] ;

[0082] Therefore, the pixel voltage after discharge can be calculated as follows:

[0083] ;

[0084] After the discharge is complete, the transfer signal line (Tran) jumps to a low level;

[0085] Therefore, by effectively removing the threshold voltage Vth of the first transistor T1 during the calculation, the Vth unevenness caused by process deviation and the change of Vth over time can be effectively avoided.

[0086] The beneficial effects of this embodiment are as follows: by using a pre-stored node to write a preset level into the pre-stored capacitor Cs1; in the first programming stage; on the one hand, due to the pre-writing of the pre-stored node level, the discharge impedance drift during the discharge stage is reduced, which can eliminate the threshold voltage unevenness caused by transistor process deviations during the discharge stage, as well as the influence caused by the change of threshold voltage over time; on the other hand, because a non-charge-sharing method is adopted, the output voltage range requirement of the source driver chip is lower compared to conventional pixel driving circuits; at the same time, the requirement for the size of the pre-stored capacitor Cs1 is reduced, which is conducive to improving the aperture ratio and reducing the pre-charging difficulty of the pre-stored capacitor Cs1, which is more conducive to the driving implementation of high refresh rate and high resolution display products, and has great application value. Example

[0087] See Figure 2 In some specific embodiments, the liquid crystal pixel control circuit further includes a fourth transistor T4;

[0088] The liquid crystal pixel control circuit includes: a threshold voltage compensation unit and a pixel unit;

[0089] The threshold voltage compensation unit includes a first transistor T1, a second transistor T2, a fourth transistor T4, and a pre-storage capacitor Cs1; the first source and drain of the first transistor T1 are coupled to the data signal line (Data), and the second source and drain of the first transistor T1 are coupled to the second source and drain of the second transistor T2;

[0090] The first source-drain of the fourth transistor T4 is coupled to the turn-on signal line (Vgh, which is constantly input to the turn-on voltage Vgh of the first transistor T1), and the gate of the fourth transistor T4 is coupled to the second transfer signal line (Tran2). The second source-drain of the fourth transistor T4 is coupled to the first gate of the first transistor T1, the first source-drain of the second transistor T2, and one end of the pre-storage capacitor Cs1. The other end of the pre-storage capacitor Cs1 is coupled to the coupling signal line (Couple).

[0091] The pixel unit includes a third transistor T3, a pixel capacitor Clc, and a holding capacitor Cs2. The first source and drain of the third transistor T3 are coupled to the second source and drain of the first transistor T1 and the second source and drain of the second transistor T2. The gate of the third transistor T3 is coupled to the first transfer signal line (Tran1), and the second source and drain of the third transistor T3 are coupled to one end of the pixel capacitor Clc. The other end of the pixel capacitor Clc is coupled to the common signal line (Com). One end of the holding capacitor Cs2 is coupled to the second source and drain of the third transistor T3, and the other end is coupled to the common signal line (Com).

[0092] In this embodiment, the coupling signal line (Couple) does not change during the first programming stage, but directly changes to the second high level during the second programming stage. In the first programming stage, the second transfer signal line (Tran2) changes to a high level, the fourth transistor T4 is turned on, and the enable signal line (Vgh) writes Vgh to the Vx node of the pre-storage capacitor Cs1 in advance, thereby turning on the first transistor T1, the second transfer signal line (Tran2) changes to a low level, and the fourth transistor T4 is turned off. Then the Scan signal line changes to a first high level, the second transistor T2 is turned on, and the data signal line (Data) writes a preset level to the pre-storage capacitor Cs1 through the first transistor T1 and the second transistor T2.

[0093] By setting a fourth transistor T4, the driving difficulty in the liquid crystal pixel control circuit can be reduced, and the coupling signal line no longer needs to go through complex switching to accurately compensate for the threshold voltage in the liquid crystal pixel control circuit. Example

[0094] See Figure 3 When the first transistor T1 is a dual-gate transistor, this embodiment proposes a liquid crystal pixel control circuit, which includes: a threshold voltage compensation unit and a pixel unit; the threshold voltage compensation unit includes a first transistor T1, a second transistor T2 and a pre-storage capacitor Cs1; the first source and drain of the first transistor T1 are coupled to the data signal line (Data), and the second source and drain of the first transistor T1 are coupled to the second source and drain of the second transistor T2;

[0095] When the first transistor T1 is a dual-gate transistor, the first gate of the first transistor T1 is coupled to the first source and drain of the second transistor T2, and the second gate of the first transistor T1 is coupled to the coupled signal line (Couple); the other end of the pre-storage capacitor Cs1 is coupled to the common signal line (Com).

[0096] The pixel unit includes a third transistor T3, a pixel capacitor Clc, and a holding capacitor Cs2. The first source and drain of the third transistor T3 are coupled to the second source and drain of the first transistor T1 and the second source and drain of the second transistor T2. The gate of the third transistor T3 is coupled to the transfer signal line (Tran), and the second source and drain of the third transistor T3 are coupled to one end of the pixel capacitor Clc. The other end of the pixel capacitor Clc is coupled to the common signal line (Com). One end of the holding capacitor Cs2 is coupled to the second source and drain of the third transistor T3, and the other end is coupled to the common signal line (Com).

[0097] The beneficial effect of this embodiment is that by setting the first transistor T1 as a dual-gate transistor and coupling the second gate of the first transistor T1 to the coupling signal line (Couple), the on and off of the first transistor T1 can be directly controlled through the coupling signal line (Couple). Compared with Embodiment 1 and Embodiment 2, the capacitance requirement of the pre-storage capacitor Cs1 is reduced again, thereby increasing the aperture ratio of the circuit and reducing the difficulty of pre-charging the pre-storage capacitor Cs1. Example

[0098] See Figure 4 The present invention also provides a liquid crystal pixel control method, comprising:

[0099] S1. In the first programming stage, by controlling the potential changes of the data signal line (Data), the coupling signal line (Couple), and the Scan signal line, the data signal line (Data) writes a preset potential to the pre-storage capacitor Cs1 in the threshold voltage compensation unit through the first transistor T1 and the second transistor T2;

[0100] When the Scan signal line jumps to the first high level, the second transistor T2 is turned on;

[0101] The coupling signal line transitions to a first high level, which in some specific embodiments is the turn-on voltage Vgh of the first transistor T1;

[0102] When the coupling signal line (Couple) switches to the first high level, the potential of the upper plate of the pre-storage capacitor Cs1 is raised through the pre-storage capacitor Cs1. The first gate of the first transistor T1 is at the same potential as the upper plate of the pre-storage capacitor Cs1. The potential of the first gate of the first transistor T1 becomes high, thereby turning on the first transistor T1.

[0103] This causes the data signal line (Data) to write a potential into the pre-storage capacitor Cs1 through the first transistor T1 and the second transistor T2;

[0104] When the voltage difference between the first gate and the first source and drain of the first transistor T1 is equal to the threshold voltage Vth of the first transistor T1, the first transistor T1 operates in the cutoff region. At this time, the upper plate potential of the pre-storage capacitor Cs1 reaches the preset potential, that is, the upper plate potential Vx of the pre-storage capacitor Cs1 is the sum of the voltage of the data signal line (Data) and the threshold voltage of the first transistor T1.

[0105] The formula for calculating the preset potential Vx is as follows:

[0106] ;

[0107] In the formula:

[0108] ; Voltage input to the data signal line;

[0109] The threshold voltage of the first transistor T1;

[0110] After the pre-storage capacitor Cs1 has been pre-charged, the Couple signal line and Scan signal line jump to a low potential;

[0111] S2, Second Programming Stage: By controlling the potential changes of the data signal line (Data), the coupling signal line (Couple), and the transfer signal line (Tran), the data signal line (Data) writes a reset level to the pixel capacitor Clc and the holding capacitor Cs2 in the pixel unit through the first transistor T1 and the third transistor T3;

[0112] When the coupling signal line (Couple) transitions to a second high level, the first transistor T1 is fully turned on; in some specific embodiments, the second high level is twice the turn-on voltage of the first transistor T1, i.e., 2*Vgh, so that the first transistor T1 is fully turned on.

[0113] When the transfer signal line (Tran) goes high, the third transistor (T3) turns on;

[0114] This causes the data signal line (Data) to write a reset potential into the pixel capacitor Clc and the holding capacitor Cs2 through the first transistor T1 and the third transistor T3.

[0115] When the pixel control circuit is in a positive frame, the pixel node potential Vpixel is written as Vpixel = Vop_max + Vcom, where Vop_max is the voltage value of the data signal line (Data) at the maximum gray level.

[0116] When the pixel control circuit is in a negative frame, the pixel node potential Vpixel is written to Vpixel=Vcom, where Vcom is the potential of the common signal line.

[0117] S3. By controlling the level changes of the data signal line (Data) and the coupling signal line (Couple), the pixel capacitor Clc and the holding capacitor Cs2 are discharged to the data signal line (Data signal line) through the first transistor T1 and the third transistor T3.

[0118] The transfer signal line (Tran) remains high, and the third transistor T3 remains on.

[0119] The coupling signal line (Couple) switches to the first high level, keeping the upper plate potential Vx of the pre-storage capacitor Cs1 at the preset potential; the data signal line (Data) switches to the third level, and the first transistor T1 is turned on;

[0120] When the pixel node potential is written as Vpixel = Vdata + Vcom, the third level is the level Vcom of the common signal line (Com), and the data signal line (Data) Vdata jumps to the potential Vcom of the common signal line (Com).

[0121] When the pixel node potential is written as Vpixel=Vcom, the third level is Vcom-Vop_max, and the level Vdata of the data signal line (Data signal line) is restored to Vcom-Vop_max;

[0122] The pixel capacitor (Clc) and the holding capacitor (Cs2) discharge to the data signal line (Data) through the third transistor (T3) and the first transistor (T1); the discharge at this time satisfies the following formula:

[0123] ;

[0124] In the formula

[0125] Pixel voltage;

[0126] Pixel reset voltage;

[0127] Discharge time;

[0128] : The discharge characteristic time of the pixel capacitor and the holding capacitor; (discharge time);

[0129] The formula for calculating the characteristic discharge time is as follows:

[0130] ;

[0131] In the formula:

[0132] Req: Equivalent impedance of the first transistor T1;

[0133] The formula for calculating the equivalent impedance of the first transistor T1 is as follows:

[0134]

[0135] In the formula

[0136] : Channel length of the first transistor T1;

[0137] The channel bandwidth of the first transistor T1;

[0138] Electron mobility;

[0139] : Gate dielectric layer capacitance per unit area of ​​the first transistor T1;

[0140] The first gate voltage of the first transistor T1;

[0141] The threshold voltage of the first transistor T1;

[0142] When the first gate of the first transistor T1 is written with Vdata+Vth, that is... Therefore, the following formula can be further derived:

[0143] ;

[0144] Therefore, the pixel voltage after discharge can be calculated as follows:

[0145] ;

[0146] Therefore, by effectively removing the threshold voltage Vth of the first transistor T1 during the calculation, the unevenness of Vth caused by process deviations during panel manufacturing, as well as the change of Vth over time, can be effectively avoided.

[0147] After the discharge is complete, the transfer signal line (Tran) jumps to a low level. Example

[0148] When the liquid crystal pixel control circuit also includes a fourth transistor T4, see [reference needed]. Figure 5 The present invention also provides a liquid crystal pixel control method, comprising:

[0149] S1, First programming stage: By controlling the potential changes of the data signal line (Data), the second transfer signal line (Tran2) and the Scan signal line, the data signal line (Data) writes a preset potential to the pre-storage capacitor Cs1 in the threshold voltage compensation unit through the first transistor T1 and the second transistor T2;

[0150] The second transfer signal line (Tran2) first jumps to a high level, and the fourth transistor T4 is turned on; the turn-on signal line (Vgh) first writes the turn-on voltage value Vgh of the first transistor T1 into the first gate of the first transistor T1 and the pre-storage capacitor Cs1; the second transfer signal line (Tran2) jumps to a low level, and the fourth transistor T4 is turned off.

[0151] Then the Scan signal line jumps to the first high level, and the second transistor T2 turns on;

[0152] This causes the data signal line (Data) to write a potential into the pre-storage capacitor Cs1 through the first transistor T1 and the second transistor T2;

[0153] When the voltage difference between the first gate and the first source and drain of the first transistor T1 is equal to the threshold voltage Vth of the first transistor T1, the first transistor T1 operates in the cutoff region. At this time, the upper plate potential of the pre-storage capacitor Cs1 reaches the preset potential, that is, the upper plate potential Vx of the pre-storage capacitor Cs1 is the sum of the voltage of the data signal line (Data) and the threshold voltage of the first transistor T1.

[0154] The Scan signal line jumps to a low level.

[0155] S2, Second programming stage: By controlling the potential changes of the data signal line (Data), the coupling signal line (Couple) and the first transfer signal line (Tran1), the data signal line (Data signal line) writes the reset level to the pixel capacitor Clc and the holding capacitor Cs2 in the pixel unit through the first transistor T1 and the third transistor T3;

[0156] When the coupling signal line (Couple) switches to a second high level, the first transistor T1 is turned on;

[0157] When the transfer signal line (Tran) goes high, the third transistor T3 is turned on;

[0158] This causes the data signal line (Data) to write a reset potential into the pixel capacitor Clc and the holding capacitor Cs2 through the first transistor T1 and the third transistor T3.

[0159] S3, Discharge stage: By controlling the level changes of the data signal line (Data) and the coupling signal line (Couple), the pixel capacitor Clc and the holding capacitor Cs2 are discharged to the data signal line (Data) through the first transistor T1 and the third transistor T3.

[0160] The first transfer signal line (Tran1) remains high, and the third transistor (T3) remains on;

[0161] The coupling signal line (Couple) switches to the first high level, keeping the upper plate potential Vx of the pre-storage capacitor Cs1 at the preset potential; the data signal line (Data) switches to the third level, and the first transistor T1 is turned on;

[0162] The pixel capacitor Clc and the holding capacitor Cs2 discharge to the data signal line (Data) through the third transistor T3 and the first transistor T1;

[0163] The first transfer signal line (Tran1) jumps to a low potential.

[0164] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from this invention, and these all fall within the protection scope of this invention.

Claims

1. A liquid crystal pixel control circuit, characterized in that: include: Threshold voltage compensation unit and pixel unit; The threshold voltage compensation unit includes a first transistor (T1), a second transistor (T2), and a pre-storage capacitor (Cs1); the first source and drain of the first transistor (T1) are coupled to the data signal line (Data), and the second source and drain of the first transistor (T1) are coupled to the second source and drain of the second transistor (T2); The first gate of the first transistor (T1) is coupled to the first source and drain of the second transistor (T2); The first source and drain of the second transistor (T2) are coupled to one end of the pre-storage capacitor (Cs1), and the gate of the second transistor (T2) is coupled to the Scan signal line; The liquid crystal pixel control circuit also includes a pre-storage capacitor (Cs1) whose other end is coupled to a coupling signal line (Couple). In the first programming stage, by controlling the potential changes of the data signal line (Data), the coupling signal line (Couple), and the Scan signal line, the data signal line (Data) writes a preset potential to the pre-storage capacitor (Cs1) in the threshold voltage compensation unit through the first transistor (T1) and the second transistor (T2). The preset potential, namely the upper plate potential Vx of the pre-storage capacitor (Cs1), is the sum of the voltage of the data signal line (Data) and the threshold voltage of the first transistor (T1). The pixel unit includes a third transistor (T3) and a pixel capacitor (Clc). The first source and drain of the third transistor (T3) are coupled to the second source and drain of the first transistor (T1) and the second source and drain of the second transistor (T2). The gate of the third transistor (T3) is coupled to the transfer signal line (Tran). The second source and drain of the third transistor (T3) are coupled to one end of the pixel capacitor (Clc). The other end of the pixel capacitor (Clc) is coupled to the common signal line (Com).

2. The liquid crystal pixel control circuit according to claim 1, characterized in that: The pixel unit also includes a holding capacitor (Cs2), one end of which is coupled to the second source-drain of the third transistor (T3), and the other end is coupled to the common signal line (Com).

3. A liquid crystal pixel control circuit according to claim 1 or 2, characterized in that: When the first transistor (T1) is a dual-gate transistor, the first gate of the first transistor (T1) is coupled to the first source and drain of the second transistor (T2), and the second gate of the first transistor (T1) is coupled to the coupling signal line (Couple).

4. A liquid crystal pixel control circuit according to claim 3, characterized in that... Replace the other end of the pre-stored capacitor (Cs1) with the common signal line (Com) by coupling the other end of the pre-stored capacitor (Cs1) to the coupled signal line (Couple).

5. A liquid crystal pixel control method, applied to the liquid crystal pixel control circuit of any one of claims 1 to 4, characterized in that, include: First programming stage: By controlling the potential changes of the data signal line (Data), the coupling signal line (Couple), and the Scan signal line, the data signal line (Data) writes a preset potential to the pre-storage capacitor (Cs1) in the threshold voltage compensation unit through the first transistor (T1) and the second transistor (T2). The specific steps of the first programming stage include: When the Couple signal line and Scan signal line switch to a first high level, the first transistor (T1) and the second transistor (T2) are turned on; This causes the data signal line (Data) to write a potential into the pre-storage capacitor (Cs1) through the first transistor (T1) and the second transistor (T2); When the voltage difference between the first gate and the first source and drain of the first transistor (T1) is equal to the threshold voltage Vth of the first transistor (T1), the first transistor (T1) operates in the cutoff region. At this time, the upper plate potential of the pre-storage capacitor (Cs1) reaches the preset potential, that is, the upper plate potential Vx of the pre-storage capacitor (Cs1) is the sum of the voltage of the data signal line (Data) and the threshold voltage of the first transistor (T1). The Couple and Scan signal lines switch to low potentials; Second programming stage: By controlling the potential changes of the data signal line (Data), the coupling signal line (Couple), and the transfer signal line (Tran), the data signal line (Data) writes a reset level to the pixel capacitor (Clc) and the holding capacitor (Cs2) in the pixel unit through the first transistor (T1) and the third transistor (T3); Discharge phase: By controlling the level changes of the data signal line (Data) and the coupling signal line (Couple), the pixel capacitor (Clc) and the holding capacitor (Cs2) are discharged to the data signal line (Data) through the first transistor (T1) and the third transistor (T3).

6. A liquid crystal pixel control method according to claim 5, characterized in that: The specific steps of the second programming stage include: When the coupling signal line (Couple) switches to a second high level, the first transistor (T1) turns on; When the transfer signal line (Tran) goes high, the third transistor (T3) turns on; This causes the data signal line (Data) to write a reset potential into the pixel capacitor (Clc) and the holding capacitor (Cs2) through the first transistor (T1) and the third transistor (T3).

7. A liquid crystal pixel control method according to claim 5, characterized in that: The specific steps of the discharge stage include: The transfer signal line (Tran) remains high, and the third transistor (T3) remains on. The coupling signal line (Couple) switches to a first high level, the data signal line (Data) switches to a third level, and the first transistor (T1) is turned on; The pixel capacitor (Clc) and the holding capacitor (Cs2) discharge to the data signal line (Data) through the third transistor (T3) and the first transistor (T1); The transfer signal line (Tran) jumps to a low potential.

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