FPGA-based shared multi-layer video processing system and method

Abstract

The present invention belongs to the field of professional audio-visual, and specifically relates to a shared multi-layer video processing system and method based on FPGA, which aims to solve the problem that the existing output channel increases layers, resulting in a reduction in the number of output channels or replacement of chips, and an increase in the occupancy rate of the backplane channel. The present invention includes: a backplane channel for parsing data; a video data receiving and processing module for extracting the video data stream and then reducing it; a shared layer processing module for performing window processing based on the first video and calculating the upper and lower order relationship of the layers in the video; and calculating the storage address of the current pixel point in the external storage unit to read the first video; using FPGA to amplify the read first video; an output channel processing module for receiving the amplified first video and adapting to different types of output interfaces. The present invention changes the number of layers of each output channel in a shared layer manner to meet the needs of multi-layer display.

Description

Background Art

[0002] As users' demands for multi-layer display continue to increase, from single screen to multi-screen, single layer to multi-layer, existing technical solutions generally adopt independent layer allocation, and the number of layers of a single output channel is fixed. To increase the number of layers, it is necessary to reduce the number of output channels or replace chips with more abundant resources. Hardware upgrades will also lead to increased costs. In addition, in the existing multi-channel multi-layer output solution, one backplane channel transmits one signal source, and the backplane channel and the output channel layer relationship are bound one by one. If a certain output channel needs to display the video signal source of other backplane channels, the signal source of other backplane channels needs to be connected to the backplane channel corresponding to the output channel at the same time, which will occupy more backplane channels and increase the backplane channel occupancy rate.

[0003] Therefore, in the prior art, adding layers to the output channels will result in a reduction in the number of output channels or replacement of chips with richer resources, as well as an increase in the occupancy rate of the backplane channels. Summary of the invention

[0004] In order to solve the above-mentioned problem in the prior art, that is, in the prior art, adding layers to the output channel will lead to a reduction in the number of output channels or replacement of chips with richer resources, and an increase in the occupancy rate of the backplane channels, the present invention provides a shared multi-layer video processing system based on FPGA, the system comprising:

[0005] The backplane channel is used to receive data from the signal source, parse the data from the signal source based on the protocol to obtain a video data stream, and then transmit the video data stream to the video data receiving and processing module;

[0006] A video data receiving and processing module, used for extracting video data based on the video data stream and then reducing it to obtain a first video;

[0007] A shared layer processing module is used to receive the first video, perform windowing processing based on the first video to obtain windowing information and calculate the up-down sequence relationship of the layers in the video; then calculate the storage address of the current pixel point in the external storage unit based on the up-down sequence relationship of the layers and the windowing information to read the first video; use the parallel processing capability of the FPGA to amplify the read first video and send it to the output channel processing module;

[0008] The output channel processing module is used to receive the first video after amplification processing and send it to the display screen.

[0009] In a preferred embodiment, the number of the backplane channels is one or more, wherein each backplane channel is connected to only one signal source.

[0010] In a preferred embodiment, the number of the video data receiving and processing modules is one or more; each video data receiving and processing module receives video data streams of one or more backplane channels; and each backplane channel sends video data streams to only one video data receiving and processing module.

[0011] In a preferred embodiment, the number of the shared layer processing modules is one or more; each shared layer processing module receives the first video generated by all video data receiving processing modules.

[0012] In a preferred embodiment, the method in which the shared layer processing module calculates the upper and lower order relationship of the layers in the first video is:

[0013] Assume that the maximum number of layers is N, and compare each layer pairwise. There are a total of (N×(N-1) / 2) comparison results.

[0014] The comparison result is expressed as: RZ[((N×(N-1) / 2-1):0];

[0015] Among them, N is the maximum number of layers, and RZ represents the layer comparison result.

[0016] In a preferred implementation, the shared layer processing module reading the first video specifically includes:

[0017] The shared layer processing module determines the layer information assigned to the current output channel processing module and the output video data resolution information of the current output channel processing module according to the external instruction;

[0018] Based on the assigned layer information and the output video data resolution information, according to the upper and lower order relationship of the layers and the layer windowing information, the storage address of the current pixel in the external storage unit is calculated and a read data request is generated; based on the read data request, the first video is read, and then the read first video is cached in the local storage unit.

[0019] In a preferred implementation, the shared layer processing module reading the first video further includes:

[0020] If there is only one layer, data is read from the external storage unit once; if there are multiple layers, the shared layer processing module needs to read the data of the new layer once each time it enters a new layer.

[0021] In a preferred embodiment, the shared layer processing module uses the parallel processing capability of the FPGA to amplify the read first video and then sends it to the output channel processing module, including:

[0022] The shared layer processing module reads the first video from the local storage unit according to the window opening information of the layer and the magnification coefficient of each layer; based on the magnification coefficient of each layer, the first video is magnified using the parallel processing capability of the FPGA, and the amplified first video is output to the output channel processing module according to the standard VESA video timing.

[0023] A second aspect of the present invention provides a shared multi-layer video processing method based on FPGA, the method comprising:

[0024] The backplane channel receives the data from the signal source and parses the data from the signal source based on the protocol to obtain a video data stream, and then transmits the video data stream to the video data receiving and processing module;

[0025] The video data receiving and processing module extracts the video data from the video data stream and then reduces the video data to obtain a first video, and then sends the first video to the shared layer processing module;

[0026] The shared layer processing module receives the first video, performs window processing based on the first video to obtain window information and calculates the up-down sequence relationship of the layers in the video; then calculates the storage address of the current pixel point in the external storage unit based on the up-down sequence relationship of the layers and the window information to read the first video; uses the parallel processing capability of the FPGA to amplify the read first video and then sends it to the output channel processing module;

[0027] The output channel processing module receives the first video after amplification processing and sends it to the display screen.

[0028] The third aspect of the present invention proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned FPGA-based shared multi-layer video processing method.

[0029] Beneficial effects of the present invention:

[0030] (1) The present invention proposes a system for sharing multiple layers based on FPGA. Without changing the existing hardware equipment, the total number of output channels and chip resources, by adding a shared layer processing module, the number of layers of each output channel is changed in a shared layer manner, which not only meets the needs of multi-layer display, but also reduces the occupancy rate of the backplane transmission channel;

[0031] (2) In the existing audio and video system hardware environment, the present invention can dynamically allocate the number of output layers by upgrading the FPGA firmware and software, thereby functionally increasing the maximum number of layers per channel and meeting more layer demand scenarios;

[0032] (3) The present invention realizes the demand for multi-layer display without changing the existing hardware equipment, the total number of output channels and chip resources, thereby increasing the competitiveness of the product and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0034] Figure 1 is a schematic diagram of a shared multi-layer video processing system based on FPGA according to an embodiment of the present invention;

[0035] Figure 2 is a schematic diagram of a 4-channel 2-layer processing system according to an embodiment of the present invention;

[0036] Figure 3 is a schematic diagram of a 4-channel shared multi-layer video processing system based on FPGA according to an embodiment of the present invention;

[0037] Figure 4 is a schematic diagram of a 4-channel 2-layer processing system connected to a signal source according to an embodiment of the present invention;

[0038] Figure 5 It is a schematic diagram of a 4-channel shared multi-layer video processing system based on FPGA connected to a signal source according to an embodiment of the present invention;

[0039] Figure 6 It is a schematic diagram of a shared layer processing module in an embodiment of the present invention processing N layer windowing;

[0040] Figure 7 It is a structural diagram of a computer system of a server for implementing the method, system, and device embodiments of the present application. DETAILED DESCRIPTION

[0041] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0043] The present invention provides a shared multi-layer video processing system based on FPGA, the system comprising:

[0044] The backplane channel is used to receive data from the signal source, parse the data from the signal source based on the protocol to obtain a video data stream, and then transmit the video data stream to the video data receiving and processing module;

[0045] A video data receiving and processing module, used for extracting video data from the video data stream and then reducing it to obtain a first video;

[0046] A shared layer processing module is used to receive the first video, perform windowing processing based on the first video to obtain windowing information and calculate the up-down sequence relationship of the layers in the video; then calculate the storage address of the current pixel point in the external storage unit based on the up-down sequence relationship of the layers and the windowing information to read the first video; use the parallel processing capability of the FPGA to amplify the read first video and send it to the output channel processing module;

[0047] The output channel processing module is used to receive the first video after amplification processing and send it to the display screen.

[0048] In order to more clearly explain the FPGA-based shared multi-layer video processing system of the present invention, Figure 1 Each module in the embodiment of the present invention is described in detail.

[0049] The shared multi-layer video processing system based on FPGA of the first embodiment of the present invention, each module is described in detail as follows:

[0050] The backplane channel is used to receive data from the signal source, parse the data from the signal source based on the protocol to obtain a video data stream, and then transmit the video data stream to the video data receiving and processing module;

[0051] In this embodiment, the number of backplane channels may include one or more, wherein each backplane channel is connected to only one signal source;

[0052] A video data receiving and processing module, used for extracting video data from the video data stream and then reducing it to obtain a first video;

[0053] In this embodiment, the number of the shared layer processing modules and the number of the video data receiving processing modules are not fixed; the number of the video data receiving processing modules is one or more; each video data receiving processing module receives the video data stream of one or more backplane channels; each backplane channel sends the video data stream to only one video data receiving processing module.

[0054] In this embodiment, the obtained first video may be a video obtained by extracting the video data stream and reducing it, or may be a video obtained by only extracting the video data stream without reducing it.

[0055] A shared layer processing module is used to receive the first video, perform windowing processing based on the first video to obtain windowing information and calculate the up-down sequence relationship of the layers in the video; then calculate the storage address of the current pixel point in the external storage unit based on the up-down sequence relationship of the layers and the windowing information to read the first video; use the parallel processing capability of the FPGA to amplify the read first video and send it to the output channel processing module;

[0056] In this embodiment, the number of the shared layer processing modules is one or more; each shared layer processing module receives the first video generated by all video data receiving processing modules.

[0057] In this embodiment, the method for the shared layer processing module to calculate the upper and lower order relationship of the layers in the first video is: set the maximum number of layers to N, compare each layer two by two, and there are a total of (N×(N-1) / 2) comparison results; the comparison result is expressed as: RZ[((N×(N-1) / 2-1):0]; where N is the maximum number of layers, and RZ represents the layer comparison result.

[0058] In this embodiment, the shared layer processing module reads the first video specifically including: the shared layer processing module determines the layer information assigned to the current output channel processing module and the output video data resolution information of the current output channel processing module according to external instructions; based on the assigned layer information and the output video data resolution information, according to the upper and lower order relationship of the layers and the layer windowing information, calculates the storage address of the current pixel in the external storage unit and generates a read data request; based on the read data request, reads the first video, and then caches the read first video to the local storage unit.

[0059] In this embodiment, the shared layer processing module reads the first video and further includes: if there is only one layer, reading data from the external storage unit once; if there are multiple layers currently, the shared layer processing module needs to read the data of the new layer once each time entering a new layer.

[0060] In this embodiment, the shared layer processing module uses the parallel processing capability of the FPGA to amplify the read first video and then sends it to the output channel processing module, including: the shared layer processing module reads the first video from the local storage unit according to the window information of the layer and the magnification coefficient of each layer; based on the magnification coefficient of each layer, the first video is amplified by the parallel processing capability of the FPGA, and the amplified first video is output to the output channel processing module according to the standard VESA video timing.

[0061] The FPGA-based shared multi-layer video processing system of the present invention also includes a parameter configuration module, which is specifically used to receive relevant parameters configured by the user and then send them to the shared layer module for use. The parameter configuration module plays an auxiliary role in the shared layer processing module. Both the layer information and the window opening information are realized through the parameter configuration module.

[0062] The output channel processing module is used to receive the first video after amplification processing and send it to the display screen.

[0063] This embodiment also provides a specific example of a shared multi-layer video processing system based on FPGA, which explains the specific solution of the present invention in detail by comparing with the existing solution. The example specifically includes:

[0064] like Figure 2 As shown, users' demand for multi-layer display is also increasing, from single screen to multi-screen, single layer to multi-layer. Existing solutions generally adopt independent layer allocation. The number of layers of a single output channel is fixed. To increase the number of layers, it is necessary to reduce the number of output channels or replace chips with richer resources. Hardware upgrades will also lead to increased costs.

[0065] like Figure 3 As shown, the FPGA-based shared multi-layer system of the present invention changes the number of layers of each output channel by sharing layers without changing the existing hardware equipment, the total number of output channels and chip resources, which not only meets the needs of multi-layer display but also reduces the occupancy rate of the backplane transmission channel.

[0066] like Figure 4As shown, in the existing multi-channel multi-layer output solution, one backplane channel transmits one video signal source, and the backplane channel and the output channel layer relationship are bound one by one. For example, backplane channel 1 and channel 2 are fixed to layer 1 and layer 2 of output channel 1, backplane channel 3 and channel 4 are fixed to layer 1 and layer 2 of output channel 2, and so on. Taking a 4-channel 2-layer processing card as an example, if output channel 2 also needs to display the video signal source of backplane channel 1, the signal source of backplane channel 1 needs to be connected to backplane channel 3 or backplane channel 4 at the same time, which will occupy two backplane channels, resulting in an increase in the backplane channel occupancy rate.

[0067] like Figure 5 As shown, using the shared layer method, the same signal source only occupies one backplane channel no matter it is displayed on one or more output channels, and when the same signal source is displayed on the output channels in the same group, only one output layer is occupied. Taking the 4-channel shared layer processing card as an example, after signal source 1 and signal source 2 pass through backplane channel 1 and backplane channel 2 and video data receiving unit 1, the relevant information of signal source 1 and signal source 2 is sent to shared layer processing module 1~shared layer processing module 4 for processing at the same time, and then sent to output channel 1~output channel 4, so that one signal source is displayed on multiple output channels and only occupies one backplane channel.

[0068] The focus of the present invention is on the shared layer processing module. The specific work of the shared layer processing module is to complete the mapping of video data and layer information, layer windowing and video magnification, etc. The output channel processing module completes the output interface adaptation function, such as Figure 6 As shown, it is a schematic diagram of a shared layer processing module processing N layers for windowing. The method for the shared layer processing module to process N layers includes:

[0069] (1) Calculate the order of layers, which is called Z order. The Z order of layers from top to bottom is 1, 2, ... N. Compare the Z order of N layers in pairs. There are a total of ((N × (N-1) / 2) different comparison results, which are expressed as RZ[((N × (N-1) / 2-1):0];

[0070] (2) Pre-fetch the data source. According to the layer windowing information, the layer information assigned to the current channel, the Z-sequence result RZ[((N×(N-1) / 2-1):0] and the output video resolution timing of the current channel, calculate the storage address of the current pixel in the external storage unit in advance, generate a read data request, and cache the read data to the local storage unit for later use. If the current row has only one layer, read the data from the external storage unit once; if the current row has multiple layers, read the source data of the new layer once each time a new layer is entered;

[0071] (3) Video data output processing: According to the layer window information and the magnification factor of each layer, the source data is read from the local storage unit for amplification processing. By utilizing the parallel processing capability of the FPGA, high-resolution video amplification processing can be achieved, and the processed video can be output to the subsequent module according to the standard VESA video timing.

[0072] It should be noted that the FPGA-based shared multi-layer video processing system provided in the above embodiment is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiments can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not regarded as improper limitations of the present invention.

[0073] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art can understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the scope of protection of the present invention.

[0074] The second embodiment of the present invention is a shared multi-layer video processing method based on FPGA, the method comprising: a backplane channel receives data from a signal source and parses the data of the signal source based on a protocol to obtain a video data stream, and then transmits the video data stream to a video data receiving and processing module; the video data receiving and processing module extracts video data from the video data stream and then performs shrinking processing on it to obtain a first video, and then sends the first video to a shared layer processing module; the shared layer processing module receives the first video, and performs windowing processing based on the first video to obtain windowing information and calculate the up-and-down sequence relationship of the layers in the video; then, based on the up-and-down sequence relationship of the layers and the windowing information, the storage address of the current pixel point in the external storage unit is calculated to read the first video; the parallel processing capability of the FPGA is used to amplify the read first video and send it to the output channel processing module; the output channel processing module receives the amplified first video and sends it to the display screen.

[0075] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the method described above can refer to the corresponding process in the aforementioned system embodiment, and will not be repeated here.

[0076] An electronic device according to the third embodiment of the present invention comprises: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned FPGA-based shared multi-layer video processing method.

[0077] A computer-readable storage medium according to a fourth embodiment of the present invention stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned FPGA-based shared multi-layer video processing method.

[0078] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the electronic device and storage medium described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0079] Those skilled in the art should be able to appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two, and the programs corresponding to the software modules and method steps can be placed in random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the technical field. In order to clearly illustrate the interchangeability of electronic hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0080] Reference below Figure 7 , which shows a schematic diagram of the structure of a computer system of a server for implementing the method, system, and device embodiments of the present application. Figure 7 The server shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0081] like Figure 7As shown, the computer system includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 602 or the program loaded from the storage part 608 to the random access memory (RAM) 603. In the RAM 603, various programs and data required for system operation are also stored. The CPU 601, ROM 602 and RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0082] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed so that a computer program read therefrom is installed into the storage section 608 as needed.

[0083] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 609, and / or installed from the removable medium 611. When the computer program is executed by the central processing unit (CPU) 601, the above-mentioned functions defined in the method of the present application are executed. It should be noted that the above-mentioned computer-readable medium of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, an apparatus or a device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, an apparatus or a device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0084] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0085] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0086] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.

[0087] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.

[0088] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A shared multi-layer video processing system based on FPGA, characterized in that: The system comprises: The backplane channel is used to receive data from the signal source, parse the data from the signal source based on the protocol to obtain a video data stream, and then transmit the video data stream to the video data receiving and processing module; A video data receiving and processing module, configured to extract video data from the video data stream and then reduce the video data to obtain a first video, and send the first video to the shared layer processing module; A shared layer processing module is used to receive the first video, perform windowing processing on the first video to obtain windowing information, and calculate the up-down sequence relationship of the layers in the first video; then calculate the storage address of the current pixel point in the external storage unit based on the up-down sequence relationship of the layers and the windowing information to read the first video; and use the parallel processing capability of the FPGA to amplify the read first video and send it to the output channel processing module; An output channel processing module, used for receiving the first video after amplification processing and sending it to a display screen; The method for the shared layer processing module to calculate the upper and lower order relationship of the layers in the first video is: Assume that the maximum number of layers is N, and compare each layer pairwise. Comparison results: The comparison result is expressed as: ; Among them, N is the maximum number of layers, and RZ represents the layer comparison result; The shared layer processing module reads the first video specifically including: The shared layer processing module determines the layer information assigned to the current output channel processing module and the output video data resolution information of the current output channel processing module according to the external instruction; The shared layer processing module calculates the storage address of the current pixel in the external storage unit and generates a read data request based on the assigned layer information and the output video data resolution information, according to the upper and lower order relationship of the layers and the layer windowing information; reads the first video based on the read data request, and then caches the read first video to the local storage unit.

2. The FPGA-based shared multi-layer video processing system according to claim 1, characterized in that: The number of the backplane channels is one or more, wherein each backplane channel is connected to only one signal source.

3. The FPGA-based shared multi-layer video processing system according to claim 2, characterized in that: The number of the video data receiving and processing modules is one or more; each video data receiving and processing module receives the video data streams of one or more backplane channels; and each backplane channel sends the video data stream to only one video data receiving and processing module.

4. The FPGA-based shared multi-layer video processing system according to claim 3, characterized in that: The number of the shared layer processing modules is one or more; each shared layer processing module receives the first video generated by all video data receiving processing modules.

5. The FPGA-based shared multi-layer video processing system according to claim 4, characterized in that: The shared layer processing module reading the first video also includes: If there is only one layer, the shared layer processing module reads data from the external storage unit once; if there are multiple layers currently, the shared layer processing module needs to read the data of the new layer once each time it enters a new layer.

6. The FPGA-based shared multi-layer video processing system according to claim 5, characterized in that: The shared layer processing module utilizes the parallel processing capability of the FPGA to amplify the read first video and then sends it to the output channel processing module, including: The shared layer processing module reads the first video from the local storage unit according to the window opening information of the layer; the shared layer processing module amplifies the first video based on the amplification factor of each layer and utilizes the parallel processing capability of the FPGA, and outputs the amplified first video to the output channel processing module according to the standard VESA video timing.

7. A shared multi-layer video processing method based on FPGA, characterized in that: The method comprises: The backplane channel receives the data from the signal source and parses the data from the signal source based on the protocol to obtain a video data stream, and then transmits the video data stream to the video data receiving and processing module; The video data receiving and processing module extracts the video data from the video data stream and then reduces the video data to obtain a first video, and then sends the first video to the shared layer processing module; The shared layer processing module receives the first video, performs window processing based on the first video to obtain window information and calculates the up-down sequence relationship of the layers in the video; then calculates the storage address of the current pixel point in the external storage unit based on the up-down sequence relationship of the layers and the window information to read the first video; uses the parallel processing capability of the FPGA to amplify the read first video and then sends it to the output channel processing module; The output channel processing module receives the amplified first video and sends it to the display screen; The method for the shared layer processing module to calculate the upper and lower order relationship of the layers in the first video is: Assume that the maximum number of layers is N, and compare each layer pairwise. Comparison results: The comparison result is expressed as: ; Among them, N is the maximum number of layers, and RZ represents the layer comparison result; The shared layer processing module reads the first video specifically including: The shared layer processing module determines the layer information assigned to the current output channel processing module and the output video data resolution information of the current output channel processing module according to the external instruction; The shared layer processing module calculates the storage address of the current pixel in the external storage unit and generates a read data request based on the assigned layer information and the output video data resolution information, according to the upper and lower order relationship of the layers and the layer windowing information; reads the first video based on the read data request, and then caches the read first video to the local storage unit.

8. An electronic device, characterized in that: include: at least one processor; And a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the FPGA-based shared multi-layer video processing method described in claim 7.

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