A feature selection method and system for intelligent testing of circuits
By selecting the optimal feature set through dimensionality reduction and combined incremental method based on time-frequency domain extension, the problem of insufficient number of effective features in intelligent circuit testing is solved, achieving a balance between feature selection effectiveness and computational speed, and improving the efficiency of circuit testing.
Patent Information
- Application Number
- CN202410919642.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-10
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2044-07-10
AI Technical Summary
In existing intelligent circuit testing, the number of effective features in the feature set after dimensionality reduction is insufficient, and the feature selection method is difficult to balance performance and computational speed.
A dimensionality reduction method based on time-frequency domain extension is adopted, combined with the combinatorial incremental method to select the optimal feature set. The feature set is gradually expanded through discrete wavelet analysis, principal component analysis and correlation ranking. The optimal feature combination is selected by training and testing a machine learning model.
This increases the number of effective features in the feature set after dimensionality reduction, balancing the effectiveness of feature selection with computational speed, and improving the efficiency of intelligent circuit testing.
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Figure CN118897975B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of circuit testing technology, and more specifically, relates to a feature selection method and system for intelligent circuit testing. Background Technology
[0002] Circuit testing technology is a crucial step in ensuring the quality of electronic products and is widely used in all stages of electronic system / integrated circuit production. By analyzing the electrical signals at each output port of a circuit, various circuit performance indicators are derived. Only products with all indicators within acceptable ranges are delivered to the customer.
[0003] Traditional circuit testing requires expensive equipment, complex procedures, and lengthy testing times. With the development of machine learning technology, machine learning-based intelligent circuit testing has attracted considerable attention. Machine learning-based intelligent circuit testing is being used to replace traditional circuit testing methods, aiming to reduce circuit testing costs and time.
[0004] Feature selection from the time-domain response signal of a circuit is a crucial step in intelligent circuit testing. Existing time-domain signal feature selection methods mainly involve two stages: dimensionality reduction and selection. First, the original signal is dimensionality reduced to decrease the feature dimension and avoid problems such as data sparsity or model overfitting when training machine learning models. Next, the optimal feature combination is selected from the dimensionality-reduced original feature set for indicator prediction. The selection stage mainly employs two methods: packaging and filtering. The packaging method selects the optimal feature combination by testing the effectiveness of all possible combinations of the original feature set for training the machine learning model; the filtering method does not involve model training but selects feature combinations based on the correlation between each feature in the original feature set and the indicator to be tested.
[0005] Current methods for selecting features from time-domain signals suffer from the following shortcomings. Firstly, in the dimensionality reduction stage, it's difficult to guarantee the number of effective features (effective features are those highly correlated with the indicator to be predicted) within the reduced feature set. Secondly, the selection process struggles to balance selection effectiveness with computational speed. While the wrapping method can reliably select the optimal feature combination, it requires training a machine learning model for each possible combination, consuming significant time. The filtering method, based on correlation, is fast but unreliable in selecting the optimal feature combination (two low-correlation features may combine to achieve high correlation). Therefore, there is an urgent need to propose a feature selection method that can increase the number of effective features within the reduced feature set while balancing feature selection effectiveness and computational speed. Summary of the Invention
[0006] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a feature selection method and system for intelligent circuit testing, so as to increase the number of effective features in the feature set after dimensionality reduction and take into account both the feature selection effect and the calculation speed.
[0007] To achieve the above invention purpose, the feature selection method for intelligent circuit testing of the present invention is characterized in that it includes the following steps:
[0008] (1) Perform dimensionality reduction on the circuit time-domain response signal based on time-frequency domain expansion
[0009] First, perform discrete wavelet analysis on the circuit time-domain response signal to obtain wavelet approximation coefficients and the first n levels of wavelet detail coefficients, and then use principal component analysis to process them respectively, retaining the first m dimensions of the wavelet approximation coefficients and the first n levels of wavelet detail coefficients after principal component analysis, to obtain m×(n + 1) features after dimensionality reduction;
[0010] (2) Perform correlation-based sorting on the features after dimensionality reduction to obtain the original feature set;
[0011] For the m×(n + 1) features after dimensionality reduction, calculate the correlation coefficient between each feature and the待测指标 (to be determined what this "待测指标" exactly means in English, assume it's "test index" for now) respectively, and sort the m×(n + 1) features from high to low based on the correlation coefficient size to obtain the original feature set S0: S0 = {f1, f2, …, f m×(n+1)}, where f i , i = 1, 2, …, m×(n + 1) represents the i-th feature sorted from high to low based on the correlation coefficient size;
[0012] (3) Use the combined incremental method to select the optimal feature set
[0013] For each feature f i in the original feature set S0, perform feature selection. Add features one by one to the feature set S1 from high to low according to the correlation coefficient, that is, select feature f1 to train and test the machine learning model, and obtain the test mean square error, that is, the loss is loss1. Select features f1 and f2 to train and test the machine learning model, and obtain the mean square error as loss2. If the mean square error loss2 < loss1, then continue to add features. Use features f1, f2, and f3 to train and test the machine learning model, and obtain the mean square error as loss3. If the mean square error loss3 < loss2, then continue to add features, and so on, gradually expanding the feature set S1 until loss k+1 ≮loss k , at this time the feature set is S1: S1 = {f1, f2, …, f k};
[0014] The remaining features f k+2 , f k+3 , …, fm×(n+1) Each feature in the original feature set S0 is combined with the feature set S1 to train and test the machine learning model. The combination with the smallest mean squared error is selected as the feature set S2. Features in the original feature set S0 other than those in feature set S2 are combined pairwise, and each pair is combined with feature set S2 to train and test the machine learning model. The combination with the smallest mean squared error is selected as the optimal feature set S1. optimal Feature selection for completing intelligent circuit testing;
[0015] Among them, the feature label value for training and testing the machine learning model is the correlation coefficient between the feature and the indicator to be tested.
[0016] This invention relates to a feature selection system for intelligent circuit testing, characterized by comprising: a dimensionality reduction and sorting module and a combination selection module. The circuit's time-domain response signal first passes through the dimensionality reduction and sorting module to obtain an original feature set S0. The original feature set S0 is then input into the combination selection module to obtain the optimal feature set S. optimal ;
[0017] The dimension reduction and sorting module includes a discrete wavelet analysis unit, a feature dimension reduction unit, a correlation calculation unit, and a feature sorting unit. The discrete wavelet analysis unit performs discrete wavelet analysis on the input circuit time-domain response signal and outputs the wavelet approximation coefficients and the first n-level wavelet detail coefficients obtained after analysis. The feature dimension reduction unit performs principal component analysis on the wavelet approximation coefficients and the first n-level wavelet detail coefficients simultaneously. The principal component analysis is used to process them separately, and the first m dimensions of the wavelet approximation coefficients and the first n-level wavelet detail coefficients after principal component analysis are retained to obtain m×(n+1) features. The correlation calculation unit calculates the correlation coefficient between each of the m×(n+1) features after dimension reduction and the index to be measured. The feature sorting unit sorts the m×(n+1) features from high to low correlation coefficient to obtain the original feature set S0.
[0018] The combined selection module includes a selection unit, an expansion unit, a training unit, a comparison unit, and a difference unit. The selection unit selects features from the original feature set S0 in descending order of correlation coefficient. The expansion unit combines the selected features with the feature set stored in the previous loop, outputting the combined feature set S1. The training unit feeds the features in feature set S1 into the machine learning model for training and testing, and calculates the mean squared error. The comparison unit compares the current mean squared error with the mean squared error of the previous loop; if the difference is less, the next loop begins. The selection unit selects features from the original feature set S0 in descending order of correlation coefficient, combining, training, testing, and comparing, continuing to add features in this way, gradually expanding the feature set S1 until the loss occurs. k+1 ≮loss k At this point, the feature set is S1: S1 = {f1, f2, ..., f k};
[0019] The difference unit calculates and outputs the difference between the original feature set S0 and the feature set S1. Then, the combination unit combines the features in the difference between the original feature set S0 and the feature set S1, i.e., the residual features f. k+2 ,f k+3 ,…,f m×(n+1) Each feature set is combined with the feature set S1. The training unit then uses the combined features to train and test the machine learning model. The comparison unit selects the combination with the smallest mean squared error as the feature set S2. The difference unit calculates and outputs the difference between the original feature set S0 and the feature set S2. Then, the combination unit combines the features in the difference set between the original feature set S0 and the feature set S2 in pairs, and combines each pair with the feature set S2. The training unit then uses the combined features to train and test the machine learning model. The comparison unit selects the combination with the smallest mean squared error as the optimal feature set S2. optimal Feature selection for completing intelligent circuit testing.
[0020] The objective of this invention is achieved as follows:
[0021] This invention relates to a feature selection method and system for intelligent circuit testing. First, discrete wavelet analysis is used to transform the circuit's time-domain response signal, expanding its time-frequency domain information. Then, the wavelet approximation coefficients and the first n-level wavelet detail coefficients after discrete wavelet analysis are dimensionality-reduced to ensure that the dimensionality-reduced feature set has a sufficient number of effective features. This invention uses a combined incremental method to select the optimal feature set, combining the advantages of filtering and wrapping methods, thus balancing feature selection effectiveness and computational speed.
[0022] Compared with the prior art, the present invention has the following advantages:
[0023] Compared with existing dimensionality reduction methods, the dimensionality reduction method based on time-frequency domain extension designed in this invention has more effective features in the feature set after dimensionality reduction.
[0024] Compared to the packaging method, the combined incremental method designed in this invention is more efficient and can select the optimal feature set in a shorter computation time. Compared to the filtering method, the combined incremental method designed in this invention can select the optimal feature set more reliably.
[0025] Compared with existing feature selection systems, the feature selection system designed in this invention can improve the effectiveness of feature selection while taking into account both the efficiency of feature selection and the computational speed. Attached Figure Description
[0026] Figure 1 This is a flowchart of a specific implementation of the feature selection method for intelligent circuit testing according to the present invention;
[0027] Figure 2 yes Figure 1 The schematic diagram of the specific processing steps S1 and S2 shown is as follows;
[0028] Figure 3 yes Figure 1 The schematic diagram of the specific processing procedure in step S3 is shown below;
[0029] Figure 4 This is a schematic diagram illustrating the principle of a specific implementation of the feature selection system for intelligent circuit testing according to the present invention. Detailed Implementation
[0030] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.
[0031] Figure 1 This is a flowchart of a specific implementation of the feature selection method for intelligent circuit testing according to the present invention.
[0032] In this embodiment, as Figure 1 As shown, the feature selection method for intelligent circuit testing of the present invention includes the following steps:
[0033] Step S1: Perform dimensionality reduction on the circuit's time-domain response signal based on time-frequency domain extension.
[0034] like Figure 2 As shown, firstly, discrete wavelet analysis is performed on the time-domain response signal of the circuit to obtain the wavelet approximation coefficients and the first n-level wavelet detail coefficients. Then, principal component analysis is used to process them separately, retaining the first m dimensions of the wavelet approximation coefficients and the first n-level wavelet detail coefficients after principal component analysis, resulting in m×(n+1) features after dimensionality reduction.
[0035] In this embodiment, the Haar wavelet from the Daubechies wavelet family is used as the wavelet basis function for discrete wavelet analysis, and the decomposition level of the wavelet detail coefficients is set to 3 levels, i.e., n=3.
[0036] In this embodiment, principal component analysis is used to process the wavelet approximation coefficients and the first n-level wavelet detail coefficients respectively, and the first 5 dimensions after principal component analysis are retained, i.e., m=5.
[0037] Step S2: Rank the dimensionality-reduced features based on relevance to obtain the original feature set.
[0038] like Figure 2As shown, for the m×(n + 1) features after dimensionality reduction, calculate the correlation coefficient between each feature and the待测指标 (to-be-measured index) respectively. The correlation coefficients of all features form a correlation coefficient matrix. Sort the m×(n + 1) features from high to low based on the correlation coefficient magnitude to obtain the original feature set S0: S0 = {f1, f2, …, f m×(n+1)}, where f i , i = 1, 2, …, m×(n + 1) represents the i-th feature sorted from high to low based on the correlation coefficient magnitude.
[0039] In this embodiment, the correlation coefficient is the Pearson correlation coefficient, which is used as the correlation measurement index.
[0040] Step S3: Select the optimal feature set using the combination increment method
[0041] The present invention uses the K-fold method as the machine learning model training / testing method, and uses the combination increment method to select based on the average value of the test mean square loss for each fold as the test mean square error, and selects the optimal combination, that is, the optimal feature set:
[0042] As Figure 3 shown, for each feature f i in the original feature set S0, perform feature selection. Add features to the feature set S1 one by one from high to low according to the correlation coefficient, that is, select feature f1 to train and test the machine learning model, and obtain the test mean square error as loss1. Select features f1, f2 to train and test the machine learning model, and obtain the mean square error as loss2. If the mean square error loss2 < loss1, then continue to add features. Use features f1, f2, f3 to train and test the machine learning model, and obtain the mean square error as loss3. If the mean square error loss3 < loss2, then continue to add features, and so on, gradually expanding the feature set S1 until loss k+1 ≮loss k , at this time the feature set is S1: S1 = {f1, f2, …, f k};
[0043] Combine the remaining features f k+2 , f k+3 , …, f m×(n+1) with the feature set S1 one by one, train and test the machine learning model, and select the combination with the smallest mean square error among the obtained mean square errors as the feature set S2. Combine the features other than the features in the feature set S2 in the original feature set S0 pairwise, and combine and train and test the machine learning model with the feature set S2 pair by pair, and select the combination with the smallest mean square error among the obtained mean square errors as the optimal feature set S optim , and complete the feature selection for circuit intelligent testing;
[0044] Among them, the feature label value for training and testing the machine learning model is the correlation coefficient between the feature and the indicator to be tested.
[0045] In this embodiment, a neural network is used as the machine learning model, which includes one fully connected layer as the input layer, five fully connected layers as hidden layers, and one fully connected layer as the output layer.
[0046] Figure 4 This is a schematic diagram illustrating the principle of a specific implementation of the feature selection system for intelligent circuit testing according to the present invention.
[0047] In this embodiment, as Figure 4 As shown, the feature selection system for intelligent circuit testing of the present invention comprises two main parts: a dimensionality reduction and sorting module 1 and a combination selection module 2. The circuit time-domain response signal first passes through the dimensionality reduction and sorting module 1 to obtain the original feature set S0. The original feature set S0 is then input into the combination selection module 2 to obtain the optimal feature set S0. optimal .
[0048] like Figure 4 As shown, the dimensionality reduction and sorting module includes a discrete wavelet analysis unit 101, a feature dimensionality reduction unit 102, a correlation calculation unit 103, and a feature sorting unit 104. The discrete wavelet analysis unit 101 performs discrete wavelet analysis on the input circuit's time-domain response signal, outputting the wavelet approximation coefficients and the first n-level wavelet detail coefficients obtained after analysis. The feature dimensionality reduction unit 102 simultaneously performs principal component analysis on the wavelet approximation coefficients and the first n-level wavelet detail coefficients, processing them separately and retaining the first m dimensions of the wavelet approximation coefficients and the first n-level wavelet detail coefficients after principal component analysis, obtaining m×(n+1) features. The correlation calculation unit 103 calculates the correlation coefficient between each of the m×(n+1) features after dimensionality reduction and the target index. The feature sorting unit sorts the m×(n+1) features from high to low correlation coefficients to obtain the original feature set S0.
[0049] The combined selection module 2 includes a selection unit 201, an expansion unit 202, a training unit 203, a comparison unit 204, a difference unit 205, and a combination unit 206. The selection unit 201 selects features from the original feature set S0 in descending order of correlation coefficient. The expansion unit 202 combines the selected features with the feature set stored in the previous loop, outputting the combined feature set S1. The training unit 203 feeds the features in feature set S1 into the machine learning model for training and testing, and calculates the mean squared error. The comparison unit 204 compares the current mean squared error with the mean squared error of the previous loop; if the difference is less, the next loop begins. The selection unit 201 selects features from the original feature set S0 in descending order of correlation coefficient, combining, training, testing, and comparing, continuing to add features in this way, gradually expanding the feature set S1 until loss.k+1 ≮loss k At this point, the feature set is S1: S1 = {f1, f2, ..., f k}
[0050] The difference unit 205 calculates and outputs the difference between the original feature set S0 and the feature set S1. Then, the combination unit 206 combines the features in the difference between the original feature set S0 and the feature set S1, i.e., the residual features f. k+2 ,f k+3 ,…,f m×(n+1) Each feature set is combined with feature set S1, i.e., all combinations are iterated. Then, training unit 203 uses the features in the combinations to train and test the machine learning model. Comparison unit 204 selects the combination with the smallest mean squared error as feature set S2 based on the obtained mean squared error. Difference unit 205 calculates and outputs the difference between the original feature set S0 and feature set S2. Then, combination unit 206 combines the features in the difference between the original feature set S0 and feature set S2, i.e., the residual features, in pairs and combines them with feature set S2, i.e., iterates through all combinations. Then, training unit 203 uses the features in the combinations to train and test the machine learning model. Comparison unit 204 selects the combination with the smallest mean squared error as the optimal feature set S2 based on the obtained mean squared error. optimal Feature selection for completing intelligent circuit testing.
[0051] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.
Claims
1. A feature selection method for intelligent circuit testing, characterized in that, Includes the following steps: (1) Dimensionality reduction of the circuit time-domain response signal based on time-frequency domain extension First, discrete wavelet analysis is performed on the time-domain response signal of the circuit to obtain the wavelet approximation coefficients and the first n-level wavelet detail coefficients. Then, principal component analysis is used to process them separately, retaining the first m dimensions of the wavelet approximation coefficients and the first n-level wavelet detail coefficients after principal component analysis, resulting in m×(n+1) dimensionality-reduced features. (2) The features after dimensionality reduction are sorted based on correlation to obtain the original feature set; For the m×(n+1) features after dimensionality reduction, calculate the correlation coefficient between each feature and the indicator to be measured. Sort the m×(n+1) features from high to low based on the correlation coefficient, and obtain the original feature set S0: S0={f1,f2,...,f m×(n+1) }, where f i , i = 1, 2, ..., m × (n + 1) represents the i-th feature sorted from high to low based on the correlation coefficient; (3) Use the combinational incremental method to select the optimal feature set. For each feature f in the original feature set S0 i Feature selection is performed. The features are added one by one to the feature set S1 in descending order of correlation coefficient. That is, the feature f1 is selected to train and test the machine learning model, and the test mean squared error, i.e., the loss, is obtained as loss1. The features f1 and f2 are selected to train and test the machine learning model, and the mean squared error is obtained as loss2. If the mean squared error loss2 < loss1, then the feature is continuously added. The features f1, f2, and f3 are used to train and test the machine learning model, and the mean squared error is obtained as loss3. If the mean squared error loss3 < loss2, then the feature is continuously added, and so on, gradually expanding the feature set S1 until At this time, the feature set is S1: S1 = {f1, f2,..., f k}; The remaining feature f k+2 f k+3 , ..., f m×(n+1) Each feature in the original feature set S0 is combined with the feature set S1 to train and test the machine learning model. The combination with the smallest mean squared error is selected as the feature set S2. Features in the original feature set S0 other than those in feature set S2 are combined pairwise, and each pair is combined with feature set S2 to train and test the machine learning model. The combination with the smallest mean squared error is selected as the optimal feature set S1. optim Feature selection for completing intelligent circuit testing; Among them, the feature label value for training and testing the machine learning model is the correlation coefficient between the feature and the indicator to be tested.
2. The feature selection method for intelligent circuit testing according to claim 1, characterized in that, The correlation coefficient mentioned is the Pearson correlation coefficient.
3. The feature selection method for intelligent circuit testing according to claim 1, characterized in that, The neural network is used as the machine learning model, which includes one fully connected layer as the input layer, five fully connected layers as hidden layers, and one fully connected layer as the output layer.
4. A feature selection system for intelligent circuit testing, characterized in that, include: The dimensionality reduction and sorting module and the combination selection module work together. The circuit's time-domain response signal first passes through the dimensionality reduction and sorting module to obtain the original feature set S0. The original feature set S0 is then input into the combination selection module to obtain the optimal feature set S. optimal ; The dimension reduction and sorting module includes a discrete wavelet analysis unit, a feature dimension reduction unit, a correlation calculation unit, and a feature sorting unit. The discrete wavelet analysis unit performs discrete wavelet analysis on the input circuit time-domain response signal and outputs the wavelet approximation coefficients and the first n-level wavelet detail coefficients obtained after analysis. The feature dimension reduction unit performs principal component analysis on the wavelet approximation coefficients and the first n-level wavelet detail coefficients simultaneously. The principal component analysis is used to process them separately, and the first m dimensions of the wavelet approximation coefficients and the first n-level wavelet detail coefficients after principal component analysis are retained to obtain m×(n+1) features. The correlation calculation unit calculates the correlation coefficient between each of the m×(n+1) features after dimension reduction and the index to be measured. The feature sorting unit sorts the m×(n+1) features from high to low correlation coefficient to obtain the original feature set S0. The combined selection module includes a selection unit, an expansion unit, a training unit, a comparison unit, and a difference unit. The selection unit selects features from the original feature set S0 in descending order of correlation coefficient. The expansion unit combines the selected features with the feature set stored in the previous loop, outputting the combined feature set S1. The training unit feeds the features in feature set S1 into the machine learning model for training and testing, and calculates the mean squared error. The comparison unit compares the current mean squared error with the mean squared error of the previous loop; if the difference is less, the next loop begins. The selection unit selects features from the original feature set S0 in descending order of correlation coefficient, combining, training, testing, and comparing, continuing to add features in this way, gradually expanding the feature set S1 until... At this point, the feature set is S1: S1 = {f1, f2, ..., f...} k }; The difference unit calculates and outputs the difference between the original feature set S0 and the feature set S1. Then, the combination unit combines the features in the difference between the original feature set S0 and the feature set S1, i.e., the residual features f. k+2 f k+3 , ..., f m×(n+1) Each feature set is combined with the feature set S1. The training unit then uses the combined features to train and test the machine learning model. The comparison unit selects the combination with the smallest mean squared error as the feature set S2. The difference unit calculates and outputs the difference between the original feature set S0 and the feature set S2. Then, the combination unit combines the features in the difference set between the original feature set S0 and the feature set S2 in pairs, and combines each pair with the feature set S2. The training unit then uses the combined features to train and test the machine learning model. The comparison unit selects the combination with the smallest mean squared error as the optimal feature set S2. optim Feature selection for completing intelligent circuit testing.
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