In-memory processing chip

Abstract

The present disclosure provides an in-memory processing chip, which may at least include an interface circuit, a storage circuit and a computing unit; a first transmission path is provided between the interface circuit and the storage circuit; a second transmission path is provided between the storage circuit and the computing unit; a third transmission path is provided between the interface circuit and the computing unit, and the third transmission path is independent of the first transmission path.

Description

Technical Field

[0001] The embodiments of the present application relate to the semiconductor field, and in particular to an in-memory processing chip. Background Art

[0002] With the continuous development of artificial intelligence and big data, the demand for computing power in various application scenarios continues to increase. However, since the mainstream computing architecture adopts the von Neumann architecture with separated storage and computing, and the growth rate of memory bandwidth is far behind the increase in processor computing power, there will be a storage wall problem where the actual computing power of the computing system is limited due to insufficient bandwidth. Existing in-memory processing chips are implemented by replacing some storage units in the memory chip with computing units. The packaging method of the entire chip does not need to be changed, but there are problems of capacity loss and low computing power. Summary of the invention

[0003] The embodiments of the present application provide a new architecture of an in-memory processing chip.

[0004] According to some embodiments of the present application, the embodiments of the present application provide an in-memory processing chip, including an interface circuit, a storage circuit and a computing unit; a first transmission path is provided between the interface circuit and the storage circuit; a second transmission path is provided between the storage circuit and the computing unit; a third transmission path is provided between the interface circuit and the computing unit, and the third transmission path is independent of the first transmission path.

[0005] In some embodiments, the in-memory processing chip includes a plurality of the storage circuits and a plurality of the computing units, each computing unit corresponds to at least one storage circuit, different storage circuits have corresponding first transmission paths and second transmission paths, and different storage circuits are connected to the interface circuit via corresponding first transmission paths.

[0006] In some embodiments, the first transmission path is at least used to transmit model data, the second transmission path is at least used to transmit model data, the third transmission path is at least used to transmit initial data and target data, and the calculation unit performs calculation processing on the initial data based on the model data to obtain the target data.

[0007] In some embodiments, the first transmission path is also used to transmit the initial data and the target data, and the second transmission path is also used to transmit the initial data and the target data.

[0008] In some embodiments, the bandwidth of the first transmission path and the second transmission path is greater than that of the third transmission path, and the priority of the third transmission path in transmitting the initial data and the target data is higher than that of the first transmission path and the second transmission path.

[0009] In some embodiments, the in-memory processing chip further includes: a gating circuit, and the storage circuit is connected to the first transmission path or the second transmission path through the gating circuit.

[0010] In some embodiments, the gating circuit is further used to record refresh information of the corresponding storage circuit, and to send the recorded refresh information to the interface circuit before the interface circuit is disconnected from the storage circuit or after it is reconnected.

[0011] In some embodiments, the in-memory processing chip also includes: a storage controller, which is arranged between the corresponding storage circuit and the corresponding selection circuit, or between the corresponding selection circuit and the computing unit, and the storage controller is at least used to read the data in the storage circuit.

[0012] In some embodiments, the in-memory processing chip further includes: a mode control circuit for controlling the storage circuit to be connected to the first transmission path, or controlling the storage circuit to be connected to the second transmission path.

[0013] In some embodiments, the mode control circuit is further configured to turn on or off the third transmission path.

[0014] In some embodiments, the mode control circuit is located in the area where the interface circuit is located.

[0015] In some embodiments, a total bandwidth between the storage circuit and the computing unit in the in-memory processing chip is greater than a bandwidth between the in-memory processing chip and an external processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0017] Figures 1 to 7 A schematic diagram of the structure of an in-memory processing chip provided in an embodiment of the present application;

[0018] Figure 8 A schematic diagram of the structure of a computing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0020] Figures 1 to 7 A schematic diagram of the structure of an in-memory processing chip provided in an embodiment of the present application.

[0021] refer to Figure 1 The in-memory processing chip includes: an interface circuit 11, a storage circuit 12 and a computing unit 13. There is a first transmission path TR1 between the interface circuit 11 and the storage circuit 12, a second transmission path TR2 between the storage circuit 12 and the computing unit 13, and a third transmission path TR3 between the interface circuit 11 and the computing unit 13. The third transmission path TR3 is independent of the first transmission path TR1.

[0022] In the present disclosure, the calculation unit 13 is connected to the interface circuit 11 and the storage circuit 12 respectively, and the first transmission path TR1, the second transmission path TR2 and the third transmission path TR3 can all be used for data transmission. The third transmission path TR3 and the first transmission path TR1 are independent of each other, which means that there is no necessary association between the available state of the first transmission path TR1 and the available state of the third transmission path TR3. Both can be in an available state or an unavailable state at the same time, or one can be in an available state and the other can be in an unavailable state, depending on the corresponding control signal. The available state of each transmission path is related to at least two factors: 1. The conduction or disconnection inside the transmission path, such as the conduction or disconnection of the internal driver. If the transmission path itself is turned off, the transmission path is unavailable; 2. Whether the transmission path is data connected with the data input circuit or the data output circuit. If the data path of the transmission path and the data input circuit or the data output circuit is disconnected, the transmission path is unavailable. The data input circuit is directly connected to the input end of the transmission path, and the data output circuit is directly connected to the output end of the transmission path.

[0023] In this way, after completing the calculation processing, the calculation unit 13 does not need to transmit data through the second transmission path TR2 or forward data through the storage circuit 12, but can directly output the processed target data through the independent third transmission path TR3 through the interface circuit 11. This is beneficial to directly improve the data transmission efficiency and indirectly improve the data processing efficiency of the in-memory processing chip. In addition, since two independent transmission paths are provided, the calculation unit 13 can receive data through one of the transmission paths and output data through the other transmission path at the same time, which is beneficial to simplify the timing and further improve the data transmission efficiency.

[0024] It can be understood that data transmission and signal transmission are different concepts. In this application, signal transmission refers to the transmission of control signals, data transmission refers to the transmission of model data and regular data, and the purpose of signal transmission is to assist data transmission.

[0025] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0026] In the present disclosure, the interface circuit 11 can not only receive and output data, but also undertake part of the signal processing function. The signal processing function of the interface circuit 11 can be adjusted according to the actual architecture of other circuits in the memory processing chip. The storage circuit 12 can be regarded as a storage chip, including a volatile storage chip and a non-volatile storage chip, etc. The storage circuit 12 includes a storage unit for storing data and a peripheral circuit for controlling data storage.

[0027] The calculation unit 13 is used to calculate and process the input data based on the target rules, and output the processed target data; wherein the calculation processing can be to operate on the target data to extract other types of information required therefrom, such as the colors of different positions in the video at different times, or to simplify the target data to reduce the bandwidth required for transmission. For the simplified data, it may be necessary to restore it to a certain extent or completely in the future to facilitate the extraction of other types of information. The present application does not impose any restrictions on the functions of the calculation unit, and the functions of the calculation unit can be adaptively adjusted according to the actual application scenario. In addition, the present application does not impose any restrictions on the type of calculation unit. The calculation unit 13 can be implemented using a traditional arithmetic logic unit or a new type of CIM (Compute in Memory) in-memory calculation unit, such as an SRAM in-memory calculation unit.

[0028] In some embodiments, reference Figure 2 The in-memory processing chip includes multiple storage circuits 22 (Bank) and multiple computing units 23 (PU). Each computing unit 23 corresponds to at least one storage circuit 22. Different storage circuits 22 have corresponding first transmission paths TR1 and second transmission paths TR2. Different storage circuits 22 are connected to the interface circuit 21 through the corresponding first transmission paths TR1.

[0029] exist Figure 2In the example shown, each computing unit 23 corresponds to a storage circuit 22, each storage circuit 22 has a corresponding first transmission path and a second transmission path, and the transmission paths corresponding to different storage circuits 22 are independent of each other. The first ends of different first transmission paths are used to connect different storage circuits 22, and the second ends of different first transmission paths are used to connect the interface circuit 21 for receiving or outputting data. The first ends of different second transmission paths are used to connect different storage circuits 22, and the second ends of different second transmission paths are used to connect different computing units 23. When each computing unit 23 corresponds to at least two storage circuits 22, the second ends of different second transmission paths can be used to connect the same computing unit 23. It can be understood that in some scenarios, a part of the computing units 23 can correspond to one storage circuit 22 and another part of the computing units 23 can correspond to at least two storage circuits, which is conducive to improving the computing power distribution inside the in-memory processing chip and avoiding computing power waste.

[0030] The storage circuit 22 and the computing unit 23 both have corresponding connection modules 24, and the storage circuit 22 and the computing unit 23 are connected through the corresponding connection modules 24, and the connection method includes at least one of TSV (Through Silicon Vias) and hybrid bonding, so as to perform data transmission and signal control.

[0031] Furthermore, the in-memory processing chip may be composed of multiple chips stacked in a vertical direction, the communication protocol between the chips is a private protocol, and the multiple chips are packaged together to form an in-memory computing chip. Figure 2 , the in-memory processing chip includes a computing chip and a memory chip stacked in a vertical direction, the computing unit 23 and the interface circuit 21 are both arranged in the computing chip, and the memory circuit 22 is arranged in the memory chip. It can be understood that the in-memory processing chip can also be composed of at least one memory chip and at least one computing chip stacked in a vertical direction, such as two memory chips or two computing chips. Theoretically, there can be N memory chips and M computing chips, where M and N are natural numbers greater than 1.

[0032] In other embodiments, the in-memory processing chip includes an interface chip, a computing chip, and a storage chip stacked in a vertical direction, and the interface circuit 21 is arranged in the interface chip, that is, the interface circuit 21 and the computing unit 23 are arranged in different chips. When the three chips are stacked, any chip can be arranged in the middle position. In some scenarios, a chip with a large amount of input and output data can be arranged in the middle position, such as a storage chip for pre-storing model data with a large amount of data, and / or a chip with a high heat generation due to data transmission or data calculation can be arranged in a non-middle position, that is, arranged on the outside, such as a computing chip that needs to perform calculations or an interface chip that needs to perform frequent input and output.

[0033] Re-reference Figure 1 In some embodiments, the first transmission path TR1 is at least used to transmit model data, the second transmission path TR2 is at least used to transmit model data, and the third transmission path TR3 is at least used to transmit initial data and target data. The calculation unit 13 performs calculation processing on the initial data based on the model data to obtain the target data.

[0034] The model data can also be understood as model weight data, which is used to characterize the target rule of the calculation process. After receiving the model data, the interface circuit 11 can first store it in the storage circuit 12. The calculation unit 13 can read the model data from the storage circuit 12 through the second transmission path TR2, and receive the initial data through the interface circuit 11 and the third transmission path TR3, and then calculate and process the initial data based on the model data to obtain the processed target data. The target data can be output through the third transmission path TR3 and the interface circuit 11.

[0035] It is understandable that "initial data" refers to unprocessed data, and "target data" refers to processed data. The only difference between the initial data and the target data is whether they have been processed by calculation, but they are both regular data relative to the model data. For the sake of simplicity, the subsequent description will use "regular data" to refer to both the initial data and the target data.

[0036] In some embodiments, the interface circuit 11 may receive the model data first and then the initial data. In this way, the model data can be pre-stored in the storage circuit 12 to stagger the timing, so that the interface circuit 11 can use the same input and output port (hereinafter referred to as IO port) to sequentially receive the model data and the initial data, thereby simplifying the IO port; in other embodiments, the ports used to receive the model data and the initial data in the interface circuit 11 are different. It should be noted that even if the interface circuit 11 uses the same IO port to receive and output the model data and the regular data, the interface circuit can also perform data transmission through different transmission parameters, and the transmission parameters include the continuous transmission length (burst length) and the number of ports used at the same time. For example, the interface circuit 11 can use 16 ports to transmit model data, and use 8 of the 16 ports to transmit regular data; and the continuous transmission length is 16 when transmitting the model data, and the continuous transmission length is 8 when transmitting the regular data.

[0037] In some scenarios, the volume of model data is generally much larger than the volume of initial data, the former is usually at the GB level, and the latter is usually at the MB level. Therefore, the storage circuit 12 can be used to pre-store model data to speed up loading instead of storing initial data.

[0038] In some embodiments, the first transmission path TR1 is also used to transmit initial data and target data, and the second transmission path TR2 is used to transmit initial data and target data. In this way, the initial data can also be input into the computing unit 13 through the first transmission path TR1 and the second transmission path TR2, and the target data can be output through the third transmission path or through the second transmission path and the first transmission path. In this way, it is helpful to ensure that when the third transmission path is damaged or congested (insufficient buffer space), the initial data is input and the target data is output through the first transmission path and the second transmission path.

[0039] In some embodiments, the bandwidth of the first transmission path and the second transmission path is greater than the bandwidth of the third transmission path, and the third transmission path has a higher priority in transmitting the initial data and the target data than the first transmission path and the second transmission path.

[0040] It should be noted that the data volume of the target data and the data volume of the initial data do not have an absolute size relationship, and it depends on the calculation rules of the calculation unit. In some embodiments, if the data volume of the target data is greater than the data volume of the initial data or if the data volume of the target data is greater than the target threshold, at least part of the target data can be transmitted through the first transmission path and the second transmission path, thereby improving the efficiency of transmitting the target data. Among them, the part of the target data exceeding the target threshold can be transmitted by the first transmission path and the second transmission path, or all the target data can be transmitted by the first transmission path and the second transmission path.

[0041] After the initial data is input through the first transmission path and before it is transmitted to the second transmission path TR2, it can be stored in the storage unit in the storage circuit 12, or temporarily stored in a buffer circuit such as a buffer or latch in the storage circuit 12. After the initial data is transmitted to the second transmission path TR2, the initial data stored in the storage unit can be retained or cleared (data clearing of the storage unit means that the potential of the storage unit is adjusted to a pre-charged state and does not represent any data, or the storage unit is adjusted to a state that can be overwritten by new data), and the initial data temporarily stored in the buffer circuit is usually cleared (clearing of the buffer circuit means that the data line in the buffer circuit is adjusted to the default potential state).

[0042] When the target data is output through the second transmission path, it can be temporarily stored in the buffer circuit of the storage circuit 12 or stored in the storage unit of the storage circuit. The target data transmitted to the storage circuit 12 can be stored in the storage circuit 12 and not output temporarily, or can be directly output through the first transmission path TR1 and the interface circuit 11. If it is stored in the storage circuit 12 and not output temporarily, it can be stored in the storage unit of the storage circuit 12 to ensure the accurate storage of the target data by refreshing. After the processed target data is transmitted to the first transmission path TR1 or output through the interface circuit 11, the target data stored in the storage unit can be retained or cleared. Each storage circuit 12 can output the target data that has not been output before after receiving the output instruction or the amount of target data that has not been output stored by itself reaches the first preset threshold, or output the target data that has not been output before after the total amount of target data that has not been output stored by all storage circuits 12 reaches the second preset threshold.

[0043] In some other embodiments, the second transmission path TR2 is used for unidirectional transmission of initial data, which means that only the initial data is allowed to be transmitted from the storage circuit 12 to the computing unit 13, but the target data is not allowed to be transmitted from the computing unit 13 to the storage circuit 12. This is conducive to simplifying the timing control, avoiding conflicts caused by simultaneous input and output of the second transmission path due to instruction errors, and retaining the possibility of temporarily inputting the initial data to be processed through the first transmission path and the second transmission path due to congestion of the third transmission path.

[0044] In some embodiments, reference Figure 3The in-memory processing chip further includes: a gating circuit 35, through which the storage circuit 32 is connected to the first transmission path TR1 or the second transmission path TR2. That is, the gating circuit 35 includes the function of a gating device, and at the same time, only one of the calculation unit 33 and the interface circuit 31 can be connected to the storage circuit 32. In this way, it is beneficial to control the data transmission flow, separate the data storage operation of the initial data and the model data from the data calculation operation of the initial data, and avoid conflicts caused by the parallel operation of the data storage operation and the data calculation operation.

[0045] In some embodiments, the gating circuit 35 is also used to record the refresh information of the corresponding storage circuit 32, and to send the recorded refresh information to the interface circuit 31 before the interface circuit 31 is disconnected from the storage circuit 32 or after it is reconnected. The refresh information includes the current refresh row of the regular refresh operation (i.e., sequential refresh), and the current refresh row can be obtained according to the count value of the refresh counter. The refresh information can also include row hammer address information, and the row hammer address information can include the address of the attacked row or victim row that has reached the row hammer refresh threshold, and the address of the attacked row that has not yet reached the row hammer refresh threshold but is in the process of address accumulation. If the interface circuit 31 has a memory management function, the interface circuit 31 can control the internal refresh of the storage circuit 32 according to the received refresh information. If the interface circuit 31 does not have a memory management function, the internal refresh of the storage circuit 32 can be controlled by an external circuit (such as a CPU) connected to the interface circuit 31.

[0046] The selection circuit 35 can record the refresh information of the corresponding storage circuit 32 through an independent built-in counter, or directly obtain the information of the refresh counter in the storage circuit 32 to realize the recording of the refresh information.

[0047] It should be noted that if the selection circuit 35 sends refresh information before the interface circuit 31 is disconnected from the storage circuit 32, the interface circuit 31 or the external circuit can control the connection timing between the storage circuit 32 and the interface circuit 31 according to the refresh information and whether the target data is output through the interface circuit 31, so as to ensure the timely refresh of the storage circuit 32. If the in-memory processing chip contains multiple storage circuits 32, since each storage circuit 32 has a corresponding selection circuit 35 (different storage circuits 32 have different selection circuits 35), the interface circuit 31 or the external circuit will receive the refresh information of multiple storage circuits 32, and then control the connection order between the interface circuit 31 and different storage circuits 32 according to the refresh information of different storage circuits 32, and then refresh the different storage circuits 32 in sequence.

[0048] In some embodiments, reference Figure 4The in-memory processing chip further includes a storage controller 46 (LMC(s), local memory controller(s)), which is arranged between the corresponding storage circuit 42 and the corresponding gating circuit (not shown), or between the corresponding gating circuit and the calculation unit 43, and the storage controller 46 is at least used to read the data in the storage circuit 42. It can be understood that no matter where the storage controller 46 is located, it will be used to control the storage circuit 42 in part of the time period.

[0049] The interface between the storage controller 46 and the storage circuit 42 mainly includes a data bus, an address / instruction bus, and a test mode bus. The basic functions and corresponding contents that the storage controller 46 needs to have include: an instruction translation module, which is used to receive instructions transmitted by the calculation unit 43 or the interface circuit 41 and convert them into instructions that can be recognized by the storage circuit 42 under the private protocol, and perform instruction scheduling according to the timing requirements of the private interface; a data processing module, which is used to perform ECC error detection and correction, to convert data asynchronously and synchronously, to cache data, and to receive and send data; a memory management module, which is used to refresh the storage circuit, to control the mode of the storage circuit, to control and repair the redundancy of hybrid bonding or silicon penetration, and to control the test mode of the storage circuit.

[0050] Specifically, refer to Figure 5 When the storage controller 56 is arranged between the gating circuit 55 and the computing unit 53, the interface circuit 51 is connected to the storage circuit 52 through the gating circuit 55, and the storage controller 56 is on the second transmission path. At this time, if the gating circuit 55 is connected to the first transmission path and disconnected from the second transmission path, the storage controller 56 cannot control the storage circuit 52. In this way, the interface circuit 51 needs to play a part of the function of controlling the storage circuit, that is, the interface circuit 51 and the storage controller 56 have repeated functions. The repeated functions include storage circuit instruction decoding, data processing, and memory processing.

[0051] In some embodiments, when the storage controller 56 is arranged between the selection circuit 55 and the computing unit 53, the selection circuit is also used to send refresh information of the storage circuit 52 to the storage controller 56 through the second transmission path, so that the memory management module in the storage controller 56 can refresh the storage circuit 52 based on the refresh information.

[0052] refer to Figure 6When the storage controller 66 is set between the gating circuit 65 and the storage circuit 62, no matter the storage circuit 62 is connected to the first transmission path or the second transmission path, the storage controller 66 will maintain the connection with the storage circuit 62, so that the function of the interface circuit 61 may not overlap with the function of the storage controller 66. In this scenario, the main functions of the interface circuit 61 include instruction decoding and translation, data processing functions, and connection with the storage controller 66 through an on-chip bus standard (such as AXI, Advanced extensible Interface).

[0053] In addition, whether in Figure 5 still Figure 6 In the embodiment, different storage circuits are connected to the interface circuit through the main data path datapath, and the interface circuit can be connected to at least one storage circuit at the same time. Figure 5 When the connection method shown is used, the interface circuit can use the JEDEC standard DRAM interface. Figure 6 When the connection mode is shown, the interface circuit can use the JEDEC standard DRAM interface or other universal buses, including CXL (Compute ExpressLink) and UCIE (Universal Chiplet Interconnect Express). In addition to the connection protocol between the interface circuit and the external circuit using the public standard, the data transmission protocol between different circuits inside the memory processing chip can use private protocols, such as between the interface circuit and the storage controller, between the interface circuit and the storage circuit, between the interface circuit and the computing unit, and between the computing unit and the storage controller.

[0054] It should be noted that in Figure 4 In the illustrated embodiment, the storage circuit 42 is marked with Bank(s), the storage controller 46 is marked with LMC(s), and the computing unit 43 is marked with PU, which indicates that the storage circuit 42 corresponds to the storage controller 46 one by one, and each computing unit 43 corresponds to at least one storage circuit 42 and at least one storage controller 46. Figure 5 and Figure 6In the illustrated embodiment, the storage circuit is marked with Bank, the storage controller is marked with LMC, and the computing unit is marked with PU, which indicates that each computing unit corresponds to a storage circuit and a storage controller, different storage circuits are arranged in parallel, and the storage circuits correspond to the gating circuits one by one. It can be understood that the more storage circuits 42 and storage controllers 46 corresponding to each computing unit 43, the greater the maximum bandwidth of each computing unit 43, and at the same time, the larger the area occupied by each computing unit 43. Furthermore, the number of computing units 43 determines the maximum internal bandwidth of the entire in-memory processing chip.

[0055] In addition, Figure 4 In the example, two dotted lines are used to connect the storage circuit 42 and the storage controller 46, respectively. Figure 5 and Figure 6 In the two embodiments shown, the interface circuit 41 can be connected to the storage circuit 42 through the gating circuit but not connected to the storage controller 46, or can be connected to the storage circuit 42 through the gating circuit storage controller 46 in turn.

[0056] In some embodiments, reference Figure 7 The memory processing chip further includes a mode control circuit 77, which is used to control the storage circuit 72 to be connected to the first transmission path TR1, or to control the storage circuit 72 to be connected to the second transmission path TR2. In other words, the mode control circuit 77 switches the transmission path by controlling the selection circuit 75. Figure 7 In the figure, the solid line represents the data flow, the dotted line represents the control flow, and the storage controller 76 is located between the selection circuit 75 and the storage circuit 72 as an example. In this scenario, part of the core function of the interface circuit is to translate the instructions of the external standard interface into instructions that can be recognized by the storage controller 76 and the mode control circuit 77.

[0057] exist Figure 7 In the embodiment, by setting the mode control circuit 77, the in-memory processing chip can have two completely independent working modes, and the two working modes do not interfere with each other. When the storage circuit 72 is connected to the first transmission path TR1 and disconnected from the second transmission path TR2, the function of the in-memory processing chip is a normal storage chip, which can be used as a regular storage chip or write model data in this scenario. When the storage circuit 72 is disconnected from the first transmission path TR1 and connected to the second transmission path TR2, the function of the in-memory processing chip at least includes the calculation function. The mode control circuit 77 can send a control instruction to the calculation unit 73 after identifying the instruction. The control signal can be used to control the timing of the calculation unit 73 to perform calculation processing, and control the calculation unit 73 to adjust from the sleep mode to the working mode, etc.

[0058] In some embodiments, Figure 5 In the illustrated embodiment, the repeated functions of the interface circuit 51 and the storage controller 56 may also include control instruction decoding, the interface circuit 51 is used to receive and decode external input instructions, and the storage controller 56 is used to receive and decode control instructions output by the mode control circuit, and the decoding result may at least indicate whether the gating circuit is disconnected from the first transmission path and connected to the second transmission path. The storage controller 76 may also have a dormant state and an enabled state, when the gating circuit is connected to the first transmission circuit and the storage controller does not need to transmit data, the storage controller is in a dormant state, and when the gating circuit is connected to the second transmission circuit, the storage controller is in an enabled state.

[0059] According to the previous description, when the storage circuit 72 is disconnected from the first transmission path TR1 and connected to the second transmission path TR2, the calculation unit 73 can receive the initial data through the second transmission path TR2 or the initial data pre-stored in the storage circuit 72 through the second transmission path. After the calculation unit 73 completes the calculation process, the target data can be output through the third transmission path TR3 or stored in the storage circuit 72 through the second transmission path TR2. The target data stored in the storage circuit 72 can be output or not after the selection circuit 75 (MUX) is connected to the first transmission path TR1. The target data stored in the storage circuit 72 can be cleared or not after being transmitted through the first transmission path TR1. It can be understood that the calculation unit 73 can store the target data in the storage circuit 72 through the second transmission path TR2 and output the target data through the third transmission path TR3 and the interface circuit 71 at the same time.

[0060] In some embodiments, the mode control circuit 77 is also used to control the third transmission path TR3 to be turned on or off. For example, when the selection circuit 75 is connected to the first transmission path TR1, the third transmission path TR3 is controlled to be turned off, so that the calculation unit 73 is not connected to the interface circuit 71 or the storage circuit 72, and when the selection circuit 75 is connected to the second transmission path TR2, the third transmission path TR3 is controlled to be turned on, so that the calculation unit 73 can receive the initial data and output the target data through the third transmission path TR3.

[0061] In some embodiments, a global buffer 78 is also provided on the third transmission path TR3 for receiving initial data and outputting target data, and timing adjustment can be performed on the initial data and target data to wait for the computing unit to complete the computing operation or for the interface circuit to complete the data output operation.

[0062] In some embodiments, reference Figure 2, the mode control circuit 27 is located in the area where the interface circuit 21 is located. In addition, in some embodiments, the in-memory processing chip includes a storage chip and a computing chip, the storage circuit 22 is located on the storage chip, and the interface circuit 21 and the computing unit 23 are located on the computing chip.

[0063] Figure 8 This is a schematic diagram of the structure of a computing system provided in an embodiment of the present application. The computing system includes at least an external processor and an in-memory processing chip in any of the above embodiments. Figure 8 In some embodiments, the total bandwidth between the storage circuit 82 and the computing unit 83 in the in-memory processing chip is greater than the bandwidth between the in-memory processing chip 84 and the external processor. The external processor includes a central processing unit 85 (CPU). It should be noted that when the computing power of the in-memory processing chip 84 itself is low, it can also perform collaborative computing with an external graphics processing unit (GPU) and / or neural processing unit (NPU); when the computing power of the in-memory processing chip 84 itself is high, the in-memory processing chip 84 can independently complete the artificial intelligence computing.

[0064] It should be noted that the “connection” described in this application refers to the ability to perform data transmission or signal communication.

[0065] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application, so the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. An in-memory processing chip, characterized in that: It includes an interface circuit, a storage circuit and a computing unit; There is a first transmission path between the interface circuit and the storage circuit; A second transmission path is provided between the storage circuit and the computing unit; A third transmission path is provided between the interface circuit and the computing unit, and the third transmission path is independent of the first transmission path; Among them, the storage circuit receives model data from the interface circuit through the first transmission path, the calculation unit receives the model data from the storage circuit through the second transmission path, the calculation unit also receives initial data through the interface circuit and the third transmission path, and performs calculation processing on the initial data based on the model data to obtain processed target data, and the calculation unit is also used to output the target data through the third transmission path and the interface circuit.

2. The in-memory processing chip according to claim 1, characterized in that: The in-memory processing chip includes a plurality of the storage circuits and a plurality of the computing units, each computing unit corresponds to at least one storage circuit, different storage circuits have corresponding first transmission paths and second transmission paths, and different storage circuits are connected to the interface circuit via corresponding first transmission paths.

3. The in-memory processing chip according to claim 1, characterized in that: The first transmission path is also used to transmit the initial data and the target data, and the second transmission path is also used to transmit the initial data and the target data.

4. The in-memory processing chip according to claim 3, characterized in that: The bandwidth of the first transmission path and the second transmission path is greater than that of the third transmission path, and the priority of the third transmission path in transmitting the initial data and the target data is higher than that of the first transmission path and the second transmission path.

5. The in-memory processing chip according to claim 1 or 2, characterized in that: The in-memory processing chip further includes a gating circuit, through which the storage circuit is connected to the first transmission path or the second transmission path.

6. The in-memory processing chip according to claim 5, characterized in that: The gating circuit is also used to record the refresh information of the corresponding storage circuit, and to send the recorded refresh information to the interface circuit before the interface circuit is disconnected from the storage circuit or after it is reconnected.

7. The in-memory processing chip according to claim 5, characterized in that: The in-memory processing chip also includes: a storage controller, which is arranged between the corresponding storage circuit and the corresponding gating circuit, or between the corresponding gating circuit and the computing unit, and the storage controller is at least used to read data in the storage circuit.

8. The in-memory processing chip according to claim 5, characterized in that: The in-memory processing chip further includes: a mode control circuit, which is used to control the storage circuit to be connected to the first transmission path, or to control the storage circuit to be connected to the second transmission path.

9. The in-memory processing chip according to claim 8, characterized in that: The mode control circuit is also used to turn on or off the third transmission path.

10. The in-memory processing chip according to claim 8, characterized in that: The mode control circuit is located in the area where the interface circuit is located.

11. The in-memory processing chip according to claim 1, characterized in that: The total bandwidth between the storage circuit and the computing unit in the in-memory processing chip is greater than the bandwidth between the in-memory processing chip and an external processor.

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