Display panel, display panel control method, controller and display device

Abstract

The present disclosure provides a display panel, a control method for a display panel, a controller, and a display device, relating to the field of display technology. The display panel includes: multiple drive circuits and multiple pixel circuits, the pixel circuits including: a data write unit, an isolation unit, a first reset unit, and a drive unit; the drive circuit includes: an N-level first drive module and a K-level second drive module, the n-level first drive module is used to provide a first drive signal to the data write unit of the n-th row of pixel circuits, the n-level first drive module is used to provide a second drive signal to the first reset unit of the n+x-th row of pixel circuits, and the n-level second drive module is used to provide a third drive signal to the isolation unit of the n-th row of pixel circuits. The same drive module can be used for staggered driving, reducing the number of drive modules in a group of drive circuits and effectively narrowing the border.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and more particularly, to a display panel, a control method for a display panel, a controller, and a display device. Background Art

[0002] For general LTPO (Low Temperature Polycrystalline Oxide) circuits, the gate reset tube of the DTFT (driving transistor) and the TFT (Thin Film Transistor) used for data writing are affected by the circuit timing and need to be driven by two different driving signals, which can easily cause afterimages on the display panel.

[0003] Therefore, a new technical solution is urgently needed to solve the above technical problems. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this disclosure is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] A first aspect of an embodiment of the present disclosure provides a display panel including a plurality of driving circuits and a plurality of pixel circuits.

[0006] The pixel circuit includes: a data writing unit, an isolation unit, a first reset unit, and a driving unit, wherein the data writing unit is electrically connected to the first node, the isolation unit is electrically connected between the first node and a third node, the first reset unit is electrically connected to the third node, the first reset unit is used to transmit a first reset signal to the first node via the isolation unit, and the driving unit is electrically connected between the first node, the second node, and the third node;

[0007] The driving circuit includes: an N-level first driving module and a K-level second driving module, wherein the n-th-level first driving module is used to provide a first driving signal to a data writing unit of an n-th row of pixel circuits, the n-th-level first driving module is used to provide a second driving signal to a first reset unit of an n+x-th row of pixel circuits, and the n-th-level second driving module is used to provide a third driving signal to an isolation unit of an n-th row of pixel circuits, wherein n, x, N and K are all natural numbers greater than 0, n+x≤N, and n+x≤K.

[0008] In some embodiments, within the same frame, the effective level starting point of the third drive signal is before the first effective level starting point of the first drive signal, the effective level starting point of the third drive signal is before the first effective level starting point of the second drive signal, the effective level end point of the third drive signal is after the last effective level end point of the first drive signal, and the effective level end point of the third drive signal is after the last effective level end point of the second drive signal.

[0009] In some embodiments, the pixel circuit further includes:

[0010] A second reset unit, the second reset unit is electrically connected between the second node and the data writing unit, the second reset unit is used to transmit a second reset signal to the second node, the n-th level first driving module is used to provide a fourth driving signal to the second reset unit of the ny-th row pixel circuit, wherein, within the same frame image, the effective level end point of the third driving signal is before the first effective level starting point of the fourth driving signal, y is a natural number greater than 0, and 1≤y<n.

[0011] In some embodiments, the pixel circuit further includes: a first light emitting control unit, a second light emitting control unit, a light emitting unit, and a third reset unit;

[0012] One end of the first light emitting control unit is electrically connected to the second node, and the other end is used to receive the first power signal;

[0013] The second light emitting control unit is electrically connected to the third node and the fourth node respectively;

[0014] One end of the light emitting unit is electrically connected to the fourth node, and the other end is used to receive the second power signal;

[0015] The third reset unit is electrically connected to the fourth node, and is configured to transmit a third reset signal to the light emitting unit under the driving of any one of the first driving signal, the second driving signal, and the fourth driving signal.

[0016] In some embodiments, within the same frame, the first drive signal includes a first write timing segment and a first reset timing segment, and the second drive signal includes a second write timing segment and a second reset timing segment, wherein the effective level starting point of the third drive signal is before the first write timing segment and the second write timing segment, the effective level ending point of the third drive signal is after the first write timing segment and the second write timing segment, and the effective level ending point of the third drive signal is before the first reset timing segment and the second reset timing segment.

[0017] In some embodiments, when both the first drive signal and the second drive signal are multi-pulse waveforms, the time sequence of the effective level starting points of the first drive signal and the second drive signal are alternately spaced.

[0018] In some embodiments, the first reset unit includes a first transistor, the data writing unit includes a second transistor, both the first transistor and the second transistor are P-type, and the isolation unit includes a third transistor, which is N-type.

[0019] In some embodiments, the plurality of first driving modules are divided into two groups, the two groups of first driving modules are respectively disposed on both sides of the pixel circuit, each group of first driving modules includes a first-stage driving module to an N-stage driving module, and the first driving modules of the same stage are electrically connected to the pixel circuits of the same row;

[0020] The driving circuit further includes a plurality of third driving modules, and the third driving modules are used to provide light-emitting driving signals to the first light-emitting control unit and the second light-emitting control unit.

[0021] In some embodiments, a plurality of second driving modules are respectively disposed on both sides of the pixel circuit;

[0022] Each second driving module is correspondingly connected to at least two rows of pixel circuits, and each row of pixel circuits is correspondingly connected to two second driving modules on different sides;

[0023] A plurality of third driving modules are respectively arranged on both sides of the pixel circuit;

[0024] Each third driving module is correspondingly connected to at least two rows of pixel circuits, and each row of pixel circuits is correspondingly connected to two third driving modules on different sides.

[0025] In some embodiments, the second driving module is disposed on a side of the first driving module away from the pixel circuit, and the third driving module is disposed on a side of the second driving module away from the pixel circuit.

[0026] In some embodiments, a plurality of third driving modules are respectively disposed on both sides of the pixel circuit;

[0027] Each third driving module is correspondingly connected to at least two rows of pixel circuits, and each row of pixel circuits is correspondingly connected to one third driving module.

[0028] In some embodiments, the second driving module is arranged on one side of the pixel circuit, the third driving module is arranged on the other side of the pixel circuit, part of the first driving module is arranged between the second driving module and the pixel circuit, and part of the first driving module is arranged between the third driving module and the pixel circuit.

[0029] A second aspect of the present disclosure provides a method for controlling a display panel, which is applied to the display panel described above. The method includes:

[0030] Controlling the n-th stage first driving module in the driving circuit to provide a first driving signal to the data writing unit of the n-th row pixel circuit; and

[0031] Controlling the n-th stage first driving module in the driving circuit to provide a second driving signal to the first reset unit of the n+x-th row pixel circuit; and

[0032] Controlling the n-th stage second driving module in the driving circuit to provide a third driving signal to the isolation unit of the n-th row pixel circuit;

[0033] In the same frame, the effective level starting point of the third drive signal is before the first effective level starting point of the first drive signal, the effective level starting point of the third drive signal is before the first effective level starting point of the second drive signal, the effective level end point of the third drive signal is after the last effective level end point of the first drive signal, and the effective level end point of the third drive signal is after the last effective level end point of the second drive signal.

[0034] In some embodiments, the method further comprises:

[0035] The n-th level first driving module in the control driving circuit provides a fourth driving signal to the second reset unit of the ny-th row pixel circuit, wherein, within the same frame image, the effective level end point of the third driving signal is before the first effective level starting point of the fourth driving signal, y is a natural number greater than 0, and 1≤y<n.

[0036] In some embodiments, the method further comprises:

[0037] The control driving circuit provides any one of the first driving signal, the second driving signal and the fourth driving signal to the third reset unit of the pixel circuit, so that the third reset unit transmits the third reset signal to the light emitting unit.

[0038] In some embodiments, when both the first drive signal and the second drive signal are multi-pulse waveforms, the time sequence of the effective level starting points of the first drive signal and the second drive signal are alternately spaced.

[0039] A third aspect of the present disclosure provides a controller, including:

[0040] a memory storing a computer program;

[0041] The processor is used to call the computer program in the memory, and the computer program is used to execute the control method as described above.

[0042] A fourth aspect of the embodiments of the present disclosure provides a display device, comprising the display panel as described above and / or the controller as described above.

[0043] According to the above technical solution, the reset signal and data write signal in the existing driver circuit can be driven by the same set of drive signals. That is, the first drive signal and the second drive signal are combined into the same set, and staggered drive is performed using the same drive module. This can reduce the number of drive modules in a set of drive circuits, effectively narrowing the bezel.

[0044] The display panel of the present disclosure, and other advantages, objectives and features of the present disclosure will be reflected in part through the following description, and will also be understood by those skilled in the art through research and practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0046] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the exemplary embodiments below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present disclosure. The same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0048] Figure 1 A schematic structural block diagram of a driving circuit provided by the present disclosure;

[0049] Figure 2 A driving timing diagram of a driving circuit provided by the present disclosure;

[0050] Figure 3 A schematic structural block diagram of a display panel provided in an embodiment of the present disclosure;

[0051] Figure 4 A driving timing diagram of a driving circuit provided in an embodiment of the present disclosure;

[0052] Figure 5 A schematic structural block diagram of another display panel provided in an embodiment of the present disclosure;

[0053] Figure 6 A driving timing diagram of another driving circuit provided in an embodiment of the present disclosure;

[0054] Figure 7A schematic structural diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0055] Figure 8 A schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0056] Figure 9 A driving timing diagram of another driving circuit provided in an embodiment of the present disclosure;

[0057] Figure 10 A driving timing diagram of another driving circuit provided in an embodiment of the present disclosure;

[0058] Figure 11 A schematic structural block diagram of a driving circuit provided in an embodiment of the present disclosure;

[0059] Figure 12 A schematic structural block diagram of another driving circuit provided in an embodiment of the present disclosure;

[0060] Figure 13 A schematic structural block diagram of another driving circuit provided in an embodiment of the present disclosure;

[0061] Figure 14 A schematic structural block diagram of another driving circuit provided in an embodiment of the present disclosure;

[0062] Figure 15 A schematic structural block diagram of a driving circuit provided in an embodiment of the present disclosure;

[0063] Figure 16 A schematic structural block diagram of another driving circuit provided in an embodiment of the present disclosure;

[0064] Figure 17 A schematic flow chart of a control method provided in an embodiment of the present disclosure;

[0065] Figure 18 A schematic structural block diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0067] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or that are inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments.

[0068] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0069] Typically, for AMOLED (Active-matrix organic light-emitting diode) display devices, the pixel circuit requires multiple drive signals. In order to generate these drive signals that are turned on / off in sequence, GOA (Gate On Array) circuits are set on both sides of the AA (Active Area) area. The pixel circuit cannot be placed at the same time in the area where the GOA circuit is placed, thus forming a border area around the display device that cannot emit light. In order to ensure the image quality of the AA area, the number of different drive signals required by the pixel structure is increasing, and correspondingly, the number of GOA circuits is also increasing, which is obviously not in line with the design concept of narrowing the border. However, if some important drive signals are forced to drive the pixel circuit unilaterally in order to narrow the border, it will also affect the screen image quality.

[0070] Figure 1 This is a schematic structural block diagram of a driving circuit provided by the present disclosure. Figure 1As shown, "EM T5&T6" represents a driving module for generating a light-emitting control signal EM, which is used to drive T5 and T6. T5 and T6 represent transistors for light-emitting control. When T5 and T6 are turned on, the light-emitting control unit can be considered to be turned on. "Gate_N T2" represents a driving module for generating an N-Gate signal, which is used to drive T2. T2 represents a transistor for isolation. "P-Gate T4" represents a driving module for generating a P-Gate signal, which is used to drive T4, where T4 is a data writing transistor. "Reset-P T1" represents a driving module for generating a driving reset signal Reset-P, which is used to drive T1, where T1 represents a transistor for resetting the gate of the driving transistor. "Reset-H T7&T8" represents a driving module for generating a driving reset signal Reset-H, which is used to drive T7 and T8. T7 represents a transistor for resetting the light-emitting unit. T8 represents a transistor for resetting the input terminal of the driving transistor. Since the P-Gate signal is used to drive the data writing transistor, the driving strength of the P-Gate signal has the greatest impact on the image quality compared to the other four groups of driving signals, so a P-Gate driving signal is used to drive both sides of a row of pixel circuits. Figure 1 denoted as "row_n" and "row_n+1," where row_n represents the nth row of pixel circuits and row_n+1 represents the n+1th row of pixel circuits. For the remaining drive signals, a one-to-two unilateral drive is employed. For example, a single emission control signal EM is used to simultaneously drive two rows of pixel circuits, employing a unilateral drive approach.

[0071] Figure 2 This is a driving timing diagram of a driving circuit provided by the present disclosure. Figure 2 As shown, each set of drive signals has a different waveform, making it impossible to use the same driver module. This can easily cause the display panel to produce afterimages, resulting in poor image quality. Furthermore, since the same driver module cannot be used, a new driver module must be added, resulting in a wider bezel on the display device.

[0072] In order to solve the above technical problems, according to the first aspect of the present disclosure, Figure 3 A schematic structural block diagram of a display panel provided in an embodiment of the present disclosure. Figure 3 , the display panel 300 may include a plurality of driving circuits 310 and a plurality of pixel circuits 320. For example, referring to Figure 3, the pixel circuit 320 may include: a data writing unit 321, an isolation unit 322, a first reset unit 323 and a driving unit 324. The data writing unit 321 is electrically connected to the first node N1. The isolation unit 322 is electrically connected between the first node N1 and the third node N3. The first reset unit 323 is electrically connected to the third node N3. The first reset unit 323 is used to transmit the first reset signal Vinit1 to the first node N1 via the isolation unit 322. The driving unit 324 is electrically connected between the first node N1, the second node N2 and the third node N3. The driving circuit 310 may include: an N-level first driving module 311 and a K-level second driving module 312, where N represents the total number of levels of the first driving module 311 and K represents the total number of levels of the second driving module 312. Figure 3 As shown, the n-th first driver module 311 is configured to provide a first drive signal Gate1(n) to the data write unit 321 of the n-th row of pixel circuits 320. The n-th first driver module 311 is configured to provide a second drive signal Gate2(n+x) to the first reset unit 323 of the n+x-th row of pixel circuits. The n-th second driver module 312 is configured to provide a third drive signal Gate3(n) to the isolation unit 322 of the n-th row of pixel circuits 320. n, x, N, and K are all natural numbers greater than 0, where n+x≤N and n+x≤K.

[0073] It should be noted that when the transistors driven by the first drive signal, the second drive signal, and the third drive signal are P-type transistors, the effective levels of the first drive signal, the second drive signal, and the third drive signal are low levels. When the transistors driven by the first drive signal, the second drive signal, and the third drive signal are N-type transistors, the effective levels of the first drive signal, the second drive signal, and the third drive signal are high levels.

[0074] In some embodiments, the pixel circuit may further include: a first light-emitting control unit, a second light-emitting control unit, and a light-emitting unit. The driving circuit may further include multiple third driving modules. The third driving modules are configured to provide light-emitting drive signals to the first and second light-emitting control units. Exemplarily, one end of the first light-emitting control unit is electrically connected to the second node, and the other end is configured to receive a first power supply signal. Driven by the light-emitting drive signal, the first light-emitting control unit controls the conduction between the first power supply and the second node. When conduction occurs between the first power supply and the second node, the first power supply signal is written to the second node. The second light-emitting control unit is electrically connected to the third and fourth nodes, respectively. Driven by the light-emitting drive signal, the second light-emitting control unit controls the conduction between the third and fourth nodes. The light-emitting unit has one end electrically connected to the fourth node, and the other end is configured to receive a second power supply signal. When the first and second light-emitting control units, as well as the driving unit, are all conductive, the light-emitting unit emits light in response to the first and second power supply signals. Exemplarily, the third node may be connected to a pixel electrode, and the display panel may be a liquid crystal display panel. Exemplarily, the light-emitting unit may be a light-emitting device, and the display panel may be an active light emitting display panel.

[0075] Exemplary, reference Figure 3 The isolation unit 322 can control the conduction and cutoff between the first node N1 and the third node N3. When the isolation unit 322 is conductive, the first reset unit 323 can transmit a first reset signal Vinit1 to the first node N1 via the isolation unit 322. The first reset signal Vinit1 can reset the gate of the driving transistor. When the driving unit includes a driving transistor, the first node N1 can represent a node directly connected to the gate of the driving transistor. That is, the first node N1 can be equivalent to the gate of the driving transistor.

[0076] It should be noted that in order to better meet the low-frequency functional requirements of the driving circuit, the transistor directly connected to the first node N1 is an N-type transistor. Therefore, an N-type transistor can be set in the isolation unit, and the N-type transistor is electrically connected to the first node N1. In some embodiments, the first reset unit may include a first transistor, the data write unit may include a second transistor, the first transistor and the second transistor may both be P-type, and the isolation unit may include a third transistor, and the third transistor is N-type. In other embodiments, the first transistor and the second transistor may both be N-type, and the third transistor is also N-type. Therefore, providing an isolation unit between the first reset unit and the first node can reduce the restrictions on the transistor type in the first reset unit, so that the above technical solution can be applied to a wider range of circuit structures. Among them, the P-type transistor can be LTPS (Low Temperature Poly-Silicon, low temperature polycrystalline silicon), and the N-type transistor can be LTPO (Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide).

[0077] For example, the following description is based on the example of the first transistor and the second transistor being P-type transistors and the third transistor being an N-type transistor. It should be noted that when the first transistor, the second transistor, and the third transistor are all N-type transistors, the specific implementation can be understood in conjunction with the following detailed description, which will not be elaborated on in detail for the sake of brevity.

[0078] For example, see Figure 3, the first driving module in the driving circuit can be used to provide a first driving signal Gate1(n) to the data writing unit in the n-th row of pixel circuits. The first driving module at the same level can be used to provide a second driving signal Gate2(n+x) to the first reset unit in the n+x-th row of pixel circuits. The first driving signal and the second driving signal can be different branch output signals of the same signal generated by the same driving module. The occurrence time of the first effective level starting point of the first driving signal and the second driving signal can be related to the number of rows x of pixel circuits that differ. For example, when x=1, the first effective level starting point of the first driving signal can be 1h later than the first effective level starting point of the second driving signal, where h can represent the refresh time of a row of pixel circuits, and h=the inverse of (refresh rate×number of pixel circuit rows). Therefore, the first driving signal can be represented by P-Gate(n). The second driving signal can be represented by P-Gate(n+x). The second driving module at the same level can be used to provide a third driving signal N-Gate(n) to the isolation unit of the n-th row of pixel circuits. For example, if the effective level is a high level, the corresponding effective level starting point may be the moment when the signal changes from a low level to a high level, and the effective level end point may be the moment when the signal changes from a high level back to a low level. If the effective level is a low level, the corresponding effective level starting point may be the moment when the signal changes from a high level to a low level, and the effective level end point may be the moment when the signal changes from a low level back to a high level.

[0079] Thus, the same first driving module can be used to provide a first driving signal to the pixel circuit in the nth row and a second driving signal to the pixel circuit in the (n+x)th row, thereby realizing the use of the same driving module to provide different driving signals to pixel circuits in different rows, thereby effectively reducing the number of driving modules in the driving circuit.

[0080] Figure 4 A driving timing diagram of a driving circuit provided in an embodiment of the present disclosure. For example, refer to Figure 4 , the difference between the first effective level starting point of the first driving signal P-Gate(n) and the second driving signal P-Gate(n+x) is xh. Figure 2 Compared to the signal timing diagram, the duration of the active level of the first drive signal P-Gate(n) and the second drive signal P-Gate(n+x) is equal. Furthermore, logically, the Reset-P signal can also achieve the corresponding reset function by driving it using the corresponding driver module of P-Gate. Therefore, the second drive signal P-Gate(n+x) can replace the existing drive reset signal Reset-P. The second drive signal P-Gate(n+x) can be output by the same driver module as the first drive signal P-Gate(n).

[0081] In the disclosed embodiments, the reset signal Reset-P and the data write signal P-Gate in the existing driver circuit can be driven by the same set of drive signals. That is, the first drive signal and the second drive signal are combined into a single set, and staggered drive is performed using the same drive module. This reduces the number of drive modules in a set of drive circuits, effectively narrowing the bezel.

[0082] In some embodiments, within the same frame, the effective level starting point of the third drive signal is before the first effective level starting point of the first drive signal, the effective level starting point of the third drive signal is before the first effective level starting point of the second drive signal, the effective level end point of the third drive signal is after the last effective level end point of the first drive signal, and the effective level end point of the third drive signal is after the last effective level end point of the second drive signal.

[0083] For example, the driving circuit can provide a scanning signal to the pixel circuit, and the pixel circuit can be scanned row by row based on the scanning signal. The picture corresponding to the first row of pixel circuits and the last row of pixel circuits can be called a frame. Taking up and down scanning as an example, the first row can represent the bottom row of pixel circuits or the top row of pixel circuits. When the scanning mode is left and right scanning, the first row can represent the leftmost row of pixel circuits or the rightmost row of pixel circuits. The last row corresponds to the first row. See Figure 4 In the same frame, the rising edge of the third drive signal N-Gate(n) is before the falling edge of the first drive signal P-Gate(n) and the second drive signal P-Gate(n+x), and the falling edge of the third drive signal N-Gate(n) is before the rising edge of the first drive signal P-Gate(n) and the second drive signal P-Gate(n+x). That is, the first drive signal P-Gate(n) and the second drive signal P-Gate(n+x) are included in a valid level range of the third drive signal N-Gate(n). The third drive signal N-Gate(n) is used to control the conduction and cutoff of the isolation unit 322. Figure 4, when the third drive signal N-Gate(n) is at a high level (valid level), the isolation unit 322 is turned on. At this time, the first reset unit 323 can provide the first reset signal Vinit1 to the first node N1. The first reset signal Vinit1 is thereby used to reset the first node N1. Afterwards, the data write unit 321 can write the data signal Data to the first node N1. When the first drive signal P-Gate(n) and the second drive signal P-Gate(n+x) are both within the range of a valid level of the third drive signal N-Gate(n), it can be ensured that the first reset signal Vinit1 is effectively given to the first node N1, thereby ensuring that the image quality after the data signal Data is written is better. Among them, the same frame picture can be the same frame picture, or it can be multiple frames within a predetermined time, and the number of frames is not limited here. For example, the following description is made using the same frame picture as an example.

[0084] Thus, the first driving signal and the second driving signal are included in a valid level range of the third driving signal, which can ensure the reset of the gate of the driving transistor and the effective writing of the data signal Data, and help improve the afterimage.

[0085] In some embodiments, the pixel circuit may further include a second reset unit. Figure 5 A schematic structural block diagram of another display panel provided in an embodiment of the present disclosure. Figure 5 The second reset unit 325 is electrically connected between the second node N2 and the data writing unit 321. The second reset unit 325 is used to transmit the second reset signal Vinit2 to the second node N2. The n-th level first driving module 311 is used to provide the fourth driving signal Gate4(ny) to the second reset unit 325 of the ny-th row pixel circuit 320, wherein, within the same frame image, the effective level end point of the third driving signal Gate3(n) is before the first effective level starting point of the fourth driving signal Gate4(ny), y is a natural number greater than 0, and 1≤y<n.

[0086] Figure 6 A driving timing diagram of another driving circuit provided in an embodiment of the present disclosure. Exemplarily, similar to the data writing unit and the first reset unit, the second reset unit also includes a transistor. The transistor in the second reset unit can be of the same type as the first transistor and the second transistor. In this embodiment, the transistor in the second reset unit is also a P-type transistor. Therefore, when the transistors in the data writing unit, the first reset unit, and the second reset unit are of the same type, it is more convenient to use the same driving module to output the same driving signal for staggered driving, thereby effectively reducing the number of driving modules in the driving circuit. Reference Figure 5 and Figure 6, the first driving module can be used to provide a first driving signal Gate1(n) to the data writing unit in the pixel circuit of the nth row. The first driving module of the same level can be used to provide a second driving signal Gate2(n+x) to the first reset unit in the pixel circuit of the n+xth row. The first driving module of the same level can be used to provide a fourth driving signal Gate4(n+x) to the second reset unit in the pixel circuit of the nyth row. Among them, the first driving signal, the second driving signal and the fourth driving signal can be different branch output signals of the same signal generated by the same driving module. The occurrence time of the first effective level starting point of the first driving signal and the second driving signal can be related to the number of rows x of the pixel circuits that differ. The occurrence time of the first effective level starting point of the first driving signal and the fourth driving signal can be related to the number of rows y of the pixel circuits that differ. Reference Figure 6 , the difference between the first effective level starting point of the first driving signal P-Gate(n) and the fourth driving signal P-Gate(ny) is yh. Figure 2 Compared with the signal timing diagram of , the duration of the effective level of the first driving signal P-Gate(n) and the fourth driving signal P-Gate(ny) is equal. Figure 2 Removing the first pulse of the drive reset signal Reset-H in the circuit does not negatively impact circuit debugging. Therefore, for similar reasons to the second drive signal P-Gate(n+x), the existing drive reset signal Reset-H can be replaced with the fourth drive signal P-Gate(ny). The fourth drive signal P-Gate(ny) can be output from the same drive module, along with the first drive signal P-Gate(n) and the second drive signal P-Gate(n+x), in staggered configurations.

[0087] See also Figure 6 Within the same frame, the effective level endpoint of the third drive signal N-Gate(n) precedes the first effective level starting point of the fourth drive signal P-Gate(ny). Specifically, when the third drive signal is low and the isolation unit 322 is turned off, the fourth drive signal P-Gate(ny) becomes effective. The fourth drive signal P-Gate(ny) can drive the second reset unit to transmit the second reset signal Vinit2 to the second node N2, thereby resetting the second node N2.

[0088] Thus, the fourth driving signal can be combined with the first driving signal and the second driving signal into one group, and staggered driving can be performed using the same driving module, which can effectively reduce the number of driving modules in the driving circuit and effectively narrow the frame.

[0089] Figure 7 A schematic structural diagram of a pixel circuit provided in an embodiment of the present disclosure. Figure 7 The first light-emitting control unit 326 may include a transistor T5. One end of the transistor T5 is electrically connected to the second node N2, and the other end is configured to receive the first power supply signal VDD. The second light-emitting control unit 327 may include a transistor T6. The transistor T6 is electrically connected to the third node N3 and the fourth node N4, respectively. The light-emitting unit 328 may have one end electrically connected to the fourth node N4, and the other end is configured to receive the second power supply signal VSS. The third reset unit 329 may include a transistor T7. The transistor T7 is electrically connected to the fourth node N4.

[0090] Exemplary, reference Figure 7 When a second reset unit 325 is present in the pixel circuit, the second reset unit 325 may include a transistor T8. The second reset unit 325 may be used to provide a second reset signal Vinit2 to the second node N2 to reset the second node. At the same time, the third reset unit 329 may be used to provide a third reset signal Vinit3 to the light-emitting unit 328 to reset the light-emitting unit 328. At this time, the gate drive signal of the transistor T7 of the third reset unit 329 may be any one of the first drive signal P-Gate(n), the second drive signal P-Gate(n+x), and the fourth drive signal P-Gate(ny). Therefore, the drive signal of the transistor T7 may be combined with the first drive signal P-Gate(n), the second drive signal P-Gate(n+x), and the fourth drive signal P-Gate(ny) into a group and driven in a staggered manner using the same drive module.

[0091] Figure 8 A schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure. Figure 8 , the second reset unit 325 does not exist in the pixel circuit. The transistor T4 in the data write unit 321 can be used to reset the second node. At this time, the drive signal of transistor T7 can be the first drive signal P-Gate(n) or the second drive signal P-Gate(n+x). Therefore, the drive signal of transistor T7 can also be combined with the first drive signal P-Gate(n) and the second drive signal P-Gate(n+x) into a group, and staggered drive can be used using the same drive module.

[0092] Therefore, the gate signal of the transistor T7 in the third reset unit 329 can be any one of the existing drive signals for driving transistors of the same type. There is no need to add a new drive signal, which reduces the setting of the drive module in the drive circuit and can affect the width of the border to a certain extent.

[0093] refer to Figure 8When the transistor T4 in the data writing unit 321 is used to perform a reset operation on the second node, the first driving signal and the second driving signal can be divided into time segments within the same frame. Figure 9 A driving timing diagram of another driving circuit provided in an embodiment of the present disclosure. For example, refer to Figure 9 The first drive signal P-Gate(n) may include a first write timing segment 910 and a first reset timing segment 920. The second drive signal P-Gate(n+x) may include a second write timing segment 930 and a second reset timing segment 940. The rising edge of the third drive signal N-Gate(n) occurs before the first write timing segment 910 and the second write timing segment 930, the falling edge of the third drive signal N-Gate(n) occurs after the first write timing segment 910 and the second write timing segment 930, and before the first reset timing segment 920 and the second reset timing segment 940. As described above, the third drive signal N-Gate(n) is used to control the isolation unit 322 to be turned on and off. When the third drive signal N-Gate(n) is a high-level signal, the isolation unit can be turned on. When the third drive signal N-Gate(n) is a low-level signal, the isolation unit can be turned off. Thus, when the isolation unit 322 is in the on state, the first node N1 can be reset and data written to the first node N1 can be completed using the first reset unit 323 driven by the signal of the first write timing section 910 and the data write unit 321 driven by the signal of the second write timing section 930. When the isolation unit 322 is in the off state, the second node N2 can be reset using the data write unit 321 driven by the signal of the second reset timing section 940.

[0094] Therefore, when the pixel circuit does not have a bias unit (ie, the second reset unit 325), the data writing unit 321 can be used to replace the bias unit to achieve the reset of the second node N2.

[0095] Figure 10 A driving timing diagram of another driving circuit provided in an embodiment of the present disclosure. For example, refer to Figure 10 , the first driving signal P-Gate(n) and the second driving signal P-Gate(n+x) are both multi-pulse waveforms. Figure 10In the embodiment shown, a 3-pulse waveform is shown. The effective level starting point of each pulse of the first drive signal P-Gate(n) is shown as 1010. The effective level starting point of each pulse of the second drive signal P-Gate(n+x) is shown as 1020. The time sequence of the effective level starting points of the first drive signal P-Gate(n) and the second drive signal P-Gate(n+x) is alternately spaced, and both are located within the effective level period of 1 N-Gate(n). In other words, the effective level starting points of the first drive signal P-Gate(n) and the second drive signal P-Gate(n+x) appear alternately in time sequence. Figure 10 , the time sequence of the effective level starting points may be: the first effective level starting point of the second drive signal P-Gate(n+x), the first effective level starting point of the first drive signal P-Gate(n), the second effective level starting point of the second drive signal P-Gate(n+x), the second effective level starting point of the first drive signal P-Gate(n), the third effective level starting point of the second drive signal P-Gate(n+x), and the third effective level starting point of the first drive signal P-Gate(n).

[0096] Therefore, it is ensured that each resetting and data writing to the first node N1 is not interfered with by other signals, which is beneficial to improving afterimage and enhancing image quality.

[0097] It should be noted that Figure 10 The illustrated embodiment uses 3 pulses as an example. In actual applications, the number of pulses can be appropriately set based on screen refresh time and image quality requirements, and is not limited here. The number of pulses is inversely proportional to the screen refresh time; a greater number of pulses results in a longer refresh time. The number of pulses is directly proportional to image quality; a greater number of pulses results in better image quality. Therefore, the number of pulses can be set based on their impact on both factors.

[0098] It should be noted that the driver module corresponding to the pixel circuit in the nth row can output any set of signals from P-Gate(ny) to P-Gate(n+x). For example, when the output signal is P-Gate(n+a), an additional a+y driver module can be placed above the driver module corresponding to the pixel circuit in the nth row, and an additional xa driver module can be placed below it. Where a is an integer, -y≤a≤x.

[0099] Figure 11 This is a schematic structural block diagram of a driving circuit provided by an embodiment of the present disclosure. Figure 11, multiple first driving modules 311 are divided into two groups. The two groups of first driving modules 311 are respectively arranged on both sides of the pixel circuit 320. Each group of first driving modules 311 includes the first-level first driving module to the N-level driving module. The first driving modules 311 of the same level are electrically connected to the pixel circuits 320 of the same row. Two first-level first driving modules 311 are electrically connected on both sides of the first row of pixel circuits 320. Two second-level first driving modules 311 are electrically connected on both sides of the second row of pixel circuits 320. Two N-level first driving modules 311 are electrically connected on both sides of the N-th row of pixel circuits 320. Reference Figure 11 , two first driving modules 311 of the same level are connected to the pixel circuit 320 of the same row and are respectively placed on both sides of the pixel circuit 320. It should be noted that, Figure 11 In the embodiment shown, the first driving module 311 and the pixel circuit 320 are in a one-to-one bilateral driving relationship. The use of the bilateral driving method can ensure that both sides of the pixel circuit have driving signals and the driving signals are the same, effectively improving image quality.

[0100] Figure 12 This is a schematic structural block diagram of another driving circuit provided by an embodiment of the present disclosure. Figure 12 , multiple second driving modules 312 are respectively arranged on both sides of the pixel circuit 320. Each second driving module 312 is connected to at least two rows of pixel circuits 320. For example, Figure 12 For the first-level second driving module 312 in the upper left corner, it is electrically connected to the first row of pixel circuits 320 and the second row of pixel circuits 320 at the same time. Similarly, for the first-level second driving module 312 in the upper right corner, it is also electrically connected to the first row of pixel circuits 320 and the second row of pixel circuits 320 at the same time. Each row of pixel circuits 320 is correspondingly connected to two second driving modules 312 on different sides. For example, for Figure 12 For the first row of pixel circuits, two sides are connected to a second driving module 312. Figure 12 In the illustrated embodiment, the second driving module 312 and the pixel circuit 320 form a one-to-two bilateral driving relationship.

[0101] Figure 13 This is a schematic structural block diagram of another driving circuit provided by an embodiment of the present disclosure. Figure 13 , multiple third driving modules are respectively arranged on both sides of the pixel circuit 320. Each third driving module is connected to at least two rows of pixel circuits 320. For example, for Figure 13For the third driving module of the first level in the upper left corner, it is electrically connected to the first row of pixel circuits 320 and the second row of pixel circuits 320 at the same time. Similarly, for the third driving module of the first level in the upper right corner, it is also electrically connected to the first row of pixel circuits 320 and the second row of pixel circuits 320 at the same time. Each row of pixel circuits 320 is connected to two third driving modules on different sides. For example, for Figure 13 For the first row of pixel circuits, two sides are connected to a third driving module. Figure 13 In the illustrated embodiment, the third driving module and the pixel circuit 320 form a one-to-two bilateral driving relationship.

[0102] Combined with the aforementioned driver module placement, the first, second, and third driver modules can drive the pixel circuit from both sides, significantly improving image quality. This avoids image quality degradation caused by the third driver signal N-Gate's inability to drive both sides, which can be associated with issues such as reliability streaks and unilateral dimming.

[0103] Figure 14 This is a schematic structural block diagram of another driving circuit provided by an embodiment of the present disclosure. For example, in order to reduce the interference of the connection on the relationship display of each module, Figure 14 The electrical connection relationship between the driving module and the pixel circuit is not shown. Figure 11-13 The corresponding electrical connection relationship between each driving module and the pixel circuit can be known. In addition, in order to simplify the image, Figure 14 Only the relationship between two rows of pixel circuits and each driving module and the placement position of each driving module are shown. Figure 14 The embodiment shown can obtain the relationship between other rows of pixel circuits and each driving module, which will not be listed here one by one. Figure 14 For the first row of pixel circuits, the first-stage first driver module 311 is disposed at the innermost side. The first-stage second driver module 312 is disposed on the side of the first-stage first driver module 311 away from the first row of pixel circuits 320. In other words, the first-stage first driver module 311 is disposed between the first-stage second driver module 312 and the first row of pixel circuits 320. The first-stage third driver module is disposed on the side of the first-stage second driver module 312 away from the first row of pixel circuits 320. In other words, the first-stage third driver module is disposed at the outermost side and is the farthest away from the first row of pixel circuits 320.

[0104] Because the first driver module 311 and the pixel circuit 320 have a one-to-one bilateral driving relationship, while the other two driver modules each have a one-to-two bilateral driving relationship, the first driver module 311 is positioned closest to the pixel circuit 320 to simplify wiring design and facilitate manufacturing. The second and third driver modules 312 can be positioned interchangeably based on actual needs.

[0105] Figure 15 This is a schematic structural block diagram of a driving circuit provided by an embodiment of the present disclosure. Figure 15 , multiple third driving modules are respectively arranged on both sides of the pixel circuit 320. Each third driving module is connected to at least two rows of pixel circuits 320, and each row of pixel circuits 320 is connected to a third driving module. For example, the third driving module of the first level on the left can be electrically connected to the pixel circuits 320 of the first and second rows, and the third driving module of the first level on the right can be electrically connected to the pixel circuits 320 of the third and fourth rows. Figure 14 Compared with the embodiment shown in FIG, the width of the third driving module is narrowed and the length is increased. It can be considered that the effective area of ​​the third driving module remains substantially unchanged, ensuring the normal driving function of the third driving module. Figure 14 Compared to the embodiment shown. Figure 15 In the embodiment shown, one third driving module can be reduced on one side, thereby narrowing the frame width corresponding to half of the driving modules.

[0106] Figure 16 This is a schematic structural block diagram of another driving circuit provided by an embodiment of the present disclosure. Figure 16 For the first row of pixel circuits, the first-stage second driver module 312 is disposed on the left side of the first row of pixel circuits 320. The first-stage third driver module is disposed on the right side of the first row of pixel circuits 320. Part of the first-stage first driver module 311 is disposed between the first-stage second driver module 312 and the first row of pixel circuits 320, and part of the first-stage first driver module 31 is disposed between the first-stage third driver module and the first row of pixel circuits 320.

[0107] In this way, a set of driver modules can be saved, and the border can be narrowed as much as possible while ensuring the image quality.

[0108] It should be noted that Figures 11-16 It is merely a schematic block diagram of the driving circuit structure and does not imply a specific limitation on the placement of each driving module and the connection relationship between each driving module and the pixel circuit.

[0109] A second aspect of the embodiments of the present disclosure provides a method for controlling a display panel, which is applied to the display panel as described above. Figure 17Schematic flow chart of a control method provided by an embodiment of the present disclosure. Figure 17 As shown, the above control method may include the following steps.

[0110] Step S1710, controlling the n-th stage first driving module in the driving circuit to provide a first driving signal to the data writing unit of the n-th row pixel circuit; and

[0111] Step S1720, controlling the n-th stage first driving module in the driving circuit to provide a second driving signal to the first reset unit of the n+x-th row pixel circuit; and

[0112] Step S1730 : Control the n-th stage second driving module in the driving circuit to provide a third driving signal to the isolation unit of the n-th row of pixel circuits.

[0113] Exemplarily, according to the control instruction, the n-th level first driver module can be controlled to provide a first drive signal to the data writing unit of the n-th row pixel circuit. According to the control instruction, the n-th level first driver module can also be controlled to provide a second drive signal to the first reset unit of the n+x-th row pixel circuit. The first drive signal and the second drive signal can be different branch output signals of the same signal generated by the same driver module. The time of occurrence of the first effective level starting point of the first drive signal and the second drive signal can be related to the number of rows x of the pixel circuits that differ. According to the control instruction, the n-th level second driver module can also be controlled to provide a third drive signal to the isolation unit of the n-th row pixel circuit. The time when the driver circuit provides the first drive signal, the second drive signal and the third drive signal is not fixed. The three signals can be provided simultaneously or in a time-sharing manner. The above steps S1710-S1730 are only for the convenience of description and drawing, and do not mean that the above three steps have a sequence of execution. In addition, Figure 17 In the embodiment shown, the order in which the steps appear does not necessarily mean the order in which the steps will be actually executed.

[0114] In some embodiments, the method may further include: controlling the n-th level first driving module in the driving circuit to provide a fourth driving signal to the second reset unit of the ny-th row pixel circuit, wherein, within the same frame image, the effective level end point of the third driving signal is before the first effective level starting point of the fourth driving signal, y is a natural number greater than 0, and 1≤y<n.

[0115] For example, a first driver module at the same level as the one that provides the first and second driver signals can be used to provide a fourth driver signal to the second reset unit in the pixel circuit in the nyth row. The first, second, and fourth driver signals can be branched output signals of the same signal generated by the same driver module. The time at which the first effective level starting point of the first and second driver signals occurs can be related to the number of pixel circuit rows x that differ. The time at which the first effective level starting point of the first and fourth driver signals occurs can be related to the number of pixel circuit rows y that differ. Thus, the fourth driver signal can be combined with the first and second driver signals into a group, and staggered driving can be performed using the same driver module.

[0116] In some embodiments, the method further includes: controlling the driving circuit to provide any one of the first driving signal, the second driving signal, and the fourth driving signal to the third reset unit of the pixel circuit, so that the third reset unit transmits a third reset signal to the light emitting unit.

[0117] In some embodiments, when both the first drive signal and the second drive signal are multi-pulse waveforms, the time sequence of the effective level starting points of the first drive signal and the second drive signal are alternately spaced.

[0118] For example, when the effective level starting points of the first drive signal and the second drive signal are offset by 1 hour, the gates of T1 and T4 can be turned on 1 hour earlier, thereby achieving a multi-pulse gate reset of the drive transistor. The offset time can be any natural number greater than or equal to 1.

[0119] A third aspect of an embodiment of the present disclosure provides a controller, comprising: a memory storing a computer program; and a processor for calling the computer program in the memory, wherein the computer program is used to execute the control method described above.

[0120] For example, the controller can be integrated into the driving circuit, the driving circuit can use a driving chip to implement the above driving function, and the driving chip can be bound to the non-display area of ​​the display panel. In some embodiments, the controller can also be integrated into the driving chip.

[0121] A fourth aspect of the embodiments of the present disclosure provides a display device, comprising the display panel as described above and / or the controller as described above. Figure 18 This is a schematic structural block diagram of a display device provided by an embodiment of the present disclosure. Figure 18 In the embodiment shown, the display device 1800 may include both the display panel 1810 and the controller 1820 as described above. In some embodiments, the display device 1800 may further include one of the display panel 1810 and the controller 1820.

[0122] For example, the display device of the embodiment of the present disclosure can be applied to scenarios such as vehicle-mounted display, smart phones, computers, medical displays, televisions, smart wearable displays, etc. Smart wearable devices may include smart watches, AR (augmented reality) devices, and VR (virtual reality) devices, etc., which are not specifically limited by the embodiment of the present disclosure.

[0123] A person skilled in the art can understand the specific details and beneficial effects of the control method, controller and display device of the display panel by reading the above description of the display panel, and will not be repeated here for the sake of brevity.

[0124] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and / or equipment can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0125] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0126] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0127] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the various embodiments of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0128] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display panel, characterized in that: including a plurality of driving circuits and a plurality of pixel circuits, The pixel circuit includes: a data writing unit, an isolation unit, a first reset unit, and a driving unit, wherein the data writing unit is electrically connected to a first node, the isolation unit is electrically connected between the first node and a third node, the first reset unit is electrically connected to the third node, the first reset unit is configured to transmit a first reset signal to the first node via the isolation unit, and the driving unit is electrically connected between the first node, the second node, and the third node; The driving circuit includes: N-level first driving modules and K-level second driving modules, wherein the first driving module of the nth level is used to provide a first driving signal to the data writing unit of the pixel circuit of the nth row, the first driving module of the nth level is used to provide a second driving signal to the first reset unit of the pixel circuit of the n+xth row, and the second driving module of the nth level is used to provide a third driving signal to the isolation unit of the pixel circuit of the nth row, and n, x, N and K are all natural numbers greater than 0, n+x≤N, n+x≤K.

2. The display panel according to claim 1, wherein: In the same frame, the effective level starting point of the third drive signal is before the first effective level starting point of the first drive signal, the effective level starting point of the third drive signal is before the first effective level starting point of the second drive signal, the effective level end point of the third drive signal is after the last effective level end point of the first drive signal, and the effective level end point of the third drive signal is after the last effective level end point of the second drive signal.

3. The display panel according to claim 1, wherein: The pixel circuit further includes: A second reset unit, the second reset unit is electrically connected between the second node and the data writing unit, the second reset unit is used to transmit a second reset signal to the second node, the first driving module of the nth level is used to provide a fourth driving signal to the second reset unit of the pixel circuit of the nyth row, wherein, within the same frame image, the effective level end point of the third driving signal is before the first effective level starting point of the fourth driving signal, y is a natural number greater than 0, and 1≤y<n.

4. The display panel according to any one of claims 1 to 3, characterized in that The pixel circuit further includes: a first light emitting control unit, a second light emitting control unit, a light emitting unit and a third reset unit; One end of the first light emitting control unit is electrically connected to the second node, and the other end is used to receive a first power signal; The second light emitting control unit is electrically connected to the third node and the fourth node respectively; One end of the light emitting unit is electrically connected to the fourth node, and the other end is used to receive a second power signal; The third reset unit is electrically connected to the fourth node, and is configured to transmit a third reset signal to the light emitting unit under the driving of any one of the first driving signal, the second driving signal, and the fourth driving signal.

5. The display panel according to claim 2, wherein: Within the same frame, the first drive signal includes a first write timing segment and a first reset timing segment, and the second drive signal includes a second write timing segment and a second reset timing segment, wherein the effective level starting point of the third drive signal is before the first write timing segment and the second write timing segment, the effective level end point of the third drive signal is after the first write timing segment and the second write timing segment, and the effective level end point of the third drive signal is before the first reset timing segment and the second reset timing segment.

6. The display panel according to claim 2, wherein: In the case that both the first driving signal and the second driving signal are multi-pulse waveforms, the time sequence of the effective level starting points of the first driving signal and the second driving signal are alternately spaced.

7. The display panel according to claim 1, wherein: The first reset unit includes a first transistor, the data writing unit includes a second transistor, both the first transistor and the second transistor are P-type, and the isolation unit includes a third transistor, which is N-type.

8. The display panel according to claim 4, wherein: The plurality of first driving modules are divided into two groups, the two groups of first driving modules are respectively arranged on both sides of the pixel circuit, each group of the first driving modules includes a first-stage first driving module to an N-stage first driving module, and the first driving modules of the same stage are electrically connected to the pixel circuits of the same row; The driving circuit further includes a plurality of third driving modules, and the third driving modules are configured to provide light-emitting driving signals to the first light-emitting control unit and the second light-emitting control unit.

9. The display panel according to claim 8, wherein: A plurality of the second driving modules are respectively arranged on both sides of the pixel circuit; Each of the second driving modules is correspondingly connected to at least two rows of pixel circuits, and each row of pixel circuits is correspondingly connected to two second driving modules on different sides; The plurality of third driving modules are respectively arranged on both sides of the pixel circuit; Each of the third driving modules is correspondingly connected to at least two rows of pixel circuits, and each row of pixel circuits is correspondingly connected to two third driving modules on different sides.

10. The display panel according to claim 9, wherein: The second driving module is disposed on a side of the first driving module away from the pixel circuit, and the third driving module is disposed on a side of the second driving module away from the pixel circuit.

11. The display panel according to claim 8, wherein The plurality of third driving modules are respectively arranged on both sides of the pixel circuit; Each of the third driving modules is correspondingly connected to at least two rows of pixel circuits, and each row of pixel circuits is correspondingly connected to one of the third driving modules.

12. The display panel according to claim 8, wherein The second driving module is arranged on one side of the pixel circuit, the third driving module is arranged on the other side of the pixel circuit, part of the first driving module is arranged between the second driving module and the pixel circuit, and part of the first driving module is arranged between the third driving module and the pixel circuit.

13. A method for controlling a display panel, characterized in that: Applied to the display panel according to any one of claims 1 to 12, the control method comprises: controlling the first driving module of the nth stage in the driving circuit to provide a first driving signal to the data writing unit of the pixel circuit of the nth row; and controlling the first driving module of the nth stage in the driving circuit to provide a second driving signal to the first reset unit of the pixel circuit of the n+xth row; and The n-th stage second driving module in the driving circuit is controlled to provide a third driving signal to the isolation unit of the n-th row of pixel circuits.

14. The control method according to claim 13, characterized in that: The method further comprises: Control the first driving module of the nth level in the driving circuit to provide a fourth driving signal to the second reset unit of the pixel circuit of the nyth row, wherein, within the same frame image, the effective level end point of the third driving signal is before the first effective level starting point of the fourth driving signal, y is a natural number greater than 0, and 1≤y<n.

15. The control method according to claim 13 or 14, characterized in that: The method further comprises: The driving circuit is controlled to provide any one of the first driving signal, the second driving signal, and the fourth driving signal to a third reset unit of the pixel circuit, so that the third reset unit transmits a third reset signal to the light emitting unit.

16. The control method according to claim 13, characterized in that: In the case that both the first driving signal and the second driving signal are multi-pulse waveforms, the time sequence of the effective level starting points of the first driving signal and the second driving signal are alternately spaced.

17. A controller, characterized in that: include: a memory storing a computer program; A processor is configured to call the computer program in the memory, wherein the computer program is configured to execute the control method according to any one of claims 13 to 16.

18. A display device, characterized in that: The device comprises the display panel according to any one of claims 1 to 12 and / or the controller according to claim 17.

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