Memory and method of making the same, layout structure
By setting slit patterns in the memory to avoid contact with the target pattern or pattern pillars, the problem of damage during fabrication is solved, and the density and reliability of the memory are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-08-08
- Publication Date
- 2026-07-10
AI Technical Summary
During the fabrication of the isolation structure between different read/write cell regions of a three-dimensional non-volatile memory, damage or breakage of the memory cells can easily occur, leading to a decrease in storage density, performance, and reliability.
By setting slit patterns or slit patterns between target patterns or pattern pillars, and ensuring that the length of the slit pattern in the first direction is not less than the size of the target pattern or pattern pillar in the first direction, the slit pattern avoids contact with its adjacent patterns. Wavy, zigzag, or combinations thereof are used to adapt to the actual distribution, thereby reducing the complexity and cost of fabrication.
It effectively avoids damage to the target pattern or pattern pillar caused by the fabrication of slit patterns, increases the distribution density per unit area, ensures the morphology and quality of the pattern, and improves the performance and reliability of the memory.
Smart Images
Figure CN119005105B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit design and manufacturing technology, and in particular to a memory and its fabrication method and layout structure. Background Technology
[0002] With the rapid development of semiconductor technology, the market has increasingly higher requirements for the integration, performance and reliability of integrated circuits.
[0003] In semiconductor memory devices such as three-dimensional non-volatile memory, in order to improve the flexibility of data read and write control, an isolation structure is used to isolate the memory cell array into multiple read and write cell regions that serve as data read and write units.
[0004] However, during the fabrication of the isolation structure between different read / write unit regions, it is easy to cause damage or breakage to the memory cells, resulting in a decrease in the storage density, performance, and reliability of the memory. Summary of the Invention
[0005] Based on this, it is necessary to provide a memory and its fabrication method and layout structure to address the technical problems mentioned above, which can at least effectively avoid damage or destruction of the target pattern caused by fabricating slit patterns.
[0006] According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a layout structure including a plurality of target graphics and a slit graphic, wherein the plurality of target graphics are arranged in rows at intervals along a first direction and in columns at intervals along a second direction intersecting the first direction; the slit graphic is located between the plurality of target graphics, and at least one slit graphic extends along the second direction; wherein the slit graphic is located at least in the region between two target graphics distributed along the first direction, and the length of the slit graphic in the first direction is not less than the size of the target graphics in the first direction.
[0007] The layout structure in the above embodiments, by setting a slit pattern extending along the second direction between multiple target patterns, and setting the length of the slit pattern in the first direction to be not less than the size of the target pattern in the first direction, makes the slit pattern located in the area between two target patterns distributed along the first direction, so as to ensure that the slit pattern does not contact the target pattern adjacent to it along the first direction, effectively avoiding damage or destruction of the target pattern caused by the preparation of the slit pattern, which is conducive to improving the distribution density of the target pattern per unit area and ensuring the morphology and quality of the prepared target pattern.
[0008] In some embodiments, the length of the slit pattern in the first direction is not less than twice the size of the target pattern in the first direction, so that the size of the slit pattern in the first direction can be set according to twice the size of the target pattern in the first direction, ensuring that the slit pattern is located in the area between two target patterns distributed along the first direction, and ensuring that the slit pattern does not contact the target pattern adjacent to it along the first direction as much as possible, effectively avoiding damage or destruction of the target pattern caused by the preparation of the slit pattern.
[0009] In some embodiments, at least two slit patterns of different lengths along the first direction are arranged at intervals along the first direction, so as to set the size of different slit patterns according to the actual arrangement of the target patterns in the target pattern array, so as to minimize the amount of target pattern removal caused by the preparation of slit patterns while ensuring the morphology and quality of the prepared target pattern.
[0010] In some embodiments, at least one slit pattern includes a wavy, zigzag, or combination thereof, so as to set the curvature or curvature of the slit pattern according to the distribution of the target patterns, ensuring that the slit pattern is located in the region between two target patterns distributed along the first direction, and ensuring as much as possible that the slit pattern does not contact the target pattern adjacent to it along the first direction.
[0011] In some embodiments, the slit pattern does not contact the target pattern, completely avoiding damage to the target pattern caused by the fabrication of the slit pattern.
[0012] In some embodiments, the slit pattern overlaps with at least one target pattern.
[0013] According to some embodiments of the present disclosure, a second aspect of the present disclosure provides a memory including a substrate, a stacked structure, a plurality of patterned pillars, and a slit pattern; the stacked structure is located on the substrate; the plurality of patterned pillars are arranged in rows at intervals along a first direction and in columns at intervals along a second direction intersecting the first direction; the plurality of patterned pillars penetrate the stacked structure along a third direction, the third direction intersecting both the first and second directions; at least one slit pattern extending along the second direction is located at least in the region between two patterned pillars distributed along the first direction, and extends to the substrate along the third direction, and the length of the slit pattern along the first direction is not less than the size of the patterned pillars in the first direction.
[0014] In the memory described above, a slit pattern extending along a second direction is positioned between multiple pattern pillars, and the length of the slit pattern in the first direction is not less than the size of the pattern pillar in the first direction. This ensures that the slit pattern is located within the area between two pattern pillars distributed along the first direction, minimizing contact between the slit pattern and its adjacent pattern pillars along the first direction. This effectively avoids damage or destruction of the pattern pillars caused by the fabrication of the slit pattern, thereby increasing the distribution density of the pattern pillars per unit area and ensuring the morphology and quality of the fabricated pattern pillars.
[0015] In some embodiments, the size of the slit pattern along the first direction gradually increases in the direction away from the substrate along the third direction, effectively avoiding damage to adjacent pattern pillars during the etching process to form the slit pattern.
[0016] In some embodiments, the length of the slit pattern in the first direction is not less than twice the size of the graphic column in the first direction, so as to set the size of the slit pattern in the first direction according to twice the size of the graphic column in the first direction, ensuring that the slit pattern is located in the area between two graphic columns distributed along the first direction, and ensuring that the slit pattern does not contact its adjacent graphic column along the first direction as much as possible, effectively avoiding damage or destruction of the graphic column caused by the preparation of the slit pattern.
[0017] In some embodiments, at least two slit patterns of different lengths along the first direction are arranged at intervals along the first direction, so as to set the size of different slit patterns according to the actual arrangement of the pattern pillars in the pattern pillar array, so as to minimize the number of pattern pillars removed due to the preparation of slit patterns while ensuring the morphology and quality of the prepared pattern pillars.
[0018] In some embodiments, at least one slit pattern includes a wavy, zigzag, or combination thereof, which enables the curvature or curvature of the slit pattern to be set according to the distribution of the graphic columns, ensuring that the slit pattern is located in the area between two graphic columns distributed along the first direction, and ensuring that the slit pattern does not contact its adjacent graphic columns along the first direction as much as possible.
[0019] In some embodiments, the slit pattern does not contact the pattern pillars, completely avoiding damage to the pattern pillars caused by the fabrication of the slit pattern.
[0020] In some embodiments, at least one other pattern pillar in the slit pattern contact portion enables the slit pattern to be set according to the actual distribution of the pattern pillars, thereby reducing the process complexity and cost of preparing the slit pattern.
[0021] According to some embodiments of this disclosure, a third aspect of this disclosure provides a method for fabricating a memory, comprising:
[0022] A front layer is provided, comprising a plurality of graphic columns spaced apart in rows along a first direction and spaced apart in columns along a second direction intersecting the first direction;
[0023] A mask layer is formed on the front layer, the mask layer including at least one slit opening extending along a second direction, the slit opening being located at least in the region between two graphic pillars distributed along a first direction, and at least one graphic pillar also existing between the two graphic pillars along the first direction, the slit opening completely exposing at least one graphic pillar.
[0024] The previous layer is etched based on the mask layer to form slits on the previous layer; and
[0025] An insulating material is formed to fill the slits to create a slit pattern.
[0026] The memory fabrication method in the above embodiments, by fabricating slit patterns extending along a second direction between multiple pattern pillars, and setting the length of the slit pattern in the first direction to be not less than the size of the pattern pillar in the first direction, so that the slit pattern is located in the area between two pattern pillars distributed along the first direction, it is possible to ensure that the slit pattern does not contact its adjacent pattern pillars along the first direction, effectively avoiding damage or destruction of the pattern pillars caused by the fabrication of the slit pattern, which is beneficial to improving the distribution density of pattern pillars per unit area and ensuring the morphology and quality of the fabricated pattern pillars.
[0027] In some embodiments, the length of the slit pattern along the first direction is not less than the dimension of the graphic column along the first direction, so that the slit pattern is located in the area between two graphic columns distributed along the first direction, so as to ensure that the slit pattern does not contact its adjacent graphic column along the first direction, effectively avoiding damage or destruction of the graphic column caused by the preparation of the slit pattern, which is conducive to improving the distribution density of graphic columns per unit area and ensuring the morphology and quality of the prepared graphic column.
[0028] In some embodiments, the graphic column has a dimension in the first direction, and the length of the slit pattern along the first direction is not less than twice the dimension of the graphic column in the first direction, so that the dimension of the slit pattern in the first direction can be set according to twice the dimension of the graphic column in the first direction, ensuring that the slit pattern is located in the area between two graphic columns distributed along the first direction, and ensuring that the slit pattern does not contact its adjacent graphic column along the first direction as much as possible, effectively avoiding damage or destruction of the graphic column caused by the preparation of the slit pattern.
[0029] In some embodiments, at least two slit patterns of different lengths along the first direction are arranged at intervals along the first direction, so as to set the size of different slit patterns according to the actual arrangement of the pattern pillars in the pattern pillar array, so as to minimize the number of pattern pillars removed due to the preparation of slit patterns while ensuring the morphology and quality of the prepared pattern pillars.
[0030] In some embodiments, at least one slit pattern includes a wavy, zigzag, or combination thereof, which enables the curvature or curvature of the slit pattern to be set according to the distribution of the graphic columns, ensuring that the slit pattern is located in the area between two graphic columns distributed along the first direction, and ensuring that the slit pattern does not contact its adjacent graphic columns along the first direction as much as possible.
[0031] In some embodiments, the slit pattern does not contact the pattern pillars, completely avoiding damage to the pattern pillars caused by the fabrication of the slit pattern.
[0032] In some embodiments, at least one other patterned pillar of the exposed slit portion enables the slit to be set according to the actual distribution of the patterned pillars, thereby reducing the process complexity and cost of preparing the slit pattern. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a top view schematic diagram of the layout structure in one embodiment of this application;
[0035] Figure 2a This is a top view schematic diagram of the layout structure in another embodiment of this application;
[0036] Figure 2b This is a top view schematic diagram of the layout structure in another embodiment of this application;
[0037] Figure 3 This is a top view schematic diagram of the structure obtained after forming a mask layer including a slit opening in a memory fabrication method according to an embodiment of this application;
[0038] Figure 4 In one embodiment of this application, after forming a slit in the memory fabrication method, the resulting structure follows... Figure 3 A schematic diagram of the longitudinal section structure in the aa' direction shown in the figure;
[0039] Figure 5 For one embodiment of this application, the memory edge Figure 3 The diagram shows a longitudinal section structure along the aa' direction.
[0040] Explanation of reference numerals in the attached figures:
[0041] 1000, Layout structure; 10, Front layer; 11, Target pattern; 21, Slit pattern; 2000, Memory; 100, Substrate; 200, Stack structure; 11', Pattern pillar; 211, Slit; 211', Slit opening. Detailed Implementation
[0042] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0043] Please refer to Figure 1 In some embodiments, a layout structure 1000 is provided, including a plurality of target graphics 11 and a slit graphic 21. The plurality of target graphics 11 are arranged in rows at intervals along a first direction (e.g., the ox direction) and in columns at intervals along a second direction intersecting the first direction (e.g., the oy direction). The slit graphic 21 is located between the plurality of target graphics 11, and at least one slit graphic 21 extends along the second direction. The slit graphic 21 is located at least in the region between two target graphics 11 distributed along the first direction, and the length W of the slit graphic 21 in the first direction is not less than the size D of the target graphics 11 in the first direction.
[0044] For example, please continue to refer to Figure 1 By setting a slit pattern 21 extending along a second direction (e.g., the oy direction) between multiple target patterns 11, and setting the length W of the slit pattern 21 in the first direction (e.g., the ox direction) to be not less than the dimension D of the target pattern 11 in the first direction, the slit pattern 21 is located in the area between two target patterns 11 distributed along the first direction. This ensures that the slit pattern 21 does not contact its adjacent target pattern 11 along the first direction, effectively avoiding damage or destruction of the target pattern 11 caused by the preparation of the slit pattern 21. This is beneficial to increasing the distribution density of the target pattern 11 per unit area and ensuring the morphology and quality of the prepared target pattern 11.
[0045] For example, please continue to refer to Figure 1 The first direction, such as the ox direction, can be the row direction of multiple target graphics 11 arranged together. The second direction, such as the oy direction, can be the column direction of multiple target graphics 11 arranged together. For the sake of brevity, these will not be elaborated further in the following text.
[0046] Please refer to Figures 2a-2bIn some embodiments, the length W of the slit pattern 21 in the first direction is not less than twice the size D of the target pattern 11 in the first direction (e.g., the ox direction), so that the size W of the slit pattern 21 in the first direction can be set according to the value of 2D, ensuring that the slit pattern 21 is located in the area between two target patterns 11 distributed along the first direction, and ensuring that the slit pattern 21 does not contact the target pattern 11 adjacent to it along the first direction as much as possible, effectively avoiding damage or destruction of the target pattern 11 caused by the preparation of the slit pattern 21.
[0047] Please refer to Figures 2a-2b In some embodiments, at least two slit patterns 21 of different lengths along a first direction (e.g., the ox direction) are arranged at intervals along the first direction so as to set the size of different slit patterns 21 according to the actual arrangement of the target patterns 11 in the array of target patterns 11, so as to minimize the number of target patterns 11 removed due to the preparation of slit patterns 21 while ensuring the morphology and quality of the prepared target patterns 11.
[0048] For example, please continue to refer to Figures 2a-2b The slit pattern 21 and its adjacent target pattern 11 along the first direction are located within the surrounding space of the slit pattern 21. This ensures that the two adjacent target patterns 11 along the first direction do not contact the slit pattern 21 between them, and the slit pattern 21 is used to isolate the two target patterns 11. This helps to increase the distribution density of the target patterns 11 and reduce the number of target patterns 11 that are reduced due to the introduction of the slit pattern 21.
[0049] Please continue to refer to this. Figures 2a-2b In some embodiments, at least one slit pattern 21 includes a wavy shape, a zigzag shape, or a combination thereof, so as to set the curvature or curvature of the slit pattern 21 according to the distribution of the target pattern 11, ensuring that the slit pattern 21 is located in the area between two target patterns 11 distributed along the first direction, and ensuring as much as possible that the slit pattern 21 does not contact the target pattern 11 adjacent to it along the first direction.
[0050] Please continue to refer to this. Figure 2a In some embodiments, the slit pattern 21 does not contact the target pattern 11, completely avoiding damage to the target pattern caused by the fabrication of the slit pattern.
[0051] Please continue to refer to this. Figure 2b In some embodiments, the slit pattern 21 is tangent to at least one target pattern 11. In some embodiments, the slit pattern overlaps with at least one target pattern to meet different process requirements in practical applications and improve cost-effectiveness.
[0052] Please refer to Figures 3-5In some embodiments, a memory fabrication method is provided, including steps S310-S340.
[0053] Step S310: Provide a front layer 10, which includes a plurality of graphic columns 11' arranged in rows at intervals along a first direction and in columns at intervals along a second direction intersecting the first direction.
[0054] For example, please continue to refer to Figure 3 The pattern pillar 11' can be a sacrificial pillar, used to define the shape, position or size of the subsequently fabricated semiconductor structure, and the semiconductor structure can be, but is not limited to, at least one of word lines, bit lines, memory strings, capacitor pillars, capacitor strings, etc.
[0055] Step S320: A mask layer is formed on the front layer 10. The mask layer includes at least one slit opening 211' extending along a second direction. The slit opening 211' is located at least in the region between two pattern pillars 11' distributed along a first direction, and at least one pattern pillar 11' also exists between the two pattern pillars 11' along the first direction. The slit opening 211' completely exposes at least one pattern pillar 11'.
[0056] For example, please continue to refer to Figure 3 A mask layer can be formed on the front layer 10 using processes such as photolithography and etching. The mask layer can be a single-layer structure or a multi-layer structure. The mask layer includes at least one slit opening 211' extending along a second direction, the slit opening 211' exposing the pattern pillar 11' to be removed.
[0057] Step S330: Etch the front layer 10 based on the mask layer to form a slit 211 on the front layer 10.
[0058] For example, please continue to refer to Figures 3-4 The mask layer can be a mask, and the pattern pillars 11' exposed by the slit opening 211' can be dry etched to remove them, thereby obtaining the slit 211 that exposes the substrate 100. The material of the mask layer can be a single layer or a multi-layer stacked structure.
[0059] Step S340: Form an insulating material to fill the slit 211 to form a slit pattern 21.
[0060] For example, please continue to refer to Figures 3-5 An insulating material that at least fills the slit 211 can be formed using a deposition process, and then the top surface of the insulating material is planarized to obtain a slit pattern 21 located within the slit 211 with its top surface flush with the top surface of the slit 211. The planarization process includes, but is not limited to, at least one or more of the following: chemical mechanical polishing (CMP), dry etching, wet etching, and planarization.
[0061] For example, insulating materials may include, but are not limited to, one or more of oxides, nitrides and oxynitrides, and carbides.
[0062] For example, oxides include silicon dioxide (SiO2); nitrides include silicon nitride (SiN); nitrogen oxides include silicon oxynitride (SiON); and carbides include silicon carbide.
[0063] For example, please continue to refer to Figures 3-5 By preparing a slit pattern 21 extending along a second direction between multiple patterned pillars 11', and setting the length of the slit pattern 21 in the first direction to be no less than the size of the patterned pillar 11' in the first direction, the slit pattern 21 is located in the area between two patterned pillars 11' distributed along the first direction. This ensures that the slit pattern 21 does not contact its adjacent patterned pillar 11' along the first direction, effectively avoiding damage or destruction of the patterned pillars 11' caused by the preparation of the slit pattern 21. This is beneficial to increasing the distribution density of the patterned pillars 11' per unit area and ensuring the morphology and quality of the prepared patterned pillars 11'.
[0064] For example, please continue to refer to Figures 3-5 The length W of the slit pattern 21 along the first direction is not less than the dimension D of the pattern column 11' along the first direction, so that the slit pattern 21 is located in the area between two pattern columns 11' distributed along the first direction. This ensures that the slit pattern 21 does not contact its adjacent pattern column 11' along the first direction, effectively avoiding damage or destruction of the pattern column 11' caused by the preparation of the slit pattern 21. This is beneficial to increasing the distribution density of the pattern column 11' per unit area and ensuring the morphology and quality of the prepared pattern column 11'.
[0065] In some embodiments, the graphic column has a dimension D in the first direction, and the length W of the slit graphic along the first direction is not less than twice the dimension D of the graphic column in the first direction, so as to set the dimension of the slit graphic in the first direction according to the value of 2D, ensuring that the slit graphic is located in the area between two graphic columns distributed along the first direction, and ensuring that the slit graphic does not contact its adjacent graphic column along the first direction as much as possible, effectively avoiding damage or destruction of the graphic column caused by the preparation of the slit graphic.
[0066] In some embodiments, at least two slit patterns of different lengths along the first direction are arranged at intervals along the first direction, so as to set the size of different slit patterns according to the actual arrangement of the pattern pillars in the pattern pillar array, so as to minimize the number of pattern pillars removed due to the preparation of slit patterns while ensuring the morphology and quality of the prepared pattern pillars.
[0067] In some embodiments, at least one slit pattern includes a wavy, zigzag, or combination thereof, which enables the curvature or curvature of the slit pattern to be set according to the distribution of the graphic columns, ensuring that the slit pattern is located in the area between two graphic columns distributed along the first direction, and ensuring that the slit pattern does not contact its adjacent graphic columns along the first direction as much as possible.
[0068] In some embodiments, the slit pattern does not contact the pattern pillars, completely avoiding damage to the pattern pillars caused by the fabrication of the slit pattern.
[0069] In some embodiments, at least one other patterned pillar of the exposed slit portion enables the slit to be set according to the actual distribution of the patterned pillars, thereby reducing the process complexity and cost of preparing the slit pattern.
[0070] Please refer to Figures 3-5 In some embodiments, a memory 2000 is provided, including a substrate 100, a stacked structure 200, a plurality of patterned pillars 11', and a slit pattern 21; the stacked structure 200 is located on the substrate 100; the plurality of patterned pillars 11' are arranged in rows at intervals along a first direction and in columns at intervals along a second direction intersecting the first direction; the plurality of patterned pillars 11' penetrate the stacked structure 200 along a third direction (e.g., the oz direction), the third direction intersecting both the first and second directions; at least one slit pattern 21 extending along the second direction is located at least in the region between two patterned pillars 11' distributed along the first direction, and extends along the third direction to the substrate 100, and the length of the slit pattern 21 along the first direction is not less than the size of the patterned pillars 11' in the first direction.
[0071] For example, please continue to refer to Figure 5 By setting a slit pattern 21 extending along the second direction between multiple pattern pillars 11', and setting the length of the slit pattern 21 in the first direction to be no less than the size of the pattern pillar 11' in the first direction, the slit pattern 21 is located in the area between two pattern pillars 11' distributed along the first direction. This ensures that the slit pattern 21 does not contact its adjacent pattern pillar 11' along the first direction, effectively avoiding damage or destruction of the pattern pillars 11' caused by the preparation of the slit pattern 21. This is beneficial to increasing the distribution density of the pattern pillars 11' per unit area and ensuring the morphology and quality of the prepared pattern pillars 11'.
[0072] For example, please continue to refer to Figure 5 The size of the slit pattern 21 along the first direction gradually increases in the direction away from the substrate 100 along the third direction (e.g., the oz direction), effectively avoiding damage to the adjacent pattern pillars 11' during the etching process to form the slit pattern 21.
[0073] For example, please continue to refer to Figure 5The pattern pillar 11' can be a sacrificial pillar, used to define the shape, position or size of the subsequently fabricated semiconductor structure, and the semiconductor structure can be, but is not limited to, at least one of word lines, bit lines, memory strings, capacitor pillars, capacitor strings, etc.
[0074] For example, please continue to refer to Figure 5 The graphic column 11' can be at least one of word line, bit line, memory string, capacitor column, capacitor string, etc.
[0075] If the patterned pillars are capacitor pillars or capacitor strings, slit patterns extending along a second direction for isolation are prepared between multiple patterned pillars. The length of the slit patterns in the first direction is not less than the size of the patterned pillars in the first direction, so that the slit patterns are located in the area between two patterned pillars distributed along the first direction. This ensures that the slit patterns do not contact their adjacent patterned pillars along the first direction, effectively avoiding damage or destruction of capacitor pillars or capacitor strings caused by the preparation of slit patterns. This is beneficial to improving the storage density per unit area and ensuring the performance and reliability of the prepared memory.
[0076] In some embodiments, the length of the slit pattern in the first direction is not less than twice the size of the graphic column in the first direction, so as to set the size of the slit pattern in the first direction according to twice the size of the graphic column in the first direction, ensuring that the slit pattern is located in the area between two graphic columns distributed along the first direction, and ensuring that the slit pattern does not contact its adjacent graphic column along the first direction as much as possible, effectively avoiding damage or destruction of the graphic column caused by the preparation of the slit pattern.
[0077] In some embodiments, at least two slit patterns of different lengths along the first direction are arranged at intervals along the first direction, so as to set the size of different slit patterns according to the actual arrangement of the pattern pillars in the pattern pillar array, so as to minimize the number of pattern pillars removed due to the preparation of slit patterns while ensuring the morphology and quality of the prepared pattern pillars.
[0078] In some embodiments, at least one slit pattern includes a wavy, zigzag, or combination thereof, which enables the curvature or curvature of the slit pattern to be set according to the distribution of the graphic columns, ensuring that the slit pattern is located in the area between two graphic columns distributed along the first direction, and ensuring that the slit pattern does not contact its adjacent graphic columns along the first direction as much as possible.
[0079] In some embodiments, the slit pattern does not contact the pattern pillars, completely avoiding damage to the pattern pillars caused by the fabrication of the slit pattern.
[0080] In some embodiments, at least one other pattern pillar in the slit pattern contact portion enables the slit pattern to be set according to the actual distribution of the pattern pillars, thereby reducing the process complexity and cost of preparing the slit pattern.
[0081] It should be noted that, Figures 4-5 To be on the corresponding three-dimensional structure, along Figure 3 A schematic diagram of the longitudinal section structure described in the aa' direction.
[0082] Please note that, for the sake of brevity, in the structural diagrams given in the embodiments, unless a separate cross-sectional structural diagram is given, structural diagrams from different perspectives related to the inventive points of the embodiments of this disclosure can be referred to each other.
[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0084] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A layout structure for a semiconductor structure, characterized in that, include: Multiple target graphics, wherein the multiple target graphics are arranged in rows at intervals along a first direction and in columns at intervals along a second direction intersecting the first direction; A slit pattern is located between the plurality of target patterns, and at least one of the slit patterns extends along the second direction and penetrates the plurality of target patterns arranged in multiple rows; The slit pattern is located at least in the region between two target patterns distributed along the first direction, for isolating the two target patterns, and the length of the slit pattern in the first direction is not less than twice the size of the target pattern in the first direction, and at least one of the slit patterns is wavy, zigzag, or a combination thereof, surrounding and not contacting at least one target pattern adjacent to it along the first direction.
2. The layout structure of the semiconductor structure according to claim 1, characterized in that, The plurality of target patterns are used to define the semiconductor structure to be subsequently fabricated, the semiconductor structure including at least one of word lines, bit lines, memory strings, capacitor pillars, and capacitor strings.
3. The layout structure of the semiconductor structure according to claim 1, characterized in that, At least two slit patterns of different lengths are arranged at intervals along the first direction.
4. A memory, characterized in that, include: Substrate; A multilayer structure is located on the substrate; Multiple graphic columns are arranged in rows at intervals along a first direction and in columns at intervals along a second direction intersecting the first direction; the multiple graphic columns penetrate the stacked structure along a third direction, which intersects both the first direction and the second direction; as well as At least one slit pattern extending along the second direction and penetrating the plurality of graphic pillars arranged in multiple rows, is located at least in the region between two graphic pillars distributed along the first direction, and extends to the substrate along the third direction. The length of the slit pattern along the first direction is not less than twice the size of the graphic pillars in the first direction. At least one of the slit patterns is wavy, zigzag, or a combination thereof, and surrounds but does not contact at least one graphic pillar adjacent to it along the first direction.
5. The memory according to claim 4, characterized in that, The dimension of the slit pattern along the first direction gradually increases in the third direction away from the substrate.
6. The memory according to claim 4, characterized in that, At least two slit patterns of different lengths are arranged at intervals along the first direction.
7. The memory according to claim 4, characterized in that, The plurality of patterned pillars are used to define the semiconductor structure to be subsequently fabricated, the semiconductor structure including at least one of word lines, bit lines, memory strings, capacitor pillars, and capacitor strings.
8. A method for fabricating a memory, characterized in that, include: A front layer is provided, the front layer comprising a plurality of graphic columns spaced apart in rows along a first direction and spaced apart in columns along a second direction intersecting the first direction; A mask layer is formed on the front layer, the mask layer including at least one slit opening extending along the second direction, the slit opening being located at least in the region between two graphic pillars distributed along the first direction, and at least one graphic pillar also existing between the two graphic pillars along the first direction, the slit opening completely exposing the at least one graphic pillar; The front layer is etched based on the mask layer to form a slit on the front layer; as well as An insulating material is formed to fill the slit to create a slit pattern; The length of the slit pattern along the first direction is not less than twice the dimension of the graphic column along the first direction, and at least one of the slit patterns is wavy, zigzag, or a combination thereof, surrounding and not contacting at least one graphic column adjacent to it along the first direction.
9. The memory fabrication method according to claim 8, characterized in that, At least two slit patterns of different lengths along the first direction are arranged at intervals along the first direction.
10. The memory fabrication method according to claim 8, characterized in that, The patterned pillars are sacrificial pillars used to define the semiconductor structure to be fabricated subsequently. The semiconductor structure includes at least one of word lines, bit lines, memory strings, capacitor pillars, and capacitor strings.