Pixel driving circuit, pixel driving method, and display device

Abstract

The present application discloses a pixel driving circuit, a pixel driving method and a display device. The pixel driving circuit includes: a first sub-pixel circuit, a second sub-pixel circuit, a third transistor (T3) and a fourth transistor (T4); the third transistor (T3) and the fourth transistor (T4) are arranged between the first sub-pixel circuit and the second sub-pixel circuit, and the conduction or cut-off of the third transistor (T3) and the fourth transistor (T4) is controlled to control the series or parallel connection of the first sub-pixel circuit and the second sub-pixel circuit, so as to perform display mode switching. The present application controls the connection states of the first sub-pixel circuit and the second sub-pixel circuit through T3 and T4, thereby realizing multiple display modes, and the multiple display modes can be switched to meet the various mode requirements of users.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and more particularly, to a pixel driving circuit, a pixel driving method, and a display device. Background Art

[0002] With the rapid development of display technologies, whether it is a liquid crystal display (LCD) or an active matrix organic light-emitting diode (AMOLED) display, the red (R), green (G), and blue (B) sub-pixels are arranged in an m-row and n-column array, and each sub-pixel requires a data line to provide a corresponding voltage to present an image.

[0003] Currently, for different display scenarios such as gaming and movie viewing, there are various display requirements such as high refresh rate and normal. How to achieve the switching between multiple modes to meet the various mode requirements of users is a technical problem that needs to be solved urgently at present.

[0004] In view of the above problems in the related art, no effective solution has been found yet. Summary of the Invention

[0005] The present application provides a pixel driving circuit, a pixel driving method, and a display device to solve the above technical problem of multiple display mode requirements in the related art.

[0006] According to an embodiment of the present application, a pixel driving circuit is provided. The pixel driving circuit includes: a first sub-pixel circuit, a second sub-pixel circuit, a third transistor (T3), and a fourth transistor (T4); the third transistor (T3) and the fourth transistor (T4) are disposed between the first sub-pixel circuit and the second sub-pixel circuit, and the series or parallel connection of the first sub-pixel circuit and the second sub-pixel circuit is controlled by controlling the conduction or cutoff of the third transistor (T3) and the fourth transistor (T4) to perform display mode switching.

[0007] According to another embodiment of the present application, a pixel driving method is provided, which is applied to the above pixel driving circuit. The method includes: detecting whether a display mode switching request is triggered; if the display mode switching request is triggered, identifying the target display mode corresponding to the display mode switching request; and controlling the conduction or cutoff of the third transistor (T3) and the fourth transistor (T4) in the pixel driving circuit according to the target display mode.

[0008] According to still another embodiment of the present application, a display device is further provided, including a display panel, and the display panel includes the pixel driving circuit as described above.

[0009] Through the embodiments of the present application, two transistors (the third transistor T3 and the fourth transistor T4) are added between the first sub-pixel circuit and the second sub-pixel circuit to control the states of the first sub-pixel circuit and the second sub-pixel circuit. When in series, the first sub-pixel and the second sub-pixel are scanned and charged simultaneously, enabling the display to enter the high refresh rate mode. When in parallel, the first sub-pixel and the second sub-pixel are scanned and charged line by line, enabling the display to enter the normal mode, etc., thus realizing a multi-functional and switchable pixel driving circuit to meet the various mode requirements of users. Description of the Drawings

[0010] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0011] Figure 1 is a schematic structural diagram of the pixel driving circuit according to the embodiments of the present application;

[0012] Figure 2 is a schematic structural diagram of an example of the pixel driving circuit according to the embodiments of the present application;

[0013] Figure 3 is a schematic diagram of the working principle of the pixel driving circuit according to the embodiments of the present application in the normal mode;

[0014] Figure 4 is a schematic diagram of the working principle of the pixel driving circuit according to the embodiments of the present application in the high refresh rate mode;

[0015] Figure 5 is a schematic diagram of the working principle of the pixel driving circuit according to the embodiments of the present application in the energy-saving mode;

[0016] Figure 6 is a flowchart of a pixel driving method according to the embodiments of the present application;

[0017] Figure 7 is a schematic flowchart of the first mode switching method according to the embodiments of the present application;

[0018] Figure 8 is a schematic flowchart of the second mode switching method according to the embodiments of the present application. Detailed Embodiments

[0019] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0021] First embodiment:

[0022] Reference Figure 1 An embodiment of the present invention provides a pixel driving circuit, which includes: a first sub-pixel circuit, a second sub-pixel circuit, a third transistor T3 and a fourth transistor T4; the third transistor T3 and the fourth transistor T4 are arranged between the first sub-pixel circuit and the second sub-pixel circuit, and the display mode is switched by controlling the conduction or closing of the third transistor T3 and the fourth transistor T4 to control the series connection or parallel connection of the first sub-pixel circuit and the second sub-pixel circuit.

[0023] In this embodiment, the first sub-pixel and the second sub-pixel have the same color. In this embodiment, the first sub-pixel and the second sub-pixel are both red sub-pixels, that is, the first sub-pixel is R1 and the second sub-pixel is R2. In this embodiment, since the control voltages of different colors may be different, there will be differences from the ideal color when connected in series, resulting in color deviation, affecting the overall display effect, while the sub-pixels of the same color produce similar brightness and color saturation under the same voltage, thereby maintaining color consistency.

[0024] In an implementation manner of this embodiment, the pixel driving circuit is composed of a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. For specific connection details, reference can be made to Figure 2 , Figure 2 which is a schematic diagram of an embodiment of the pixel driving circuit in this embodiment. In this pixel driving circuit, the first sub-pixel circuit includes a first transistor T1, a fifth transistor T5, a first capacitor C1, and a first sub-pixel R1; the second sub-pixel circuit includes a second transistor T2, a sixth transistor T6, a second capacitor C2, and a second sub-pixel R2; the first scan signal scan1 controls the switching state of the first transistor T1; the second scan signal scan2 controls the switching state of the second transistor T2; the fifth transistor T5 and the first capacitor C1 are used to control the magnitude of the current passing through the first sub-pixel R1; the sixth transistor T6 and the second capacitor C2 are used to control the magnitude of the current passing through the second sub-pixel R2; the gate of the first transistor T1 is electrically connected to the first scan signal scan1 of the nth row (Sn), the first source-drain of the first transistor T1 is electrically connected to the data signal (data line Dm), and the second source-drain of the first transistor T1 is electrically connected to the gate of the fifth transistor T5 and one end of the first capacitor C1, where n is a positive integer greater than 0; among them, according to different transistor types, the first source-drain can be one of the source and drain of the first transistor T1, and the second source-drain can be the other of the source and drain of the first transistor T1. The source-drains of other transistors in this embodiment are similar to those of the first transistor, and will not be elaborated here.

[0025] The anode of the first sub-pixel R1 is electrically connected to the seventh source-drain of the fifth transistor T5, the cathode of the first sub-pixel R1 is electrically connected to the third source-drain of the third transistor T3 and the fifth source-drain of the fourth transistor T4, and the eighth source-drain of the fifth transistor T5 is electrically connected to the first power supply voltage VDD and the other end of the first capacitor C1; the gate of the third transistor T3 is electrically connected to the third scan signal scan3, the third source-drain of the third transistor T3 is electrically connected to the fifth source-drain of the fourth transistor T4, and the fourth source-drain of the third transistor T3 is electrically connected to the ground voltage; the gate of the fourth transistor T4 is electrically connected to the fourth scan signal scan4, the sixth source-drain of the fourth transistor T4 is electrically connected to the anode of the second sub-pixel R2, and the cathode of the second sub-pixel R2 is electrically connected to the ground voltage; the gate of the second transistor T2 is electrically connected to the second scan signal scan2 of the (n + 1)-th row (Sn+1), the eleventh source-drain of the second transistor T2 is electrically connected to the data signal, and the twelfth source-drain of the second transistor T2 is electrically connected to the gate of the sixth transistor T6 and one end of the second capacitor C2; the ninth source-drain of the sixth transistor T6 is connected to the anode of the second sub-pixel, and the tenth source-drain of the sixth transistor T6 is electrically connected to the second power supply voltage and the other end of the second capacitor C2.

[0026] Through this embodiment, two transistors (the third transistor T3 and the fourth transistor T4) are added between the first sub-pixel circuit and the second sub-pixel circuit to control the series or parallel connection of the first sub-pixel circuit and the second sub-pixel circuit. In the series state, the first sub-pixel and the second sub-pixel are charged simultaneously, enabling the display to enter the high refresh rate mode. In the parallel state, the first sub-pixel and the second sub-pixel are charged row by row, enabling the display to enter the normal mode, etc., thereby realizing a multi-functional and switchable pixel driving circuit to meet the various mode requirements of users.

[0027] Through the pixel driving circuit in this embodiment, multiple display modes can be realized, and the switching between multiple display modes can also be achieved. In this embodiment, the display modes include the normal mode, the high refresh rate mode, the energy-saving mode, etc.

[0028] In the normal mode, by controlling the third transistor T3 to conduct and the fourth transistor T4 to turn off, the first sub-pixel circuit and the second sub-pixel circuit are controlled to be connected in parallel. The phase difference between the first scan signal passing through the first sub-pixel circuit and the second scan signal passing through the second sub-pixel circuit is the charging time of the first capacitor C1 or the second capacitor C2, that is, the charging time of one row of pixels, enabling the display to enter the normal mode. When the data line charges the first sub-pixel R1 and the second sub-pixel R2, the first scan signal and the second scan signal perform row-by-row scanning on R1 and R2 according to the normal mode, which is applicable to display scenarios such as watching movies.

[0029] In the high refresh rate mode, by controlling the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to conduct, and the third transistor T3 and the second transistor T2 to turn off, the first sub-pixel circuit and the second sub-pixel circuit are controlled to be connected in series. The first scan signal turns on the first transistor T1 to charge the first capacitor C1. After charging, the first capacitor C1 maintains the fifth transistor T5 in the on state, and the current flowing through the first sub-pixel R1 flows through the fourth transistor T4 and the second sub-pixel R2 to the ground terminal in sequence, while lighting the first sub-pixel R1 and the second sub-pixel R2, so that the display enters the high refresh rate mode. The refresh time of the entire screen is reduced, thereby achieving a higher refresh rate, and it can be applied to display scenarios such as games that require a high refresh rate.

[0030] In the energy-saving mode, in the current frame, the first transistor T1, the third transistor T3, and the fifth transistor T5 are controlled to conduct, and the second transistor T2 and the fourth transistor T4 are turned off. The first scan signal turns on the first transistor T1 to charge the first capacitor C1. After charging, the first capacitor C1 maintains the fifth transistor T5 in the on state, and the current flowing through the first sub-pixel R1 flows through the third transistor T3 to the ground terminal. At this time, only the first sub-pixel R1 is lit, that is, the sub-pixels in the Nth row are lit, and the second sub-pixel R2 has no scan signal and R2 is not lit. In the next frame, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are controlled to conduct, and the first transistor T1, the third transistor T3, and the fourth transistor T4 are turned off. The second scan signal turns on the second transistor T2 to charge the second capacitor C2. After charging, the second capacitor C2 maintains the sixth transistor T6 in the on state, and the current flowing through the second sub-pixel R2 directly flows to the ground terminal. At this time, only the R2 pixel is lit, that is, the sub-pixels in the (N + 1)th row are lit, and the first sub-pixel R1 has no scan signal and R1 is not lit, so that the display enters the energy-saving mode.

[0031] Second Embodiment:

[0032] In this embodiment, a pixel driving method is provided. This pixel driving method is applied to the pixel driving circuit described in the above embodiment. Refer to Figure 6 , Figure 6 which is a flowchart of a pixel driving method according to an embodiment of the present application. As shown in Figure 6 , this process includes the following steps:

[0033] Step S10, detecting whether a display mode switching request is triggered;

[0034] Step S20, if a display mode switching request is triggered, identifying the target display mode corresponding to the display mode switching request;

[0035] Step S30, according to the target display mode, controlling the conduction or turn-off of the third transistor T3 and the fourth transistor T4 in the pixel driving circuit.

[0036] In this embodiment, the user can trigger a display mode switching request by selecting different modes on the whole machine keys (such as the mode key on a TV or a TV remote control) or software. If a display mode switching request is triggered, the target display mode corresponding to the triggered display mode switching request is identified, and the conduction or cutoff of the third transistor T3 and the fourth transistor T4 in the pixel driving circuit is controlled, so as to control the output of the scan waveform corresponding to the target display mode and realize mode switching.

[0037] Through the above steps, the conduction or cutoff of the third transistor T3 and the fourth transistor T4 in the pixel driving circuit is controlled to make the display enter the target display mode, so as to meet the user's various mode requirements such as normal mode, energy-saving mode, and high refresh rate mode.

[0038] In the first implementation manner of this embodiment, the target display mode is the normal mode. In the normal mode, the fourth transistor T4 is controlled to be cutoff, the third transistor T3 is controlled to be conductive, and the first sub-pixel circuit and the second sub-pixel circuit are connected in parallel; the first sub-pixel circuit includes a first sub-pixel R1, and the first scanning signal and the second scanning signal sequentially turn on the first transistor T1 and the second transistor T2 to sequentially charge the first capacitor C1 and the second capacitor C2; the charged first capacitor C1 maintains the fifth transistor T5 in the on state, and the current flowing through the first sub-pixel R1 flows to the ground terminal through the third transistor T3 to light up the first sub-pixel R1; the second sub-pixel circuit includes a second sub-pixel R2, and the charged second capacitor C2 maintains the sixth transistor T6 in the on state, and the current flowing through the second sub-pixel R2 directly flows to the ground terminal to light up the second sub-pixel R2; the phase difference between the first scanning signal and the second scanning signal is the charging time of the first capacitor C1 or the second capacitor C2.

[0039] In an application scenario of this implementation manner, referring to Figure 3 , the target display mode is the normal mode, the fourth transistor T4 is controlled to be cutoff, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are conductive, and the first scanning signal scan1, the second scanning signal scan2, the third scanning signal scan3, and the fourth scanning signal scan4 respectively output waveforms as shown in Figure 3 . Each row of sub-pixels needs to wait for the scanning signal to arrive before starting to charge. Among them, the scanning signals of the first transistor T1 and the third transistor T3 are in a synchronous state, and they are switched on at the same time and flow through the third transistor T3 to the ground voltage OVSS to ensure that the first sub-pixel R1 is lit. The phase difference between scan1 of the first transistor T1 and scan2 of the second transistor T2 is maintained as the time for charging one row of pixels (after charging one row of pixels of the first sub-pixel R1, the charging of the next row of second sub-pixel R2 pixels is started).

[0040] In this embodiment, the third transistor T3 and the fourth transistor T4 are used to control the parallel connection of the first sub-pixel R1 and the second sub-pixel R2, and the first sub-pixel R1 and the first sub-pixel R1 are charged row by row, so that the display enters the normal mode.

[0041] In the second embodiment of this example, refer to Figure 4 , the target display mode is the high refresh rate mode. In the high refresh rate mode, the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are controlled to be turned on, and the third transistor T3 and the second transistor T2 are turned off. At this time, the first sub-pixel circuit and the second sub-pixel circuit are in a series connection state; when the data line charges the first sub-pixel R1 and the second sub-pixel R2, the first scan signal turns on the first transistor T1 to charge the first capacitor C1; the charged first capacitor C1 maintains the fifth transistor T5 in the on state, and the current flowing through the first sub-pixel R1 sequentially passes through the fourth transistor T4 and the second sub-pixel R2 to flow to the ground terminal, while lighting up the first sub-pixel R1 and the second sub-pixel R2.

[0042] When the data line charges the first sub-pixel R1 and the second sub-pixel R2, the first scan signal scan1 and the fourth scan signal scan4 are kept in sync, so the first sub-pixel R1 and the second sub-pixel R2 display the same data. T2 is turned off and the second scan signal scan2 has no signal.

[0043] In this embodiment, originally it took two rows of scanning and charging time to light up R1 and R2. By controlling R1 and R2 in series in this embodiment, the scan signal scan1 passing through R1 and the scan signal scan4 passing through R2 are kept in sync, that is, R1 and R2 are charged in parallel, and it only takes one row of scanning and charging time to light up R1 and R2. That is, originally it took 1 frame time to complete the scanning of the entire picture, and at this time it only takes half of the original time to scan the entire picture, shortening the refresh time of the entire picture. That is, within the same 1 frame time, the high refresh rate mode can achieve the effect of 2 frames, that is, the Frame rate is doubled (for example: the original refresh rate is 240Hz, and the refresh rate can be increased to 480Hz in the high refresh rate mode).

[0044] In the trend of the panel industry towards high resolution, the panel display technology faces greater challenges. High resolution means more data lines and more thin film transistors (TFTs). On the one hand, it increases the design difficulty and cost of the driver chip (driver IC), and on the other hand, it also continuously increases the RC load (RC loading, that is, resistance-capacitance delay) of the panel. At the same time, the high resolution panel inevitably brings power consumption problems.

[0045] Therefore, in the third implementation manner of this embodiment, referring to Figure 5 , the target display mode is the energy-saving mode. In the energy-saving mode, in the current frame, the first transistor T1, the third transistor T3, and the fifth transistor T5 are controlled to conduct, and the second transistor T2 and the fourth transistor T4 are turned off; the first scan signal turns on the first transistor T1 to charge the first capacitor C1; after charging, the first capacitor C1 maintains the fifth transistor T5 in the on state, and the current flowing through the first sub-pixel R1 flows to the ground terminal through the third transistor T3, turning on the first sub-pixel R1; at this time, only the first sub-pixel R1 is lit, that is, the sub-pixels in the Nth row are lit, and the second sub-pixel R2 has no scan signal and the second sub-pixel R2 is not lit.

[0046] In the next frame, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are controlled to conduct, and the first transistor T1, the third transistor T3, and the fourth transistor T4 are turned off; the second scan signal turns on the second transistor T2 to charge the second capacitor C2; after charging, the second capacitor C2 maintains the sixth transistor T6 in the on state, and the current flowing through the second sub-pixel flows directly to the ground terminal, turning on the second sub-pixel R2. At this time, only the second sub-pixel R2 is lit, that is, the sub-pixels in the (N + 1)th row are lit, and the first sub-pixel R1 has no scan signal and the first sub-pixel R1 is not lit.

[0047] Through the energy-saving mode in this implementation manner, due to the visual persistence characteristic of the human eye, when the refresh rate remains unchanged, only half of the pixels are charged for each frame display, and theoretically the power consumption is halved, greatly reducing the power consumption.

[0048] In this embodiment, the third transistor T3 and the fourth transistor T4 are used to control the light-emitting states of the first sub-pixel R1 and the second sub-pixel R2, thereby implementing three working modes: the normal mode, the high-refresh mode, and the energy-saving mode.

[0049] In this embodiment, according to the target display mode, controlling the conduction or turning off of the third transistor T3 and the fourth transistor T4 in the pixel driving circuit includes:

[0050] S31, sending a switching instruction to the timing control chip, and the switching instruction is used to instruct the timing control chip to switch the current mode to the target display mode;

[0051] S32, based on the switching instruction, the timing control chip outputs the timing and data signals of the target display mode;

[0052] S33, according to the timing and data signals, controlling the conduction and turning off of the third transistor T3 and the fourth transistor T4 in the pixel driving circuit.

[0053] In one embodiment, a switching instruction is sent to the timing control chip TCON by raising the pin voltage of the corresponding CNN (connector), causing the timing control chip to switch the code in the target display mode. Refer to Figure 7 , Step 1, after the user selects different modes on the whole machine keys or software, the system circuit board SOC of the whole machine will make corresponding actions; Step 2, the SOC raises the TCON control pin PIN of the target display mode through the CNN connected to the OC (Open cell, display panel) (such as raising the corresponding PIN, and the TCON is ready to burn the code of the target display mode); Step 3, the TCON burns the corresponding code from the EEPROM (the memory for storing the TCON IC code) through the I2C bus (such as switching the code in different modes by selecting different Byte1, where Byte1 represents the I2C instruction here, and different instructions correspond to the code in different modes); Step 4, after the mode switching is completed, the TCON outputs the timing and data signals of the target display mode, so that the display enters the corresponding target display mode.

[0054] In another embodiment, the SOC sends a switching instruction to the timing control chip through the I2C, and the timing control chip executes the burning of the corresponding code. Refer to Figure 8 , Step 1, the user selects different modes on the whole machine keys or software; Step 2, the SOC transfers the instruction to the TCON through the I2C to cause the TCON to switch the code; Step 3, the TCON switches the corresponding code through the I2C instruction; Step 4, after the code is switched, the TCON outputs the timing and data signals of the target display mode, so that the display enters the corresponding target display mode. Among them, the I2C bus includes the data line (SDA) of the I2C communication protocol, the clock line (SCL) of the IIC communication protocol, and the control signal (WP) for controlling the I2C read and write. For example, only when it is raised can the code be rewritten, otherwise the code cannot be rewritten and only the code can be read.

[0055] Optionally, in this embodiment, detecting whether a display mode switching request is triggered includes: detecting an operation instruction of the user on the whole machine; if no operation instruction is detected within a preset time, a display mode switching request corresponding to the energy-saving mode is default triggered.

[0056] In this embodiment, the system-on-chip (SOC) of the whole machine device monitors the usage of the whole machine. When it is detected that the user has not performed any operations for a certain period of time, the device can be considered to be in an idle state. At this time, the energy-saving mode can be default entered, and the SOC automatically triggers a display mode switching request for the energy-saving mode, that is, the device is switched to a low-power working state. The energy-saving mode keeps the screen brightness from decreasing while reducing power consumption.

[0057] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a terminal device (which can be a television, a computer, etc.) to execute the methods described in the various embodiments of the present application.

[0058] Third Embodiment:

[0059] The embodiment of the present application provides a display device, and the display device includes a display panel, and the display panel includes the pixel driving circuit in the above embodiments.

[0060] In the above embodiments of the present application, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0061] In the several embodiments provided by the present application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some interfaces. The indirect coupling or communication connection of units or modules can be in an electrical or other form.

[0062] In addition, each functional unit in the various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0063] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned computer storage medium includes: various media that can store program codes, such as USB flash drives, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), mobile hard disks, magnetic disks, or optical discs.

[0064] The above are only the preferred embodiments of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of this application.

Claims

1. A pixel driving method, applied to a pixel driving circuit, the pixel driving circuit comprising: A first sub-pixel circuit, a second sub-pixel circuit, a third transistor (T3), and a fourth transistor (T4); the third transistor (T3) and the fourth transistor (T4) are disposed between the first sub-pixel circuit and the second sub-pixel circuit, and the first sub-pixel circuit and the second sub-pixel circuit are controlled to be connected in series or in parallel by controlling the on or off of the third transistor (T3) and the fourth transistor (T4), so as to perform display mode switching; The first sub-pixel circuit includes a first transistor (T1), a fifth transistor (T5), a first capacitor (C1), and a first sub-pixel; The second sub-pixel circuit includes a second transistor (T2), a sixth transistor (T6), a second capacitor (C2), and a second sub-pixel; A first scan signal controls the switching state of the first transistor (T1); a second scan signal controls the switching state of the second transistor (T2); the fifth transistor (T5) and the first capacitor (C1) control the magnitude of the current passing through the first sub-pixel; the sixth transistor (T6) and the second capacitor (C2) control the magnitude of the current passing through the second sub-pixel; The gate of the first transistor (T1) is electrically connected to the first scan signal of the nth row, the first source-drain of the first transistor (T1) is electrically connected to the data signal, and the second source-drain of the first transistor (T1) is electrically connected to the gate of the fifth transistor (T5) and one end of the first capacitor (C1), where n is a positive integer greater than 0; The anode of the first sub-pixel is electrically connected to the seventh source-drain of the fifth transistor (T5), the cathode of the first sub-pixel is electrically connected to the third source-drain of the third transistor (T3) and the fifth source-drain of the fourth transistor (T4), and the eighth source-drain of the fifth transistor (T5) is electrically connected to the first power supply voltage and the other end of the first capacitor (C1); The gate of the third transistor (T3) is electrically connected to the third scan signal, the third source-drain of the third transistor (T3) is electrically connected to the fifth source-drain of the fourth transistor (T4), and the fourth source-drain of the third transistor (T3) is electrically connected to the ground voltage; The gate of the fourth transistor (T4) is electrically connected to the fourth scan signal, the sixth source-drain of the fourth transistor (T4) is electrically connected to the anode of the second sub-pixel, and the cathode of the second sub-pixel is electrically connected to the ground voltage; The gate of the second transistor (T2) is electrically connected to the second scan signal of the (n + 1)th row, the eleventh source-drain of the second transistor (T2) is electrically connected to the data signal, and the twelfth source-drain of the second transistor (T2) is electrically connected to the gate of the sixth transistor (T6) and one end of the second capacitor (C2); The ninth source-drain of the sixth transistor (T6) is connected to the anode of the second sub-pixel, and the tenth source-drain of the sixth transistor (T6) is electrically connected to the second power supply voltage and the other end of the second capacitor (C2); The first sub-pixel and the second sub-pixel have the same color; Characterized in that, the method includes: Detecting whether a display mode switching request is triggered; If a display mode switching request is triggered, identifying a target display mode corresponding to the display mode switching request; According to the target display mode, controlling the conduction or cutoff of the third transistor (T3) and the fourth transistor (T4) in the pixel driving circuit; According to the target display mode, controlling the conduction or cutoff of the third transistor (T3) and the fourth transistor (T4) in the pixel driving circuit includes: If the target display mode is the normal mode, controlling the fourth transistor (T4) to be cutoff, the third transistor (T3) to be conducting, and the first sub-pixel circuit and the second sub-pixel circuit to be connected in parallel; The first scan signal and the second scan signal sequentially turn on the first transistor (T1) and the second transistor (T2) to sequentially charge the first capacitor (C1) and the second capacitor (C2); the charged first capacitor (C1) maintains the fifth transistor (T5) in the on state, and the current flowing through the first sub-pixel flows to the ground terminal through the third transistor (T3); the charged second capacitor (C2) maintains the sixth transistor (T6) in the on state, and the current flowing through the second sub-pixel directly flows to the ground terminal; the phase difference between the first scan signal and the second scan signal is the charging time of the first capacitor (C1) or the second capacitor (C2); According to the target display mode, controlling the conduction or cutoff of the third transistor (T3) and the fourth transistor (T4) in the pixel driving circuit includes: If the target display mode is the high refresh rate mode, controlling the first transistor (T1), the fourth transistor (T4), the fifth transistor (T5) and the sixth transistor (T6) to be conducting, the third transistor (T3) and the second transistor (T2) to be cutoff, and the first sub-pixel circuit and the second sub-pixel circuit to be connected in series; The first scan signal turns on the first transistor (T1) to charge the first capacitor (C1); the charged first capacitor (C1) maintains the fifth transistor (T5) in the on state, and the current flowing through the first sub-pixel sequentially flows through the fourth transistor (T4) and the second sub-pixel to the ground terminal.

2. The method according to claim 1, wherein According to the target display mode, controlling the conduction or cutoff of the third transistor (T3) and the fourth transistor (T4) in the pixel driving circuit includes: If the target display mode is the energy-saving mode, controlling the first transistor (T1), the third transistor (T3) and the fifth transistor (T5) to be conducting, the second transistor (T2) and the fourth transistor (T4) to be cutoff in the current frame; the first scan signal turns on the first transistor (T1) to charge the first capacitor (C1); the charged first capacitor (C1) maintains the fifth transistor (T5) in the on state, and the current flowing through the first sub-pixel flows to the ground terminal through the third transistor (T3); In the next frame, control the second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) to conduct, and turn off the first transistor (T1), the third transistor (T3), and the fourth transistor (T4); the second scan signal turns on the second transistor (T2) to charge the second capacitor (C2); the charged second capacitor (C2) maintains the sixth transistor (T6) in the on state, and the current flowing through the second sub-pixel directly flows to the ground terminal.

3. The method according to claim 1, wherein Detecting whether a display mode switching request is triggered includes: Detecting an operation instruction of the user on the entire machine; If no operation instruction is detected within a preset time, a display mode switching request corresponding to the energy-saving mode is triggered by default.

4. The method according to claim 1, wherein Controlling the conduction or cutoff of the third transistor (T3) and the fourth transistor (T4) in the pixel driving circuit according to the target display mode includes: Sending a switching instruction to the timing control chip, where the switching instruction is used to instruct the timing control chip to switch the current mode to the target display mode; Based on the switching instruction, the timing control chip outputs the timing and data signals of the target display mode; According to the timing and data signals, control the conduction and cutoff of the third transistor (T3) and the fourth transistor (T4) in the pixel driving circuit.

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