A high-speed data flow device based on SRIO bus and working method

Abstract

The present invention discloses a high-speed data flow device and working method based on the SRIO bus, comprising a high-speed interface board connected to a high-speed camera, an image processing node, and a data computing node, all of which are connected to a 16-way 1X SRIO switching network; the 16-way 1X SRIO switching network is connected to a low-speed interface board; the low-speed interface board is externally connected to a receiving device; the high-speed interface board packages the received image data and sends it to the SRIO switching network; the SRIO switching network distributes the received image data packets to the image processing node and the data computing node for processing, and the SRIO switching network outputs the final processing results as low-speed real-time information through the low-speed interface board, and the low-speed real-time information enters the receiving device. The present invention connects the internal data input interface of a computer to multiple computing nodes, enabling data exchange between any nodes, enabling flexible configuration of the computing resources of a high-performance computer, and non-blocking communication between computing nodes, effectively improving the application efficiency of the computer.

Description

Technical Field

[0001] The present invention belongs to the technical field of space embedded computers and relates to a high-speed data flow device based on an SRIO bus and a working method. Background Art

[0002] As space application technology continues to improve, image resolution and measurement accuracy continue to rise. Traditional approaches relying on digital transmission channels to downlink data for analysis are no longer able to meet the demands of massive data transmission and real-time performance. Space products, such as space reconnaissance and situational awareness satellites, are placing high-performance, real-time processing computers at the forefront of these applications. Currently, onboard processing systems typically handle relatively small amounts of data, often relying on point-to-point transmission. This approach, while limited in its single path and flexibility in resource allocation, is unable to support the transmission and interaction of massive data resources. Summary of the Invention

[0003] The purpose of the present invention is to solve the problems in the prior art that the data volume of onboard processing systems is generally small, point-to-point transmission is mostly adopted, resource allocation flexibility is poor, and it is unable to support data transmission and resource interaction of massive data resources. A high-speed data flow device and working method based on the SRIO bus are provided.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] The present invention proposes a high-speed data flow device based on SRIO bus, comprising a high-speed camera, a high-speed interface board, a switching unit and a low-speed interface board;

[0006] The high-speed interface board is externally connected to a high-speed camera. The switching unit includes a 16-way 1X SRIO switching network, an image processing node, and a data computing node. The image processing node and the data computing node are both connected to the 16-way 1X SRIO switching network. The 16-way 1X SRIO switching network is connected to a low-speed interface board. The low-speed interface board is externally connected to a receiving device. The high-speed camera transmits the image to the high-speed interface board. The high-speed interface board packages the received image data and sends it to the SRIO switching network. The SRIO switching network distributes the received image data packets to the image processing node and the data computing node for processing. The SRIO switching network outputs the final processing results as low-speed real-time information through the low-speed interface board, and the low-speed real-time information enters the receiving device.

[0007] Preferably, there are several high-speed cameras; the high-speed cameras transmit images to the high-speed interface board, specifically: high-speed cameras in different working modes transmit images to the high-speed interface board via the camera-specific channel Serdes interface.

[0008] Preferably, the high-speed interface board packages the received image data, specifically: the high-speed interface board packages the image data according to the data sources of different cameras and identifies the destination ID, and transmits it to the SRIO switching network through the 2-way 1XSRIO bus.

[0009] Preferably, the SRIO switching network distributes the received image data packets to the image processing nodes and data computing nodes for processing, specifically: each node on the SRIO switching network has a unique ID number and only receives image data packets with the same ID number as itself; the image data packets are distributed to their respective destination ID nodes through the SRIO switching network for image data processing; the image processing nodes and data computing nodes are bound with different data processing algorithms to perform computational processing on the data; data interaction can be performed between any nodes on the SRIO switching network, and each image processing node and data computing node is in a parallel relationship.

[0010] Preferably, the SRIO switching network is externally connected to a power-on reset circuit, a clock circuit and a routing table storage area EEPROM; the power-on reset circuit completes the reset function of the switching network after power-on, and the routing table storage area EEPROM is used to store the routing table; the routing table storage area EEPROM is connected to the SRIO switching network through an I2C interface chip; the clock circuit includes a single-ended clock and a differential clock, both of which are used to provide clock signals to the SRIO switching network.

[0011] Preferably, the routing table storage area EEPROM determines its output port based on the SRIO packet and control symbol of the input chip. Each port of the SRIO switching network has an independent routing table of size 512. When the SRIO packet arrives at the entrance, the destination ID of the SRIO packet is checked, and the routing lookup table is checked with this as an index to determine the exit of the SRIO packet.

[0012] Preferably, when there are two SRIO switching networks, the two SRIO switching networks are connected using 4X SRIO; each of the SRIO switching networks is externally connected to a power-on reset circuit, a clock circuit and a routing table storage area EEPROM, and each of the SRIO switching networks is externally connected to 14 1X SRIO nodes.

[0013] Preferably, the rate of the SRIO switching network is not less than 2.5 Gbps.

[0014] Preferably, after the SRIO switching network outputs the low-speed real-time information of the final processing result through the low-speed interface board, it also includes: the low-speed real-time information enters the SRIO switching network through the low-speed interface board, the low-speed real-time information is packaged through the low-speed interface board, and enters the image processing node and the data calculation node through the ID number of each node on the SRIO switching network; the low-speed real-time information is the time code information required by the image data processing algorithm, and the low-speed interface board transmits the final data to the receiving device.

[0015] The present invention proposes a method for operating a high-speed data stream device based on an SRIO bus, comprising the following steps:

[0016] The high-speed camera transmits the image to the high-speed interface board, which packages the received image data and sends it to the SRIO switching network. The SRIO switching network distributes the received image data packets to the image processing node and data computing node for processing. The SRIO switching network outputs the final processing results as low-speed real-time information through the low-speed interface board, and the low-speed real-time information enters the receiving device.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention proposes a high-speed data flow device based on the SRIO bus, which uses the clear data flow characteristics of image data in the computer, and the computing resources composed of multiple nodes to process the image in real time and transmit the results. The SRIO network rate designed by the present invention is not less than 2.5Gbps, which meets the requirements of image data transmission. The present invention connects the computer's internal data input interface and multiple computing nodes, which can realize data interaction between any nodes, so that the computing resources of high-performance computers can be flexibly configured, and there is non-blocking communication between computing nodes, which effectively improves the application efficiency of the computer. Therefore, the solution proposed by the present invention can solve the problem that the data volume of satellite-borne processing systems in the prior art is generally small, and point-to-point transmission methods are mostly used, and resource allocation flexibility is poor, and it is impossible to support data transmission and resource interaction of massive data resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 The block diagram of the 1X SRIO switching network data flow design of the present invention is shown.

[0021] Figure 2 This is a block diagram of the design principle of the 1X SRIO switch unit of the present invention.

[0022] Figure 3 This is a schematic diagram of the design principle of a two-level switching 28-way 1X SRIO switching network according to the present invention.

[0023] Figure 4 This is a functional block diagram of the high-performance real-time processing computer of the present invention. DETAILED DESCRIPTION

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0026] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0027] In the description of the embodiments of the present invention, it should be noted that if the terms "upper," "lower," "horizontal," "inner," etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the inventive product is typically placed when in use. These terms are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0029] In the description of the embodiments of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0030] The present invention is described in further detail below with reference to the accompanying drawings:

[0031] The present invention proposes a high-speed data flow device based on SRIO bus, such as Figure 1 As shown, it includes a high-speed camera, a high-speed interface board, a switching unit and a low-speed interface board;

[0032] A high-speed interface board is externally connected to a high-speed camera. The switching unit includes a 16-way 1X SRIO switching network, an image processing node, and a data computing node. The image processing node and the data computing node are both connected to the 16-way 1X SRIO switching network. The 16-way 1X SRIO switching network is connected to a low-speed interface board. The low-speed interface board is externally connected to a receiving device. The high-speed camera transmits images to the high-speed interface board. The high-speed interface board packages the received image data and sends it to the SRIO switching network. The SRIO switching network distributes the received image data packets to the image processing node and the data computing node for processing. The SRIO switching network outputs the final processing results as low-speed real-time information through the low-speed interface board. The low-speed real-time information enters the receiving device.

[0033] The SRIO switching network is externally connected to a power-on reset circuit, a clock circuit, and an EEPROM for storing a routing table. The power-on reset circuit completes the reset function of the switching network after power-on, and the EEPROM for storing the routing table is used to store the routing table. The EEPROM for storing the routing table is connected to the SRIO switching network via an I2C interface chip. The clock circuit includes a single-ended clock and a differential clock, both of which are used to provide clock signals to the SRIO switching network.

[0034] There are several high-speed cameras; the high-speed cameras transmit images to the high-speed interface board. Specifically, high-speed cameras in different working modes transmit images to the high-speed interface board via the camera-specific channel Serdes interface.

[0035] The high-speed interface board packages the received image data. Specifically, the high-speed interface board packages the image data according to the data sources of different cameras and identifies the destination ID, and transmits it to the SRIO switching network through the 2-way 1X SRIO bus.

[0036] The SRIO switching network distributes the received image data packets to the image processing nodes and data computing nodes for processing. Specifically, each node on the SRIO switching network has a unique ID number and only receives image data packets with the same ID number as itself; the image data packets are distributed to their respective destination ID nodes through the SRIO switching network for image data processing; the image processing nodes and data computing nodes are bound with different data processing algorithms to calculate and process the data; data exchange can be carried out between any nodes on the SRIO switching network, and each image processing node and data computing node is in a parallel relationship.

[0037] After the SRIO switching network outputs the final processing result as low-speed real-time information through the low-speed interface board, the low-speed real-time information also enters the SRIO switching network through the low-speed interface board, the low-speed real-time information is packaged through the low-speed interface board, and enters the image processing node and the data calculation node through the ID number of each node on the SRIO switching network; the low-speed real-time information is the time code information required by the image data processing algorithm, and the low-speed interface board transmits the final data to the receiving device.

[0038] The routing table storage area EEPROM determines the output port based on the SRIO packet and control character of the input chip. Each port of the SRIO switching network has an independent 512-byte routing table. When an SRIO packet arrives at the ingress, the SRIO packet's destination ID is checked and used as an index to check the routing lookup table to determine the SRIO packet's egress. When there are two SRIO switching networks, they are connected using a 4X SRIO connection; each SRIO switching network is externally connected to a power-on reset circuit, clock circuit, and routing table storage area EEPROM. Each SRIO switching network is also externally connected to 14 1X SRIO nodes. The SRIO switching network's speed is no less than 2.5Gbps.

[0039] The technical solution designed and implemented by the present invention is to use a single or multiple SRIO switching circuits to connect the data input interface and the computing node together to form an expandable and flexibly configurable on-board high-speed data flow network. Figure 1 As shown in the figure, a high-speed image data flow working mode based on SRIO bus is realized, and its data flow is as follows:

[0040] 1) Cameras in different operating modes transmit images to the high-speed interface board at a rate of at least 10 Hz via a camera-specific SerDes interface. The high-speed interface board packages the image data based on the camera's data source, identifies the destination ID, and transmits it to the switching unit via two 1X SRIO buses.

[0041] 2) The switching unit consists of a 16-way 1X SRIO switching network, image processing nodes, and data computing nodes. Each node in the switching network has a unique ID number and directly receives data from the same source. Image data from the high-speed interface board is distributed by the switching unit to its respective destination ID node (computing node or processing node) for image data processing. Image processing nodes and data computing nodes are equipped with different data processing algorithms to perform computations on the data. Data exchange can be achieved between any nodes on the switching unit. Each node is in parallel and can communicate data according to algorithm requirements, thus forming a resource pool composed of processing nodes, computing nodes, and switching units, which rapidly realizes image data processing and calculations.

[0042] 3) The final image processing results are transmitted to the low-speed interface board through the SRIO of the switching unit. Low-speed real-time information can also enter the switching unit through the low-speed interface board, and then enter the processing node and computing node; low-speed real-time information is the time code information required by the image data processing algorithm. The low-speed interface board transmits the final data to other single machines in the system.

[0043] 4) In the SRIO protocol specification, communication between endpoints is carried out by sending packets. The transport layer field of the packet contains the destination device ID. The switching unit forwards the packet to the node corresponding to the destination ID based on the destination ID. The routing table (lookup table, LUT) determines the output port based on the SRIO packet and control characters of the input switching chip. Each port in the switching network has an independent routing table of size 512. When a packet arrives at the ingress, the packet's destination ID is checked and used as an index to check the routing lookup table to determine the packet's egress, enabling data packet transmission and data flow interaction between ports.

[0044] SRIO switch unit as attached Figure 2 , consists of a power-on reset circuit, a clock circuit, a switching network, and an EEPROM for storing the routing table. The power-on reset circuit completes the reset function of the switching network after power-on. The switching network implements 16-way 1X SRIO switching function. The EEPROM is used to store the routing table. The clock circuit includes a single-ended clock and a differential clock to provide a clock signal to the switching network. After the switching circuit is powered on and reset, the routing table information is read from the EEPROM for storing the routing table and the operation begins. The routing table information is used to configure the corresponding ID number of each port, and the data flow is redirected to the corresponding node according to the destination ID number of the data entering the switching network, thereby realizing the transmission of data packets and data flow interaction between ports. The routing table information stored in the EEPROM can be updated by any SRIO node according to the protocol, which increases the flexibility and scalability of product applications.

[0045] A single switching circuit can support 8 4X modes or 16 1X modes. When the number of computing nodes is greater than 16, a two-stage switching method can be used. Figure 3 The two switching circuits use 4X SRIO connections, which can support a data flow switching network consisting of up to 28 1X SRIO nodes.

[0046] The present invention provides a high-performance satellite-borne image data real-time processing computer based on a high-speed data stream exchange network of an SRIO bus. The block diagram of the scheme design is shown in the attached figure. Figure 4 The computer, with switching circuits at its core, includes a camera image interface, switching network, image processing, data processing, and power supply and distribution. It also incorporates a redundant backup design and has been applied and flight-verified in a high-performance computer for a certain mission.

[0047] The present invention proposes a method for operating a high-speed data stream device based on an SRIO bus, comprising the following steps:

[0048] The high-speed camera transmits the image to the high-speed interface board, which packages the received image data and sends it to the SRIO switching network. The SRIO switching network distributes the received image data packets to the image processing node and data computing node for processing. The SRIO switching network outputs the final processing results as low-speed real-time information through the low-speed interface board, and the low-speed real-time information enters the receiving device.

[0049] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A high-speed data stream device based on SRIO bus, characterized in that: Includes high-speed camera, high-speed interface board, switching unit and low-speed interface board; The high-speed interface board is externally connected to a high-speed camera. The switching unit includes a 16-way 1X SRIO switching network, an image processing node, and a data computing node. The image processing node and the data computing node are both connected to the 16-way 1X SRIO switching network. The 16-way 1X SRIO switching network is connected to a low-speed interface board. The low-speed interface board is externally connected to a receiving device. The high-speed camera transmits images to the high-speed interface board, which packages the received image data and sends it to the SRIO switching network. The SRIO switching network distributes the received image data packets to the image processing node and the data computing node for processing. The SRIO switching network outputs the final processing results as low-speed real-time information through the low-speed interface board, and the low-speed real-time information enters the receiving device. After the SRIO switching network outputs the final processing result as low-speed real-time information through the low-speed interface board, the process also includes: the low-speed real-time information enters the SRIO switching network through the low-speed interface board, the low-speed real-time information is packaged through the low-speed interface board, and enters the image processing node and the data computing node through the ID number of each node on the SRIO switching network; The low-speed real-time information is the time code information required by the image data processing algorithm, and the low-speed interface board transmits the final data to the receiving device.

2. The high-speed data stream device based on SRIO bus according to claim 1, characterized in that: There are several high-speed cameras; the high-speed cameras transmit images to the high-speed interface board. Specifically, high-speed cameras in different working modes transmit images to the high-speed interface board via a camera-specific channel Serdes interface.

3. The high-speed data stream device based on SRIO bus according to claim 1, characterized in that: The high-speed interface board packages the received image data. Specifically, the high-speed interface board packages the image data according to the data sources of different cameras and identifies the destination ID, and transmits it to the SRIO switching network through the 2-way 1X SRIO bus.

4. The high-speed data stream device based on SRIO bus according to claim 1, characterized in that: The SRIO switching network distributes the received image data packets to the image processing nodes and data computing nodes for processing. Specifically, each node on the SRIO switching network has a unique ID number and only receives image data packets with the same ID number as itself; the image data packets are distributed to their respective destination ID nodes through the SRIO switching network for image data processing; Image processing nodes and data computing nodes are bound with different data processing algorithms to perform data processing; data interaction can be carried out between any nodes on the SRIO switching network, and each image processing node and data computing node is in a parallel relationship.

5. The high-speed data stream device based on SRIO bus according to claim 1, characterized in that: The SRIO switching network is externally connected to a power-on reset circuit, a clock circuit, and a routing table storage area EEPROM; the power-on reset circuit completes the reset function of the switching network after power-on, and the routing table storage area EEPROM is used to store the routing table; the routing table storage area EEPROM is connected to the SRIO switching network through an I2C interface chip; the clock circuit includes a single-ended clock and a differential clock, both of which are used to provide clock signals to the SRIO switching network.

6. The high-speed data stream device based on SRIO bus according to claim 5, characterized in that: The routing table storage area EEPROM determines its output port based on the SRIO packet and control character of the input chip. Each port of the SRIO switching network has an independent routing table of size 512. When the SRIO packet arrives at the entrance, the destination ID of the SRIO packet is checked and used as an index to check the routing lookup table to determine the exit of the SRIO packet.

7. The high-speed data stream device based on SRIO bus according to claim 1, characterized in that: When there are two SRIO switching networks, the two SRIO switching networks are connected using 4X SRIO; each of the SRIO switching networks is externally connected to a power-on reset circuit, a clock circuit, and a routing table storage area EEPROM, and each of the SRIO switching networks is externally connected to 14 1X SRIO nodes.

8. The high-speed data stream device based on SRIO bus according to claim 1, characterized in that: The rate of the SRIO switching network is not less than 2.5 Gbps.

9. A method for operating a high-speed data stream device based on an SRIO bus, characterized in that: The high-speed data stream device based on the SRIO bus according to any one of claims 1 to 8 comprises the following steps: The high-speed camera transmits the image to the high-speed interface board, which packages the received image data and sends it to the SRIO switching network. The SRIO switching network distributes the received image data packets to the image processing node and data computing node for processing. The SRIO switching network outputs the final processing results as low-speed real-time information through the low-speed interface board, and the low-speed real-time information enters the receiving device.

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