Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises: a plurality of data signal lines, the data signal lines comprising: first data signal lines and second data signal lines; the first data signal lines are respectively electrically connected with first color sub-pixels and second color sub-pixels; the display substrate further comprises: first selection signal lines, second selection signal lines, a plurality of data power supply lines and a data selection circuit; the data selection circuit is configured to provide signals of the data power supply lines to the first data signal lines under the control of signals of the first selection signal lines or the second selection signal lines; the data power supply lines comprise: first data power supply lines and second data power supply lines; the first data power supply lines are configured to provide first color data signals, the first color data signals being data signals provided to the first color sub-pixels; the second data power supply lines are configured to provide second color data signals, the second color data signals being data signals provided to the second color sub-pixels.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, the present disclosure provides a display substrate, comprising: a plurality of sub-pixels and a plurality of data signal lines, the sub-pixels comprising: a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; the data signal lines comprising: a first data signal line and a second data signal line, the first data signal line being electrically connected with the first color sub-pixel and the second color sub-pixel respectively, the second data signal line being electrically connected with the third color sub-pixel, the first data signal line and the second data signal line being arranged alternately along a first direction, the data signal lines extending along a second direction, the first direction and the second direction intersecting;

[0005] The display substrate further comprises: a first selection signal line, a second selection signal line, a plurality of data power supply lines and a data selection circuit;

[0006] The data selection circuit is electrically connected with the first selection signal line, the second selection signal line, the plurality of first data signal lines and the plurality of data power supply lines respectively, and is configured to provide the signal of the data power supply line to the first data signal line under the control of the signal of the first selection signal line or the second selection signal line;

[0007] The data supply lines include a first data supply line and a second data supply line, the first data supply line is configured to supply a first color data signal, the first color data signal is a data signal supplied to a first color sub-pixel, the second data supply line is configured to supply a second color data signal, the second color data signal is a data signal supplied to a second color sub-pixel, the data supply lines extend along a second direction, the first data supply line and the second data supply line are arranged alternately along a first direction.

[0008] In an example embodiment, the display substrate further includes N scanning signal lines, an nth scanning signal line is electrically connected with an nth row of sub-pixels and extends along the first direction, 1≤n≤N;

[0009] The signal of the first selection signal line and the signal of the second selection signal line are not simultaneously valid level signals;

[0010] When the signal of an odd-numbered scanning signal line is a valid level signal, the signal of the first selection signal line is a valid level signal, and when the signal of an even-numbered scanning signal line is a valid level signal, the signal of the second selection signal line is a valid level signal.

[0011] In an example embodiment, a 4a-3th column of sub-pixels in an odd-numbered row is a first color sub-pixel, a 4a-1th column of sub-pixels in an odd-numbered row is a second color sub-pixel, a 4a-3th column of sub-pixels in an even-numbered row is a second color sub-pixel, and a 4a-1th column of sub-pixels in an odd-numbered row is a first color sub-pixel, 1≤a≤M / 4, M is the total number of columns of sub-pixels and is even;

[0012] The first color is one of red or blue, the second color is the other of red or blue, and the third color is green.

[0013] In an example embodiment, the number of data signal lines in the display substrate is equal to M or 3M / 2;

[0014] When the number of data signal lines is equal to M, an mth column of sub-pixels is electrically connected with an mth data signal line, wherein an odd-numbered data signal line is a first data signal line, an even-numbered data signal line is a second data signal line, the number of data supply lines is equal to K or K+1, K=M / 2, 1≤m≤M;

[0015] When the number of data signal lines is equal to 3M / 2, the xth column of sub-pixels is electrically connected to the 3x / 2th data signal line, the yth column of sub-pixels in the odd row is electrically connected to the (3y-1) / 2th data signal line, the yth column of sub-pixels in the even row is electrically connected to the (3y+1) / 2th data signal line, the 3z-1th data signal line and the 3z-2th data signal line are first data signal lines, the 3zth data signal line is a second data signal line, the number of data supply lines is equal to K, 1≤x≤M and is even, 1≤y≤M and is odd, and 1≤z≤K.

[0016] In an example embodiment, when the number of data supply lines is equal to K, the odd data supply line is a first data supply line, and the even data supply line is a second data supply line.

[0017] In an example embodiment, the data selection circuit includes a first data selection circuit and a second data selection circuit.

[0018] The first data selection circuit is electrically connected to a first selection signal line, a plurality of first data signal lines, and the first data supply line to the Kth data supply line, respectively, and is configured to provide the signal of the data supply line to the first data signal line under the control of the signal of the first selection signal line when the odd row of sub-pixels is displayed.

[0019] The second data selection circuit is electrically connected to a second selection signal line, a plurality of first data signal lines, and the first data supply line to the Kth data supply line, respectively, and is configured to provide the signal of the data supply line to the first data signal line under the control of the signal of the second selection signal line when the even row of sub-pixels is displayed.

[0020] In an example embodiment, when the number of data signal lines is equal to M, the first data selection circuit includes K first transistors, and the second data selection circuit includes K second transistors.

[0021] The control electrode of the bth first transistor is electrically connected to the first selection signal line, the first electrode of the bth first transistor is electrically connected to the 2b-1th data signal line, and the second electrode of the bth first transistor is electrically connected to the bth data supply line, 1≤b≤K.

[0022] The control electrode of the bth second transistor is electrically connected to the second selection signal line, the first electrode of the bth second transistor is electrically connected to the 2b-1th data signal line, and the second electrode of the bth second transistor is electrically connected to the cth data supply line, c=b+1 when b is odd, and c=b-1 when k is even.

[0023] In an example embodiment, when the number of data signal lines is equal to 3M / 2, the first data selection circuit comprises K first transistors, and the second data selection circuit comprises K second transistors.

[0024] The control electrode of the bth first transistor is electrically connected to the first selection signal line, the first electrode of the bth first transistor is electrically connected to the 3b-2th data signal line, and the second electrode of the bth first transistor is electrically connected to the bth data supply line, where 1≤b≤K.

[0025] The control electrode of the bth second transistor is electrically connected to the second selection signal line, the first electrode of the bth second transistor is electrically connected to the 3b-1th data signal line, and the second electrode of the bth second transistor is electrically connected to the wth data supply line, where c=b+1 when b is odd, and c=b-1 when b is even.

[0026] In an example embodiment, when the number of data supply lines is equal to K+1, the odd-numbered data supply lines are second data supply lines, and the even-numbered data supply lines are first data supply lines.

[0027] In an example embodiment, the data selection circuit comprises a first data selection circuit and a second data selection circuit.

[0028] The first data selection circuit is electrically connected to a first selection signal line, a plurality of first data signal lines, and the second data supply line to the (K+1)th data supply line, and is configured to provide the first data signal line with a signal of the data supply line under the control of a signal of the first selection signal line when the odd-numbered row of sub-pixels is displayed.

[0029] The second data selection circuit is electrically connected to a second selection signal line, a plurality of first data signal lines, and the first data supply line to the Kth data supply line, and is configured to provide the first data signal line with a signal of the data supply line under the control of a signal of the second selection signal line when the even-numbered row of sub-pixels is displayed.

[0030] In an example embodiment, the first data selection circuit comprises K first transistors, and the second data selection circuit comprises K second transistors.

[0031] The control electrode of the bth first transistor is electrically connected to the first selection signal line, the first electrode of the bth first transistor is electrically connected to the 2b-1th data signal line, and the second electrode of the bth first transistor is electrically connected to the (b+1)th data supply line, where 1≤b≤K.

[0032] The control electrode of the bth second transistor is electrically connected to the second selection signal line, the first electrode of the bth second transistor is electrically connected to the 2b-1th data signal line, and the second electrode of the bth second transistor is electrically connected to the bth data power supply line.

[0033] In an exemplary embodiment, the display substrate includes: a base and a driving structure layer disposed on the base, the driving structure layer including: a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked on the base, and the transistor includes an active pattern;

[0034] The semiconductor layer includes at least: an active pattern of a first transistor and an active pattern of a second transistor;

[0035] The first conductive layer at least includes: a gate electrode of a first transistor, a gate electrode of a second transistor and a second data signal line;

[0036] The second conductive layer at least includes: a first data signal line and a data power supply line;

[0037] The third conductive layer at least includes: a first selection signal line, a second selection signal line, a first electrode and a second electrode of a first transistor, and a first electrode and a second electrode of a second transistor.

[0038] In an exemplary embodiment, the first selection signal line and the second selection signal line extend along a first direction and are arranged along a second direction;

[0039] The orthographic projection of the second data signal line on the substrate partially overlaps with the orthographic projections of the first selection signal line and the second selection signal line on the substrate;

[0040] An orthographic projection of one of the first selection signal line and the second selection signal line close to the sub-pixel on the substrate partially overlaps with an orthographic projection of the first data signal line on the substrate.

[0041] In an exemplary embodiment, when the number of data signal lines is equal to M and the number of data power supply lines is equal to K, the display substrate further includes: R first connection electrodes, R second connection electrodes, R third connection electrodes, and R fourth connection electrodes, the first connection electrodes and the second connection electrodes extend along the second direction and are located in the second conductive layer, the third connection electrodes and the fourth connection electrodes extend along the first direction and are located in the third conductive layer, and R=K / 2;

[0042] An orthographic projection of any one of the first connection electrode and the second connection electrode on the substrate partially overlaps with an orthographic projection of the first selection signal line on the substrate;

[0043] The rth first connection electrode is connected with the second electrode of the 2r-1th second transistor and the rth third connection electrode, the rth second connection electrode is connected with the second electrode of the 2rth second transistor and the rth fourth connection electrode, the rth third connection electrode is connected with the 2rth data supply line, the rth fourth connection electrode is connected with the 2r-1th data supply line, and 1≤r≤R.

[0044] In an exemplary embodiment, when the number of data signal lines is M and the number of data supply lines is equal to K+1, the display substrate further comprises K+1 first connection electrodes and K+1 second connection electrodes, the first connection electrodes extend along the second direction and are located in the second conductive layer, and the second connection electrodes extend along the first direction and are located in the third conductive layer.

[0045] The first first connection electrode is connected with the second electrode of the first second transistor and the first second connection electrode, the s th first connection electrode is connected with the second electrode of the s-1 th first transistor and the s th second connection electrode, and the i th second connection electrode is connected with the i th data supply line, and 2≤s≤K+1.

[0046] In an exemplary embodiment, when the number of data signal lines is equal to M, the active pattern of the k th first transistor and the active pattern of the k th second transistor are integrated structures.

[0047] When the number of data signal lines is equal to 3M / 2, the active pattern of the k th first transistor and the active pattern of the k th second transistor are arranged at intervals.

[0048] In a second aspect, the present disclosure further provides a display device, comprising the above display substrate.

[0049] In an exemplary embodiment, further comprising a driver.

[0050] The driver is connected with the plurality of second data signal lines and the plurality of data supply lines.

[0051] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0052] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, together with the embodiments of the present application, to explain the technical solutions of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0053] FIG. 1 FIG. 1 is a structural schematic diagram of a display device;

[0054] FIG. 2 FIG. 2 is a plan structural schematic diagram of a display substrate;

[0055] FIG. 3 Equivalent circuit diagram of a pixel driving circuit

[0056] FIG. 4A Structure schematic of a display substrate provided by an embodiment of the present disclosure FIG. 1

[0057] FIG. 4B Structure schematic of a display substrate provided by an embodiment of the present disclosure FIG. 2

[0058] FIG. 5 Timing diagram of partial signals of a display substrate

[0059] FIG. 6 Structure schematic of a data selection circuit provided by an exemplary embodiment FIG. 1

[0060] Equivalent circuit diagram of a data selection circuit provided by FIG. 7 FIG. 6

[0061] FIG. 8 Structure schematic of a data selection circuit provided by an exemplary embodiment FIG. 2

[0062] Equivalent circuit diagram of a data selection circuit provided by FIG. 9 FIG. 8

[0063] FIG. 10 Structure schematic of a data selection circuit provided by an exemplary embodiment FIG. 3

[0064] Equivalent circuit diagram of a data selection circuit provided by FIG. 11 FIG. 10 Planar schematic of a data conversion circuit provided by

[0065] FIG. 12 FIG. 7 Planar schematic of a data conversion circuit provided by

[0066] FIG. 13 Planar schematic of a data conversion circuit provided by FIG. 11

[0067] Planar schematic of a data conversion circuit provided by FIG. 14 FIG. 9 Planar schematic of a data conversion circuit provided by

[0068] FIG. 15 FIG. 12 Schematic of a semiconductor layer pattern in

[0069] ​​​​​​​​​​FIG. 16 is a schematic view of a semiconductor layer pattern in FIG. 13

[0070] FIG. 17 is a schematic view of a semiconductor layer pattern in FIG. 14

[0071] FIG. 18 is a schematic view of a first conductive layer pattern in FIG. 12

[0072] FIG. 19 is a schematic view after forming a first conductive layer pattern FIG. 12

[0073] FIG. 20 is a schematic view of a first conductive layer pattern in FIG. 13

[0074] FIG. 21 is a schematic view after forming a first conductive layer pattern FIG. 13

[0075] FIG. 22 is a schematic view of a first conductive layer pattern in FIG. 14

[0076] FIG. 23 is a schematic view after forming a first conductive layer pattern FIG. 14

[0077] FIG. 24 is a schematic view of a second conductive layer pattern in FIG. 12

[0078] FIG. 25 is a schematic view after forming a second conductive layer pattern FIG. 12

[0079] FIG. 26 is a schematic view of a second conductive layer pattern in FIG. 13

[0080] FIG. 27 is a schematic view after forming a second conductive layer pattern FIG. 13

[0081] FIG. 28 is a schematic view of a second conductive layer pattern in FIG. 14

[0082] FIG. 29 is a schematic view after forming a second conductive layer pattern FIG. 14

[0083] FIG. 30 is a schematic view after forming a third insulating layer pattern FIG. 12 is a schematic view after forming a third insulating layer pattern​​​​​​​​​​​​​​

[0084] FIG. 31 To FIG. 13 schematic view after forming a third insulating layer pattern;

[0085] FIG. 32 To FIG. 14 schematic view after forming a third insulating layer pattern;

[0086] FIG. 33 To FIG. 12 schematic view of the third conductive layer pattern in

[0087] FIG. 34 To FIG. 12 schematic view after forming a third conductive layer pattern;

[0088] FIG. 35 To FIG. 13 schematic view of the third conductive layer pattern in

[0089] FIG. 36 To FIG. 13 schematic view after forming a third conductive layer pattern;

[0090] FIG. 37 To FIG. 14 schematic view of the third conductive layer pattern in

[0091] FIG. 38 To FIG. 14 schematic view after forming a third conductive layer pattern. DETAILED DESCRIPTION

[0092] In order to make the objects, technical solutions, and advantages of the present disclosure clearer, below will be a detailed description of the embodiments of the present disclosure in conjunction with the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. One skilled in the art can easily understand that the means and content can be varied into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

[0093] In the drawings, the size, the thickness of the layers, or the region of each constituent element is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to such a size. The shapes and the sizes of the components shown in the drawings do not reflect the true proportions of the components. Furthermore, the drawings are schematically showing ideal examples, and one embodiment of the present disclosure is not limited to the shapes or the values shown in the drawings.

[0094] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0095] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0096] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0097] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0098] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0099] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0100] In the present specification, "parallel" means a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus, a state in which the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus, a state in which the angle is 85° or more and 95° or less is also included.

[0101] In the present specification, "film" and "layer" can be replaced with each other. For example, "a conductive layer" can be replaced with "a conductive film" at times. Similarly, "an insulating film" can be replaced with "an insulating layer" at times.

[0102] In the present specification, "disposed in the same layer" means that two (or more) structures are patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of precursors for forming the plurality of structures disposed in the same layer are the same, and the materials finally formed can be the same or different.

[0103] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly so, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. There can be some small deformation due to a tolerance, and there can be an inside corner, an arc edge, and a deformation, etc.

[0104] In the present disclosure, "about" means not strictly limited to a boundary, and allows a value within a range of process and measurement error.

[0105] FIG. 1 A structure diagram of a display device. As shown in FIG. 1 The display device can include a timing controller, a data signal driver, a scan signal driver, and a pixel array, and the pixel array can include a plurality of scan signal lines (Gate1 to Gate N ), a plurality of data signal lines (Data1 to Data L ), and a plurality of sub-pixels Pxij.

[0106] In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data signal driver to the data signal driver, and can provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver to the scan signal driver. The data signal driver can generate a data signal to be provided to the data signal lines Data1, Data2, Data3,..., and Data LFor example, the data signal driver can sample the grayscale value using the clock signal and apply the data voltage corresponding to the grayscale value to the data signal lines Data1, Data2, Data3, ... and Data1 in units of sub-pixel rows. L , L can be a natural number. The scan signal driver can generate the scan signal lines Gate1, Gate2, Gate3, ... and Gate 1 by receiving the clock signal, scan start signal, etc. from the timing controller. N For example, the scan signal driver may sequentially supply a scan signal having an on-level pulse to the scan signal lines Gate1 to Gate2. N For example, the scan signal driver may be constructed in the form of a shift register and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal, where N may be a natural number. The sub-pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line, where i and j may be natural numbers.

[0107] FIG. 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. FIG. 2 As shown, a display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line and a data signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0108] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the shape of the subpixels may be rectangular, diamond, pentagonal, or hexagonal.

[0109] In an exemplary embodiment, FIG. 2As shown, one pixel unit can include four sub-pixels, which can be one first sub-pixel, one second sub-pixel, and two third sub-pixels. The four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure. FIG. 2 The four sub-pixels are arranged in a square manner. FIG. 2 The arrangement manner of the four sub-pixels in the pixel unit is called a Bayer arrangement manner.

[0110] In an exemplary embodiment, the light-emitting device can be an organic electroluminescent diode (OLED) including a stacked electrode (anode), organic light-emitting layer, and second electrode (cathode).

[0111] In an exemplary embodiment, the organic light-emitting layer can include a stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0112] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. FIG. 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown, FIG. 3As shown, the pixel driving circuit is of 3T1C structure, which can include 3 pixel transistors (a first pixel transistor M1, a second pixel transistor M2 and a third pixel transistor M3), 1 capacitor C and 6 signal lines (a data signal line Data, a scanning signal line Gate, a control signal line Sn, a compensation signal line Se, a first power supply line VDD and a second power supply line VSS). In the exemplary embodiment, the first pixel transistor M1 is a switch transistor, the second pixel transistor M2 is a driving transistor, and the third pixel transistor M3 is a compensation transistor. The gate electrode of the first pixel transistor M1 is coupled to the scanning signal line Gate, the first electrode of the first pixel transistor M1 is coupled to the data signal line Data, and the second electrode of the first pixel transistor M1 is coupled to the gate electrode of the second pixel transistor M2. The first pixel transistor M1 is configured to receive a data signal transmitted by the data signal line Data under the control of the scanning signal line Gate, so that the gate electrode of the second pixel transistor M2 receives the data signal. The gate electrode of the second pixel transistor M2 is coupled to the second electrode of the first pixel transistor M1, the first electrode of the second pixel transistor M2 is coupled to the first power supply line VDD, and the second electrode of the second pixel transistor M2 is coupled to the first electrode of the light emitting device L. The second pixel transistor M2 is configured to generate a corresponding current at the second electrode under the control of the data signal received by the gate electrode thereof. The gate electrode of the third pixel transistor M3 is coupled to the second scanning signal line Sn, the first electrode of the third pixel transistor M3 is coupled to the compensation signal line Se, and the second electrode of the third pixel transistor M3 is coupled to the second electrode of the second pixel transistor M2. The third pixel transistor M3 is configured to extract the threshold voltage Vth and the mobility of the second pixel transistor M2 in response to the compensation timing, so as to compensate the threshold voltage Vth. The first electrode of the light emitting device L is coupled to the second electrode of the second pixel transistor M2, the second electrode of the light emitting device L is coupled to the second power supply line VSS, and the light emitting device L is configured to emit light of a corresponding brightness in response to the current of the second electrode of the second pixel transistor M2. The first electrode of the capacitor C is coupled to the gate electrode of the second pixel transistor M2, and the second electrode of the capacitor C is coupled to the second electrode of the second pixel transistor M2. The capacitor C is configured to store the potential of the gate electrode of the second pixel transistor M2.

[0113] In the exemplary embodiment, the second electrode of the light emitting device L is electrically connected to the second power supply line VSS.

[0114] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0115] In an exemplary embodiment, the first to third pixel transistors M1 to M3 may be P-type transistors.

[0116] In an exemplary embodiment, the first power line VDD continuously provides a high level signal, and the second power line VSS continuously provides a low level signal.

[0117] With the development of display technology, the Bayer sub-pixel arrangement design has become a common design for mainstream products. FIG. 2 As shown, the odd-numbered column data signal lines connect two different light-emitting sub-pixels, the first sub-pixel and the second sub-pixel, so that when the display product displays a pure red and blue color image, the driver that provides signals to the data signal lines will switch between the first color data signal and the second color data signal at a high frequency, resulting in higher power consumption of the display product.

[0118] FIG. 4A Schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure FIG. 1 , FIG. 4B Schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure FIG. 2 .like FIG. 4A and FIG. 4B As shown, the display substrate provided by the embodiment of the present disclosure may include: a plurality of sub-pixels and a plurality of data signal lines Data, the sub-pixels include: a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; the data signal lines Data include: a first data signal line and a second data signal line, the first data signal line is electrically connected to the first color sub-pixel and the second color sub-pixel respectively, the second data signal line is electrically connected to the third color sub-pixel, the first data signal line and the second data signal line are alternately arranged along the first direction D1, the data signal line Data extends along the second direction D2, and the first direction D1 and the second direction D2 intersect.

[0119] like FIG. 4A and FIG. 4B As shown, the display substrate further includes: a first selection signal line SW1, a second selection signal line SW2, a plurality of data power supply lines DL1 to DL TAnd a data selection circuit. The data selection circuit is respectively connected to the first selection signal line SW1, the second selection signal line SW2, a plurality of first data signal lines Data and a plurality of data power supply lines DL1 to DL T The first data power supply line DL is electrically connected to the first data signal line and is configured to provide a data power supply line signal to the first data signal line under the control of a signal of the first selection signal line SW1 or the second selection signal line SW2; wherein the data power supply line includes: a first data power supply line and a second data power supply line, the first data power supply line is configured to provide a first color data signal, the first color data signal is a data signal provided to the first color sub-pixel, the second data power supply line is configured to provide a second color data signal, the second color data signal is a data signal provided to the second color sub-pixel, the data power supply line DL extends along the second direction D2, and the first data power supply line and the second data power supply line are alternately arranged along the first direction D1.

[0120] In an exemplary embodiment, FIG. 4A and FIG. 4B As shown, the subpixel in the 4a-3 column of the odd-numbered row is a first color subpixel, the subpixel in the 4a-1 column of the odd-numbered row is a second color subpixel, the subpixel in the 4a-3 column of the even-numbered row is a second color subpixel, and the subpixel in the 4a-1 column of the odd-numbered row is a first color subpixel, where 1≤a≤M / 4, and M is the total number of subpixel columns, which is an even number. For example, the subpixels in all odd-numbered rows are arranged in the same manner, and the arrangement in all even-numbered rows is the same. Taking the subpixels in the first row as an example, the subpixels in the first column of the first row, the subpixels in the fifth column of the first row, and the subpixels in the ninth column of the first row, etc., are first color subpixels, and the subpixels in the third column of the first row, the subpixels in the seventh column of the first row, and the subpixels in the eleventh column of the first row, etc., are second color subpixels. Taking the second row of sub-pixels as an example, the second row first column sub-pixels, the second row fifth column sub-pixels, the second row ninth column sub-pixels, etc. are second color sub-pixels, and the second row third column sub-pixels, the second row seventh column sub-pixels, the second row eleventh column sub-pixels, etc. are first color sub-pixels.

[0121] In an exemplary embodiment, FIG. 4A and FIG. 4B As shown, all even-numbered columns of sub-pixels are third-color sub-pixels. Exemplarily, the second, fourth, and sixth columns of sub-pixels are third-color sub-pixels.

[0122] In an exemplary embodiment, the first color is one of red or blue, the second color is the other of red or blue, and the third color is a green sub-pixel. Exemplarily, when the first color is red, the second color is blue, and when the first color is blue, the second color is red. FIG. 4A and FIG. 4Bis described by taking the first color as red, the second color as blue, i.e. the first color sub-pixel as a red sub-pixel R, the second color sub-pixel as a blue sub-pixel B, and the third color sub-pixel as a green sub-pixel G as an example.

[0123] In an exemplary embodiment, the number of data signal lines can be greater than or equal to M, FIG. 4A is described by taking the number of data signal lines as M as an example, FIG. 4B is described by taking the number of data signal lines greater than M and the number of data signal lines equal to 3M / 2 as an example. FIG. 4A In the case of FIG. 8, only 8 data signal lines Data1 to Data8 are shown, FIG. 4A In the case of FIG. 12, 12 data signal lines Data1 to Data 12 .

[0124] In an exemplary embodiment, as shown in FIG. 1, FIG. 4B when the number of data signal lines is equal to M, the mth column of sub-pixels is electrically connected with the mth data signal line Data m . Exemplarily, the first column of sub-pixels is electrically connected with the first data signal line Data1, the second column of sub-pixels is electrically connected with the second data signal line Data2, and so on.

[0125] In an exemplary embodiment, as shown in FIG. 1, FIG. 4B when the number of data signal lines is equal to M, the odd-numbered data signal lines are first data signal lines, and the even-numbered data signal lines are second data signal lines, i.e. the first data signal line Data1, the third data signal line Data3, and so on are first data signal lines, and the second data signal line Data2, the fourth data signal line Data4, and so on are second data signal lines.

[0126] In an exemplary embodiment, as shown in FIG. 1, FIG. 4AAs shown, when the number of data signal lines is equal to 3M / 2, the xthcolumn of sub-pixels is electrically connected to the 3x / 2thdata signal line, the ythcolumn of sub-pixels in the odd row is electrically connected to the (3y-1) / 2thdata signal line, and the ythcolumn of sub-pixels in the even row is electrically connected to the (3y+1) / 2thdata signal line, 1≤x≤M, and x is even, 1≤y≤M, and y is odd. For example, the second column of sub-pixels is electrically connected to the third data signal line Data3, the fourth column of sub-pixels is electrically connected to the sixth data signal line Data6, and so on. The same connection mode is used for the same column of sub-pixels in the odd row. For example, the first column of sub-pixels in the first row is electrically connected to the first data signal line Data1, the third column of sub-pixels in the first row is electrically connected to the fourth data signal line Data4, the fifth column of sub-pixels in the first row is electrically connected to the seventh data signal line Data4, and so on. The same connection mode is used for the same column of sub-pixels in the even row. For example, the first column of sub-pixels in the second row is electrically connected to the second data signal line Data2, the third column of sub-pixels in the second row is electrically connected to the fifth data signal line Data5, the fifth column of sub-pixels in the second row is electrically connected to the eighth data signal line Data8, and so on.

[0127] In an exemplary embodiment, as shown in FIG. 1, the display substrate is electrically connected to the data selection circuit, and the data selection circuit is configured to provide signals to the data supply lines. FIG. 4B As shown, when the number of data signal lines is equal to 3M / 2, the 3z-1thdata signal line and the 3z-2thdata signal line are the first data signal lines, the 3zthdata signal line is the second data signal line, and 1≤z≤K. That is, the first data signal line Data1, the second data signal line Data2, the fourth data signal line Data4, the fifth data signal line Data5, the seventh data signal line Data7, the eighth data signal line Data8, and so on are the first data signal lines, and the third data signal line Data3, the sixth data signal line Data6, the ninth data signal line Data9, and so on are the second data signal lines.

[0128] In an exemplary embodiment, the display substrate is further electrically connected to a driver, and the driver is configured to provide signals to the data supply lines. Due to the arrangement of the data selection circuit of the present disclosure, the data supply lines continuously provide the same color data signal regardless of the picture displayed by the display substrate, that is, the driver providing signals to the data supply lines does not need to switch between different color data signals at a high frequency.

[0129] The display substrate provided by the embodiment of the present disclosure includes: a plurality of sub-pixels and a plurality of data signal lines, the sub-pixels include: a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; the data signal lines include: a first data signal line and a second data signal line, the first data signal line is electrically connected to the first color sub-pixel and the second color sub-pixel respectively, the second data signal line is electrically connected to the third color sub-pixel, the first data signal line and the second data signal line are alternately arranged along a first direction, the data signal line extends along a second direction, and the first direction and the second direction intersect; the display substrate also includes: a first selection signal line, a second selection signal line, a plurality of data power supply lines and a data selection circuit; the data selection circuit is respectively connected to the first selection signal line. A plurality of first data signal lines and a plurality of data power supply lines are electrically connected and configured to provide a signal of a data power supply line to the first data signal line under the control of a signal of the first selection signal line or the second selection signal line; the data power supply line includes a first data power supply line and a second data power supply line, the first data power supply line is configured to provide a first color data signal, the first color data signal is a data signal provided to a first color sub-pixel, the second data power supply line is configured to provide a second color data signal, the second color data signal is a data signal provided to a second color sub-pixel, the data power supply line extends along a second direction, and the first data power supply line and the second data power supply line are alternately arranged along the first direction. The present disclosure can provide a signal to the first data signal line by providing a data power supply line by setting a data selection circuit, so that when the display product is displaying a red and blue pure color picture, the driver that provides the data signal does not need to switch between different data signals at high frequency, which can reduce the power consumption of the display product and improve the reliability of the display product.

[0130] In an exemplary embodiment, FIG. 4A and FIG. 4B As shown, the display substrate further includes: N scanning signal lines Gate1 to Gate N , the nth scanning signal line Gate 年 Electrically connected to the n-th row of sub-pixels, 1≤n≤N.

[0131] In an exemplary embodiment, FIG. 5 and FIG. 5 As shown, the scan signal lines may extend along the first direction D1.

[0132] In an exemplary embodiment, the content displayed by the display substrate may include a plurality of display frames. FIG. 5 This is a timing diagram showing some signals of the substrate. FIG. 5 As shown, in any display frame, the signal of any scanning signal line is a single pulse signal, and the signals of the first selection signal line SW1 and the second selection signal line SW2 are multiple pulse signals.

[0133] In an exemplary embodiment, the duration of the valid level signal of any scan signal line is t1, where t1≤t2, t1≤t3, t2 is the duration of one of the valid level signals of the first selection signal line SW1, and t3 is the duration of one of the valid level signals of the second selection signal line SW2.

[0134] like FIG. 5 As shown, the signal of the first selection signal line SW1 and the signal of the second selection signal line SW2 are not both active level signals. For example, when the signal of the first selection signal line SW1 is an active level signal, the signal of the second selection signal line SW2 is an inactive level signal; and when the signal of the second selection signal line SW2 is an active level signal, the signal of the first selection signal line SW1 is an inactive level signal. A signal line signal being an active level signal means that the transistor connected to the signal line is turned on, and a signal line signal being an inactive level signal means that the transistor connected to the signal line is turned off.

[0135] In an exemplary embodiment, FIG. 6 As shown, when the signal of the odd-numbered scanning signal line is an active-level signal, the signal of the first selection signal line SW1 is an active-level signal. For example, when the signal of the first scanning signal line Gate1 is an active-level signal, the signal of the first selection signal line SW1 is an active-level signal. When the signal of the third scanning signal line Gate3 is an active-level signal, the signal of the first selection signal line SW1 is an active-level signal, and so on.

[0136] In an exemplary embodiment, FIG. 1 As shown, when the signal of the even-numbered scanning signal line is an effective level signal, the signal of the second selection signal line SW2 is an effective level signal. For example, when the signal of the second scanning signal line Gate2 is an effective level signal, the signal of the second selection signal line SW2 is an effective level signal. When the signal of the fourth scanning signal line Gate4 is an effective level signal, the signal of the second selection signal line SW2 is an effective level signal, and so on.

[0137] In an exemplary embodiment, when the number of data signal lines is equal to M, the number of data power supply lines T may be equal to K or K+1, where K=M / 2, wherein the number of second data power supply lines is greater than or equal to the number of first data power supply lines. For example, when M=8, T may be equal to 4 or 5.

[0138] In an exemplary embodiment, when the number of data signal lines is equal to 3M / 2, the number of data power supply lines is equal to K.

[0139] In an exemplary embodiment, FIG. 7Structure diagram of data selection circuit provided for an exemplary embodiment FIG. 6 , FIG. 8 Data selection circuit provided for FIG. 2 Equivalent circuit diagram of data selection circuit provided for FIG. 9 Structure diagram of data selection circuit provided for an exemplary embodiment FIG. 8 , FIG. 10 Data selection circuit provided for FIG. 3 Equivalent circuit diagram of data selection circuit provided for FIG. 11 Structure diagram of data selection circuit provided for an exemplary embodiment FIG. 10 , FIG. 6 Data selection circuit provided for FIG. 7 Equivalent circuit diagram of data selection circuit provided for FIG. 8 and FIG. 9 are described by taking an example of the number of data signal lines being equal to M and the number of data supply lines being equal to K, FIG. 10 and FIG. 11 are described by taking an example of the number of data signal lines being equal to 3M / 2 and the number of data supply lines being equal to K, FIG. 6 and FIG. 8 are described by taking an example of the number of data signal lines being equal to M and the number of data supply lines being equal to K+1.

[0140] In an exemplary embodiment, when the number of data supply lines is equal to K, the odd-numbered data supply lines are first data supply lines, and the even-numbered data supply lines are second data supply lines.

[0141] In an exemplary embodiment, as shown in FIG. 7 and FIG. 7 , when the number of data signal lines is equal to M or 3M / 2 and the number of data supply lines is equal to K, the data selection circuit can include a first data selection circuit and a second data selection circuit. The first data selection circuit is respectively electrically connected with a first selection signal line SW1, a plurality of first data signal lines, and a first data supply line DL1 to a Kth data supply line DLK, and is configured to provide the first data signal lines with signals of the data supply lines under control of a signal of the first selection signal line SW1 when odd-numbered rows of sub-pixels are displayed; and the second data selection circuit is respectively electrically connected with a second selection signal line SW2, the plurality of first data signal lines, and the first data supply line DL1 to the Kth data supply line DLK, and is configured to provide the first data signal lines with signals of the data supply lines under control of a signal of the second selection signal line SW2 when even-numbered rows of sub-pixels are displayed. K electrically connected with a first selection signal line SW1, a plurality of first data signal lines, and a first data supply line DL1 to a Kth data supply line DLK, and is configured to provide the first data signal lines with signals of the data supply lines under control of a signal of the first selection signal line SW1 when odd-numbered rows of sub-pixels are displayed; and the second data selection circuit is respectively electrically connected with a second selection signal line SW2, the plurality of first data signal lines, and the first data supply line DL1 to the Kth data supply line DLK, and is configured to provide the first data signal lines with signals of the data supply lines under control of a signal of the second selection signal line SW2 when even-numbered rows of sub-pixels are displayed. K electrically connected with a first selection signal line SW1, a plurality of first data signal lines, and a first data supply line DL1 to a Kth data supply line DLK, and is configured to provide the first data signal lines with signals of the data supply lines under control of a signal of the first selection signal line SW1 when odd-numbered rows of sub-pixels are displayed; and the second data selection circuit is respectively electrically connected with a second selection signal line SW2, the plurality of first data signal lines, and the first data supply line DL1 to the Kth data supply line DLK, and is configured to provide the first data signal lines with signals of the data supply lines under control of a signal of the second selection signal line SW2 when even-numbered rows of sub-pixels are displayed.

[0142] In an exemplary embodiment, as shown in FIG. 7As shown, when the number of data signal lines is equal to M, the first data selection circuit may include K first transistors T1 , and the second data selection circuit may include K second transistors T2 . FIG. 7 Only four first transistors T1 and four second transistors T2 are shown.

[0143] In an exemplary embodiment, FIG. 7 As shown, the control electrode of the b-th first transistor is electrically connected to the first selection signal line, the first electrode of the b-th first transistor is electrically connected to the 2b-1th data signal line, and the second electrode of the b-th first transistor is electrically connected to the b-th data power supply line, where 1≤b≤K. For example, the control electrode of the first first transistor T1 is electrically connected to the first selection signal line SW1, the first electrode of the first first transistor T1 is electrically connected to the first data signal line Data1, and the second electrode of the first first transistor T1 is electrically connected to the first data power supply line DL1; the control electrode of the second first transistor T1 is electrically connected to the first selection signal line SW1, the first electrode of the second first transistor is electrically connected to the third data signal line Data3, and the second electrode of the second first transistor is electrically connected to the second data power supply line DL2; the control electrode of the third first transistor T1 is electrically connected to the first selection signal line SW1, the first electrode of the third first transistor is electrically connected to the fifth data signal line Data5, and the second electrode of the third first transistor is electrically connected to the third data power supply line DL3, and so on. When the number of data signal lines is equal to M, all odd-numbered data signal lines are first data signal lines. Therefore, the first electrodes of all first transistors are electrically connected to the first data signal lines.

[0144] In an exemplary embodiment, FIG. 5 As shown, the control electrode of the b-th second transistor T2 is electrically connected to the second selection signal line SW2, and the first electrode of the b-th second transistor T2 is electrically connected to the 2b-1 data signal line Data 2b-1 The second electrode of the bth second transistor T2 is electrically connected to the cth data power supply line DL cThe first electrode of the first second transistor T2 is electrically connected with the first data signal line Data1, the second electrode of the first second transistor T2 is electrically connected with the second data supply line DL2, the control electrode of the second second transistor T2 is electrically connected with the second selection signal line SW2, the first electrode of the second second transistor T2 is electrically connected with the third data signal line Data3, the second electrode of the second second transistor T2 is electrically connected with the first data supply line DL1, the control electrode of the third second transistor T2 is electrically connected with the second selection signal line SW2, the first electrode of the third second transistor T2 is electrically connected with the fifth data signal line Data5, the second electrode of the third second transistor T2 is electrically connected with the fourth data supply line DL4, the control electrode of the fourth second transistor T2 is electrically connected with the second selection signal line SW2, the first electrode of the fourth second transistor T2 is electrically connected with the seventh data signal line Data7, the second electrode of the fourth second transistor T2 is electrically connected with the third data supply line DL3, and so on. Since the number of the data signal lines is equal to M, all the odd-numbered data signal lines are the first data signal lines, and therefore the first electrodes of all the second transistors are electrically connected with the first data signal lines.

[0145] As shown in FIG. 8, according to the working timing, the working timing of the display substrate can include an odd-numbered row display stage S1 and an even-numbered row display stage S2 alternately occurring, wherein, FIG. 9 FIG. 9 As shown in FIG. 8, according to the working timing, the working timing of the display substrate can include an odd-numbered row display stage S1 and an even-numbered row display stage S2 alternately occurring, wherein,

[0146] ​In the odd row display stage S1, the signals of the first selection signal line SW1 and the odd-numbered scan signal lines are low signals, the signal of the first selection signal line SW1 is a low signal, all the first transistors T1 are turned on, the signal of the first data supply line DL1 is written into the first column of sub-pixels (the first color sub-pixel) of the odd-numbered rows through the first first transistor T1 and the first data signal line Data1, the signal of the second data supply line DL2 is written into the third column of sub-pixels (the second color sub-pixel) of the odd-numbered rows through the second first transistor T1 and the third data signal line Data3, the signal of the third data supply line DL3 is written into the fifth column of sub-pixels (the first color sub-pixel) of the odd-numbered rows through the third first transistor T1 and the fifth data signal line Data5, the signal of the fourth data supply line DL4 is written into the seventh column of sub-pixels (the second color sub-pixel) of the odd-numbered rows through the fourth first transistor T1 and the seventh data signal line Data7, and the like. Since the odd-numbered data supply line is the first data supply line and the even-numbered data supply line is the second data supply line when the number of data supply lines is equal to K, the signal of the first data supply line can be provided into the first color sub-pixel and the signal of the second data supply line can be provided into the second color sub-pixel in the present disclosure.

[0147] In the even row display stage S2, the signals of the second selection signal line SW2 and the even-numbered scan signal lines are low signals, the signal of the second selection signal line SW2 is a low signal, all the second transistors T2 are turned on, the signal of the second data supply line DL2 is written into the first column of sub-pixels (the second color sub-pixel) of the even-numbered rows through the first second transistor T2 and the first data signal line Data1, the signal of the first data supply line DL1 is written into the third column of sub-pixels (the first color sub-pixel) of the even-numbered rows through the second second transistor T2 and the third data signal line Data3, the signal of the fourth data supply line DL4 is written into the fifth column of sub-pixels (the second color sub-pixel) of the even-numbered rows through the third second transistor T2 and the fifth data signal line Data5, the signal of the third data supply line DL3 is written into the seventh column of sub-pixels (the first color sub-pixel) of the even-numbered rows through the fourth second transistor T2 and the seventh data signal line Data7, and the like. Since the odd-numbered data supply line is the first data supply line and the even-numbered data supply line is the second data supply line when the number of data supply lines is equal to K, the signal of the first data supply line can be provided into the first color sub-pixel and the signal of the second data supply line can be provided into the second color sub-pixel in the present disclosure.

[0148] In the example embodiment, as FIG. 9As shown, when the number of data signal lines is equal to M, the first data selection circuit can include K first transistors T1, and the second data selection circuit can include K second transistors T2. FIG. 9 Only 4 first transistors T1 and 4 second transistors T2 are shown.

[0149] In an exemplary embodiment, as shown, FIG. 9 the control electrode of the bth first transistor is electrically connected with the first selection signal line, the first electrode of the bth first transistor is electrically connected with the 3b-2th data signal line, and the second electrode of the bth first transistor is electrically connected with the bth data supply line, 1≤b≤K. Exemplarily, the control electrode of the first first transistor T1 is electrically connected with the first selection signal line SW1, the first electrode of the first first transistor T1 is electrically connected with the first data signal line Data1, and the second electrode of the first first transistor T1 is electrically connected with the first data supply line DL1; the control electrode of the second first transistor T1 is electrically connected with the first selection signal line SW1, the first electrode of the second first transistor is electrically connected with the fourth data signal line Data4, and the second electrode of the second first transistor is electrically connected with the second data supply line DL2; the control electrode of the third first transistor T1 is electrically connected with the first selection signal line SW1, the first electrode of the third first transistor is electrically connected with the seventh data signal line Data7, and the second electrode of the third first transistor is electrically connected with the third data supply line DL3; and so on. Since when the number of data signal lines is equal to M, all odd data signal lines are first data signal lines, the first electrode of all first transistors is electrically connected with the first data signal line.

[0150] In an exemplary embodiment, as shown, FIG. 5As shown, the control electrode of the bth second transistor is electrically connected to the second selection signal line, the first electrode of the bth second transistor is electrically connected to the 3b-1th data signal line, and the second electrode of the bth second transistor is electrically connected to the wth data power supply line. When b is an odd number, c=b+1, and when b is an even number, c=b-1. Illustratively, the control electrode of the first second transistor T2 is electrically connected to the second selection signal line SW2, the first electrode of the first second transistor T2 is electrically connected to the second data signal line Data2, and the second electrode of the first second transistor T2 is electrically connected to the second data power supply line DL2; the control electrode of the second second transistor T2 is electrically connected to the second selection signal line SW2, the first electrode of the second second transistor T2 is electrically connected to the fifth data signal line Data5, the second electrode of the second second transistor T2 is electrically connected to the first data power supply line DL1, the control electrode of the third second transistor T2 is electrically connected to the second selection signal line SW2, the first electrode of the third second transistor T2 is electrically connected to the eighth data signal line Data8, the second electrode of the third second transistor T2 is electrically connected to the fourth data power supply line DL4, the control electrode of the fourth second transistor T2 is electrically connected to the second selection signal line SW2, and the first electrode of the fourth second transistor is electrically connected to the eleventh data signal line Data 11 The second electrode of the fourth second transistor is electrically connected to the third data power supply line DL3, and so on. Since when the number of data signal lines is equal to M, all odd-numbered data signal lines are first data signal lines, the first electrodes of all second transistors are electrically connected to the first data signal lines.

[0151] like FIG. 10 As shown, according to FIG. 11 Taking the transistor as a P-type transistor as an example, the working timing of the display substrate may include an odd-numbered row display phase S1 and an even-numbered row display phase S2 that occur alternately, wherein:

[0152] In the odd-numbered row display phase S1, the signals of the first selection signal line SW1 and the odd-numbered scanning signal lines are low-level signals, the signal of the first selection signal line SW1 is a low-level signal, all the first transistors T1 are turned on, the signal of the first data power supply line DL1 is written into the sub-pixel (first color sub-pixel) of the first column of the odd-numbered row through the first first transistor T1 and the first data signal line Data1, the signal of the second data power supply line DL2 is written into the sub-pixel (second color sub-pixel) of the third column of the odd-numbered row through the second first transistor T1 and the fourth data signal line Data4, the signal of the third data power supply line DL3 is written into the sub-pixel (first color sub-pixel) of the fifth column of the odd-numbered row through the third first transistor T1 and the seventh data signal line Data7, the signal of the fourth data power supply line DL4 is written into the sub-pixel (first color sub-pixel) of the fifth column of the odd-numbered row through the fourth first transistor T1 and the tenth data signal line Data10 The odd-numbered row seventh column sub-pixel (second color sub-pixel) is written, and the like. Since when the number of data supply lines is equal to K, the odd-numbered data supply line is the first data supply line, and the even-numbered data supply line is the second data supply line, the present disclosure can achieve that the signal of the first data supply line can be provided to the first color sub-pixel, and the signal of the second data supply line can be provided to the second color sub-pixel.

[0153] In the even-numbered row display stage S2, the signals of the second selection signal line SW2 and the even-numbered scan signal lines are low signals, the signal of the second selection signal line SW2 is a low signal, all the second transistors T2 are turned on, the signal of the second data supply line DL2 is written to the even-numbered row first column sub-pixel (second color sub-pixel) through the first second transistor T2 and the second data signal line Data2, the signal of the first data supply line DL1 is written to the even-numbered row third column sub-pixel (first color sub-pixel) through the second second transistor T2 and the fifth data signal line Data5, the signal of the fourth data supply line DL4 is written to the even-numbered row fifth column sub-pixel (second color sub-pixel) through the third second transistor T2 and the eighth data signal line Data8, and the signal of the third data supply line DL3 is written to the even-numbered row seventh column sub-pixel (first color sub-pixel) through the fourth second transistor T2 and the eleventh data signal line Data 11 The odd-numbered row seventh column sub-pixel (second color sub-pixel) is written, and the like. Since when the number of data supply lines is equal to K, the odd-numbered data supply line is the first data supply line, and the even-numbered data supply line is the second data supply line, the present disclosure can achieve that the signal of the first data supply line can be provided to the first color sub-pixel, and the signal of the second data supply line can be provided to the second color sub-pixel.

[0154] In the exemplary embodiment, as shown in FIG. 10 and FIG. 11 When the number of data supply lines is K+1, the odd-numbered data supply line is the second data supply line, and the even-numbered data supply line is the first data supply line.

[0155] In the exemplary embodiment, as shown in FIG. 11 and FIG. 11 The data selection circuit includes a first data selection circuit and a second data selection circuit. The first data selection circuit is respectively connected with the first selection signal line SW1, the plurality of first data signal lines, and the second data supply line DL2 to the K+1th data supply line DL K+1The first data selection circuit is electrically connected to the first selection signal line SW1 and the first data signal line, and is configured to provide the signal of the data supply line to the first data signal line under the control of the signal of the first selection signal line SW1 when the odd-numbered row sub-pixels are displayed. K The second data selection circuit is electrically connected to the second selection signal line SW2 and the first data signal line, and is configured to provide the signal of the data supply line to the first data signal line under the control of the signal of the second selection signal line SW2 when the even-numbered row sub-pixels are displayed.

[0156] In an example embodiment, as shown in FIG. 1, the first data selection circuit can include K first transistors T1, and the second data selection circuit can include K second transistors T2. FIG. 11 FIG. 11 Only 4 first transistors T1 and 4 second transistors T2 are shown.

[0157] In an example embodiment, as shown in FIG. 1, the first data selection circuit can include K first transistors T1, and the second data selection circuit can include K second transistors T2. FIG. 11 The control electrode of the bth first transistor is electrically connected to the first selection signal line, the first electrode of the bth first transistor is electrically connected to the 2b-1th data signal line, the second electrode of the bth first transistor is electrically connected to the b+1th data supply line, and 1≤b≤K. For example, the control electrode of the first first transistor T1 is electrically connected to the first selection signal line SW1, the first electrode of the first first transistor T1 is electrically connected to the second data signal line Data2, and the second electrode of the first first transistor T1 is electrically connected to the first data supply line DL1; the control electrode of the second first transistor T1 is electrically connected to the first selection signal line SW1, the first electrode of the second first transistor is electrically connected to the third data signal line Data3, and the second electrode of the second first transistor is electrically connected to the third data supply line DL3; the control electrode of the third first transistor T1 is electrically connected to the first selection signal line SW1, the first electrode of the third first transistor is electrically connected to the fifth data signal line Data5, and the second electrode of the third first transistor is electrically connected to the fourth data supply line DL4; and so on. Since the number of data signal lines is equal to M, all odd-numbered data signal lines are first data signal lines, and therefore the first electrodes of all first transistors are electrically connected to the first data signal line.

[0158] In an example embodiment, as shown in FIG. 1, the first data selection circuit can include K first transistors T1, and the second data selection circuit can include K second transistors T2. FIG. 5 ​As shown, the control electrode of the bth second transistor is electrically connected to the second selection signal line, the first electrode of the bth second transistor is electrically connected to the 2b-1th data signal line, and the second electrode of the bth second transistor is electrically connected to the bth data power supply line. Illustratively, the control electrode of the first second transistor T2 is electrically connected to the second selection signal line SW2, the first electrode of the first second transistor T2 is electrically connected to the first data signal line Data1, and the second electrode of the first second transistor T2 is electrically connected to the first data power supply line DL1; the control electrode of the second second transistor T2 is electrically connected to the second selection signal line SW2, the first electrode of the second second transistor T2 is electrically connected to the second data signal line Data2, and the second electrode of the second second transistor T2 is electrically connected to the first data power supply line DL1; the control electrode of the third second transistor T2 is electrically connected to the second selection signal line SW2, the first electrode of the third second transistor is electrically connected to the fifth data signal line Data5, and the second electrode of the third second transistor is electrically connected to the third data power supply line DL3; the control electrode of the fourth second transistor T2 is electrically connected to the second selection signal line SW2, the first electrode of the fourth second transistor is electrically connected to the seventh data signal line Data7, and the second electrode of the fourth second transistor is electrically connected to the fourth data power supply line DL4, and so on. Since when the number of data signal lines is equal to M, all odd-numbered data signal lines are first data signal lines, the first electrodes of all second transistors are electrically connected to the first data signal lines.

[0159] like FIG. 12 As shown, according to FIG. 7 Taking the transistor as a P-type transistor as an example, the working timing of the display substrate may include an odd-numbered row display phase S1 and an even-numbered row display phase S2 that occur alternately, wherein:

[0160] The signals of the odd row display stage S1, the first selection signal line SW1 and the first odd scan signal line are low level signals, the signal of the first selection signal line SW1 is a low level signal, all the first transistors T1 are turned on, the signal of the second data supply line DL2 is written into the first column sub-pixel (the first color sub-pixel) of the first odd row through the first first transistor T1 and the first data signal line Data1, the signal of the third data supply line DL3 is written into the third column sub-pixel (the second color sub-pixel) of the first odd row through the second first transistor T1 and the third data signal line Data3, the signal of the fourth data supply line DL4 is written into the fifth column sub-pixel (the first color sub-pixel) of the first odd row through the third first transistor T1 and the fifth data signal line Data5, the signal of the fifth data supply line DL5 is written into the seventh column sub-pixel (the second color sub-pixel) of the first odd row through the fourth first transistor T1 and the seventh data signal line Data7, and the like. Since the number of the data supply lines is equal to K+1, the first odd data supply line is the first data supply line and the second even data supply line is the second data supply line, the signal of the first data supply line can be provided into the first color sub-pixel, and the signal of the second data supply line can be provided into the second color sub-pixel.

[0161] The signals of the even row display stage S2, the second selection signal line SW2 and the second even scan signal line are low level signals, the signal of the second selection signal line SW2 is a low level signal, all the second transistors T2 are turned on, the signal of the first data supply line DL1 is written into the first column sub-pixel (the second color sub-pixel) of the second even row through the first second transistor T2 and the first data signal line Data1, the signal of the second data supply line DL2 is written into the third column sub-pixel (the first color sub-pixel) of the second even row through the second second transistor T2 and the third data signal line Data3, the signal of the third data supply line DL3 is written into the fifth column sub-pixel (the second color sub-pixel) of the second even row through the third second transistor T2 and the fifth data signal line Data5, the signal of the fourth data supply line DL4 is written into the seventh column sub-pixel (the first color sub-pixel) of the second even row through the fourth second transistor T2 and the seventh data signal line Data7, and the like. Since the number of the data supply lines is equal to K+1, the first odd data supply line is the second data supply line and the second even data supply line is the first data supply line, the signal of the first data supply line can be provided into the first color sub-pixel, and the signal of the second data supply line can be provided into the second color sub-pixel.

[0162] FIG. 13 For FIG. 11 a plan view of a data conversion circuit, FIG. 14 for FIG. 9A plan view of the data conversion circuit is provided, FIG. 12 to FIG. 14 For FIG. 12 A plan view of the data conversion circuit is provided. In an exemplary embodiment, as shown in FIG. 13 The display substrate can include a base and a driving structure layer disposed on the base, the driving structure layer including a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked on the base, and the transistor includes an active pattern.

[0163] In an exemplary embodiment, the semiconductor layer includes at least an active pattern of a first transistor T1 and an active pattern of a second transistor T2.

[0164] In an exemplary embodiment, the first conductive layer includes at least a gate electrode of the first transistor T1, a gate electrode of the second transistor T2, and a second data signal line. FIG. 14 The second data signal line in the above FIG. 12 The second data signal line in the above FIG. 13 The second data signal line in the above

[0165] In an exemplary embodiment, the second conductive layer includes at least a first data signal line and a data power line DL. FIG. 14 The first data signal line in the above FIG. 12 to FIG. 14 The first data signal line in the above FIG. 12 to FIG. 14 The first data signal line in the above

[0166] In an exemplary embodiment, the third conductive layer includes at least a first selection signal line SW1, a second selection signal line SW2, a first electrode and a second electrode of the first transistor T1, and a first electrode and a second electrode of the second transistor T2.

[0167] In an exemplary embodiment, as shown in FIG. 12As shown, the first selection signal line SW1 and the second selection signal line SW2 extend along the first direction D1 and are arranged along the second direction D2. The orthographic projection of the second data signal line on the substrate partially overlaps with the orthographic projection of the first selection signal line SW1 and the second selection signal line SW2 on the substrate.

[0168] In an exemplary embodiment, FIG. 12 As shown, the orthographic projection of one of the first selection signal line SW1 and the second selection signal line SW2 close to the sub-pixel on the substrate partially overlaps with the orthographic projection of the first data signal line on the substrate.

[0169] In an exemplary embodiment, FIG. 12 As shown, when the number of data signal lines is equal to M and the number of data power supply lines is equal to K, the display substrate further includes: R first connection electrodes CL1, R second connection electrodes CL2, R third connection electrodes CL3 and R fourth connection electrodes CL4, the first connection electrode CL1 and the second connection electrode CL2 extend along the second direction D2 and are located in the second conductive layer, the third connection electrode CL3 and the fourth connection electrode CL4 extend along the first direction D1 and are located in the third conductive layer, and R = K / 2. FIG. 12 Only two first connection electrodes CL1 , two second connection electrodes CL2 , two third connection electrodes CL3 and two fourth connection electrodes CL4 are shown.

[0170] In an exemplary embodiment, FIG. 12 As shown, an orthographic projection of any one of the first link electrode CL1 and the second link electrode CL2 on the substrate partially overlaps with an orthographic projection of the first selection signal line SW1 on the substrate.

[0171] In an exemplary embodiment, FIG. 12 As shown, the rth first connection electrode CL1 is respectively connected to the second electrode of the 2r-1th second transistor T2 and the rth third connection electrode CL3, where 1≤r≤R. Exemplarily, the first first connection electrode CL1 is respectively electrically connected to the second electrode of the first second transistor and the first third connection electrode CL3, and the second first connection electrode CL1 is respectively electrically connected to the second electrode of the third second transistor and the second third connection electrode CL3.

[0172] In an exemplary embodiment, FIG. 12 As shown, the r-th second connection electrode CL2 is respectively connected to the second electrode of the 2r-th second transistor T2 and the r-th fourth connection electrode CL4. For example, the first second connection electrode CL2 is respectively electrically connected to the second electrode of the second second transistor and the first fourth connection electrode CL4, and the second second connection electrode CL2 is respectively electrically connected to the second electrode of the fourth second transistor and the second fourth connection electrode CL4.

[0173] In an exemplary embodiment, FIG. 13 As shown, the rth third link electrode CL3 is electrically connected to the 2rth data power supply line. Exemplarily, the first third link electrode CL3 is electrically connected to the second data power supply line DL2, and the second third link electrode CL3 is electrically connected to the fourth data power supply line DL4.

[0174] In an exemplary embodiment, FIG. 13 As shown, the rth fourth link electrode CL4 is electrically connected to the 2r-1th data power supply line. Exemplarily, the first fourth link electrode CL4 is electrically connected to the first data power supply line DL1, and the second fourth link electrode CL4 is electrically connected to the third data power supply line DL3.

[0175] In an exemplary embodiment, FIG. 13 As shown, when the number of data signal lines is M and the number of data power supply lines is equal to K+1, the display substrate further includes: K+1 first connection electrodes VL1 and K+1 second connection electrodes VL2, the first connection electrodes VL1 extend along the second direction D2 and are located in the second conductive layer, and the second connection electrodes VL2 extend along the first direction D1 and are located in the third conductive layer.

[0176] In an exemplary embodiment, FIG. 13 As shown, the first first connection electrode VL1 is electrically connected to the second electrode of the first second transistor and the first second connection electrode VL2 respectively.

[0177] In an exemplary embodiment, FIG. 12 As shown, the sth first connection electrode is electrically connected to the second electrode of the s-1th first transistor and the sth second connection electrode, respectively, where 2≤s≤K+1. Exemplarily, the second first connection electrode is electrically connected to the second electrode of the first first transistor and the second second connection electrode, respectively, the third first connection electrode is electrically connected to the second electrode of the second first transistor and the third second connection electrode, and so on.

[0178] In an exemplary embodiment, FIG. 13 As shown, the i-th second connection electrode is electrically connected to the i-th data power supply line. Exemplarily, the first second connection electrode VL2 is electrically connected to the first data power supply line DL1, the second second connection electrode VL2 is electrically connected to the second data power supply line DL2, the third second connection electrode VL2 is electrically connected to the third data power supply line DL3, and so on.

[0179] In an exemplary embodiment, FIG. 14 and FIG. 15 to FIG. 38As shown, when the number of data signal lines is equal to M, the active pattern of the kth first transistor T1 and the active pattern of the kth second transistor T2 are integrated structures.

[0180] In an exemplary embodiment, as shown, FIG. 15 to FIG. 38 As shown, when the number of data signal lines is equal to 3M / 2, the active pattern of the kth first transistor T1 and the active pattern of the kth second transistor T2 are spaced apart.

[0181] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be, but is not limited to, one or more of glass, metal foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl acid ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0182] In an exemplary embodiment, the driving structure layer can further include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a planar layer. The first insulating layer is between the semiconductor layer and the first conductive layer, the second insulating layer is between the first conductive layer and the second conductive layer, the third insulating layer is between the second conductive layer and the third conductive layer, the fourth insulating layer is on the side of the third conductive layer away from the substrate, and the planar layer is on the side of the fourth insulating layer away from the substrate.

[0183] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on the driving structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate.

[0184] In an exemplary embodiment, the display substrate can further include other film layers, such as a touch structure layer, etc., which are not limited in the present disclosure.

[0185] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need a patterning process in the whole preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the whole preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0186] FIG. 15 to FIG. 38 The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need a patterning process in the whole preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the whole preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. FIG. 12 to FIG. 14 FIG. 15 to FIG. 17 FIG. 15 The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need a patterning process in the whole preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the whole preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0187] (1) Forming a semiconductor layer pattern. In the exemplary embodiments, forming a semiconductor layer pattern can include: sequentially depositing a semiconductor thin film on a substrate, patterning the semiconductor thin film by a patterning process, and forming a semiconductor layer pattern covering the substrate, as shown in FIG. 1A. FIG. 12 FIG. 16 FIG. 1B is a schematic diagram of the semiconductor layer pattern in FIG. 1A, FIG. 13 FIG. 1C is a schematic diagram of the semiconductor layer pattern in FIG. 1A, FIG. 17 FIG. 1D is a schematic diagram of the semiconductor layer pattern in FIG. 1A, FIG. 14 FIG. 1E is a schematic diagram of the semiconductor layer pattern in FIG. 1A. FIG. 15 to FIG. 17 FIG. 15 In the exemplary embodiments, as shown in FIG. 1A, the semiconductor layer pattern can at least include: an active pattern T11 of a first transistor and an active pattern T21 of a second transistor.

[0188] In the exemplary embodiments, as shown in FIG. 1A, the semiconductor layer pattern can at least include: an active pattern T11 of a first transistor and an active pattern T21 of a second transistor. FIG. 16 ​​​​​

[0189] In an example embodiment, as shown in FIG. 15 and FIG. 16 The active pattern T11 of the kth first transistor and the active pattern T21 of the kth second transistor are in one structure.

[0190] In an example embodiment, as shown in FIG. 17 The active pattern of the dth first transistor and the active pattern of the d+1th first transistor are located between the active pattern of the dth second transistor and the active pattern of the d+1th second transistor, d is greater than or equal to 1 and less than an odd number of K. For example, the active pattern of the first first transistor and the active pattern of the second first transistor are located between the active pattern of the first second transistor and the active pattern of the second second transistor, the active pattern of the third first transistor and the active pattern of the second fourth transistor are located between the active pattern of the third second transistor and the active pattern of the second fourth transistor, and so on.

[0191] In an example embodiment, as shown in FIG. 15 The active pattern T11 of the first transistor and the active pattern T21 of the second transistor are alternately arranged along the first direction D1, and the active pattern T11 of the first first transistor is located between the active pattern T21 of the first second transistor and the active pattern T21 of the second second transistor.

[0192] In an example embodiment, as shown in FIG. 16 The active pattern T11 of the first transistor and the active pattern T21 of the kth second transistor are separately provided. The active pattern T11 of the first transistor and the active pattern T21 of the second transistor are alternately arranged along the first direction D1, and the active pattern T21 of the first second transistor is located between the active pattern T11 of the first first transistor and the active pattern T11 of the second first transistor.

[0193] In an example embodiment, the active pattern T11 of the first transistor and the active pattern T21 of the second transistor can be in the shape of a strip extending along the second direction and arranged along the first direction D1.

[0194] In an example embodiment, the active pattern of each transistor can include a first region, a second region, and a channel region located between the first region and the second region.

[0195] In an example embodiment, as shown in FIG. 17 and FIG. 18 to FIG. 23As shown, the first region T11-1 of the active pattern T11 of the kth first transistor can also serve as the first region T21-1 of the active pattern T21 of the second transistor, and the second region T11-2 of the active pattern T11 of the kth first transistor and the second region T21-2 of the active pattern T21 of the second transistor can be separately provided.

[0196] In an exemplary embodiment, FIG. 18 As shown, the first and second regions T11 - 1 and T11 - 2 of the active pattern T11 of the first transistor and the first and second regions T21 - 1 and T21 - 2 of the active pattern T21 of the second transistor may be separately provided.

[0197] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, such as FIG. 12 As shown, FIG. 19 for FIG. 12 Schematic diagram of the first conductive layer pattern in FIG. 20 for FIG. 13 Schematic diagram after forming the first conductive layer pattern, FIG. 21 for FIG. 13 Schematic diagram of the first conductive layer pattern in FIG. 22 for FIG. 14 Schematic diagram after forming the first conductive layer pattern, FIG. 23 for FIG. 14 Schematic diagram of the first conductive layer pattern in FIG. 18 to FIG. 23 for FIG. 18 to FIG. 21 Schematic diagram after forming a first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0198] In an exemplary embodiment, FIG. 22 As shown, the first conductive layer may include at least: a gate electrode T12 of the first transistor, a gate electrode T22 of the second transistor, and a second data signal line. FIG. 23 As shown, the second data signal line refers to an even-numbered data signal line, such as the second data signal line Data2, the fourth data signal line Data4, the sixth data signal line Data6, and the eighth data signal line Data8. FIG. 18 to FIG. 23 river FIG. 18 The second data signal line in the data signal line refers to the 3zth data signal line, for example, the third data signal line Data3, the sixth data signal line Data6, the ninth data signal line Data9 and the twelfth data signal line Data 12 .

[0199] In an exemplary embodiment, FIG. 19 As shown, the second data signal line may be in a line shape with a main portion extending along the second direction D2.

[0200] In an exemplary embodiment, FIG. 18 and FIG. 19 As shown, the shape of the gate electrode T12 of the odd-numbered first transistor can be a horizontally flipped "L" shape, the shape of the gate electrode T12 of the even-numbered first transistor can be an "L" shape, the shape of the gate electrode T22 of the odd-numbered second transistor can be a "7" shape, and the shape of the gate electrode T12 of the even-numbered second transistor can be a horizontally flipped "7" shape.

[0201] In an exemplary embodiment, FIG. 20 to FIG. 23 and FIG. 20 As shown, the gate electrodes of adjacent first transistors are symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and the gate electrodes of adjacent second transistors are symmetrically arranged with respect to a virtual straight line extending along the second direction D2. The gate electrode of the first second transistor is located on a side of the gate electrode of the first first transistor away from the second data signal line Data2.

[0202] In an exemplary embodiment, FIG. 21 As shown, the gate electrode T12 of the first transistor may be in a horizontally inverted "L" shape, and the gate electrode T22 of the second transistor may be in a "7" shape.

[0203] In an exemplary embodiment, FIG. 22 and FIG. 23 As shown, the gate electrode of the kth second transistor is located on a side of the second data signal line that is away from the gate electrode of the kth first transistor and close to the gate electrode of the kth first transistor. For example, the gate electrode of the first second transistor is located on a side of the second data signal line (second data signal line Data2) that is away from the gate electrode of the first first transistor and close to the gate electrode of the first first transistor, the gate electrode of the second second transistor is located on a side of the second data signal line (fourth data signal line Data4) that is away from the gate electrode of the second first transistor and close to the gate electrode of the second first transistor, and so on.

[0204] In an exemplary embodiment, FIG. 24 to FIG. 29 and FIG. 24As shown, the gate electrode of the kth first transistor is located on the side of the gate electrode of the kth second transistor away from the second data signal line close to the gate electrode of the kth second transistor. For example, the gate electrode of the first first transistor is located on the side of the gate electrode of the first second transistor away from the second data signal line (the third data signal line Data3) close to the gate electrode of the first second transistor, the gate electrode of the second first transistor is located on the side of the gate electrode of the second second transistor away from the second data signal line (the sixth data signal line Data6) close to the gate electrode of the second second transistor, and so on.

[0205] In the exemplary embodiment, after the first conductive layer pattern is formed, the semiconductor layer pattern can be subjected to a conductorization treatment using the first conductive layer as a shield. The semiconductor layer pattern in the region shielded by the first conductive layer forms the channel region of the first transistor T1 and the second transistor T2, and the semiconductor layer pattern in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the active pattern of the first transistor to the second transistor are both conductorized.

[0206] In the exemplary embodiment, the gate electrode T12 of the first transistor is arranged across the active pattern of the first transistor, and the gate electrode T22 of the second transistor is arranged across the active pattern of the second transistor, that is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0207] (3) Forming a second conductive layer pattern, comprising: sequentially depositing a second insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the second insulating thin film and the second conductive thin film by a patterning process to form a second insulating layer and a second conductive layer pattern on the second insulating layer, such as FIG. 12 As shown, FIG. 25 for FIG. 12 a schematic diagram of the second conductive layer pattern in FIG. 26 for FIG. 13 a schematic diagram after the second conductive layer pattern is formed, FIG. 27 for FIG. 13 a schematic diagram of the second conductive layer pattern in FIG. 28 for FIG. 14 a schematic diagram after the second conductive layer pattern is formed, FIG. 29 for FIG. 14 a schematic diagram of the second conductive layer pattern in FIG. 24 to FIG. 29 for FIG. 24 to FIG. 27 a schematic diagram after the second conductive layer pattern is formed. In the exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0208] In the exemplary embodiment, as shown in FIG. 29As shown, the second conductive layer pattern may include at least: a first data signal line and a data power supply line. FIG. 29 The first data signal line in the reference numeral refers to an odd-numbered data signal line, such as the first data signal line Data1, the third data signal line Data3, the fifth data signal line Data5, and the seventh data signal line Data7, and so on. FIG. 24 and FIG. 25 The first data signal line in the data signal line refers to the 3z-2 data signal line and the 3z-1 data signal line, for example, the first data signal line Data1, the second data signal line Data2, the fourth data signal line Data4, the fifth data signal line Data5, the seventh data signal line Data7, the eighth data signal line Data8, the tenth data signal line Data 10 , the eleventh data signal line Data 11 , and so on.

[0209] In an exemplary embodiment, the first data signal line has a line shape in which a main portion extends along the second direction D2.

[0210] In an exemplary embodiment, the data power supply line has a line shape in which a main body portion extends along the second direction D2.

[0211] In an exemplary embodiment, FIG. 26 and FIG. 27 As shown, the second conductive layer may include at least a first connection electrode CL1 and a second connection electrode CL2 , wherein the first connection electrode CL1 and the second connection electrode CL2 are in the shape of strips extending along the second direction D2 .

[0212] In an exemplary embodiment, FIG. 30 to FIG. 32 and FIG. 30 As shown, the second conductive layer may include at least a first connection electrode VL1 , wherein the first connection electrode VL1 is in a strip shape extending along the second direction D2 .

[0213] (4) forming a third insulating layer pattern, comprising: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned pattern, wherein the third insulating layer is provided with a plurality of via patterns, such as FIG. 12 As shown, FIG. 31 for FIG. 13 Schematic diagram after forming the third insulating layer pattern, FIG. 32 for FIG. 14 Schematic diagram after forming the third insulating layer pattern, FIG. 30 for FIG. 31 Schematic diagram after forming the third insulation layer pattern.

[0214] In the example embodiment, as shown in FIG. 1, the plurality of via holes of the third insulating layer at least include: a first via hole V1 to a ninth via hole V9. FIG. 31

[0215] In the example embodiment, the first via hole V1 is configured such that a first electrode of the first transistor (also a first electrode of the second transistor) to be formed later is connected to the first region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor) through the first via hole V1.

[0216] In the example embodiment, the second via hole V2 is configured such that a second electrode of the first transistor to be formed later is connected to the second region of the active pattern of the first transistor through the second via hole V2.

[0217] In the example embodiment, the third via hole V3 is configured such that a second electrode of the second transistor to be formed later is connected to the second region of the active pattern of the second transistor through the third via hole V3.

[0218] In the example embodiment, the fourth via hole V4 is configured such that a first selection signal line to be formed later is connected to the gate electrode of the first transistor through the fourth via hole V4.

[0219] In the example embodiment, the fifth via hole V5 is configured such that a second selection signal line to be formed later is connected to the gate electrode of the second transistor through the fifth via hole V5.

[0220] ​In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first data signal line on the substrate, the sixth via V6 exposes the surface of the first data signal line, and the sixth via V6 is configured to connect the first electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor) to the first data signal line through the via.

[0221] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the data power supply line on the substrate, the seventh via hole V7 exposes the surface of the data power supply line, and the seventh via hole V7 is configured to connect the subsequently formed third connecting electrode or fourth connecting electrode to the data power supply line through the via hole.

[0222] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first connecting electrode on the substrate, the eighth via V8 exposes the surface of the first connecting electrode, and the eighth via V8 is configured to connect the subsequently formed third connecting electrode to the first connecting electrode through the via.

[0223] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second connecting electrode on the substrate, the ninth via hole V9 exposes the surface of the second connecting electrode, and the ninth via hole V9 is configured to connect the subsequently formed fourth connecting electrode to the second connecting electrode through the via hole.

[0224] In an exemplary embodiment, FIG. 30 As shown, the plurality of via holes in the third insulating layer include at least: a first via hole V1 to an eighth via hole V8. FIG. 32 The first through hole V1 to the seventh through hole V7 and FIG. 33 to FIG. 38 The first through holes V1 to the seventh through holes V7 are the same, and the difference lies in the eighth through hole V8.

[0225] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first connecting electrode on the substrate, the eighth via V8 exposes the surface of the first connecting electrode, and the eighth via V8 is configured to connect the subsequently formed second connecting electrode to the first connecting electrode through the via hole.

[0226] In an exemplary embodiment, FIG. 33 As shown, the plurality of via holes in the third insulating layer include at least: a first via hole V1 to an eighth via hole V8.

[0227] In an example embodiment, a first via V1 is located within a range of a normal projection of the first region of the active pattern of the first transistor on the substrate, the first insulating layer and the second insulating layer within the first via V1 are etched away to expose a surface of the first region of the active pattern of the first transistor, and the first via V1 is configured to connect the first electrode of the first transistor formed subsequently therethrough to the first region of the active pattern of the first transistor.

[0228] In an example embodiment, a second via V2 is located within a range of a normal projection of the second region of the active pattern of the first transistor on the substrate, the first insulating layer and the second insulating layer within the second via V2 are etched away to expose a surface of the second region of the active pattern of the first transistor, and the second via V2 is configured to connect the second electrode of the first transistor formed subsequently therethrough to the second region of the active pattern of the first transistor.

[0229] In an example embodiment, a third via V3 is located within a range of a normal projection of the first region of the active pattern of the second transistor on the substrate, the first insulating layer and the second insulating layer within the third via V3 are etched away to expose a surface of the first region of the active pattern of the second transistor, and the third via V3 is configured to connect the first electrode of the second transistor formed subsequently therethrough to the first region of the active pattern of the second transistor.

[0230] In an example embodiment, a fourth via V4 is located within a range of a normal projection of the second region of the active pattern of the second transistor on the substrate, the first insulating layer and the second insulating layer within the fourth via V4 are etched away to expose a surface of the second region of the active pattern of the second transistor, and the fourth via V4 is configured to connect the second electrode of the second transistor formed subsequently therethrough to the first region of the active pattern of the second transistor.

[0231] In an example embodiment, a fifth via V5 is located within a range of a normal projection of the gate electrode of the first transistor on the substrate, the second insulating layer within the fifth via V5 is etched away to expose a surface of the gate electrode of the first transistor, and the fifth via V5 is configured to connect the first selection signal line formed subsequently therethrough to the gate electrode of the first transistor.

[0232] In an example embodiment, a sixth via V6 is located within a range of a normal projection of the gate electrode of the second transistor on the substrate, the second insulating layer within the sixth via V6 is etched away to expose a surface of the gate electrode of the second transistor, and the sixth via V6 is configured to connect the second selection signal line formed subsequently therethrough to the gate electrode of the second transistor.

[0233] In an exemplary embodiment, the seventh via V7 exposes a surface of the first data signal line, and the seventh via V7 is configured to connect the first electrode of the first transistor or the first electrode of the second transistor formed subsequently to the first data signal line through the via.

[0234] In an exemplary embodiment, the eighth via V8 exposes a surface of the data supply line, and the eighth via V8 is configured to connect the second electrode of the first transistor and the second electrode of the second transistor formed subsequently to the data supply line through the via.

[0235] (5) forming a third conductive layer pattern, comprising: depositing a third conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive thin film through a patterning process to form a third conductive layer pattern, as shown in FIG. 12 , FIG. 34 , FIG. 12 is a schematic diagram of the third conductive layer pattern in FIG. 35 , FIG. 13 is a schematic diagram after forming the third conductive layer pattern, FIG. 36 , FIG. 13 is a schematic diagram of the third conductive layer pattern in FIG. 37 , FIG. 14 is a schematic diagram after forming the third conductive layer pattern, FIG. 38 , FIG. 14 is a schematic diagram of the third conductive layer pattern in FIG. 33 to FIG. 38 , FIG. 33 to FIG. 38 is a schematic diagram after forming the third conductive layer pattern. In an exemplary embodiment, the third conductive layer can be referred to as a source-drain metal (SD) layer.

[0236] In an exemplary embodiment, as shown in FIG. 33 to FIG. 36 , the third conductive layer can at least include: a first selection signal line SW1, a second selection signal line SW2, a first electrode T13 and a second electrode T14 of the first transistor, and a first electrode T23 and a second electrode T24 of the second transistor.

[0237] In an exemplary embodiment, as shown in FIG. 37 , the first selection signal line SW1 and the second selection signal line SW2 extend along the first direction D1, and the second selection signal line SW2 is located on the side of the first selection signal line SW1 close to the data signal line.

[0238] In an exemplary embodiment, as shown in FIG. 38As shown, the first selection signal line SW1 is electrically connected with the gate electrode of the first transistor through the fourth via, and the second selection signal line SW2 is electrically connected with the gate electrode of the second transistor through the fifth via.

[0239] In an exemplary embodiment, as shown in FIG. 33 to FIG. 36 and FIG. 33 to FIG. 36 the first selection signal line SW1 is electrically connected with the gate electrode of the first transistor through the fifth via, and the second selection signal line SW2 is electrically connected with the gate electrode of the second transistor through the sixth via.

[0240] In an exemplary embodiment, as shown in FIG. 33 to FIG. 36 the first pole T13 of the kth first transistor and the first pole T23 of the kth second transistor are in an integrated structure, and the second pole T14 of the first transistor and the second pole T24 of the second transistor are separately arranged.

[0241] In an exemplary embodiment, as shown in FIG. 33 the first pole T13 of the first transistor (also the first pole T23 of the second transistor), the second pole T14 of the first transistor, and the second pole T24 of the second transistor are all in the shape of a strip extending along the second direction D2.

[0242] In an exemplary embodiment, as shown in FIG. 34 the first pole T13 of the first transistor (also the first pole T23 of the second transistor) is connected with the first area of the active pattern of the first transistor (also the first area of the active pattern of the second transistor) through the first via, the second pole T14 of the first transistor is connected with the second area of the active pattern of the first transistor through the second via, and the second pole T24 of the second transistor is connected with the second area of the active pattern of the second transistor through the third via.

[0243] In an exemplary embodiment, as shown in FIG. 35 and FIG. 36 the second pole T24 of the odd-numbered second transistor is electrically connected with the first connection electrode through the eighth via, the second pole of the even-numbered second transistor is electrically connected with the second connection electrode through the ninth via, and the second pole T14 of the first transistor is electrically connected with the data power supply line through the seventh via.

[0244] In an exemplary embodiment, as shown in FIG. 37 and FIG. 38 the second pole T14 of the first transistor and the second pole T24 of the second transistor are connected with the first connection electrode through the eighth via.

[0245] In an exemplary embodiment, as shown in FIG. 37 and FIG. 38As shown in FIG. 1, the first electrode T13 of the first transistor and the first electrode T23 of the second transistor can be separately arranged, the second electrode T14 of the dth first transistor and the second electrode T24 of the (d+1)th second transistor can be in an integrated structure, the second electrode T24 of the dth second transistor and the second electrode T14 of the (d+1)th first transistor can be in an integrated structure, and so on.

[0246] In an exemplary embodiment, as shown in FIG. 1, the first electrode T13 of the first transistor and the first electrode T23 of the second transistor can be separately arranged, the second electrode T14 of the dth first transistor and the second electrode T24 of the (d+1)th second transistor can be in an integrated structure, the second electrode T24 of the dth second transistor and the second electrode T14 of the (d+1)th first transistor can be in an integrated structure, and so on. FIG. 37 FIG. 38 As shown in FIG. 1, the shape of the first electrode T13 of the first transistor and the first electrode T23 of the second transistor can be a strip extending along the second direction D2. The integrated structure of the second electrode T14 of the dth first transistor and the second electrode T24 of the (d+1)th second transistor can be in a groove shape.

[0247] In an exemplary embodiment, as shown in FIG. 1, the first electrode T13 of the first transistor and the first electrode T23 of the second transistor can be separately arranged, the second electrode T14 of the dth first transistor and the second electrode T24 of the (d+1)th second transistor can be in an integrated structure, the second electrode T24 of the dth second transistor and the second electrode T14 of the (d+1)th first transistor can be in an integrated structure, and so on. FIG. 37 FIG. 38 As shown in FIG. 1, the first electrode T13 of the first transistor and the first electrode T23 of the second transistor can be separately arranged, the second electrode T14 of the dth first transistor and the second electrode T24 of the (d+1)th second transistor can be in an integrated structure, the second electrode T24 of the dth second transistor and the second electrode T14 of the (d+1)th first transistor can be in an integrated structure, and so on.

[0248] In an exemplary embodiment, as shown in FIG. 1, the first electrode T13 of the first transistor and the first electrode T23 of the second transistor can be separately arranged, the second electrode T14 of the dth first transistor and the second electrode T24 of the (d+1)th second transistor can be in an integrated structure, the second electrode T24 of the dth second transistor and the second electrode T14 of the (d+1)th first transistor can be in an integrated structure, and so on. FIG. 33 FIG. 34 As shown in FIG. 1, the first electrode T13 of the first transistor and the first electrode T23 of the second transistor can be separately arranged, the second electrode T14 of the dth first transistor and the second electrode T24 of the (d+1)th second transistor can be in an integrated structure, the second electrode T24 of the dth second transistor and the second electrode T14 of the (d+1)th first transistor can be in an integrated structure, and so on.

[0249] In an exemplary embodiment, as shown in FIG. 1, the first electrode T13 of the first transistor and the first electrode T23 of the second transistor can be separately arranged, the second electrode T14 of the dth first transistor and the second electrode T24 of the (d+1)th second transistor can be in an integrated structure, the second electrode T24 of the dth second transistor and the second electrode T14 of the (d+1)th first transistor can be in an integrated structure, and so on. FIG. 35 FIG. 36 ​​​​As shown, the third conductive layer at least further includes a third connection electrode CL3 and a fourth connection electrode CL4. The third connection electrode CL3 and the fourth connection electrode CL4 are in the shape of a strip extending along the first direction D1. The third connection electrode CL3 is connected to the data supply line through the seventh via, and is connected to the first connection electrode through the eighth via. The fourth connection electrode CL4 is connected to the data supply line through the seventh via, and is connected to the second connection electrode through the ninth via.

[0250] As shown in the example embodiment, the third conductive layer at least further includes a second connection electrode VL2. The second connection electrode VL2 is in the shape of a strip extending along the first direction D1. The second connection electrode VL2 is connected to the data supply line through the seventh via, and is connected to the first connection electrode through the eighth via. ​ ​ As shown, the third conductive layer at least further includes a second connection electrode VL2. The second connection electrode VL2 is in the shape of a strip extending along the first direction D1. The second connection electrode VL2 is connected to the data supply line through the seventh via, and is connected to the first connection electrode through the eighth via.

[0251] (6) Forming a planar layer pattern, including: depositing a sixth insulating thin film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating thin film through a patterning process to form a fourth insulating layer, coating a planar thin film on the sixth insulating layer, and patterning the planar thin film through a patterning process to form a planar layer pattern covering the aforementioned pattern.

[0252] So far, the driving structure layer is prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer can include a data conversion circuit. The driving structure layer can be disposed on the substrate. The driving structure layer can include, in sequence, a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planar layer on the substrate.

[0253] In the example embodiment, the semiconductor layer pattern can be an amorphous silicon layer or a polycrystalline silicon layer, or can be a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0254] In the example embodiment, the first conductive layer, the second conductive layer and the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0255] ​In the exemplary embodiments, the first, second, third and fourth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multiple layers or a composite layer.

[0256] In the exemplary embodiments, the planar layer can be made of an organic material, such as resin or the like.

[0257] In the exemplary embodiments, after the driving structure layer is prepared, the light-emitting structure layer is prepared on the driving structure layer, and the preparation process of the light-emitting structure layer can include the following operations.

[0258] (7) Forming the anode conductive layer pattern. In the exemplary embodiments, forming the anode conductive layer pattern can include: depositing an anode conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive thin film by a patterning process to form the anode conductive layer pattern disposed on the planar layer.

[0259] In the exemplary embodiments, the anode conductive layer pattern includes at least a plurality of first electrode patterns.

[0260] In the exemplary embodiments, the anode conductive layer can be made of a single layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or can be made of a multi-layer composite structure, such as ITO / Ag / ITO or the like.

[0261] (8) Forming the cathode conductive layer pattern. In the exemplary embodiments, forming the cathode conductive layer can include: coating a pixel definition thin film on the substrate on which the aforementioned pattern is formed, depositing the pixel definition thin film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition thin film by a patterning process to form a pixel definition layer pattern exposing the sixth conductive layer pattern, coating an organic light-emitting material on the substrate on which the pixel definition layer pattern is formed, patterning the organic light-emitting material by a patterning process to form an organic structure layer pattern, depositing a cathode conductive thin film on the substrate on which the organic material layer pattern is formed, and patterning the cathode conductive thin film by a patterning process to form the cathode conductive layer.

[0262] In the exemplary embodiments, the subsequent preparation process can include: forming an encapsulation structure layer on the cathode conductive layer, the encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer can be made of an inorganic material, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to prevent external water vapor from entering the light-emitting structure layer.

[0263] In the exemplary embodiments, the organic structure layer can include at least an organic light-emitting layer of the light-emitting device.

[0264] In an exemplary embodiment, the cathode conductive layer can at least include a cathode of a plurality of light emitting devices.

[0265] In an exemplary embodiment, the cathode layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an electrically conductive alloy material, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer can be a three-layer stacked structure of titanium, aluminum, and titanium.

[0266] The display substrate provided by the embodiments of the present disclosure can be applied to any resolution display product.

[0267] The embodiments of the present disclosure also provide a display device, which includes a display substrate and a photosensitive sensor.

[0268] In an exemplary embodiment, the photosensitive sensor can be located in a light-transmissive region of the display substrate.

[0269] The display substrate provided by any one of the above embodiments has similar principles and effects, and thus will not be described here again.

[0270] In an exemplary embodiment, the display substrate can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be an OLED display, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function, and the embodiments of the present disclosure are not limited thereto.

[0271] In an exemplary embodiment, the light-transmissive region includes a via region, a packaging region, and a wiring region, and the photosensitive sensor is located in the via region.

[0272] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0273] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of a layer or microstructure are exaggerated. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly” on or under the other element, or there can be an intermediate element.

[0274] Although the disclosed embodiments have been fully described above with reference to the attachments, figures, and the accompanying drawings, other embodiments can be utilized and changes can be made without departing from the scope of the disclosure, which is not to be limited by the above-described embodiments. Accordingly, various modifications and changes can be made to the embodiments without departing from the scope of the disclosure as set forth in the claims below. The disclosure is not to be limited to the embodiments set forth herein for the purpose of the practice of the present disclosure.

Claims

1. A display substrate, characterized by, The display substrate comprises: a plurality of sub-pixels and a plurality of data signal lines, the sub-pixels comprising: a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; the data signal lines comprising: a first data signal line and a second data signal line, the first data signal line being electrically connected with the first color sub-pixel and the second color sub-pixel respectively, the second data signal line being electrically connected with the third color sub-pixel, the first data signal line and the second data signal line being arranged alternately along a first direction, the data signal lines extending along a second direction, the first direction intersecting the second direction; the display substrate further comprises: a first selection signal line, a second selection signal line, a plurality of data power supply lines, and a data selection circuit; the data selection circuit is electrically connected with the first selection signal line, the second selection signal line, the plurality of first data signal lines, and the plurality of data power supply lines respectively, and is configured to provide the first data signal line with a signal of the data power supply line under control of a signal of the first selection signal line or the second selection signal line; the data power supply lines comprise: a first data power supply line and a second data power supply line, the first data power supply line being configured to provide a first color data signal, the first color data signal being a data signal provided to the first color sub-pixel, the second data power supply line being configured to provide a second color data signal, the second color data signal being a data signal provided to the second color sub-pixel, the data power supply lines extending along the second direction, the first data power supply line and the second data power supply line being arranged alternately along the first direction.

2. The display substrate of claim 1, wherein, The display substrate further comprises N scanning signal lines, an nth scanning signal line is electrically connected with the nth row of sub-pixels and extends along the first direction, 1 n N; the signals of the first selection signal line and the second selection signal line are not simultaneously valid level signals; when the signals of the odd-numbered scanning signal lines are valid level signals, the signal of the first selection signal line is a valid level signal, and when the signals of the even-numbered scanning signal lines are valid level signals, the signal of the second selection signal line is a valid level signal. 3.The display substrate of claim 2, wherein, The sub-pixel in the 4th column of the odd-numbered row is a first color sub-pixel, the sub-pixel in the 4th column of the even-numbered row is a second color sub-pixel, the sub-pixel in the 4th column of the odd-numbered row is a second color sub-pixel, the sub-pixel in the 4th column of the even-numbered row is a first color sub-pixel, 1 a M / 4, M is the total number of columns of sub-pixels, and is even. the first color is one of red and blue, the second color is the other of red and blue, and the third color is green.

4. The display substrate of claim 3, wherein, the number of data signal lines in the display substrate is equal to M or 3M / 2; When the number of data signal lines is equal to M, the mth column of sub-pixels is electrically connected with the mth data signal line, wherein the odd-numbered data signal lines are first data signal lines, the even-numbered data signal lines are second data signal lines, the number of data supply lines is equal to K or K+1, K=M / 2, 1 m M; When the number of data signal lines is equal to 3M / 2, the xth column of sub-pixels is electrically connected to the 3x / 2th data signal line, the yth column of sub-pixels in odd rows is electrically connected to the (3y-1) / 2th data signal line, the yth column of sub-pixels in even rows is electrically connected to the (3y+1) / 2th data signal line, the 3z-1th data signal line and the 3z-2th data signal line are first data signal lines, the 3zth data signal line is a second data signal line, the number of data supply lines is equal to K, 1 x M, and is even, 1 y M, and is odd, 1 z K.

5. The display substrate of claim 4, wherein, when the number of data power supply lines is equal to K, the odd-numbered data power supply lines are the first data power supply lines, and the even-numbered data power supply lines are the second data power supply lines. 6.The display substrate of claim 5, wherein, the data selection circuit comprises: a first data selection circuit and a second data selection circuit; the first data selection circuit is electrically connected with the first selection signal line, the plurality of first data signal lines, and the first data power supply line to the Kth data power supply line respectively, and is configured to provide the first data signal line with a signal of the data power supply line under control of a signal of the first selection signal line when the odd-numbered rows of sub-pixels are displayed; the second data selection circuit is electrically connected with the second selection signal line, the plurality of first data signal lines, and the first data power supply line to the Kth data power supply line respectively, and is configured to provide the first data signal line with a signal of the data power supply line under control of a signal of the second selection signal line when the even-numbered rows of sub-pixels are displayed. 7.The display substrate of claim 6, wherein, When the number of data signal lines is equal to M, the first data selection circuit comprises K first transistors, and the second data selection circuit comprises K second transistors. The control electrode of the bth first transistor is electrically connected with a first selection signal line, the first electrode of the bth first transistor is electrically connected with the 2b-1th data signal line, the second electrode of the bth first transistor is electrically connected with the bth data power supply line, 1 b K; The control electrode of the bth second transistor is electrically connected with the second selection signal line, the first electrode of the bth second transistor is electrically connected with the 2b-1th data signal line, and the second electrode of the bth second transistor is electrically connected with the cth data power supply line, wherein c = b+1 when b is odd, and c = b-1 when b is even. 8.The display substrate of claim 6, wherein, When the number of data signal lines is equal to 3M / 2, the first data selection circuit comprises K first transistors, and the second data selection circuit comprises K second transistors. The control electrode of the bth first transistor is electrically connected with a first selection signal line, the first electrode of the bth first transistor is electrically connected with the 3b-2th data signal line, the second electrode of the bth first transistor is electrically connected with the bth data power supply line, 1 b K; The control electrode of the bth second transistor is electrically connected with the second selection signal line, the first electrode of the bth second transistor is electrically connected with the 3b-1th data signal line, and the second electrode of the bth second transistor is electrically connected with the wth data power supply line, wherein c = b+1 when b is odd, and c = b-1 when b is even. 9.The display substrate of claim 4, wherein, When the number of data power supply lines is equal to K+1, the odd data power supply lines are second data power supply lines, and the even data power supply lines are first data power supply lines. 10.The display substrate of claim 9, wherein, The data selection circuit comprises a first data selection circuit and a second data selection circuit. The first data selection circuit is electrically connected with a first selection signal line, a plurality of first data signal lines and the second data power supply line to the K+1th data power supply line, respectively, and is configured to provide the first data signal line with a signal of the data power supply line under the control of a signal of the first selection signal line when the odd row of sub-pixels is displayed. The second data selection circuit is electrically connected with a second selection signal line, a plurality of first data signal lines and the first data power supply line to the Kth data power supply line, respectively, and is configured to provide the first data signal line with a signal of the data power supply line under the control of a signal of the second selection signal line when the even row of sub-pixels is displayed. 11.The display substrate of claim 10, wherein, The first data selection circuit comprises K first transistors, and the second data selection circuit comprises K second transistors. The control electrode of the bth first transistor is electrically connected to the first selection signal line, the first electrode of the bth first transistor is electrically connected to the 2b-1th data signal line, the second electrode of the bth first transistor is electrically connected to the b+1th data power supply line, and the 1st first transistor is electrically connected to the 2b-1th data signal line. b K; The control electrode of the bth second transistor is electrically connected with the second selection signal line, the first electrode of the bth second transistor is electrically connected with the 2b-1th data signal line, and the second electrode of the bth second transistor is electrically connected with the bth data power supply line. 12.The display substrate of claim 11, wherein, The display substrate comprises a substrate and a driving structure layer arranged on the substrate, wherein the driving structure layer comprises a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer which are sequentially stacked on the substrate, and a transistor comprises an active pattern. The semiconductor layer comprises at least an active pattern of a first transistor and an active pattern of a second transistor. The first conductive layer comprises at least a gate electrode of the first transistor, a gate electrode of the second transistor and a second data signal line. The second conductive layer comprises at least a first data signal line and a data power supply line. The third conductive layer comprises at least a first selection signal line, a second selection signal line, a first electrode and a second electrode of the first transistor and a first electrode and a second electrode of the second transistor. 13.The display substrate of claim 12, wherein, The first selection signal line and the second selection signal line extend along a first direction and are arranged along a second direction. A normal projection of the second data signal line on the substrate partially overlaps with a normal projection of the first selection signal line and the second selection signal line on the substrate; A normal projection of one of the first selection signal line and the second selection signal line close to the sub-pixel on the substrate partially overlaps with a normal projection of the first data signal line on the substrate. 14.The display substrate of claim 13, wherein, When the number of data signal lines is equal to M, and the number of data power supply lines is equal to K, the display substrate further comprises: R first connection electrodes, R second connection electrodes, R third connection electrodes and R fourth connection electrodes, the first connection electrodes and the second connection electrodes extend along the second direction and are located in the second conductive layer, the third connection electrodes and the fourth connection electrodes extend along the first direction and are located in the third conductive layer, and R=K / 2; A normal projection of any one of the first connection electrodes and the second connection electrodes on the substrate partially overlaps with a normal projection of the first selection signal line on the substrate; The rth first connection electrode is connected to the second electrode of the 2r-1th second transistor and the rth third connection electrode, and the rth second connection electrode is connected to the second electrode of the 2rth second transistor and the rth fourth connection electrode. The rth third connection electrode is electrically connected to the 2rth data supply line, and the rth fourth connection electrode is electrically connected to the 2r-1th data supply line. r R. 15.The display substrate of claim 13, wherein, When the number of data signal lines is M, and the number of data power supply lines is equal to K+1, the display substrate further comprises: K+1 first connection electrodes and K+1 second connection electrodes, the first connection electrodes extend along the second direction and are located in the second conductive layer, and the second connection electrodes extend along the first direction and are located in the third conductive layer; The first first connection electrode is electrically connected to the second electrode of the first second transistor and the first second connection electrode respectively, the sth first connection electrode is electrically connected to the second electrode of the s-1th first transistor and the sth second connection electrode respectively, the i-th second connection electrode is electrically connected to the i-th data power supply line, 2 s K+1. 16.The display substrate of claim 13, wherein, When the number of data signal lines is equal to M, the active pattern of the kth first transistor and the active pattern of the kth second transistor are an integral structure; When the number of data signal lines is equal to 3M / 2, the active pattern of the kth first transistor and the active pattern of the kth second transistor are arranged at intervals.

17. A display device, characterized in that: Comprise: The display substrate according to any one of claims 1 to 16.

18. The display device of claim 17, wherein, Further comprise: A driver; The driver is electrically connected with the plurality of second data signal lines and the plurality of data power supply lines respectively.

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