Field effect transistor on-resistance characterization device and method with multi-stress regulation

Abstract

The present invention relates to the field of electronic circuit technology, and provides a field effect transistor on-resistance characterization device and method with multi-stress regulation, wherein the device comprises: a multi-stress dynamic characteristic characterization circuit module and an on-resistance characterization module; the multi-stress dynamic characteristic characterization circuit module is connected to the on-resistance characterization module; the multi-stress dynamic characteristic characterization circuit module comprises a drive signal control circuit, a multi-stress regulation circuit and a clamp measurement circuit; the drive signal control circuit is connected to the multi-stress regulation circuit, and the multi-stress regulation circuit is connected to the clamp measurement circuit. The present invention applies a variety of single electrical stresses or mixed electrical stresses to the field effect transistor to be tested by configuring the multi-stress dynamic characteristic characterization circuit module and the on-resistance characterization module, and observes the recovery process of its dynamic on-resistance, which is helpful to deeply study the physical mechanism affecting the dynamic on-resistance, and makes the characterization and research of the dynamic on-resistance of the power semiconductor field effect transistor more accurate and comprehensive.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a device and method for characterizing on-resistance of a field effect transistor with multi-stress regulation. Background Art

[0002] At present, field effect transistor devices are mainly Si-based high-frequency field effect transistor devices, but Si-based high-frequency field effect transistors can no longer meet the needs of increased operating frequency, increased power density, and improved power conversion efficiency. Compared with Si-based high-frequency field effect transistor devices, third-generation wide bandgap semiconductor power devices (GaN devices and SiC devices) with high withstand voltage, low on-resistance, and high switching speed can meet the above needs and are widely used in high-voltage, medium-to-high-power, and high-switching-frequency applications. However, due to the limitations of the third-generation wide bandgap semiconductor power device preparation process technology, the dynamic characteristics stability and reliability of GaN and SiC field effect transistors are currently poor. Specifically, after the GaN field effect transistor is subjected to electrical stress for a period of time, the on-resistance and threshold voltage of the device will change. This dynamic characteristic change of the device will affect the stability and safety of the circuit system operation, reduce the power efficiency, and in severe cases, make the circuit system unable to work normally. In order to ensure the qualification and reliability of the power field effect transistor, it is necessary to conduct a multi-dimensional and comprehensive test characterization of the dynamic on-resistance of the power field effect transistor.

[0003] However, in the existing testing devices and methods, it is impossible to strictly control the electrical stress of the device under test, and different types of electrical stress are not separated and studied separately. Mixed electrical stress will produce different action mechanisms on the device under test, and it is impossible to study a single physical mechanism, making it impossible to conduct in-depth research on the physical mechanism of the dynamic on-resistance change of the device under test. For example, hard switching stress is a mixed type of electrical stress, which is a combination of off-state drain voltage stress and semi-on-state stress. The physical mechanisms of off-state drain voltage stress and semi-on-state stress on the change of dynamic on-resistance of the device under test are different. Therefore, in order to deeply study the physical mechanism of a specific dynamic on-resistance change, it is necessary to split the mixed type of electrical stress into independent electrical stresses, and then study a single physical mechanism, and study the influence of a single electrical stress on the dynamic on-resistance of power semiconductor field effect transistors. It can also achieve real-time observation of the entire process from one hundred nanoseconds after the electrical stress is removed to the recovery of on-resistance, and then deeply study a single physical mechanism of dynamic on-resistance, so that the characterization and research of the dynamic on-resistance of power semiconductor field effect transistors is more accurate and comprehensive, which is helpful for in-depth research on the physical mechanism affecting the dynamic on-resistance.

[0004] Therefore, it is necessary to provide a field effect transistor on-resistance characterization device and method with multi-stress regulation. Summary of the invention

[0005] The present invention provides a field effect transistor on-resistance characterization device with multi-stress regulation. By configuring a multi-stress dynamic characteristic characterization circuit module and an on-resistance characterization module, electrical stress is applied to the field effect transistor to be measured, and the recovery process of its dynamic on-resistance is observed, which provides more stress type observation windows for the research and analysis of the dynamic characteristic mechanism of the field effect transistor, helps to conduct in-depth research on the physical mechanism that affects the dynamic on-resistance, and makes the characterization and research of the dynamic on-resistance of the power semiconductor field effect transistor more accurate and comprehensive.

[0006] The present invention provides a field effect transistor on-resistance characterization device with multi-stress regulation, comprising:

[0007] A multi-stress dynamic characteristic characterization circuit module and an on-resistance characterization module; the multi-stress dynamic characteristic characterization circuit module is connected to the on-resistance characterization module;

[0008] The multi-stress dynamic characteristic characterization circuit module includes a drive signal control circuit, a multi-stress regulation circuit and a clamp measurement circuit; the drive signal control circuit is connected to the multi-stress regulation circuit, and the multi-stress regulation circuit is connected to the clamp measurement circuit; the drive signal control circuit is used to generate a drive signal to control the multi-stress regulation circuit; the multi-stress regulation circuit is used to apply multiple electrical stresses to the field effect transistor to be tested according to the drive signal; the clamp measurement circuit is used to measure the conduction voltage drop between the source and the drain of the field effect transistor to be tested;

[0009] The on-resistance characterization module is used to sample and obtain the detection current flowing between the source and drain of the field effect transistor to be tested, and calculate the on-resistance based on the on-voltage drop and the detection current and perform characterization.

[0010] Furthermore, the driving signal control circuit is a field programmable gate array chip; the driving control circuit includes an output terminal A1, an output terminal A2 and an output terminal A3.

[0011] Furthermore, the multi-stress control circuit includes a high-voltage power supply Vin, an input capacitor Cin, a load resistor RL, a current detection resistor Rs, a current limiting protection resistor R1, a load inductor L, a freewheeling diode D1, a switching transistor S1, a switching transistor S2 and a field effect transistor to be tested DUT; the positive electrode of the input capacitor Cin is connected to the positive electrode of the high-voltage power supply Vin, and the negative electrode of the input capacitor Cin is connected to the negative electrode of the high-voltage power supply Vin; one end of the load resistor RL is connected to the positive electrode of the high-voltage power supply Vin, and the other end of the load resistor RL is connected to one end of the load inductor L; the freewheeling diode D1 The cathode is connected to the positive electrode of the high-voltage power supply Vin, and the anode of the freewheeling diode D1 is connected to the other end of the load inductor L; the drain of the switching transistor S1 is connected to the other end of the load inductor L, and the source of the switching transistor S1 is connected to the drain of the field effect transistor DUT to be tested; the source of the field effect transistor DUT to be tested is connected to one end of the current detection resistor Rs; the other end of the current detection resistor Rs is grounded; one end of the current limiting protection resistor R1 is connected to the source of the switching transistor S1, and the other end of the current limiting protection resistor R1 is connected to the drain of the switching transistor S2, and the source of the switching transistor S2 is grounded.

[0012] Furthermore, the output terminal A1 is connected to the gate of the switching transistor S1 to control the on and off of the switching transistor S1; the output terminal A2 is connected to the gate of the field effect transistor DUT to be tested to control the on and off of the field effect transistor DUT to be tested; the output terminal A3 is connected to the gate of the switching transistor S2 to control the on and off of the switching transistor S2.

[0013] Furthermore, one end of the clamp measurement circuit is connected to the drain of the field effect transistor DUT to be tested, and the other end of the clamp measurement circuit is connected to the other end of the current detection resistor Rs; when the power field effect transistor DUT to be tested is in the on state, the clamp measurement circuit samples and obtains the on-state voltage drop between the source and drain of the power field effect transistor DUT to be tested.

[0014] Furthermore, the on-resistance characterization module includes an oscilloscope, a probe and a processing and display component; the probe is used to measure the detection current flowing through the current detection resistor Rs, and to sample and obtain the on-voltage drop; the oscilloscope is used to display the detection current and the on-voltage drop; the processing and display component is used to calculate the on-resistance of the detection current and the on-voltage drop, and display the on-resistance.

[0015] The on-resistance characterization method of a field effect transistor with multi-stress regulation is implemented according to an on-resistance characterization device of a field effect transistor with multi-stress regulation, and the on-resistance of a power field effect transistor DUT to be tested is obtained and characterized by the following steps:

[0016] The driving signal control circuit generates a driving signal, and sends the driving signal to the multi-stress regulating circuit through output terminal A1, output terminal A2, and output terminal A3;

[0017] The multi-stress control circuit applies electrical stress to the field effect transistor DUT under test according to the received driving signal;

[0018] After the electrical stress is applied, the multi-stress control circuit controls the field effect transistor DUT to be free from the influence of the electrical stress according to the received driving signal, so that it is in the dynamic characteristic recovery stage;

[0019] The probe is used to measure the detection current flowing through the current detection resistor Rs, and the on-state voltage drop between the source and drain of the field effect transistor DUT to be tested is collected. The on-state resistance is calculated based on the detection current and the on-state voltage drop using the processing and display component, and the on-state resistance is displayed.

[0020] Furthermore, the multi-stress control circuit applies electrical stress to the field effect transistor DUT under test according to the received driving signal, including:

[0021] By controlling the on and off of the switch transistor S1 and the switch transistor S2, the electrical stress of the power field effect transistor DUT to be tested is regulated, so that the field effect transistor DUT to be tested is subjected to a variety of different electrical stresses or is not subjected to electrical stress; the electrical stress includes hard switching stress, off-state drain voltage stress and half-on-state stress; specifically, it includes:

[0022] Apply hard switching stress to the field effect transistor DUT to be tested, specifically: first keep the switch transistor S1 off, then turn on the field effect transistor DUT to be tested, and then turn on the switch transistor S1 to make the field effect transistor DUT to be tested soft-on; keep the switch transistor S1 on, then turn off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is hard-off; reasonably control the time interval, turn on the field effect transistor DUT to be tested, under the freewheeling action of the load inductor L, the current flowing through the field effect transistor DUT to be tested in the turn-on state is not zero, so that the field effect transistor DUT to be tested is hard-on;

[0023] Applying off-state drain voltage stress to the field effect transistor DUT to be tested, specifically: first keep the switch transistor S1 off, then turn on the field effect transistor DUT to be tested, then turn on the switch transistor S1, so that the field effect transistor DUT to be tested is soft-turned on; then turn off the switch transistor S1 first, then turn off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is soft-turned off, then turn on the switch transistor S1 to increase the drain voltage of the field effect transistor DUT to be tested, and at this time, applying off-state drain voltage stress to the field effect transistor DUT to be tested; when the field effect transistor DUT to be tested needs to be turned on again, first turn off the switch transistor S1, turn on the switch transistor S2, so that the drain voltage of the field effect transistor DUT to be tested drops to zero, then turn on the field effect transistor DUT to be tested, turn off the switch transistor S2, and then turn on the switch transistor S1, so that the field effect transistor DUT to be tested is soft-turned on;

[0024] A semi-open stress is applied to the field effect transistor DUT to be tested, specifically: first keep the switch transistor S1 off, then turn on the field effect transistor DUT to be tested, and then turn on the switch transistor S1, so that the field effect transistor DUT to be tested is soft-opened and the current rises; then turn off the field effect transistor DUT to be tested, at this time the drain voltage of the field effect transistor DUT to be tested rises, the current drops, and the time interval is reasonably controlled. When the drain voltage of the field effect transistor DUT to be tested rises to a high voltage, turn on the field effect transistor DUT to be tested again, the drain voltage drops, and under the freewheeling action of the load inductor L, the current rises rapidly, so that the field effect transistor DUT to be tested is subjected to the semi-open stress; when it is necessary to turn off the field effect transistor DUT to be tested, turn off the field effect transistor DUT to be tested first, at this time the drain voltage rises, the current drops, and the time interval is reasonably controlled. When the drain voltage of the field effect transistor DUT to be tested rises to a high voltage, turn off the switch transistor S1, turn on the switch transistor S2, so that the drain voltage of the field effect transistor DUT to be tested drops and is kept in a low voltage state.

[0025] Furthermore, after the electrical stress is applied, the multi-stress control circuit controls the field effect transistor DUT to be not affected by the electrical stress according to the received driving signal, so that the DUT is in a dynamic characteristic recovery stage, including:

[0026] Keep the switch transistor S1 off, keep the drain voltage of the field effect transistor DUT to be tested zero, first turn on the field effect transistor DUT to be tested, and then turn on the switch transistor S1 to make the field effect transistor DUT to be tested soft-turn on; then turn off the switch transistor S1 first to make the current drop to zero, and then turn off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is soft-turned off, and the switch transistor S1 is subjected to the high voltage.

[0027] Furthermore, it also includes monitoring and controlling the process of applying electrical stress to the field effect transistor DUT by using a set monitoring control circuit, specifically including:

[0028] Build a monitoring and control circuit module connected to the multi-stress dynamic characteristic characterization circuit module; the monitoring and control circuit module includes a monitoring component and a control component; the monitoring component is connected to the control component; the control component is connected to the drive signal control circuit;

[0029] Using the monitoring component, the process of applying electrical stress to the field effect transistor DUT to be tested is monitored to obtain monitoring result data;

[0030] Compare the monitoring result data with the set standard monitoring data. If there is an abnormality in the monitoring result data, generate a monitoring signal and send it to the control component;

[0031] The control component generates a control command according to the received monitoring signal;

[0032] According to the control command, the driving signal control circuit is controlled to adjust the type of the output driving signal; wherein the type of the output driving signal is obtained by integrating the driving signal generated by the driving signal control circuit based on the set integral parameter.

[0033] Compared with the prior art, the present invention has the following advantages and beneficial effects: by configuring a multi-stress dynamic characteristic characterization circuit module and an on-resistance characterization module, electrical stress is applied to the field effect transistor to be tested, and the recovery process of its dynamic on-resistance is observed, which provides more stress type observation windows for the research and analysis of the dynamic characteristic mechanism of the field effect transistor, helps to conduct in-depth research on the physical mechanism that affects the dynamic on-resistance, and makes the characterization and research of the dynamic on-resistance of the power semiconductor field effect transistor more accurate and comprehensive.

[0034] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0035] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0037] Figure 1 A schematic diagram of the structure of a field effect transistor on-resistance characterization device with multi-stress regulation;

[0038] Figure 2 It is a schematic diagram of the device structure connection of the multi-stress dynamic characteristics characterization circuit module;

[0039] Figure 3 A schematic diagram of a method and steps for characterizing the on-resistance of a field effect transistor with multi-stress regulation;

[0040] Figure 4 Schematic diagrams of three electrical stress waveforms;

[0041] Figure 5 A schematic diagram of a control waveform for applying hard switching stress to a field effect transistor DUT;

[0042] Figure 6 A schematic diagram of a control waveform for applying off-state drain voltage stress to a field effect transistor DUT under test;

[0043] Figure 7 It is a schematic diagram of a control waveform for applying a half-on stress to a field effect transistor DUT under test;

[0044] Figure 8 This is a schematic diagram of the on-resistance measurement control waveform for the field effect transistor DUT under test without applying electrical stress. DETAILED DESCRIPTION

[0045] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0046] The present invention provides a field effect transistor on-resistance characterization device with multi-stress regulation, such as Figure 1 As shown, including:

[0047] A multi-stress dynamic characteristic characterization circuit module and an on-resistance characterization module; the multi-stress dynamic characteristic characterization circuit module is connected to the on-resistance characterization module;

[0048] The multi-stress dynamic characteristic characterization circuit module includes a drive signal control circuit, a multi-stress regulation circuit and a clamp measurement circuit; the drive signal control circuit is connected to the multi-stress regulation circuit, and the multi-stress regulation circuit is connected to the clamp measurement circuit; the drive signal control circuit is used to generate a drive signal to control the multi-stress regulation circuit; the multi-stress regulation circuit is used to apply multiple electrical stresses to the field effect transistor to be tested according to the drive signal; the clamp measurement circuit is used to measure the conduction voltage drop between the source and the drain of the field effect transistor to be tested;

[0049] The on-resistance characterization module is used to sample and obtain the detection current flowing between the source and drain of the field effect transistor to be tested, and calculate the on-resistance based on the on-voltage drop and the detection current and perform characterization.

[0050] The working principle of the above technical solution is: in order to realize a field effect transistor on-resistance characterization device with multi-stress regulation, the present invention is configured with a multi-stress dynamic characteristic characterization circuit module and an on-resistance characterization module; the multi-stress dynamic characteristic characterization circuit module is connected to the on-resistance characterization module; wherein the multi-stress dynamic characteristic characterization circuit module includes a drive signal control circuit, a multi-stress regulation circuit and a clamp measurement circuit; the drive signal control circuit is connected to the multi-stress regulation circuit, and the multi-stress regulation circuit is connected to the clamp measurement circuit; the drive signal control circuit is used to generate a drive signal to control the multi-stress regulation circuit; the multi-stress regulation circuit is used to apply multiple electrical stresses to the field effect transistor to be measured according to the drive signal; the clamp measurement circuit is used to measure the on-voltage drop between the source and the drain of the field effect transistor to be measured; the on-resistance characterization module is used to sample and obtain the detection current flowing between the source and the drain of the field effect transistor to be measured, and calculate the on-resistance according to the on-voltage drop and the detection current and characterize it; the calculation of the dynamic on-resistance is the ratio of the on-voltage drop to the detection current.

[0051] The beneficial effects of the above technical solution are: by adopting the solution provided in this embodiment, electrical stress is applied to the field effect transistor to be tested through the configured multi-stress dynamic characteristic characterization circuit module and on-resistance characterization module, and the recovery process of its dynamic on-resistance is observed, which provides more stress type observation windows for the research and analysis of the dynamic characteristic mechanism of the field effect transistor, helps to conduct in-depth research on the physical mechanism that affects the dynamic on-resistance, and makes the characterization and research of the dynamic on-resistance of the power semiconductor field effect transistor more accurate and comprehensive.

[0052] In one embodiment, the driving signal control circuit is a field programmable gate array chip; the driving control circuit includes an output terminal A1, an output terminal A2 and an output terminal A3.

[0053] The working principle of the above technical solution is: the present invention uses a field programmable gate array chip as a drive control circuit; the drive control circuit includes an output terminal A1, an output terminal A2 and an output terminal A3.

[0054] The beneficial effect of the above technical solution is: by adopting the solution provided by this embodiment, a driving signal can be provided through a field programmable gate array chip.

[0055] In one embodiment, Figure 2As shown, the multi-stress regulation circuit includes a high-voltage power supply Vin, an input capacitor Cin, a load resistor RL, a current detection resistor Rs, a current limiting protection resistor R1, a load inductor L, a freewheeling diode D1, a switching transistor S1, a switching transistor S2 and a field effect transistor to be tested DUT; the positive electrode of the input capacitor Cin is connected to the positive electrode of the high-voltage power supply Vin, and the negative electrode of the input capacitor Cin is connected to the negative electrode of the high-voltage power supply Vin; one end of the load resistor RL is connected to the positive electrode of the high-voltage power supply Vin, and the other end of the load resistor RL is connected to one end of the load inductor L; the cathode of the freewheeling diode D1 is connected to the positive electrode of the high-voltage power supply Vin, and the cathode of the freewheeling diode D1 is connected to the positive electrode of the high-voltage power supply Vin. The anode of the freewheeling diode D1 is connected to the positive electrode of the high-voltage power supply Vin, and the anode of the freewheeling diode D1 is connected to the other end of the load inductor L; the drain of the switching transistor S1 is connected to the other end of the load inductor L, and the source of the switching transistor S1 is connected to the drain of the field effect transistor DUT to be tested; the source of the field effect transistor DUT to be tested is connected to one end of the current detection resistor Rs; the other end of the current detection resistor Rs is grounded; one end of the current limiting protection resistor R1 is connected to the source of the switching transistor S1, and the other end of the current limiting protection resistor R1 is connected to the drain of the switching transistor S2, and the source of the switching transistor S2 is grounded.

[0056] The working principle of the above technical solution is as follows: the multi-stress control circuit in the present invention includes a high-voltage power supply Vin, an input capacitor Cin, a load resistor RL, a current detection resistor Rs, a current limiting protection resistor R1, a load inductor L, a freewheeling diode D1, a switching transistor S1, a switching transistor S2 and a field effect transistor to be tested DUT; the positive electrode of the input capacitor Cin is connected to the positive electrode of the high-voltage power supply Vin, and the negative electrode of the input capacitor Cin is connected to the negative electrode of the high-voltage power supply Vin; one end of the load resistor RL is connected to the positive electrode of the high-voltage power supply Vin, and the other end of the load resistor RL is connected to one end of the load inductor L; the freewheeling diode D1 is connected to the positive electrode of the high-voltage power supply Vin, and the negative electrode of the input capacitor Cin is connected to the negative electrode of the high-voltage power supply Vin; one end of the load resistor RL is connected to the positive electrode of the high-voltage power supply Vin, and the other end of the load resistor RL is connected to one end of the load inductor L; The cathode of the diode D1 is connected to the positive electrode of the high-voltage power supply Vin, and the anode of the freewheeling diode D1 is connected to the other end of the load inductor L; the drain of the switching transistor S1 is connected to the other end of the load inductor L, and the source of the switching transistor S1 is connected to the drain of the field effect transistor DUT to be tested; the source of the field effect transistor DUT to be tested is connected to one end of the current detection resistor Rs; the other end of the current detection resistor Rs is grounded; one end of the current limiting protection resistor R1 is connected to the source of the switching transistor S1, and the other end of the current limiting protection resistor R1 is connected to the drain of the switching transistor S2, and the source of the switching transistor S2 is grounded.

[0057] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, through the configuration of multiple stress control circuits, a basis and necessary conditions are provided for applying stress to the field effect transistor DUT.

[0058] In one embodiment, the output terminal A1 is connected to the gate of the switching transistor S1 to control the on and off of the switching transistor S1; the output terminal A2 is connected to the gate of the field effect transistor DUT to be tested to control the on and off of the field effect transistor DUT to be tested; the output terminal A3 is connected to the gate of the switching transistor S2 to control the on and off of the switching transistor S2.

[0059] The working principle of the above technical solution is: in order to realize the connection between the driving control circuit and the multi-stress regulation circuit, the output terminal A1 is connected to the gate of the switching transistor S1 to control the on and off of the switching transistor S1; the output terminal A2 is connected to the gate of the field effect transistor DUT to be tested to control the on and off of the field effect transistor DUT to be tested; the output terminal A3 is connected to the gate of the switching transistor S2 to control the on and off of the switching transistor S2.

[0060] The beneficial effect of the above technical solution is: by adopting the solution provided by this embodiment, the transmission of the driving signal is realized by connecting the driving control circuit with the multi-stress regulation circuit.

[0061] In one embodiment, one end of the clamp measurement circuit is connected to the drain of the field effect transistor DUT to be tested, and the other end of the clamp measurement circuit is connected to the other end of the current detection resistor Rs; when the power field effect transistor DUT to be tested is in the on state, the clamp measurement circuit samples and obtains the on-state voltage drop between the source and drain of the power field effect transistor DUT to be tested.

[0062] The working principle of the above technical solution is: the clamp measurement circuit of the present invention can be any clamp circuit with low measurement delay and high measurement accuracy, one end of the clamp measurement circuit is connected to the drain of the field effect transistor DUT to be measured, and the other end of the clamp measurement circuit is connected to the other end of the current detection resistor Rs; when the power field effect transistor DUT to be measured is in the on state, the clamp measurement circuit samples and obtains the on-state voltage drop between the source and drain of the power field effect transistor DUT to be measured.

[0063] The beneficial effect of the above technical solution is: adopting the solution provided by this embodiment and setting the clamping measurement circuit can improve the measurement accuracy of the on-state voltage drop across the source and drain of the power field effect transistor DUT to be measured, reduce the measurement delay, and make the on-state resistance measurement of the power field effect transistor DUT to be measured more accurate.

[0064] In one embodiment, the on-resistance characterization module includes an oscilloscope, a probe, and a processing and display component; the probe is used to measure the detection current flowing through the current detection resistor Rs, and to sample and obtain the on-voltage drop; the oscilloscope is used to display the detection current and the on-voltage drop; the processing and display component is used to calculate the on-resistance based on the detection current and the on-voltage drop, and display the on-resistance.

[0065] The working principle of the above technical solution is: the on-resistance characterization module of the present invention includes an oscilloscope, a probe and a processing and display component; the probe is used to measure the detection current flowing through the current detection resistor Rs, and to sample and obtain the on-voltage drop; the oscilloscope is used to display the detection current and the on-voltage drop; the processing and display component is used to calculate the on-resistance of the detection current and the on-voltage drop, and display the on-resistance.

[0066] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, data condition support is provided for on-resistance characterization through the on-resistance characterization module.

[0067] On-resistance characterization method of field effect transistor with multi-stress regulation, such as Figure 3 As shown, it is characterized in that it is implemented according to a field effect transistor on-resistance characterization device with multi-stress regulation, and the on-resistance of the power field effect transistor DUT to be tested is obtained and characterized by the following steps:

[0068] The driving signal control circuit generates a driving signal, and sends the driving signal to the multi-stress regulating circuit through output terminal A1, output terminal A2, and output terminal A3;

[0069] The multi-stress control circuit applies electrical stress to the field effect transistor DUT under test according to the received driving signal;

[0070] After the electrical stress is applied, the multi-stress control circuit controls the field effect transistor DUT to be free from the influence of the electrical stress according to the received driving signal, so that it is in the dynamic characteristic recovery stage;

[0071] The probe is used to measure the detection current flowing through the current detection resistor Rs, and the on-state voltage drop between the source and drain of the field effect transistor DUT to be tested is collected. The on-state resistance is calculated based on the detection current and the on-state voltage drop using the processing and display component, and the on-state resistance is displayed.

[0072] The working principle of the above technical solution is: in order to realize the on-resistance characterization method of the field effect transistor with multi-stress regulation, the present invention first generates a driving signal by a driving signal control circuit, and sends the driving signal to the multi-stress regulation circuit through output terminals A1, A2, and A3; then, the multi-stress regulation circuit applies electrical stress to the field effect transistor DUT to be tested according to the received driving signal; after the application of the electrical stress is completed, the multi-stress regulation circuit controls the field effect transistor DUT to be tested to be not affected by the electrical stress according to the received driving signal, so that it is in the dynamic characteristic recovery stage; finally, the detection current flowing through the current detection resistor Rs is measured by a probe, and the on-voltage drop between the source and the drain of the field effect transistor DUT to be tested is collected, and the on-resistance is calculated for the detection current and the on-voltage drop using a processing and display component, and the on-resistance is displayed.

[0073] The beneficial effects of the above technical solution are: by adopting the solution provided in this embodiment, electrical stress is applied to the field effect transistor to be tested through the configured multi-stress dynamic characteristic characterization circuit module and on-resistance characterization module, and the recovery process of its dynamic on-resistance is observed, which provides more stress type observation windows for the research and analysis of the dynamic characteristic mechanism of the field effect transistor, helps to conduct in-depth research on the physical mechanism that affects the dynamic on-resistance, and makes the characterization and research of the dynamic on-resistance of the power semiconductor field effect transistor more accurate and comprehensive.

[0074] In one embodiment, the multi-stress control circuit applies electrical stress to the field effect transistor DUT according to the received driving signal, including:

[0075] By controlling the on and off of the switch transistor S1 and the switch transistor S2, the electrical stress of the power field effect transistor DUT to be tested is regulated, so that the field effect transistor DUT to be tested is subjected to a variety of different electrical stresses or is not subjected to electrical stress; the electrical stress includes hard switching stress, off-state drain voltage stress and half-on-state stress; Figure 4 As shown in the figure, it is a schematic diagram of the applied electrical stress waveform; hard switching stress is a mixed type of stress, which can be regarded as the superposition of a single half-on stress and an off-state drain voltage stress in terms of current and voltage waveforms; the main physical mechanism of the half-on stress is the thermal electron effect, and the main physical mechanism of the off-state drain voltage stress is electron acceleration under a high electric field, and the two stresses have different physical mechanisms; while hard switching stress has both of the above physical mechanisms; splitting the hard switching stress into half-on stress and off-state drain voltage stress can split the two different physical mechanisms, and applying different electrical stresses to the device under test DUT can obtain data on the impact of different electrical stresses on the dynamic on-resistance;

[0076] Specifically include:

[0077] Apply hard switching stress to the field effect transistor DUT, such as Figure 5As shown in the figure, it is a schematic diagram of the control waveform of the hard switch stress and the current and voltage waveform of the field effect transistor DUT to be tested; before time t0, the switch transistor S1 is also kept off, the transistor S1 is subjected to high voltage, and the drain of the field effect transistor DUT to be tested is not subjected to high voltage, eliminating the influence of prestress; at time t0, the field effect transistor DUT to be tested is turned on, and at time t1, the switch transistor S1 is turned on, and the source-drain current IDS_DUT of the field effect transistor DUT to be tested begins to rise, so that the field effect transistor DUT to be tested is soft-turned on; the switch transistor S1 remains on, and at time t2, the field effect transistor DUT to be tested is turned off, the drain voltage VDS_DUT of the field effect transistor DUT to be tested rises, and the source-drain current IDS_DUT decreases, so that the field effect transistor DUT to be tested is hard-turned off; because the switch transistor S1 remains on, the high voltage Vin is added to the field effect transistor DUT to be tested. The drain of the field effect transistor DUT to be tested is subjected to the off-state drain voltage stress; the field effect transistor DUT to be tested is turned on at time t4, the drain voltage VDS_DUT of the field effect transistor DUT to be tested decreases, and the source-drain current IDS_DUT rises rapidly under the freewheeling action of the load inductor L, and the current flowing through the field effect transistor DUT to be tested in the turn-on transient state is not zero, so that the field effect transistor DUT to be tested is hard turned on; the field effect transistor DUT to be tested is turned off at time t6, the source voltage VDS_DUT of the field effect transistor DUT to be tested increases, the source-drain current IDS_DUT decreases, and the field effect transistor DUT to be tested is hard turned off. Because S1 remains in the on state, the high voltage Vin is added to the drain of the field effect transistor DUT to be tested, and the field effect transistor DUT to be tested is subjected to the off-state drain voltage stress; the subsequent control process is the same;

[0078] Apply off-state drain voltage stress to the field effect transistor DUT, such as Figure 6As shown in the figure, it is a schematic diagram of the control waveform of the off-state drain voltage stress and the current and voltage waveform of the field effect transistor DUT to be tested; before time t0, the switch transistor S1 is kept off, the high voltage Vin is borne by the switch transistor S1, the drain of the field effect transistor DUT to be tested does not bear the high voltage, and the drain voltage VDS_DUT of the field effect transistor DUT to be tested is in a low voltage state. At time t0, the field effect transistor DUT to be tested is turned on. At this time, because the switch transistor S1 is in the off state, the field effect transistor DUT to be tested has no conduction current; at time t1, the switch transistor S1 is turned on, and the source-drain current IDS_DUT of the field effect transistor to be tested begins to rise, so that the field effect transistor DUT to be tested is soft-turned on; at time t2, the switch transistor S1 is turned off, and the source-drain current IDS_DUT of the field effect transistor to be tested decreases; before time t3, the source-drain current IDS_DUT of the field effect transistor to be tested has reached 0A, at t3, the field effect transistor DUT to be tested is turned off, and the drain voltage VDS_DUT of the field effect transistor DUT to be tested is in a low voltage state throughout the whole process, so that the field effect transistor DUT to be tested is softly turned off, at t4, the switch transistor S1 is turned on to make the drain voltage of the field effect transistor DUT to be tested rise, and at this time, the off-state drain voltage stress is applied to the field effect transistor DUT to be tested; when the field effect transistor DUT to be tested needs to be turned on again, at t5, the switch transistor S1 is turned off, and the switch transistor S2 is turned on, so that the drain voltage of the field effect transistor DUT to be tested drops to zero, that is, at t6, and then the field effect transistor DUT to be tested is turned on, and the switch transistor S2 is turned off. At t7, the switch transistor S1 is turned on, and the source-drain current IDS_DUT of the field effect transistor DUT to be tested rises rapidly under the action of the load inductance L, and the field effect transistor DUT to be tested is softly turned on in the stage from t5 to t7;

[0079] Apply half-on stress to the field effect transistor DUT, such as Figure 7As shown, it is a schematic diagram of the control waveform of the semi-on stress and the current and voltage waveform of the field effect transistor DUT to be tested; before t0, the switch transistor S1 is kept off, the high voltage Vin is borne by the switch transistor S1, the drain of the field effect transistor DUT to be tested does not bear the high voltage, and the drain voltage VDS_DUT of the field effect transistor to be tested is kept in a low voltage state to avoid the influence of the off-state drain voltage stress after the circuit is powered on. At t0, the field effect transistor DUT to be tested is turned on. At this time, the switch transistor S1 is in the off state, and the field effect transistor DUT to be tested has no conduction current. At t1, the switch transistor S1 is turned on to make the field effect transistor DUT to be tested soft-on, and the source-drain current IDS_DUT of the field effect transistor DUT to be tested begins to rise; at t2, the field effect transistor DUT to be tested is turned off. At this time, the drain voltage of the field effect transistor DUT to be tested rises, and the source-drain current IDS_DUT decreases. When the drain voltage of the field effect transistor DUT to be tested rises to the high voltage, that is, at t3, the field effect transistor DUT to be tested is turned on again. UT, the drain voltage drops, and under the freewheeling effect of the load inductor L, the source-drain current IDS_DUT rises. The time from t2 to t3 is reasonably controlled to ensure that the device is in a switching state, so that the field effect transistor DUT to be tested is subjected to semi-open state stress; after the field effect transistor DUT to be tested is turned on, due to the freewheeling effect of the load inductor L, IDS_DUT rises rapidly from t3 to t4, so that the field effect transistor DUT to be tested is subjected to semi-open state stress; in the conduction stage, the current of the load inductor L continues to Rise; at t5, the field effect transistor DUT to be tested is turned off, at this time the drain voltage rises, and the current drops. When the drain voltage of the field effect transistor DUT to be tested rises to a high voltage, that is, at t6, the switching transistor S1 is turned off, and the switching transistor S2 is turned on, so that the charge stored in the drain-source electrode of the field effect transistor DUT to be tested is released through the resistor R1 and the channel of the switching transistor S2, and the drain voltage VDS_DUT drops back to a low voltage and remains in a low voltage state, thereby shielding the influence of the off-state drain voltage stress; the subsequent control process is the same.

[0080] The working principle of the above technical solution is: in order to realize the application of electrical stress to the field effect transistor DUT to be tested, the present invention controls the conduction and shutdown of the switch transistor S1 and the switch transistor S2 to regulate the electrical stress of the power field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is subjected to a variety of different electrical stresses or is not subjected to electrical stress; the electrical stress includes hard switch stress, off-state drain voltage stress and half-on-state stress; specifically includes:

[0081] Apply hard switching stress to the field effect transistor DUT to be tested, specifically: first keep the switch transistor S1 off, then turn on the field effect transistor DUT to be tested, and then turn on the switch transistor S1 to make the field effect transistor DUT to be tested soft-turn on; keep the switch transistor S1 on, then turn off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is hard-turned off; reasonably control the time interval, turn on the field effect transistor DUT to be tested, and under the freewheeling action of the load inductor L, the current that flows through the field effect transistor DUT to be tested in the transient state is not zero, so that the field effect transistor DUT to be tested is hard-turned on; through the above control, the influence of the pre-stress after the circuit is powered on can be eliminated, and the controllable hard switching stress can be applied to the field effect transistor DUT to be tested separately, eliminating the influence of the off-state drain voltage stress and the half-open state stress, and the influence of the hard switching stress on the dynamic on-resistance of the field effect transistor DUT to be tested can be explored separately;

[0082] The off-state drain voltage stress is applied to the field effect transistor DUT to be tested, specifically: first keep the switch transistor S1 off, then turn on the field effect transistor DUT to be tested, and then turn on the switch transistor S1 to make the field effect transistor DUT to be tested soft-on; then turn off the switch transistor S1 first, then turn off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is soft-off, and then turn on the switch transistor S1 to make the drain voltage of the field effect transistor DUT to be tested rise, at this time, the off-state drain voltage stress is applied to the field effect transistor DUT to be tested; when the field effect transistor DUT to be tested needs to be turned on again, turn off the switch transistor S1 first, turn on The switch transistor S2 is used to make the drain voltage of the field effect transistor DUT to be tested drop to zero, and then the field effect transistor DUT to be tested is turned on, the switch transistor S2 is turned off, and then the switch transistor S1 is turned on to make the field effect transistor DUT to be tested soft-turn on; through the above control, the influence of the pre-stress after the circuit is powered on on the field effect transistor DUT to be tested can be eliminated, and the controllable off-state drain voltage stress can be applied to the field effect transistor DUT to be tested separately, and the time of the off-state drain voltage stress can be accurately controlled, and the influence of hard switching stress and half-open stress can be eliminated, and the influence of the off-state drain voltage stress on the dynamic on-resistance of the field effect transistor DUT to be tested can be explored separately;

[0083] A semi-on stress is applied to the field effect transistor DUT to be tested, specifically: first keep the switch transistor S1 off, then turn on the field effect transistor DUT to be tested, and then turn on the switch transistor S1 to make the field effect transistor DUT to be tested soft-on, and the current rises; then turn off the field effect transistor DUT to be tested, at this time the drain voltage of the field effect transistor DUT to be tested rises, and the current drops, and the time interval is reasonably controlled. When the drain voltage of the field effect transistor DUT to be tested rises to a high voltage, turn on the field effect transistor DUT to be tested again, the drain voltage drops, and under the freewheeling effect of the load inductor L, the current rises rapidly, so that the field effect transistor DUT to be tested is subjected to the semi-on stress; when it is necessary to turn off the field effect transistor DUT to be tested, the drain voltage of the field effect transistor DUT to be tested is turned on again, and the drain voltage drops. Under the freewheeling effect of the load inductor L, the current rises rapidly, so that the field effect transistor DUT to be tested is subjected to the semi-on stress; When the transistor DUT is tested, the field effect transistor DUT to be tested is turned off first. At this time, the drain voltage rises and the current drops. The time interval is reasonably controlled. When the drain voltage of the field effect transistor DUT to be tested rises to a high voltage, the switching transistor S1 is turned off and the switching transistor S2 is turned on to make the drain voltage of the field effect transistor DUT to be tested drop and remain in a low voltage state. Through the above control strategy, the influence of the pre-stress after the circuit is powered on on the field effect transistor DUT to be tested can be eliminated, and controllable half-open state stress can be applied to the field effect transistor DUT to be tested separately, eliminating the influence of hard switching stress and off-state drain voltage stress, and the influence of the half-open state stress on the dynamic on-resistance of the field effect transistor DUT to be tested can be explored separately.

[0084] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, different electrical stresses can be distinguished through different control strategies to explore the impact on the dynamic on-resistance of the field effect transistor DUT under test.

[0085] In one embodiment, after the electrical stress is applied, the multi-stress control circuit controls the field effect transistor DUT to be free from the influence of the electrical stress according to the received driving signal, so that the DUT is in a dynamic characteristic recovery stage, such as Figure 8 As shown, it is a schematic diagram of the on-resistance measurement control waveform without electrical stress application and a schematic diagram of the current and voltage waveform of the field effect transistor DUT to be tested; before time t0, keep the switch transistor S1 off, keep the drain voltage of the field effect transistor DUT to be tested zero, at time t0, first turn on the field effect transistor DUT to be tested, at time t1, turn on the switch transistor S1, the drain-source IDS_DUT of the field effect transistor DUT to be tested rises, so that the field effect transistor DUT to be tested is soft-turned on; at time t2, turn off the switch transistor S1, so that the current drops to zero, at time t3, turn off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is soft-turned off, and the high voltage Vin is added to the drain-source ends of the switch transistor S1, and the drain of the field effect transistor DUT to be tested does not bear the high voltage, so the drain voltage VDS_DUT of the field effect transistor to be tested can always remain in a low voltage state; the second pulse is the same as the first one.

[0086] The working principle of the above technical solution is: in order to explore the mechanism of controlling the field effect transistor DUT to be tested so that it is not affected by electrical stress and is in the dynamic characteristic recovery stage, the present invention first keeps the switching transistor S1 turned off, keeps the drain voltage of the field effect transistor DUT to be tested to zero, first turns on the field effect transistor DUT to be tested, and then turns on the switching transistor S1 to make the field effect transistor DUT to be tested soft-turned on; then turns off the switching transistor S1 first to make the current drop to zero, and then turns off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is soft-turned off, and the switching transistor S1 is subjected to high voltage.

[0087] The beneficial effects of the above technical solution are as follows: by adopting the solution provided in this embodiment, through the above control strategy, the influence of electrical stress on the field effect transistor DUT to be tested can be eliminated, so that the field effect transistor DUT to be tested is in a dynamic characteristic recovery state, avoiding the problem of heating caused by the device to be tested being turned on for a long time; and combined with the application control of the above three electrical stresses, real-time observation of the entire process from one hundred nanoseconds after the electrical stress is removed to the recovery of the on-resistance can be achieved, thereby deeply studying the physical mechanism behind the dynamic on-resistance recovery phenomenon.

[0088] In one embodiment, the process of applying electrical stress to the field effect transistor DUT under test is monitored and controlled by using a monitoring control circuit, specifically including:

[0089] Build a monitoring and control circuit module connected to the multi-stress dynamic characteristic characterization circuit module; the monitoring and control circuit module includes a monitoring component and a control component; the monitoring component is connected to the control component; the control component is connected to the drive signal control circuit;

[0090] Using the monitoring component, the process of applying electrical stress to the field effect transistor DUT to be tested is monitored to obtain monitoring result data;

[0091] Compare the monitoring result data with the set standard monitoring data. If there is an abnormality in the monitoring result data, generate a monitoring signal and send it to the control component;

[0092] The control component generates a control command according to the received monitoring signal;

[0093] According to the control command, the driving signal control circuit is controlled to adjust the type of the output driving signal; wherein the type of the output driving signal is obtained by integrating the driving signal generated by the driving signal control circuit based on the set integral parameter.

[0094] The working principle of the above technical solution is: in order to realize the monitoring and control of the process of applying electrical stress to the field effect transistor DUT to be tested, the present invention first builds a monitoring control circuit module connected to the multi-stress dynamic characteristic characterization circuit module; the monitoring control circuit module includes a monitoring component and a control component; the monitoring component is connected to the control component; the control component is connected to the drive signal control circuit; the monitoring component is then used to monitor the process of applying electrical stress to the field effect transistor DUT to be tested, and obtain monitoring result data; the monitoring result data is compared with the set standard monitoring data, and if the monitoring result data is abnormal, a monitoring signal is generated and sent to the control component; finally, the control component generates a control command according to the received monitoring signal; according to the control command, the drive signal control circuit is controlled to adjust the category of the output drive signal; wherein, the category of the output drive signal is obtained based on the set integral parameter, and the drive signal generated by the drive signal control circuit is integrated.

[0095] The beneficial effect of the above technical solution is: adopting the solution provided in this embodiment, by monitoring and controlling the process of applying electrical stress to the field effect transistor DUT under test, it is beneficial to more accurately control the process of applying electrical stress to the field effect transistor DUT under test and improve the quality of applying electrical stress to the field effect transistor DUT under test.

[0096] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for characterizing on-resistance of a field effect transistor with multi-stress regulation, characterized in that: include: Multi-stress dynamic characteristics characterization circuit module and on-resistance characterization module; The multi-stress dynamic characteristic characterization circuit module is connected to the on-resistance characterization module; The multi-stress dynamic characteristic characterization circuit module includes a driving signal control circuit, a multi-stress regulation circuit and a clamping measurement circuit; The driving signal control circuit includes output terminal A1, output terminal A2 and output terminal A3, and is connected to the multi-stress regulation circuit; The multiple stress regulating circuit is connected to the clamp measuring circuit; The driving signal control circuit is used to generate a driving signal for controlling the multi-stress regulating circuit; The multi-stress control circuit is used for applying various electrical stresses to the field effect transistor to be tested according to the driving signal; The clamp measurement circuit is used to measure the on-state voltage drop between the source and drain of the field effect transistor to be measured; The multi-stress regulation circuit includes a high-voltage power supply Vin, an input capacitor Cin, a load resistor RL, a current detection resistor Rs, a current limiting protection resistor R1, a load inductor L, a freewheeling diode D1, a switching transistor S1, a switching transistor S2 and a field effect transistor to be tested DUT; the positive electrode of the input capacitor Cin is connected to the positive electrode of the high-voltage power supply Vin, and the negative electrode of the input capacitor Cin is connected to the negative electrode of the high-voltage power supply Vin; one end of the load resistor RL is connected to the positive electrode of the high-voltage power supply Vin, and the other end of the load resistor RL is connected to one end of the load inductor L; the cathode of the freewheeling diode D1 is connected to the positive electrode of the high-voltage power supply Vin, and the cathode of the freewheeling diode D1 is connected to the positive electrode of the high-voltage power supply Vin. Connect to the positive electrode of the high-voltage power supply Vin, and the anode of the freewheeling diode D1 is connected to the other end of the load inductor L; the drain of the switching transistor S1 is connected to the other end of the load inductor L, and the source of the switching transistor S1 is connected to the drain of the field effect transistor DUT to be tested; the source of the field effect transistor DUT to be tested is connected to one end of the current detection resistor Rs; the other end of the current detection resistor Rs is grounded; one end of the current limiting protection resistor R1 is connected to the source of the switching transistor S1, and the other end of the current limiting protection resistor R1 is connected to the drain of the switching transistor S2, and the source of the switching transistor S2 is grounded; The driving signal control circuit generates a driving signal, and sends the driving signal to the multi-stress regulating circuit through output terminal A1, output terminal A2, and output terminal A3; The multi-stress control circuit applies electrical stress to the field effect transistor DUT under test according to the received driving signal; Electrical stress includes hard switching stress, off-state drain voltage stress and half-on-state stress; After the electrical stress is applied, the multi-stress control circuit controls the field effect transistor DUT to be free from the influence of the electrical stress according to the received driving signal; specifically: Keep the switch transistor S1 off, keep the drain voltage of the field effect transistor DUT to be tested zero, first turn on the field effect transistor DUT to be tested, then turn on the switch transistor S1, so that the field effect transistor DUT to be tested is soft-turned on; then turn off the switch transistor S1 first, so that the current drops to zero, then turn off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is soft-turned off, and the switch transistor S1 bears the high voltage; Based on the detection current on the current detection resistor Rs and the on-state voltage drop between the source and drain of the field effect transistor DUT to be tested, the on-state resistance is calculated and characterized.

2. The method for characterizing on-resistance of a field effect transistor with multi-stress regulation according to claim 1, characterized in that: The driving signal control circuit is a field programmable gate array chip.

3. The method for characterizing on-resistance of a field effect transistor with multi-stress regulation according to claim 1, characterized in that: The output terminal A1 is connected to the gate of the switching transistor S1 to control the on and off of the switching transistor S1; the output terminal A2 is connected to the gate of the field effect transistor DUT to be tested to control the on and off of the field effect transistor DUT to be tested; the output terminal A3 is connected to the gate of the switching transistor S2 to control the on and off of the switching transistor S2.

4. The method for characterizing on-resistance of a field effect transistor with multi-stress regulation according to claim 1, characterized in that: One end of the clamp measurement circuit is connected to the drain of the field effect transistor DUT to be measured, and the other end of the clamp measurement circuit is connected to the other end of the current detection resistor Rs; when the power field effect transistor DUT to be measured is in the on state, the clamp measurement circuit samples and obtains the on-state voltage drop between the source and drain of the power field effect transistor DUT to be measured.

5. The method for characterizing on-resistance of a field effect transistor with multi-stress regulation according to claim 4, characterized in that: The on-resistance characterization module includes an oscilloscope, a probe, and a processing and display component; the probe is used to measure the detection current flowing through the current detection resistor Rs, and to sample and obtain the on-voltage drop; The oscilloscope is used to display the detection current and the on-state voltage drop; the processing display component is used to calculate the on-state resistance based on the detection current and the on-state voltage drop, and display the on-state resistance.

6. The method for characterizing on-resistance of a field effect transistor with multi-stress regulation according to claim 1, characterized in that: The multi-stress control circuit applies electrical stress to the field effect transistor DUT according to the received driving signal, including: Apply hard switching stress to the field effect transistor DUT to be tested, specifically: first keep the switch transistor S1 off, then turn on the field effect transistor DUT to be tested, and then turn on the switch transistor S1 to make the field effect transistor DUT to be tested soft-on; keep the switch transistor S1 on, then turn off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is hard-off; reasonably control the time interval, turn on the field effect transistor DUT to be tested, under the freewheeling action of the load inductor L, the current flowing through the field effect transistor DUT to be tested in the turn-on state is not zero, so that the field effect transistor DUT to be tested is hard-on; Applying off-state drain voltage stress to the field effect transistor DUT to be tested, specifically: first keep the switch transistor S1 off, then turn on the field effect transistor DUT to be tested, then turn on the switch transistor S1, so that the field effect transistor DUT to be tested is soft-turned on; then turn off the switch transistor S1 first, then turn off the field effect transistor DUT to be tested, so that the field effect transistor DUT to be tested is soft-turned off, then turn on the switch transistor S1 to increase the drain voltage of the field effect transistor DUT to be tested, and at this time, applying off-state drain voltage stress to the field effect transistor DUT to be tested; when the field effect transistor DUT to be tested needs to be turned on again, first turn off the switch transistor S1, turn on the switch transistor S2, so that the drain voltage of the field effect transistor DUT to be tested drops to zero, then turn on the field effect transistor DUT to be tested, turn off the switch transistor S2, and then turn on the switch transistor S1, so that the field effect transistor DUT to be tested is soft-turned on; A semi-open stress is applied to the field effect transistor DUT to be tested, specifically: first keep the switch transistor S1 off, then turn on the field effect transistor DUT to be tested, and then turn on the switch transistor S1, so that the field effect transistor DUT to be tested is soft-opened and the current rises; then turn off the field effect transistor DUT to be tested, at this time the drain voltage of the field effect transistor DUT to be tested rises, the current drops, and the time interval is reasonably controlled. When the drain voltage of the field effect transistor DUT to be tested rises to a high voltage, turn on the field effect transistor DUT to be tested again, the drain voltage drops, and under the freewheeling action of the load inductor L, the current rises rapidly, so that the field effect transistor DUT to be tested is subjected to the semi-open stress; when it is necessary to turn off the field effect transistor DUT to be tested, turn off the field effect transistor DUT to be tested first, at this time the drain voltage rises, the current drops, and the time interval is reasonably controlled. When the drain voltage of the field effect transistor DUT to be tested rises to a high voltage, turn off the switch transistor S1, turn on the switch transistor S2, so that the drain voltage of the field effect transistor DUT to be tested drops and is kept in a low voltage state.

7. The method for characterizing on-resistance of a field effect transistor with multi-stress regulation according to claim 1, characterized in that: The process of applying electrical stress to the field effect transistor DUT under test is monitored and controlled by using a monitoring and control circuit, specifically including: Build a monitoring and control circuit module connected to the multi-stress dynamic characteristic characterization circuit module; the monitoring and control circuit module includes a monitoring component and a control component; the monitoring component is connected to the control component; the control component is connected to the drive signal control circuit; Using the monitoring component, the process of applying electrical stress to the field effect transistor DUT to be tested is monitored to obtain monitoring result data; Compare the monitoring result data with the set standard monitoring data. If there is an abnormality in the monitoring result data, generate a monitoring signal and send it to the control component; The control component generates a control command according to the received monitoring signal; According to the control command, the driving signal control circuit is controlled to adjust the type of the output driving signal; wherein the type of the output driving signal is obtained by integrating the driving signal generated by the driving signal control circuit based on the set integral parameter.

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