Optimization Method, Device, Chip, Equipment and Medium for Special Function Unit

Abstract

Embodiments of the present invention disclose an optimization method, device, chip, equipment, and medium for special function units. The method includes: inputting a first operation instruction indicating to perform an operation on multimedia data into a special function unit in a chip, where the first operation instruction includes a first operator supported by the special function unit; receiving the original operation result of the special function unit executing the first operation instruction, where the special function unit executes the first operation instruction based on the operation ability corresponding to the first operator; determining an iteration method; determining an iteration result with the original operation result as the iteration initial value based on the iteration method; and determining the iteration result as the operation result of the first operation instruction. Using the original operation result as the iteration initial value, the data precision in the multimedia data operation is improved through the iteration process, realizing the optimization for the special function unit. The operation result with improved precision can be applied to many types of multimedia applications such as image rendering and multimedia data compression.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and more specifically, to an optimization method, device, chip, electronic device, storage medium, and program product for a Special Function Unit (SFU). Background Art

[0002] Many chips (such as GPUs or GPGPUs, etc.) contain SFUs. The SFU can effectively perform structured arithmetic or mathematical functions on vector data, such as sine, cosine, reciprocal, and square root. The SFU is crucial for computationally intensive tasks in graphics processing, such as 3D rendering, texture mapping, and lighting calculation.

[0003] In a large number of applications related to multimedia data (such as text data, image data, audio data, and video data, etc.), it is often necessary to call the SFU. However, the data accuracy output by the SFU is usually not high and it is difficult to meet the high requirements for data accuracy in multimedia applications. Summary of the Invention

[0004] The present invention provides an optimization method, device, chip, electronic device, storage medium, and program product for the SFU, which helps to improve the data accuracy in multimedia data applications.

[0005] The technical solution of the embodiment of the present invention is as follows:

[0006] An optimization method for an SFU, comprising:

[0007] Input a first operation instruction indicating an operation on multimedia data into the SFU in the chip, where the first operation instruction includes a first operator supported by the SFU;

[0008] Receive the original operation result of the SFU executing the first operation instruction, where the SFU executes the first operation instruction based on the operation ability corresponding to the first operator;

[0009] Determine an iteration method;

[0010] Based on the iteration method, determine an iteration result with the original operation result as the iteration initial value;

[0011] Determine the iteration result as the operation result of the first operation instruction.

[0012] In one embodiment, determining the iteration method includes determining an iteration formula, and the iteration formula includes a second operator supported by the SFU;

[0013] The determining, based on the iteration method, an iterative result with the original operation result as an iteration initial value includes:

[0014] During each iteration, a second operation instruction including the second operator is input to the SFU and an operation result of executing the second operation instruction is received from the SFU, wherein the SFU executes the second operation instruction based on an operation capability corresponding to the second operator.

[0015] In one embodiment, determining the iteration method includes:

[0016] Display multiple candidate iteration methods in the user display interface;

[0017] In response to a selection operation triggered in the user display interface, the iteration formula is selected from the multiple candidate iteration modes.

[0018] In one embodiment, the first operation instruction is generated in the process of performing regularization processing on the activation tensor of the multimedia data to obtain the regularized activation tensor of the multimedia data, wherein the first operator includes a square root operator and / or a division operator; the iterative result includes the iterative result of the square root operation and / or the iterative result of the division operation, wherein the iterative result of the square root operation is used to determine the standard deviation in the regularization processing, and the iterative result of the division operation is used to determine the data scale transformation in the regularization processing.

[0019] In one embodiment, the first operation instruction is generated during compression of the multimedia data, wherein the first operator comprises a cosine operator;

[0020] The compression process includes:

[0021] dividing the multimedia data into a plurality of blocks;

[0022] Performing a discrete cosine transform on each block; wherein in the discrete cosine transform of each block, generating a respective first operation instruction for each block, and determining a frequency coefficient of each block based on a respective operation result of the respective first operation instruction of each block;

[0023] quantizing the frequency coefficients of each block;

[0024] Based on the entropy coding method, the quantized frequency coefficients of each block are encoded.

[0025] In one embodiment, the multimedia data includes image data; the first operation instruction is generated during image rendering of the image data, wherein the first operator includes at least one of the following:

[0026] Reciprocal operator; root mean square operator; reciprocal root mean square operator; logarithmic operator; exponential operator.

[0027] An optimization device for an SFU, comprising:

[0028] An input module, configured to input a first operation instruction indicating to perform an operation on multimedia data into the SFU in a chip, where the first operation instruction includes a first operation supported by the SFU;

[0029] A receiving module, configured to receive an original operation result of the SFU executing the first operation instruction, where the SFU executes the first operation instruction based on an operation capability corresponding to the first operator;

[0030] A first determination module, configured to determine an iteration mode;

[0031] A second determination module, configured to determine an iteration result with the original operation result as an iteration initial value based on the iteration mode;

[0032] A third determination module, configured to determine the iteration result as an operation result of the first operation instruction.

[0033] A chip, comprising:

[0034] SFU;

[0035] A controller, configured to input a first operation instruction indicating to perform an operation on multimedia data into the SFU, where the first operation instruction includes a first operator supported by the SFU; receive an original operation result of the SFU executing the first operation instruction, where the SFU executes the first operation instruction based on an operation capability corresponding to the first operator; determine an iteration mode;

[0036] An iteration circuit, configured to determine an iteration result with the original operation result as an iteration initial value based on the iteration mode;

[0037] The controller is further configured to determine the iteration result as an operation result of the first operation instruction.

[0038] An electronic device, comprising:

[0039] A memory;

[0040] A processor;

[0041] Wherein an application program executable by the processor is stored in the memory, and is configured to enable the processor to execute the optimization method of the SFU as described in any one of the above.

[0042] A computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, cause the processor to execute any of the above-described SFU optimization methods.

[0043] A program product includes a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned SFU optimization methods.

[0044] It can be seen from the above technical solution that in an embodiment of the present invention, a first operation instruction indicating the execution of an operation on multimedia data is input into the SFU in the chip, the first operation instruction including the first operator supported by the SFU; the original operation result of the SFU executing the first operation instruction is received, wherein the SFU executes the first operation instruction based on the operation capability corresponding to the first operator; an iteration method is determined; based on the iteration method, an iteration result with the original operation result as the iteration initial value is determined; and the iteration result is determined as the operation result of the first operation instruction. It can be seen that the embodiment of the present invention does not directly use the original operation result of the SFU as the final operation result of the multimedia data, but uses it as the iteration initial value to improve the data accuracy in the multimedia data operation by using the iterative process, thereby achieving optimization for the SFU. In addition, the operation result with improved accuracy can be applied to many types of multimedia applications such as image rendering and multimedia data compression to enhance the media effects of multimedia applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 FIG. 4 is an exemplary flow chart of an SFU optimization method according to an embodiment of the present invention.

[0046] Figure 2 FIG. 4 is an exemplary flow chart of optimizing SFU using Newton iteration according to an embodiment of the present invention.

[0047] Figure 3 Schematic diagram of the structure of a chip according to an embodiment of the present invention.

[0048] Figure 4 This is an exemplary structural diagram of the SFU optimization device according to an embodiment of the present invention.

[0049] Figure 5 is an exemplary structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0051] For the sake of simplicity and intuitiveness in description, the solutions of the present invention will be elaborated below by describing several representative embodiments. A large number of details in the embodiments are only used to help understand the solutions of the present invention. However, it is obvious that the technical solutions of the present invention can be implemented without being limited to these details. In order to avoid unnecessarily obscuring the solutions of the present invention, some embodiments are not described in detail, but only the framework is given. Hereinafter, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the quantity of a component is not specifically indicated hereinafter, it means that the component can be one or more, or can be understood as at least one.

[0052] In view of the disadvantage that the operation results output by the SFU have low data accuracy, it is currently difficult to widely call the SFU in multimedia applications (which usually have high requirements for data accuracy). The embodiments of the present invention do not directly use the operation results of the SFU as the final operation results of multimedia data, but use them as the initial values of iteration, so as to improve the data accuracy in the operation of multimedia data through the iteration process, thereby realizing the optimization of the SFU. The operation results with improved accuracy can be applied to many types of multimedia applications such as image rendering and multimedia data compression, so as to enhance the media effects of multimedia applications (for example, improving the image quality of image rendering or the compression efficiency of multimedia data, etc.).

[0053] Figure 1 It is a schematic flowchart of the optimization method of the SFU according to the embodiments of the present invention. As Figure 1 shown, the method includes:

[0054] Step 101: Input a first operation instruction indicating to perform an operation on multimedia data into the SFU in the chip, and the first operation instruction includes a first operator supported by the SFU.

[0055] The SFU in the chip can calculate various types of functions through methods such as numerical approximation, and can be used to improve the computing performance of the chip. For example, the SFU usually supports the following instructions: (1) RCP, used to calculate the reciprocal; (2) SQRT, used to calculate the square root; (3) RSQ, used to calculate the reciprocal square root; (4) LOG2, used to calculate the logarithm with base 2; (5) POW2, used to calculate the exponent with base 2; (6) DSQ, used to calculate the division square root; (7) DIV, used to calculate division; (8) SIN, used to calculate the sine; (9) COS, used to calculate the cosine; (10) TAN, used to calculate the tangent; (11) ASIN, used to calculate the arcsine; (12) ACOS, used to calculate the arccosine; (13) ATAN, used to calculate the arctangent; and so on.

[0056] The first arithmetic instruction is used to indicate performing an operation on multimedia data. Among them, the multimedia data may include: text data, image data, audio data, video data, and so on. The first arithmetic instruction includes a first operator supported by the SFU. For example, the first operator may include RCP, SQRT, RSQ, LOG2, POW2, DSQ, DIV, SIN, COS, TAN, ASIN, ACOS, or ATAN, and so on. The first arithmetic instruction may also include the operands of the first operator, and the operands may be any data extracted from the multimedia data or the attribute data of the multimedia data. For example, when the first arithmetic instruction is used to indicate that the SFU calculates √4, the first operator is SQRT, and the operand is 4.

[0057] Step 102: Receive the original operation result of the SFU executing the first arithmetic instruction, where the SFU executes the first arithmetic instruction based on the operation ability corresponding to the first operator.

[0058] Here, the SFU executes the first arithmetic instruction based on the operation ability corresponding to the first operator and obtains the original operation result of executing the first arithmetic instruction. Different from the related art: in the embodiment of the present invention, the original operation result of the SFU is not directly used as the final operation result of the multimedia data, but is used as the iterative initial value to improve the data accuracy in the multimedia data operation by using the iterative process.

[0059] Step 103: Determine the iterative method.

[0060] In one embodiment, determining the iterative method includes: displaying multiple candidate iterative methods in the user display interface; in response to a selection operation triggered in the user display interface, selecting an iterative formula from the multiple candidate iterative methods.

[0061] For example, the candidate iterative methods may include: Newton iterative method, bisection iterative method, steepest descent method, conjugate iterative method, variable metric iterative method, least squares iterative method, linear programming iterative method, nonlinear programming iterative method, simplex method iterative method, penalty function iterative method, slope projection method iterative method, genetic algorithm iterative method, simulated annealing iterative method, and so on.

[0062] The following takes the Newton iterative method and the bisection iterative method as examples to give a demonstration of the iterative method.

[0063] (I) Newton iterative method

[0064] The Newton iterative method is a method for approximately solving equations in the real number field and the complex number field, also known as the Newton-Raphson method or the Newton tangent method. Its basic idea is to use the tangent line to approximate the curve to find the root of the function. The specific steps include:

[0065] Step (1): Determine an initial value \(x_0\) as an approximation of the root of the equation. Here, the initial value \(x_0\) is the original operation result of the SFU when executing the first operation instruction.

[0066] Step (2): Locate the point \((x_0, f(x_0))\) on the graph of the function \(f(x)\) and draw a tangent line at this point.

[0067] Step (3): Calculate the intersection point of the tangent line and the \(x\)-axis, and use it as the new approximation.

[0068] Repeat Step (2) and Step (3) until the required accuracy is met or the maximum number of iterations is reached.

[0069] (2) Bisection iteration method

[0070] The bisection iteration method is a method for solving equations. It continuously bisects the interval where the zero point of the function \(f(x)\) is located, making the two endpoints of the interval gradually approach the zero point, and then obtaining an approximation of the zero point. This method is applicable to the function \(y = f(x)\) that is monotonically continuous on the interval \([a, b]\) and \(f(a)\times f(b)<0\). The core idea of the bisection iteration method is to continuously calculate the midpoint of the interval and determine the new search interval based on the sign change of the function value at the midpoint and the function values at the interval endpoints until a certain accuracy requirement is met or the interval length is less than a certain threshold. The specific steps include:

[0071] Step (1): Determine the initial interval \([a, b]\) and confirm that the signs of \(f(a)\) and \(f(b)\) are opposite.

[0072] Step (2): Calculate the midpoint of the interval \(mid=(a + b) / 2\).

[0073] Step (3): Check the signs of the function value \(f(mid)\) at the midpoint and the function values at the interval endpoints. If the sign of \(f(mid)\) is the same as that of \(f(a)\), update the search interval to \([mid, b]\); if the sign of \(f(mid)\) is the same as that of \(f(b)\), update the search interval to \([a, mid]\); otherwise, it is considered that an approximate solution is found.

[0074] Repeat Step (2) and Step (3) until the accuracy requirement is met or the interval length is less than the preset value.

[0075] The above exemplary description shows typical examples of the candidate iteration methods. Those skilled in the art can realize that this description is only exemplary and is not used to limit the protection scope of the embodiments of the present invention.

[0076] Step 104: Based on the iteration method, determine the iteration result with the original operation result as the iteration initial value.

[0077] In one embodiment, determining the iterative manner includes determining an iterative formula for the iterative manner, where the iterative formula includes a second operator supported by the SFU; step 104 specifically includes: in each iteration process, inputting a second operation instruction including the second operator into the SFU and receiving, from the SFU, an operation result of executing the second operation instruction, where the SFU executes the second operation instruction based on the operation capability corresponding to the second operator.

[0078] Table 1 is a schematic table of the iterative formula.

[0079]

[0080] Table 1

[0081] For example, when the first operation instruction is specifically to calculate the square root of a numerical value a (i.e., the first operator is square root calculation and the operation object is a), let The iterative formula is: where x n is the operation result of the nth iteration, and x n+1 is the operation result of the (n + 1)th iteration. It can be seen that the operator " / " (i.e., division) is included in the iterative formula. Therefore, in each iteration process, a second operation instruction for calculating (a / x n ) can be generated, input the second operation instruction into the SFU and receive, from the SFU, an operation result of executing the second operation instruction, and then complete the iterative process of this round based on the operation result of the second operation instruction. It can be seen that by calling the SFU during the iteration process, the operation pressure can be reduced and the iteration speed can be increased.

[0082] Step 105: Determine the iterative result as the operation result of the first operation instruction.

[0083] It can be seen that the embodiment of the present invention does not directly use the operation result of the SFU as the final operation result of the multimedia data, but uses it as the iterative initial value to improve the data accuracy in the multimedia data operation through the iterative process, thereby achieving the optimization of the SFU. The operation result with improved accuracy can be applied to many types of multimedia applications such as image rendering and multimedia data compression, so as to improve the media effect of the multimedia application (for example, improving the image quality of image rendering or the compression efficiency of multimedia data, etc.).

[0084] In one embodiment, the operation result of the first operation instruction can be applied to various fields, such as image rendering processing, especially applied to GPUs or GUGPUs. The operation result of the first operation instruction can be used to calculate transcendental functions, such as reciprocals, square roots, power functions, logarithms, trigonometric functions, etc., which play important roles in image rendering. In another embodiment, the operation result of the first operation instruction is applicable to processing special functions such as Sigmoid, which is particularly important for neural network calculations.

[0085] The following gives a demonstration of typical application scenarios of the first operation instruction.

[0086] (1) Applied to the regularization processing of the activation tensor of multimedia data.

[0087] The regularization of the activation tensor of multimedia data mainly involves performing regularization operations on high-dimensional multimedia data to improve the processing efficiency and accuracy of the data. As a high-dimensional array, the regularization processing of tensors has extensive applications in multiple fields, especially in image processing, signal processing, and machine learning. The purpose of regularization is to improve the properties of the data by adding some constraint conditions, such as improving the piecewise smoothness of the data and reducing the complexity of the data. In image processing, the regularization processing of tensors is particularly important. For example, by combining the Laplace function and anisotropic total variation regularization, multi-order approximation of tensors can be performed, thereby improving the local piecewise smoothness and retaining the edges of the restored tensor data. Applications on color images, videos, multi-spectral images, and magnetic resonance imaging data demonstrate its effectiveness. In addition, the tensor completion problem of multimedia data is also an important application field. Tensor completion involves filling in the missing values in the tensor.

[0088] Generally speaking, the regularization processing of tensors is an important data processing technology. It improves the properties of the data by adding specific constraint conditions, enhancing the effect and accuracy of data processing. This method has extensive applications in multiple fields such as image processing, signal processing, and machine learning, and is an important technology in data processing and analysis.

[0089] In one embodiment, the first operation instruction is generated during the process of performing regularization processing on the activation tensor of multimedia data to obtain the regularized activation tensor of multimedia data, where the first operator includes a square root operator and / or a division operator; the iteration result includes the iteration result of the square root operation and / or the iteration result of the division operation, where the iteration result of the square root operation is used to determine the standard deviation in the regularization processing, and the iteration result of the division operation is used to determine the data scale transformation in the regularization processing.

[0090] For example, based on Figure 1The operation result of the first operation instruction obtained by the method shown can improve the calculation accuracy of the Norm operator in the artificial intelligence model. The input of the Norm operator can include activation tensors of multimedia data such as images and voices, and the output can include regularized activation tensors. Regularization is usually performed using the mean and variance. Based on Figure 1 The operation result of the first operation instruction obtained by the method shown can improve the calculation accuracy of calculating the standard deviation (obtained by taking the square root of the variance) and data scale transformation (dividing by the standard deviation), which helps to improve the accuracy of images, voices, etc. after regularization.

[0091] (2) Applied to the compression processing of multimedia data.

[0092] In one embodiment, the first operation instruction is generated during the compression of multimedia data, and the first operator includes a cosine operator. Specifically, the compression process includes:

[0093] (1) Divide the multimedia data into multiple blocks;

[0094] (2) Perform discrete cosine transform on each block; in the discrete cosine transform of each block, generate respective first operation instructions for each block, and determine the frequency coefficients of each block based on the respective operation results of the respective first operation instructions of each block;

[0095] (3) Quantize the frequency coefficients of each block;

[0096] (4) Encode the quantized frequency coefficients of each block based on the entropy coding method.

[0097] It can be seen that based on the operation result of the first operation instruction according to the embodiment of the present invention, the accuracy of the frequency coefficients of each block is improved, thereby improving the compression efficiency of multimedia data, which helps to reduce the storage pressure and transmission bandwidth requirements.

[0098] (3) Applied to the image rendering of image data.

[0099] Image rendering is the process of converting three-dimensional light energy transfer processing into a two-dimensional image. Before image rendering, determine the three-dimensional geometric model, three-dimensional animation definition, and material information in advance. The three-dimensional geometric model is obtained through three-dimensional scanning, three-dimensional interactive geometric modeling, and three-dimensional model libraries; the three-dimensional animation definition is obtained through motion design, motion capture, motion calculation, and dynamic deformation: the material information can be obtained from scanned photos, computer images, or drawings drawn by people. In image rendering, an image is generated through geometric transformation, projection transformation, perspective transformation, window clipping, and the obtained material and light and shadow information. After image rendering, the image information can be output to an image file or a video file, or to the frame buffer of a display device to complete graphics generation.

[0100] A large amount of data operations are involved in image rendering, including reciprocal operations, root mean square operations, reciprocal root mean square operations, logarithmic operations, exponential operations, and so on. Based on the operation result of the first operation instruction according to the embodiment of the present invention, the operation accuracy of image rendering can be improved, thereby improving the quality of image rendering.

[0101] In one embodiment, the multimedia data includes image data; the first operation instruction is generated during the process of performing image rendering on the image data, where the first operator includes at least one of the following: reciprocal operator; root mean square operator; reciprocal root mean square operator; logarithmic operator; exponential operator.

[0102] The above exemplary description shows the typical applications of the optimized SFU unit in multimedia data. Those skilled in the art can realize that the above description is only exemplary and is not used to limit the protection scope of the embodiments of the present invention. For example, the optimized SFU unit can also be applied to the feature extraction of multimedia data. During the feature extraction process, based on the optimized SFU unit to calculate features such as the frequency and phase of multimedia data, by providing efficient mathematical operation capabilities, the feature extraction process is accelerated, and the speed and efficiency of data processing are improved.

[0103] Figure 1 The method shown can be executed by a micro control unit (such as, MPU) included in a chip, or can be executed by a control unit independent of the chip. The chip can be implemented as a processor chip, a memory chip, an analog chip, a mixed signal chip, an application specific integrated circuit chip, and so on. Among them, the processor can include a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose computing on graphics processing unit (GPGPU), or a microcontroller unit (MCU), and so on.

[0104] Figure 2 It is an exemplary flowchart for optimizing the SFU in the Newton iteration manner according to the embodiment of the present invention.

[0105] As Figure 2 shown, the process of optimizing the SFU in the Newton iteration manner includes:

[0106] Step 201: Input a first operation instruction indicating to perform an operation on multimedia data into the SFU in the chip. The first operation instruction includes a first operator supported by the SFU. Thus, the SFU executes the first operation instruction based on the operation ability corresponding to the first operator to obtain an original operation result.

[0107] Step 202: Set the iteration count i, and the initial value of i is 1.

[0108] Step 203: Determine whether the stop iteration condition is reached. If so, execute Step 206; otherwise, execute Step 204 and its subsequent steps. For example, the stop iteration condition may include: reaching a predetermined number of iterations or the difference between two adjacent calculation results being less than a predetermined threshold, and so on.

[0109] Step 204: Update the calculation result x according to the Newton iteration formula n+1 .

[0110] Step 205: Increment the iteration count i by 1 and return to execute Step 203.

[0111] Step 206: Output the calculation result x n+1 .

[0112] Assume that the first operation instruction indicates to calculate The iteration formula is: x n+1 =(x n +a / x n ) / 2. A low-precision result can be obtained using the original operation result of the SFU as the initial value x0, and then the high-precision calculation result can be obtained by repeatedly iterating through the iteration formula x n+1 =(x n +a / x n ) / 2.

[0113] Table 2 describes the process of solving by the Newton iteration method.

[0114]

[0115] Table 2

[0116] As shown in Table 2, an iterative process for improving the square root calculation precision of the SFU is given. It can be found that the error rapidly decreases as the number of iterations increases, effectively improving the calculation precision of the SFU for special mathematical calculations.

[0117] Based on the above description, an embodiment of the present invention also proposes a chip. Figure 3 It is a structural schematic diagram of the chip according to the embodiment of the present invention.

[0118] As Figure 3As shown in the figure, the chip includes: an SFU; a controller configured to input a first operation instruction indicating to perform an operation on multimedia data into the SFU, the first operation instruction including a first operator supported by the SFU; receive the original operation result of the SFU executing the first operation instruction, where the SFU executes the first operation instruction based on the operation ability corresponding to the first operator; determine an iteration method; an iteration circuit configured to determine an iteration result with the original operation result as the iteration initial value based on the iteration method; and the controller is further configured to determine the iteration result as the operation result of the first operation instruction. Preferably, the chip may be implemented as a GPU chip or a GPGPU chip.

[0119] In the specific implementation of the above chip, the iteration circuit in Figure 3 can be implemented based on various circuit structures. The design key points of the iteration circuit may include: (1) implementing the iteration method with a serial computing circuit; (2) for the serial computing circuit, extracting the registers and combinational logic in the circuit timing logic, where the extracted registers are used as the storage part and the combinational logic is used as the computing part; (3) representing the serial computing circuit in the form of an iteration function and an output function; (4) compressing the computing amount that requires multiple clocks to execute in the serial computing circuit into 1 clock for execution to obtain a parallel computing iteration formula; (5) describing the parallel computing iteration formula using a design language such as FPGA; (6) generating a parallel computing circuit of the FPGA according to the described parallel computing iteration formula.

[0120] The above is an exemplary description of the implementation Figure 3 of a typical example of the iteration circuit in

[0121] Figure 4 This is an exemplary structural diagram of an optimization device for the SFU of an embodiment of the present invention. As Figure 4 shown, the optimization device 300 of the SFU includes: an input module 301 configured to input a first operation instruction indicating to perform an operation on multimedia data into the SFU 400 in the chip, the first operation instruction including a first operation supported by the SFU 400; a receiving module 302 configured to receive the original operation result of the SFU executing the first operation instruction, where the SFU 400 executes the first operation instruction based on the operation ability corresponding to the first operator; a first determination module 303 configured to determine an iteration method; a second determination module 304 configured to determine an iteration result with the original operation result as the iteration initial value based on the iteration method; and a third determination module 305 configured to determine the iteration result as the operation result of the first operation instruction.

[0122] In one embodiment, a first determination module 303 is configured to determine an iterative formula, where the iterative formula includes a second operator supported by the SFU; a second determination module 304 is configured to input, in each iteration process, a second operation instruction including the second operator into the SFU and receive, from the SFU, an operation result of executing the second operation instruction, where the SFU executes the second operation instruction based on an operation capability corresponding to the second operator.

[0123] In one embodiment, a first determination module 303 is configured to display a plurality of candidate iterative methods in a user display interface; and in response to a selection operation triggered in the user display interface, select an iterative formula from the plurality of candidate iterative methods.

[0124] In one embodiment, a first operation instruction is generated during a process of performing regularization processing on an activation tensor of multimedia data to obtain a regularized activation tensor of the multimedia data, where the first operator includes a square root operator and / or a division operator; an iterative result includes an iterative result of a square root operation and / or an iterative result of a division operation, where the iterative result of the square root operation is used to determine a standard deviation in the regularization processing, and the iterative result of the division operation is used to determine a data scale transformation in the regularization processing.

[0125] In one embodiment, a first operation instruction is generated during a process of performing compression on multimedia data, where the first operator includes a cosine operator; the compression process includes: splitting the multimedia data into a plurality of blocks; performing a discrete cosine transform on each block; where in the discrete cosine transform of each block, a respective first operation instruction is generated for each block, and based on respective operation results of the respective first operation instructions of each block, frequency coefficients of each block are determined; quantifying the frequency coefficients of each block; and encoding the quantized frequency coefficients of each block based on an entropy coding method.

[0126] In one embodiment, the multimedia data includes image data; a first operation instruction is generated during a process of performing image rendering on the image data, where the first operator includes at least one of the following: a reciprocal operator; a root mean square operator; a reciprocal root mean square operator; a logarithm operator; an exponential operator; and the like.

[0127] In summary, in the embodiments of the present invention, a first arithmetic instruction indicating to perform an operation on multimedia data is input into the SFU in the chip. The first arithmetic instruction includes a first operator supported by the SFU. The original arithmetic result of the SFU executing the first arithmetic instruction is received, where the SFU executes the first arithmetic instruction based on the arithmetic ability corresponding to the first operator. An iteration method is determined. Based on the iteration method, an iteration result with the original arithmetic result as the iteration initial value is determined. The iteration result is determined as the arithmetic result of the first arithmetic instruction. It can be seen that in the embodiments of the present invention, the original arithmetic result of the SFU is not directly used as the final arithmetic result of the multimedia data, but is used as the iteration initial value to improve the data accuracy in the multimedia data operation by using the iteration process, thereby achieving the optimization of the SFU. In addition, the arithmetic result with improved accuracy can be applied to many types of multimedia applications such as image rendering and multimedia data compression, thereby enhancing the media effect of the multimedia application.

[0128] Embodiments of the present invention also propose an electronic device having a processor-memory architecture. Figure 5 is a structural diagram of an electronic device according to an embodiment of the present invention. As Figure 5 shown, the electronic device includes a processor 501, a memory 502, and a computer program stored on the memory 502 and executable on the processor 501. When the computer program is executed by the processor 501, it implements the optimization method of the SFU as described above. Among them, the memory 502 can be specifically implemented as various storage media such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, and a programmable read-only memory (PROM). The processor 501 can be implemented as including one or more central processing units or one or more field programmable gate arrays, where the field programmable gate array integrates one or more central processing unit cores. Specifically, the central processing unit or the central processing unit core can be implemented as a CPU, a GPU, a GPGPU, an MCU, or a DSP, and so on.

[0129] It should be noted that not all steps and modules in the above-mentioned processes and structural diagrams are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted according to needs. The division of each module is only for the convenience of description by a functional division. In actual implementation, one module can be implemented by multiple modules, and the functions of multiple modules can also be implemented by the same module. These modules can be located in the same device or in different devices.

[0130] The hardware modules in each embodiment can be implemented mechanically or electronically. For example, a hardware module can include specially designed permanent circuits or logic devices (such as dedicated processors, such as FPGAs or ASICs) for performing specific operations. For instance, specific operations can be completed in various types of chips (e.g., artificial intelligence chips). A hardware module can also include programmable logic devices or circuits (such as including general-purpose processors or other programmable processors) temporarily configured by software for executing specific operations. As for whether to specifically adopt a mechanical approach, or use dedicated permanent circuits, or use temporarily configured circuits (such as configured by software) to implement the hardware module, it can be determined based on cost and time considerations.

[0131] The present invention also provides a machine-readable storage medium storing instructions for causing a machine to execute the method as described in this application. Specifically, a system or device equipped with a storage medium can be provided, on which software program codes for implementing the functions of any one of the above embodiments are stored, and the computer (or CPU or MPU) of the system or device is caused to read and execute the program codes stored in the storage medium. In addition, part or all of the actual operations can also be completed by an operating system or the like operating on the computer based on the instructions of the program codes. The program codes read from the storage medium can also be written into the memory provided in an expansion board inserted into the computer or into the memory provided in an expansion unit connected to the computer, and then based on the instructions of the program codes, the CPUs or the like installed on the expansion board or the expansion unit are caused to execute part and all of the actual operations, thereby implementing the functions of any one of the above embodiments. Embodiments of the storage medium for providing program codes include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Optionally, the program codes can be downloaded from a server computer or the cloud via a communication network.

[0132] In this document, "schematic" means "serving as an example, instance, or illustration", and any diagram or embodiment described as "schematic" in this document should not be construed as a more preferred or advantageous technical solution. To simplify the drawings, only the parts relevant to the present invention are schematically shown in each figure, and do not represent the actual structure of the product. Additionally, to simplify the drawings for better understanding, in some figures, only one of the components with the same structure or function is schematically depicted, or only one of them is labeled. In this document, "a" does not limit the quantity of the parts relevant to the present invention to "only one", and "a" does not exclude the situation where the quantity of the parts relevant to the present invention is "more than one". In this document, "up", "down", "front", "back", "left", "right", "inside", "outside", etc. are only used to represent the relative positional relationship between relevant parts, rather than defining the absolute positions of these relevant parts.

[0133] The above are only the preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An optimization method for a special function unit, characterized in that The method is executed by a micro control unit included in a chip or by a control unit independent of the chip, and the method includes: Input a first operation instruction indicating an operation on multimedia data into a special function unit in the chip, where the first operation instruction includes a first operator supported by the special function unit; Receive the original operation result of the special function unit executing the first operation instruction, where the special function unit executes the first operation instruction based on the operation ability corresponding to the first operator; Determine an iteration method; Based on the iteration method, determine an iteration result with the original operation result as the iteration initial value; Determine the iteration result as the operation result of the first operation instruction; The determining the iteration method includes determining an iteration formula, and the iteration formula includes a second operator supported by the special function unit; the determining, based on the iteration method, an iteration result with the original operation result as the iteration initial value includes: in each iteration process, input a second operation instruction including the second operator into the special function unit and receive from the special function unit the operation result of executing the second operation instruction, where the special function unit executes the second operation instruction based on the operation ability corresponding to the second operator.

2. The method according to claim 1, wherein The determining the iteration method includes: Display multiple candidate iteration methods in a user display interface; In response to a selection operation triggered in the user display interface, select the iteration formula from the multiple candidate iteration methods.

3. The method according to any one of claims 1-2, wherein The first operation instruction is generated during the process of performing regularization processing on the activation tensor of the multimedia data to obtain the regularized activation tensor of the multimedia data, where the first operator includes a square root operator and / or a division operator; the iteration result includes the iteration result of a square root operation and / or the iteration result of a division operation, where the iteration result of the square root operation is used to determine the standard deviation in the regularization processing, and the iteration result of the division operation is used to determine the data scale transformation in the regularization processing.

4. The method according to any one of claims 1-2, characterized in that, The first operation instruction is generated during the process of performing compression on the multimedia data, where the first operator includes a cosine operator; The compression process includes: Divide the multimedia data into multiple blocks; Perform discrete cosine transform on each block; where in the discrete cosine transform of each block, generate respective first operation instructions for each block, and based on the respective operation results of the respective first operation instructions of each block, determine the frequency coefficients of each block; Quantize the frequency coefficients of each block; Encode the quantized frequency coefficients of each block based on an entropy coding method.

5. The method according to any one of claims 1-2, characterized in that, The multimedia data includes image data; the first operation instruction is generated during the process of performing image rendering on the image data, where the first operator includes at least one of the following: Reciprocal operator; root mean square operator; reciprocal root mean square operator; logarithm operator; exponential operator.

6. An optimization device for a special function unit, characterized in that The device is applicable to a micro control unit included in a chip or a control unit independent of the chip, and the device includes: An input module, configured to input a first operation instruction indicating an operation on multimedia data into a special function unit in the chip, where the first operation instruction includes a first operator supported by the special function unit; A receiving module, configured to receive an original operation result of the special function unit executing the first operation instruction, where the special function unit executes the first operation instruction based on an operation capability corresponding to the first operator; A first determination module, configured to determine an iteration mode; A second determination module, configured to determine an iteration result with the original operation result as an iteration initial value based on the iteration mode; A third determination module, configured to determine the iteration result as an operation result of the first operation instruction; The determination of the iteration mode includes determining an iteration formula, where the iteration formula includes a second operator supported by the special function unit; the determination of the iteration result with the original operation result as an iteration initial value based on the iteration mode includes: in each iteration process, inputting a second operation instruction including the second operator into the special function unit and receiving an operation result of the special function unit executing the second operation instruction, where the special function unit executes the second operation instruction based on an operation capability corresponding to the second operator.

7. A chip, characterized in that, Including: A special function unit; A controller, configured to input a first operation instruction indicating an operation on multimedia data into the special function unit, where the first operation instruction includes a first operator supported by the special function unit; receive an original operation result of the special function unit executing the first operation instruction, where the special function unit executes the first operation instruction based on an operation capability corresponding to the first operator; determine an iteration mode; An iteration circuit, configured to determine an iteration result with the original operation result as an iteration initial value based on the iteration mode; The controller is further configured to determine the iteration result as an operation result of the first operation instruction; The determination of the iteration mode includes determining an iteration formula, where the iteration formula includes a second operator supported by the special function unit; the determination of the iteration result with the original operation result as an iteration initial value based on the iteration mode includes: in each iteration process, inputting a second operation instruction including the second operator into the special function unit and receiving an operation result of the special function unit executing the second operation instruction, where the special function unit executes the second operation instruction based on an operation capability corresponding to the second operator.

8. An electronic device, characterized in that, Including: A memory; A processor; Wherein an application program executable by the processor is stored in the memory, and is configured to enable the processor to execute an optimization method of the special function unit according to any one of claims 1-5.

9. A computer-readable storage medium, characterized in that, Computer-readable instructions are stored on the computer-readable storage medium, and when the computer-readable instructions are executed by a processor, the processor is caused to execute the optimization method of the special functional unit as described in any one of claims 1-5.

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