Display device and its driving method

Abstract

This application provides a display device and its driving method. The display device includes a display panel and a control circuit. The display panel includes N regions divided along a scanning direction, each region including multiple pixel units, where N is an integer greater than 1. The control circuit generates a ramp signal and inputs the ramp signal to the multiple pixel units, and sequentially controls the pixel units in each of the N regions to perform data writing and light emission within a driving cycle of one frame. The ramp signal includes N pulse cycles within a driving cycle of one frame. The driving cycle of each pixel unit includes a data writing sub-cycle and a light emission sub-cycle, with the data writing sub-cycle preceding the light emission sub-cycle. The data writing sub-cycle includes one pulse cycle of the ramp signal, and the light emission sub-cycle includes N-1 pulse cycles of the ramp signal. The display device and its driving method provided by this application can solve the technical problem of limited brightness adjustment range in existing display devices.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] Micro LED display technology mainly uses two circuit architectures: pulse width modulation (PWM) and pulse amplitude modulation (PAM), each with its own advantages and disadvantages. The corresponding light emission methods are global illumination and progressive illumination.

[0003] In global illumination schemes, the entire display panel emits light simultaneously after data is written, resulting in high instantaneous current. This is particularly noticeable in PWM circuit architectures, where high instantaneous current is generated at different gray levels. This negatively impacts the display panel's power consumption and internal voltage drop (IR drop).

[0004] On the other hand, micro-LED display technology also needs to be compatible with both ultra-high brightness and ultra-low brightness requirements, which requires the emission time to be adjusted within a wider range.

[0005] Traditional PWM driving methods struggle to simultaneously meet the demands of low power consumption and a wide brightness range. While simple progressive illumination can reduce instantaneous current, it requires feeding ramp signals line by line and shifting them line by line, increasing circuit complexity and cost.

[0006] Therefore, how to achieve a wider brightness adjustment range in micro-LED display technology while reducing power consumption, improving grayscale accuracy, and mitigating flicker has become a pressing technical problem that needs to be solved. Summary of the Invention

[0007] Embodiments of this application provide a display device and its driving method, which aim to solve the technical problem of limited brightness adjustment range in existing display devices.

[0008] An embodiment of this application provides a display device, comprising: a display panel, the display panel including N regions divided along a scanning direction, each region including a plurality of pixel units, where N is an integer greater than 1; and a control circuit electrically connected to the plurality of pixel units, the control circuit being configured to generate a ramp signal and input the ramp signal to the plurality of pixel units, and to sequentially control the pixel units in each of the N regions to perform data writing and light emission within a driving cycle of a frame; wherein the ramp signal includes N pulse cycles within a driving cycle of a frame, the driving cycle of the pixel unit in each region includes a data writing sub-cycle and a light emission sub-cycle, the data writing sub-cycle precedes the light emission sub-cycle, the data writing sub-cycle includes one pulse cycle of the ramp signal, and the light emission sub-cycle includes N-1 pulse cycles of the ramp signal.

[0009] Embodiments of this application also provide a driving method for a display device. The display panel of the display device includes N regions divided along a scanning direction, each region including multiple pixel units, where N is an integer greater than 1. The driving method includes: generating a ramp signal, the ramp signal including N pulse cycles within a driving cycle of one frame; inputting the ramp signal to the multiple pixel units; and sequentially controlling the pixel units in each of the N regions to perform data writing and light emission within a driving cycle of one frame. The driving cycle of the pixel unit in each region includes a data writing sub-cycle and a light emission sub-cycle, the data writing sub-cycle preceding the light emission sub-cycle, the data writing sub-cycle including one pulse cycle of the ramp signal, and the light emission sub-cycle including N-1 pulse cycles of the ramp signal.

[0010] The embodiments of this application employ a pulse width modulation driving method combining a global ramp signal and multiple pulses to achieve progressive light emission, effectively solving the technical problems of limited brightness adjustment range, high power consumption, insufficient grayscale accuracy, and obvious flickering in the prior art. Specifically, the embodiments of this application use a global ramp signal to ensure that all pixel units receive the same ramp signal, improving display consistency. In addition, the embodiments of this application introduce multi-pulse light emission technology. Within the driving cycle of one frame, the ramp signal contains multiple pulse cycles, allowing pixel units in each area to emit light multiple times, expanding the brightness adjustment range. Especially in low grayscale display, it can effectively improve flickering. By adjusting the number of pulses and the emission time of each pulse, the emission duty cycle can be flexibly controlled to meet a wide range of display needs from ultra-low brightness to ultra-high brightness. Furthermore, the embodiments of this application use a progressive light emission method, dividing the display panel into multiple areas. The pixel units in each area sequentially complete data writing and multiple emission within the driving cycle of one frame, which not only improves the display effect but also significantly reduces instantaneous current, effectively solving the high power consumption problem. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0012] Figure 2 This is a schematic diagram of the area division of the display device provided in the embodiments of this application.

[0013] Figure 3 This is a circuit diagram of the pixel unit of a display device provided in an embodiment of this application.

[0014] Figure 4 yes Figure 3 The waveforms of each signal in the display device are shown. Detailed Implementation

[0015] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0016] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0017] The embodiments of this application can be combined with each other.

[0018] like Figure 1As shown, the display device provided in the embodiments of this application may be, for example, a Micro-LED display device. Of course, the display device may also be a Mini-LED display device or an OLED display device. The embodiments of this application are described using a Micro-LED display device.

[0019] The display device includes a source drive circuit, a gate drive circuit, a timing controller, a light-emitting controller, a power management chip, a substrate, data lines (DATA), scan lines (SCAN), power lines (VDD, VSS), light-emitting control signal lines (EM), a pixel array, a packaging layer, a polarizer, and a color filter.

[0020] The substrate can be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The pixel array is composed of multiple pixel units PX arranged in rows and columns. Each pixel unit PX includes a light-emitting device and a driving circuit. The driving circuit includes TFT devices, which control the brightness of each light-emitting device in the display device. TFT devices include low-temperature polycrystalline silicon (LTPS) and metal oxide TFTs. The light-emitting devices are electrically connected to the driving circuit and include a light-emitting layer, an electron transport layer, a hole transport layer, a cathode, and an anode. Each gate driving unit in the gate driving circuit controls a row of pixel units PX, enabling the selection of pixel units PX. Each gate driving unit consists of a thin-film transistor (TFT) and a capacitor. The source driving circuit provides data signals to the pixel units PX. The timing controller receives externally input image data and synchronization signals, generating the signals required by the gate driving circuit and the source driving circuit. The power management chip provides the necessary operating voltage to various parts of the display device.

[0021] In addition, the display device of this application can also integrate an embedded touch circuit, which is electrically connected to the display driving circuit, and uses time-division multiplexing to realize touch function and display function.

[0022] Embodiments of this application provide a display device and a driving method thereof. The display device includes a display panel and a control circuit. Figure 2 As shown, the display panel includes N regions (R1~RN) divided along the scanning direction SD. Each region includes multiple pixel units PX, where N is an integer greater than 1. The control circuit is electrically connected to the multiple pixel units PX and is used to generate a ramp signal Sweep and input the ramp signal Sweep to the multiple pixel units PX. It is also used to sequentially control the pixel units PX in each of the N regions (R1~RN) to perform data writing and light emission within the driving cycle of one frame.

[0023] The sweep signal in the display device and driving method provided in the embodiments of this application is a global multi-pulse signal. "Global" means that one sweep signal is provided to all pixel units PX of the entire display panel, that is, the output terminal of one sweep signal is electrically connected to all pixel units PX of the entire display panel. "Multi-pulse" means that the sweep signal has multiple pulse cycles within the driving cycle of one frame. In the embodiments of this application, the number of pulse cycles is the same as the number of areas of the display panel.

[0024] The display device and driving method provided in the embodiments of this application include a sweep signal Sweep that comprises N pulse cycles within the driving cycle of a frame. The driving cycle of each pixel unit PX in each region includes a data writing sub-cycle and a light emission sub-cycle. The data writing sub-cycle precedes the light emission sub-cycle. The data writing sub-cycle includes one pulse cycle of the sweep signal Sweep, and the light emission sub-cycle includes N-1 pulse cycles of the sweep signal Sweep.

[0025] The display panel is divided into N regions (R1~RN) from top to bottom (along the scanning direction SD). After the pixel unit PX in each region finishes writing data, it enters the light-emitting stage. Because it incorporates a multi-pulse ramp signal Sweep, the pixel unit PX needs to be continuously restarted. Therefore, the pixel unit PX is reset once during the pulse cycle of each light-emitting stage to ensure that the pixel unit PX compares the ramp signal Sweep with the data signal within that pulse cycle before emitting light.

[0026] like Figure 3 and Figure 4 As shown, the pixel unit PX in the display device provided in the embodiments of this application includes a light-emitting device 204 and a driving circuit. The driving circuit includes a pulse width modulation module 201, a pulse amplitude modulation module 203, and a reset module 202. The pulse width modulation module 201 is electrically connected to the reset module 202, the reset module 202 is electrically connected to the pulse amplitude modulation module 203, and the pulse amplitude modulation module 203 is electrically connected to the light-emitting device 204.

[0027] The control circuit generates a sweeping signal (Sweep), a first reset control signal, and a light emission control signal. The first reset control signal is used to control the reset module 202 in the pixel unit PX to reset, and the light emission control signal is used to control the pixel unit PX to emit light.

[0028] In the embodiments of this application, each of the N regions (R1~RN) includes M rows of pixel units PX, where M is an integer greater than 1. During the data writing phase of the data writing sub-cycle, the control circuit provides M scan signals to the M rows of pixel units PX of each region.

[0029] Specifically, the scan signal for the Kth region (K is greater than or equal to 1 and less than or equal to N) is denoted as S(K). The first region has M scan signals, namely S1~SM, the second region has M scan signals, namely SM+1~S2M, and the Nth region has M scan signals, namely S(N-1)*M+1~SN*M.

[0030] In the embodiments of this application, the data write sub-cycle includes a pulse cycle, and the data write sub-cycle includes a first reset phase and a data write phase, with each first reset phase followed immediately by a data write phase.

[0031] In the first reset phase, the control circuit inputs a first reset control signal RST to the reset module 202 of the pixel unit PX. The light emission control signal EM(K) is a high-level signal, which turns off the first transistor T1, the sixth transistor T6, and the fourteenth transistor T14 in the pulse width modulation module 201 and the pulse amplitude modulation module 203. At the same time, the second reset control signal EMi(K) is a low-level signal, which turns on the fifth transistor T5 and the thirteenth transistor T13, and writes the low-level signal Vss to the first node A and the fifth node E, resetting the potential of these nodes.

[0032] During the data writing phase, the scan signal S(K) sequentially changes to a low level signal, which turns on the second transistor T2, the third transistor T3, the tenth transistor T10, and the eleventh transistor T11, and the data signals (including the first data signal Data_PWM(K) and the second data signal Data_PAM(K)) are written into the pixel unit PX.

[0033] In the embodiments of this application, the light-emitting sub-cycle includes multiple pulse cycles. Specifically, the light-emitting sub-cycle includes N-1 second reset phases and N-1 light-emitting phases, with each second reset phase followed by a light-emitting phase.

[0034] In the second reset phase, the control circuit inputs a first reset control signal RST to the reset module 202 of the pixel unit PX. Specifically, the first reset control signal RST is a low-level signal, which turns on the eighth transistor T8 and the ninth transistor T9 in the reset module 202, and the reset voltage is written to the third node C and the fourth node D. At the same time, the light emission control signal EM(K) is a low-level signal, which turns on the first transistor T1, the sixth transistor T6, and the fourteenth transistor T14 in the pulse width modulation module 201 and the pulse amplitude modulation module 203, and the slope signal Sweep is a high-level signal, with the high potential coupled to the first node A.

[0035] During the light-emitting stage, the control circuit inputs a slope signal Sweep and data signals (including the first data signal Data_PWM(K) and the second data signal Data_PAM(K)) to the pulse width modulation module 201 and pulse amplitude modulation module 203 of the pixel unit PX, so that the pixel unit PX controls the light-emitting device 204 to emit light according to the slope signal Sweep and the data signals. Specifically, as the potential of the slope signal Sweep decreases, the potential of the first node A gradually decreases until the fourth transistor T4 turns on, the fourth node D is pulled down to the Vdd potential, and at the same time the third node C is coupled to the seventh transistor T7 to turn on. The seventh transistor T7, the twelfth transistor T12, and the fourteenth transistor T14 on the light-emitting channel are all turned on, and the light-emitting device 204 begins to emit light.

[0036] By using this multi-pulse emission method, the display device of the present application can emit light multiple times within the driving cycle of a single frame, thereby improving the display effect. In particular, it can effectively reduce flickering when displaying low grayscale levels and achieve a wide range of controllable emission duty cycle.

[0037] like Figure 4 As shown, the driving cycle of the pixel unit PX in the Kth region includes phase 1, phase 2, phase 3, phase 4, phase 5, phase 6, etc.

[0038] In the driving cycle of the pixel unit PX in the Kth region, a data writing operation is performed first, followed by a light emission operation. The data writing operation includes a first reset phase (phase 1) and a data writing phase (phase 2). The light emission operation includes a second reset phase (phase 3, phase 5, phase 7) and a light emission phase (phase 4, phase 6, phase 8).

[0039] Phase 1: Entering the first reset phase in the data writing sub-cycle, multiple scan signals S(K) input to the Kth region are all high-level signals, the global slope signal Sweep is a high-level signal, the first reset control signal RST is a low-level signal, the light emission control signal EM(K) is a high-level signal, and the second reset control signal EMi(K) is a low-level signal. In the first reset phase, for the pulse width modulation module 201 and pulse amplitude modulation module 203, the light emission control signal EM(K) for this area is a high-level signal, and the first transistor T1, the sixth transistor T6, and the fourteenth transistor T14 are turned off. The second reset control signal EMi(K) is a low-level signal, and the fifth transistor T5 and the thirteenth transistor T13 are turned on. The low-level signal Vss is written to the first node A and the fifth node E, resetting the potentials of the first node A and the fifth node E. The fourth transistor T4 and the twelfth transistor T12 are turned on to ensure that the threshold voltage Vth is compensated for in all rows of pixel units PX in this area when data signals are written. The fourth transistor T4 uses Vdd to compensate for the threshold voltage Vth, and the twelfth transistor T12 uses the data signal (the second data signal Data_PAM(K)) to compensate for the threshold voltage Vth. The second reset control signal EMi(K) is the reset control signal for one frame.

[0040] In the reset module 202, the global first reset control signal RST is a low-level signal (the first reset control signal RST is a reset control signal corresponding to one pulse cycle; the global first reset control signal RST means that the first reset control signal input terminal is electrically connected to all pixel units PX of the entire display panel, and one first reset control signal RST is provided to all pixel units PX of the entire display panel). The eighth transistor T8 and the ninth transistor T9 are turned on, and the third node C and the fourth node D are respectively written with the first reset signal Vref and the second reset signal VH (the first reset signal Vref can be, for example, a high potential voltage, and the second reset signal VH can be a high potential voltage or a low potential voltage. When the fourth transistor T4 and the sixth transistor T6 are turned on, the voltage of the third node C is equal to Vref + Vdd - VH). The first reset signal Vref is used to turn off the seventh transistor T7.

[0041] Phase 2: Entering the data writing phase, the Sweep signal is a linearly decreasing signal, the first reset control signal RST is a high-level signal, the second reset control signal EMi(K) is a high-level signal, and the light emission control signal EM(K) is a high-level signal. Multiple scan signals S(K) sequentially input to the multi-row pixel units PX in the Kth region are low-level signals. The second transistor T2, third transistor T3, tenth transistor T10, and eleventh transistor T11 are turned on. The second reset control signal EMi(K) is high-level, the fifth transistor T5 and thirteenth transistor T13 are turned off, and the fourth transistor T4 and twelfth transistor T12 are both turned on. The first node A and the fifth node E sequentially write data to compensate for the threshold voltage Vth of the fourth transistor T4 and the twelfth transistor T12 until all rows of pixel units PX in that region have been written. In both phase 1 and phase 2, the light emission control signal EM(K) is a high-level signal. Since the first transistor T1 is turned off by the light emission control signal EM(K), the slope signal Sweep is not used to compare with the data signal (the first data signal Data_PWM(K)) during the period of this pulse (phase 1 and phase 2).

[0042] Phase 3: Entering the second reset phase of the light-emitting sub-cycle, multiple scan signals S(K) sequentially input to the multi-row pixel unit PX in the Kth region are all high-level signals. The second reset control signal EMi(K) is high-level, the first reset control signal RST is low-level, the slope signal Sweep is high-level, and the light-emitting control signal EM(K) is low-level. The first transistor T1, the sixth transistor T6, and the fourteenth transistor T14 are all turned on. The global slope signal Sweep is high-level, the first node A is coupled to a high potential, and the fourth transistor T4 is turned off. The global first reset control signal RST is low-level, the eighth transistor T8 and the ninth transistor T9 are turned on, the potential of the second reset signal VH is written to the fourth node D, and the seventh transistor T7 is turned off. The fourth transistor T4 is turned off, and the sixth transistor T6 is turned on. In the light-emitting path, the seventh transistor T7 is turned off, and the twelfth transistor T12 and the fourteenth transistor T14 are turned on.

[0043] Stage 4: During the light-emitting phase of the light-emitting sub-cycle, multiple scan signals S(K) input to the Kth region are all high-level signals, the second reset control signal EMi(K) is high-level, the first reset control signal RST is high-level, the slope signal Sweep is a slope signal with a linearly decreasing level, and the light-emitting control signal EM(K) is low-level. As the potential of the slope signal Sweep decreases, the potential of the coupled first node A gradually decreases until the fourth transistor T4 turns on, the fourth node D is pulled down to the Vdd potential, and at the same time, the third node C is coupled to the seventh transistor T7 and turns on. The seventh transistor T7, the twelfth transistor T12, and the fourteenth transistor T14 on the light-emitting channel are all turned on, and the light-emitting device 204 begins to emit light.

[0044] Phase 5: Entering the second reset phase of the next light-emitting sub-cycle, the global first reset control signal RST is low, and the seventh transistor T7 is turned off. Light-emitting device 204 stops emitting light, and simultaneously, the potentials of the third node C and the fourth node D are reset, and the ramp signal Sweep jumps to a high potential. The first node A is coupled to a high potential, and the fourth transistor T4 is turned off. In Phase 5, the levels (potentials) of each signal are the same as those in Phase 3.

[0045] Phase 6: The light-emitting phase of the next light-emitting sub-cycle begins. As the potential of the slope signal Sweep decreases, the fourth transistor T4 is turned on again, followed by the seventh transistor T7, and the light-emitting device 204 emits light again. In Phase 6, the levels (potentials) of each signal are the same as those of each signal in Phase 4.

[0046] Repeat the above steps to complete the multi-pulse emission.

[0047] The display device and driving method provided in this application achieve a combination of pulse width modulation, multi-pulse, and progressive light emission by employing a global multi-pulse ramp signal (Sweep). Specifically, by dividing the display panel into multiple regions, each region's pixel unit (PX) completes data writing and multiple light emission cycles within one frame's driving cycle, which not only improves the display effect but also reduces instantaneous current. Furthermore, the embodiments of this application improve low-grayscale flicker performance and achieve a wide range of controllable light emission duty cycles. Through the multi-pulse light emission method, multiple short-duration light emission cycles can be performed during low-grayscale display, effectively improving flicker phenomena.

[0048] Table 1

[0049]

[0050] As shown in Table 1 above, the operating states of multiple transistors (T1-T14) and multiple nodes (A, B, C, D, E) in the driving circuit at different stages are as follows:

[0051] Phase 1 (First reset phase before data writing): T1 / T6 / T14, T2 / T3 / T10 / T11 are off, T4, T5 / T13, T8 / T9, T12 are on; the voltage of node A is VSS, the voltage of node B is Sweep_H, the voltage of node C is Vref, the voltage of node D is VH, and the voltage of node E is Vss.

[0052] Phase 2 (Data Writing Phase): T1 / T6 / T14 are off, T2 / T3 / T10 / T11, T4, and T12 are on, and T5 / T13, T7, T8 / T9 are off; the voltage of node A is Vdd+Vth1, the voltage of node B is Data_PWM, the voltage of node C is Vref, the voltage of node D is VH, and the voltage of node E is Data_PAM+Vth2.

[0053] Phase 3 (Second Reset Phase): T1 / T6 / T14, T8 / T9, and T12 are turned on, while other transistors are turned off; the voltage at node A is Vdd + Vth1 + Sweep_H - Data_PWM, the voltage at node B is Sweep_H, the voltage at node C is Vref, the voltage at node D is VH, and the voltage at node E is Data_PAM + Vth2.

[0054] Phase 4 (Light Emission Phase): T1 / T6 / T14 and T12 remain on, T4 and T7 change from off to on, and other transistors are off; the voltage at node A changes from Vdd+Vth1+Sweep_H-Data_PWM to Vdd+Vth1+Sweep(t)-Data_PWM, the voltage at node B is Sweep(t), the voltage at node C changes from Vref to Vref+vdd-VH, the voltage at node D changes from VH to Vdd, and the voltage at node E remains at Data_PAM+Vth2.

[0055] Phase 5 (Next Reset Phase): Similar to Phase 3.

[0056] Phase 6 (Next Lighting Phase): Similar to Phase 4.

[0057] Within the driving cycle of one frame, these six stages are performed sequentially, realizing the processes of reset, data writing, and multiple emission. After completing the data writing, the pixel unit PX in each region emits light multiple times, thereby improving the display effect.

[0058] By employing a global multi-pulse sweep signal, each pixel unit PX of the display panel completes data writing and multiple emission within a frame's driving cycle. This enables the display device of the present application to emit light multiple times within a frame's driving cycle, thereby improving the display effect and reducing instantaneous current. Especially in low grayscale display, it can effectively improve flickering and achieve a wide range of controllable emission duty cycle.

[0059] Embodiments of this application provide a display device, including a display panel and a control circuit. The display panel is electrically connected to the control circuit. The control circuit may include a source drive circuit, a gate drive circuit, a timing controller, a light-emitting controller, and a power management chip.

[0060] like Figure 2 As shown, the display panel includes N regions (R1~RN) divided along the scanning direction SD, and each region includes multiple pixel units PX, where N is an integer greater than 1.

[0061] The control circuit is electrically connected to multiple pixel units PX. The control circuit is used to generate a ramp signal Sweep and input the ramp signal Sweep to multiple pixel units PX. It is also used to sequentially control the pixel units PX in each of N regions (R1~RN) to write data and emit light within the driving cycle of one frame.

[0062] The sweep signal Sweep consists of N pulse cycles within the driving cycle of one frame. The driving cycle of each pixel unit PX in each region includes a data writing sub-cycle and a light emission sub-cycle. The data writing sub-cycle precedes the light emission sub-cycle. The data writing sub-cycle includes one pulse cycle of the sweep signal Sweep, and the light emission sub-cycle includes N-1 pulse cycles of the sweep signal Sweep.

[0063] As an improvement, the control circuit also dynamically adjusts the number of partitions based on the complexity of the displayed content. The control circuit first analyzes the image complexity of the current frame, for example, by calculating the image's frequency components or dynamic range, and then dynamically adjusts the number of partitions N based on the analysis results. For example, for complex scenes with high dynamic range, the number of partitions is increased to improve control precision; for simple scenes with low dynamic range, the number of partitions is reduced to lower power consumption.

[0064] like Figure 3 and Figure 4 As shown, the pixel unit PX includes a light-emitting device 204 and a driving circuit. The driving circuit is electrically connected to the light-emitting device 204 and is used to control the light emission of the light-emitting device 204.

[0065] The driving circuit includes a pulse width modulation module 201, a pulse amplitude modulation module 203, and a reset module 202. The pulse width modulation module 201 is electrically connected to the reset module 202, the reset module 202 is electrically connected to the pulse amplitude modulation module 203, and the pulse amplitude modulation module 203 is electrically connected to the light-emitting device 204.

[0066] The pulse width modulation module 201 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1.

[0067] The gate of the first transistor T1 is electrically connected to the light emission control signal input terminal EM(K), one of the source and drain of the first transistor T1 is electrically connected to the slope signal input terminal Sweep, and the other of the source and drain of the first transistor T1 is electrically connected to the first node A.

[0068] The gate of the second transistor T2 is electrically connected to the scan signal input terminal S(K), one of the source and drain of the second transistor T2 is electrically connected to the first data signal input terminal Data_PWM(K), and the other of the source and drain of the second transistor T2 is electrically connected to the first node A.

[0069] One end of the first capacitor C1 is electrically connected to the first node A, and the other end of the first capacitor C1 is electrically connected to the second node B.

[0070] The gate of the third transistor T3 is electrically connected to the scan signal input terminal S(K), and one of the source and drain of the third transistor T3 is electrically connected to the second node B.

[0071] The gate of the fourth transistor T4 is electrically connected to the second node B. One of the source and drain of the fourth transistor T4 is electrically connected to the first power supply signal input terminal Vdd. The other of the source and drain of the fourth transistor T4 is electrically connected to the other of the source and drain of the third transistor T3.

[0072] The gate of the fifth transistor T5 is electrically connected to the second reset control signal input terminal EMi(K), one of the source and drain of the fifth transistor T5 is electrically connected to the second power supply signal input terminal Vss, and the other of the source and drain of the fifth transistor T5 is electrically connected to the second node B.

[0073] The gate of the sixth transistor T6 is electrically connected to the light-emitting control signal input terminal EM(K), one of the source and drain of the sixth transistor T6 is electrically connected to the drain of the fourth transistor T4, and the other of the source and drain of the sixth transistor T6 is electrically connected to the third node C of the reset module 202.

[0074] The reset module 202 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2.

[0075] The gate of the seventh transistor T7 is electrically connected to the third node C, and one of the source and drain of the seventh transistor T7 is electrically connected to the first power supply signal input terminal Vdd.

[0076] The gate of the eighth transistor T8 is electrically connected to the first reset control signal input terminal RST, one of the source and drain of the eighth transistor T8 is electrically connected to the second reset signal input terminal VH, and the other of the source and drain of the eighth transistor T8 is electrically connected to the fourth node D.

[0077] The gate of the ninth transistor T9 is electrically connected to the first reset control signal input terminal RST, one of the source and drain of the ninth transistor T9 is electrically connected to the first reset signal input terminal Vref, and the other of the source and drain of the ninth transistor T9 is electrically connected to the third node C.

[0078] One end of the second capacitor C2 is electrically connected to the third node C, and the other end of the second capacitor C2 is electrically connected to the fourth node D.

[0079] The pulse amplitude modulation module 203 includes a third capacitor C3, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

[0080] One end of the third capacitor C3 is electrically connected to the first power signal input terminal Vdd, and the other end of the third capacitor C3 is electrically connected to the fifth node E.

[0081] The gate of the tenth transistor T10 is electrically connected to the scan signal input terminal S(K), and one of the source and drain of the tenth transistor T10 is electrically connected to the fifth node E.

[0082] The gate of the eleventh transistor T11 is electrically connected to the scan signal input terminal S(K), one of the source and drain of the eleventh transistor T11 is electrically connected to the second data signal input terminal Data_PAM(K), and the other of the source and drain of the eleventh transistor T11 in the pulse amplitude modulation module 203 is electrically connected to the other of the source and drain of the seventh transistor T7.

[0083] The gate of the twelfth transistor T12 is electrically connected to the fifth node E. One of the sources and drains of the twelfth transistor T12 is electrically connected to the other of the sources and drains of the eleventh transistor T11. The other of the sources and drains of the twelfth transistor T12 is electrically connected to the other of the sources and drains of the tenth transistor T10.

[0084] The gate of the thirteenth transistor T13 is electrically connected to the second reset control signal input terminal EMi(K), one of the source and drain of the thirteenth transistor T13 is electrically connected to the second power supply signal input terminal Vss, and the other of the source and drain of the thirteenth transistor T13 is electrically connected to the fifth node E.

[0085] The gate of the fourteenth transistor T14 is electrically connected to the light-emitting control signal input terminal EM(K), one of the source and drain of the fourteenth transistor T14 is electrically connected to the drain of the twelfth transistor T12, and the other of the source and drain of the fourteenth transistor T14 is electrically connected to the anode of the light-emitting device 204.

[0086] like Figure 4 As shown, the data writing sub-cycle includes a first reset stage and a data writing stage. The control circuit is used to input a first reset control signal RST to the reset module 202 of the pixel unit PX during the first reset stage, and to write data signals (including the first data signal Data_PWM(K) and the second data signal Data_PAM(K)) to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX during the data writing stage after the first reset stage.

[0087] The light-emitting sub-cycle includes N-1 second reset stages and N-1 light-emitting stages. The control circuit is used to input a first reset control signal RST to the reset module 202 of the pixel unit PX during the second reset stage, and to input a ramp signal Sweep and a data signal to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX during the light-emitting stages after the second reset stage, so that the pixel unit PX controls the light-emitting device 204 to emit light according to the ramp signal Sweep and the data signal.

[0088] The control circuit is also used to generate a first reset control signal RST and a light emission control signal EM(K). The first reset control signal RST is used to control the reset module 202 in the pixel unit PX to reset, and the light emission control signal EM(K) is used to control the pixel unit PX to emit light.

[0089] As an improvement, the control circuit also dynamically adjusts the duration of each emission stage based on the image content of the current frame. For example, for high-brightness areas, the control circuit extends the emission time; for low-brightness areas, it shortens the emission time. The control circuit analyzes the input image data in real time, calculates the average brightness or brightness distribution of each area, and then generates emission control parameters. These emission control parameters are used to adjust the pulse width of the emission control signal EM(K), thereby dynamically adjusting the emission time.

[0090] As an improvement, the control circuit also dynamically adjusts the slopes of the rising and falling edges of the first reset control signal RST based on the current displayed content. For example, for high-contrast image areas, a steeper slope is generated for the first reset control signal RST to improve response speed; for low-contrast areas, a gentler slope is generated for the first reset control signal RST to reduce overcharging. The control circuit may include a digital-to-analog converter (DAC) and a variable current source. The DAC sets the output of the current source according to the instructions of the control circuit, thereby controlling the slope of the first reset control signal RST.

[0091] The first reset control signal RST is low during the first reset phase of the data write sub-cycle and high during the data write phase of the data write sub-cycle; the light emission control signal EM(K) is high during the data write sub-cycle and low during the light emission sub-cycle; or

[0092] The first reset control signal RST is a high-level signal during the first reset phase and a low-level signal during the data writing phase. The light emission control signal EM(K) is a low-level signal during the data writing sub-cycle and a high-level signal during the light emission sub-cycle.

[0093] The first reset control signal RST is low during the second reset phase of the light-emitting sub-cycle and high during the light-emitting phase of the light-emitting sub-cycle; the light-emitting control signal EM(K) is low during the light-emitting sub-cycle; or

[0094] The first reset control signal RST is a high-level signal during the second reset phase of the light-emitting sub-cycle and a low-level signal during the light-emitting phase of the light-emitting sub-cycle. The light-emitting control signal EM(K) is a high-level signal during the light-emitting sub-cycle.

[0095] The control circuit includes a ramp signal generation unit. The output of the ramp signal generation unit is electrically connected to multiple pixel units PX of the display panel. The ramp signal generation unit is used to generate a ramp signal Sweep and provide the ramp signal Sweep to the multiple pixel units PX.

[0096] As an improvement, the control circuit is also used to adjust the distribution and duration of each pulse of the sweep signal within the driving cycle of a frame. Specifically, the control circuit can configure more light-emitting pulses in the middle part of the frame, while reducing the number of pulses at the beginning and end of the frame.

[0097] As an improvement, the ramp signal generation unit of the control circuit includes a programmable current source. This programmable current source dynamically adjusts the slope of the ramp signal Sweep according to the brightness distribution of the currently displayed content. Specifically, the programmable current source changes its output current according to a control signal provided by the control circuit, thereby changing the charging rate of the ramp signal Sweep. For example, for high-brightness areas, a larger current is used to produce a steeper slope to improve contrast; for low-brightness areas, a smaller current is used to produce a gentler slope to improve grayscale performance. This dynamic adjustment can be performed multiple times during each frame to adapt to the brightness requirements of different areas.

[0098] Each of the N regions (R1~RN) includes M rows of pixel units PX, where M is an integer greater than 1. The control circuit is also used to provide M scan signals S(K) to the M rows of pixel units PX of each region during the data writing phase of the data writing sub-cycle.

[0099] As an improvement, the control circuit is also used to generate interleaved scanning signals, so that the same rows in different zones are scanned sequentially. For example, the first row of the first zone, the first row of the second zone, the first row of the third zone, and the first row of the fourth zone are scanned sequentially, followed by the second row of the first zone, the second row of the second zone, and so on. This can further reduce instantaneous power consumption and improve the power distribution of large-size display panels.

[0100] As an improvement, the control circuit also dynamically adjusts the pulse width of the scan signal S(K) based on the data complexity of the current row. Specifically, the control circuit first analyzes the degree of data change in each row. For rows with significant data changes, the control circuit extends the pulse width of the scan signal S(K) to allow more time for data writing; for rows with minor data changes, the pulse width of the scan signal S(K) is shortened.

[0101] As an improvement, the control circuit also precharges the first capacitor C1 of the pixel unit PX to a level close to the target voltage during the data writing phase. Specifically, before actually writing the data signal, the control circuit first applies a preset voltage to the first capacitor C1, which is close to the target voltage to be written. This precharging method can significantly shorten the data writing time and improve writing efficiency.

[0102] All transistors in the display device provided in the embodiments of this application are P-type transistors, but of course, they can also be N-type transistors.

[0103] Embodiments of this application also provide a driving method for a display device, the driving method including:

[0104] A slope signal called Sweep is generated, which consists of N pulse cycles within the driving cycle of one frame.

[0105] The sweep signal Sweep is input to multiple pixel units PX.

[0106] Within the driving cycle of one frame, the pixel unit PX in each of the N regions (R1~RN) is sequentially controlled to write data and emit light.

[0107] The driving cycle of each pixel unit PX in each region includes a data writing sub-cycle and a light emission sub-cycle. The data writing sub-cycle precedes the light emission sub-cycle. The data writing sub-cycle includes one pulse cycle of the ramp signal Sweep, and the light emission sub-cycle includes N-1 pulse cycles of the ramp signal Sweep.

[0108] The data write sub-cycle includes a first reset phase and a data write phase. The driving method also includes:

[0109] In the first reset phase, a first reset control signal RST is input to the reset module 202 of the pixel unit PX;

[0110] In the data writing phase following the first reset phase, data signals are written to the pulse width modulation module 201 and pulse amplitude modulation module 203 of the pixel unit PX in the current region.

[0111] The luminescent sub-cycle includes N-1 second reset phases and N-1 luminescence phases, and the driving method also includes:

[0112] In the second reset phase, a first reset control signal RST is input to the reset module 202 of the pixel unit PX in the current region to reset the pixel unit PX;

[0113] In the light-emitting stage following the second reset stage, a slope signal Sweep and a data signal are input to the pulse width modulation module 201 and pulse amplitude modulation module 203 of the pixel unit PX, so that the pixel unit PX controls the light-emitting device 204 to emit light according to the slope signal Sweep and the data signal.

[0114] The driving method also includes:

[0115] A first reset control signal RST and a light emission control signal EM(K) are generated. The first reset control signal RST is used to control the reset module 202 in the pixel unit PX to reset, and the light emission control signal EM(K) is used to control the pixel unit PX to emit light.

[0116] During the first reset phase of the data writing sub-cycle, the first reset control signal RST is a low-level signal.

[0117] During the data writing phase of the data writing sub-cycle, the first reset control signal RST is a high-level signal.

[0118] During the data writing sub-cycle, the light emission control signal EM(K) is a high-level signal.

[0119] During the light-emitting sub-cycle, the light-emitting control signal EM(K) is a low-level signal.

[0120] During the second reset phase of the light-emitting sub-cycle, the first reset control signal RST is a low-level signal;

[0121] During the light emission phase of the light emission sub-cycle, the first reset control signal RST is a high-level signal;

[0122] During the light-emitting sub-cycle, the light-emitting control signal EM(K) is a low-level signal.

[0123] Each of the N regions (R1~RN) includes M rows of pixel units PX, where M is an integer greater than 1. The driving method also includes:

[0124] During the data writing phase of the data writing sub-cycle, M scan signals S(K) are provided to the M-row pixel units PX of each region.

[0125] The driving method also includes the following steps:

[0126] Under the control of the light emission control signal EM(K), the slope signal Sweep is written to the first node A through the first transistor T1;

[0127] Under the control of the scan signal S(K), the data signal is written to the first node A through the second transistor T2;

[0128] The voltage between the first node A and the second node B is stored through the first capacitor C1;

[0129] Under the control of the scanning signal S(K), the threshold voltage of the first transistor T1 is compensated by the third transistor T3 and the fourth transistor T4;

[0130] Under the control of the second reset control signal EMi(K), the second node B is initialized through the fifth transistor T5;

[0131] Under the control of the light emission control signal EM(K), the first power supply signal Vdd output by the fourth transistor T4 is output to the reset module 202 through the sixth transistor T6.

[0132] The driving method also includes the following steps:

[0133] Under the control of the voltage at the third node C, the first power supply signal Vdd is selectively provided to the pulse amplitude modulation module 203 through the seventh transistor T7;

[0134] Under the control of the first reset control signal RST, the second reset signal VH is written to the fourth node D through the eighth transistor T8;

[0135] Under the control of the first reset control signal RST, the first reset signal Vref is written to the third node C through the ninth transistor T9;

[0136] The voltage of the third node C is changed by coupling the second capacitor C2 when the voltage of the fourth node D changes.

[0137] The driving method also includes the following steps:

[0138] Under the control of the scan signal S(K), the tenth transistor T10 and the eleventh transistor T11 are simultaneously turned on. The turn-on of T10 enables the voltage of the fifth node E to be transmitted; the turn-on of T11 transmits the second data signal Data_PAM(K) to the source of T12.

[0139] Under the control of the voltage at node E, the twelfth transistor T12 is selectively turned on. Specifically, the gate of T12 is connected to node E, and its conduction state depends on the voltage level at node E.

[0140] Under the control of the second reset control signal EMi(K), the thirteenth transistor T13 is turned on, transmitting the level of the second power supply signal Vss to the fifth node E, thereby initializing the fifth node E.

[0141] During the light-emitting stage, the light-emitting control signal EM(K) controls the fourteenth transistor T14 to turn on, connecting the drain of T12 to the anode of the light-emitting device 204.

[0142] The third capacitor C3 is connected between the first power signal input terminal Vdd and the fifth node E, and is used to store the control voltage.

[0143] The embodiments of this application employ a pulse width modulation driving method combining a global sweeping signal and multiple pulses to achieve progressive light emission, effectively solving the technical problems of limited brightness adjustment range, high power consumption, insufficient grayscale accuracy, and obvious flickering in the prior art. Specifically, the embodiments of this application use a global sweeping signal to ensure that all pixel units receive the same sweeping signal, improving display consistency. In addition, the embodiments of this application introduce multi-pulse light emission technology. Within the driving cycle of one frame, the sweeping signal contains multiple pulse cycles, allowing pixel units in each area to emit light multiple times, expanding the brightness adjustment range. Especially in low grayscale display, it can effectively improve flickering. By adjusting the number of pulses and the emission time of each pulse, the emission duty cycle can be flexibly controlled to meet a wide range of display needs from ultra-low brightness to ultra-high brightness. Furthermore, the embodiments of this application use a progressive light emission method, dividing the display panel into multiple areas. The pixel units in each area sequentially complete data writing and multiple emission within the driving cycle of one frame, which not only improves the display effect but also significantly reduces instantaneous current, effectively solving the high power consumption problem.

[0144] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, include: The display panel includes N regions divided along the scanning direction, each region including multiple pixel units, where N is an integer greater than 1; as well as A control circuit is electrically connected to the plurality of pixel units. The control circuit is used to generate a ramp signal and input the ramp signal to the plurality of pixel units, and to sequentially control the pixel units in each of the N regions to perform data writing and light emission within a driving cycle of a frame. The ramp signal includes N pulse cycles within the driving cycle of one frame. The driving cycle of each pixel unit in the region includes a data writing sub-cycle and a light emission sub-cycle. The data writing sub-cycle precedes the light emission sub-cycle. The data writing sub-cycle includes one pulse cycle of the ramp signal, and the light emission sub-cycle includes N-1 pulse cycles of the ramp signal. The pixel unit includes: Light-emitting devices; and A driving circuit, electrically connected to the light-emitting device, is used to control the light emission of the light-emitting device; The driving circuit includes a pulse width modulation module, a pulse amplitude modulation module, and a reset module. The pulse width modulation module is electrically connected to the reset module, the reset module is electrically connected to the pulse amplitude modulation module, and the pulse amplitude modulation module is electrically connected to the light-emitting device. The pulse width modulation module includes: The first transistor has its gate electrically connected to the light emission control signal input terminal, one of the source and drain of the first transistor electrically connected to the ramp signal input terminal, and the other of the source and drain of the first transistor electrically connected to the first node. The second transistor has its gate electrically connected to the scan signal input terminal, one of its source and drain terminals electrically connected to the first data signal input terminal, and the other of its source and drain terminals electrically connected to the first node. A first capacitor, one end of which is electrically connected to the first node, and the other end of which is electrically connected to the second node; The third transistor has its gate electrically connected to the scan signal input terminal, and one of its source and drain terminals is electrically connected to the second node. The fourth transistor has its gate electrically connected to the second node, one of its source and drain electrically connected to the first power signal input terminal, and the other of its source and drain electrically connected to the other of the source and drain of the third transistor. The fifth transistor has its gate electrically connected to the second reset control signal input terminal, one of the source and drain of the fifth transistor electrically connected to the second power supply signal input terminal, and the other of the source and drain of the fifth transistor electrically connected to the second node. The sixth transistor has its gate electrically connected to the light emission control signal input terminal, one of its source and drain terminals electrically connected to the drain terminal of the fourth transistor, and the other of its source and drain terminals electrically connected to the third node of the reset module.

2. The display device according to claim 1, characterized in that, The reset module includes: The seventh transistor has its gate electrically connected to the third node, and one of its source and drain is electrically connected to the first power signal input terminal. The eighth transistor has its gate electrically connected to the first reset control signal input terminal, one of the source and drain of the eighth transistor electrically connected to the second reset signal input terminal, and the other of the source and drain of the eighth transistor electrically connected to the fourth node. The ninth transistor has its gate electrically connected to the first reset control signal input terminal, one of its source and drain terminals electrically connected to the first reset signal input terminal, and the other of its source and drain terminals electrically connected to the third node. A second capacitor, one end of which is electrically connected to the third node, and the other end of which is electrically connected to the fourth node.

3. The display device according to claim 1, characterized in that, The pulse amplitude modulation module includes: The third capacitor has one end electrically connected to the first power signal input terminal and the other end electrically connected to the fifth node. The tenth transistor has its gate electrically connected to the scan signal input terminal, and one of its source and drain terminals is electrically connected to the fifth node. The eleventh transistor has its gate electrically connected to the scan signal input terminal, and one of its source and drain terminals is electrically connected to the second data signal input terminal. The other of the source and drain terminals of the eleventh transistor in the pulse amplitude modulation module is electrically connected to the other of the source and drain terminals of the seventh transistor in the reset module. The twelfth transistor has its gate electrically connected to the fifth node, one of its source and drain is electrically connected to the other of its source and drain of the eleventh transistor, and the other of its source and drain is electrically connected to the other of its source and drain of the tenth transistor. The thirteenth transistor has its gate electrically connected to the second reset control signal input terminal, one of the source and drain of the thirteenth transistor is electrically connected to the second power supply signal input terminal, and the other of the source and drain of the thirteenth transistor is electrically connected to the fifth node. The fourteenth transistor has its gate electrically connected to the light-emitting control signal input terminal, one of its source and drain terminals electrically connected to the drain of the twelfth transistor, and the other of its source and drain terminals electrically connected to the anode of the light-emitting device.

4. The display device according to claim 1, characterized in that, The data writing sub-cycle includes a first reset phase and a data writing phase. The control circuit is used to input a first reset control signal to the reset module of the pixel unit during the first reset phase, and to write data signals to the pulse width modulation module and pulse amplitude modulation module of the pixel unit during the data writing phase after the first reset phase. The light-emitting sub-cycle includes N-1 second reset stages and N-1 light-emitting stages. The control circuit is used to input a first reset control signal to the reset module of the pixel unit during the second reset stage, and to input the ramp signal and the data signal to the pulse width modulation module and pulse amplitude modulation module of the pixel unit during the light-emitting stages after the second reset stage, so that the pixel unit controls the light-emitting device to emit light according to the ramp signal and the data signal.

5. The display device according to claim 4, characterized in that, The control circuit is also used to generate a first reset control signal and a light emission control signal. The first reset control signal is used to control the reset module in the pixel unit to reset, and the light emission control signal is used to control the pixel unit to emit light.

6. The display device according to claim 5, characterized in that, The first reset control signal is a low-level signal during the first reset phase of the data write sub-cycle and a high-level signal during the data write phase of the data write sub-cycle; the light emission control signal is a high-level signal during the data write sub-cycle and a low-level signal during the light emission sub-cycle; or The first reset control signal is a high-level signal during the first reset phase and a low-level signal during the data writing phase. The light emission control signal is a low-level signal during the data writing sub-cycle and a high-level signal during the light emission sub-cycle.

7. The display device according to claim 6, characterized in that, The first reset control signal is a low-level signal during the second reset phase of the light-emitting sub-cycle and a high-level signal during the light-emitting phase of the light-emitting sub-cycle; the light-emitting control signal is a low-level signal during the light-emitting sub-cycle; or The first reset control signal is a high-level signal during the second reset phase of the light-emitting sub-cycle and a low-level signal during the light-emitting phase of the light-emitting sub-cycle. The light-emitting control signal is a high-level signal during the light-emitting sub-cycle.

8. The display device according to claim 1, characterized in that, The control circuit includes a ramp signal generation unit. The output terminal of the ramp signal generation unit is electrically connected to a plurality of pixel units of the display panel. The ramp signal generation unit is used to generate the ramp signal and provide the ramp signal to the plurality of pixel units.

9. The display device according to claim 1, characterized in that, Each of the N regions includes M rows of pixel units, where M is an integer greater than 1. The control circuit is also used to provide M scan signals to the M rows of pixel units in each region during the data writing phase of the data writing sub-cycle.

10. A driving method for a display device as described in any one of claims 1 to 9, characterized in that, The display panel of the display device includes N regions divided along the scanning direction, each region including multiple pixel units, where N is an integer greater than 1, and the driving method includes: A ramp signal is generated, which includes N pulse cycles within the driving cycle of one frame. The ramp signal is input to multiple pixel units; Within the driving cycle of one frame, the pixel units of each of the N regions are sequentially controlled to write data and emit light; The driving cycle of each pixel unit in each region includes a data writing sub-cycle and a light emission sub-cycle. The data writing sub-cycle precedes the light emission sub-cycle. The data writing sub-cycle includes one pulse cycle of the ramp signal, and the light emission sub-cycle includes N-1 pulse cycles of the ramp signal.

11. The driving method according to claim 10, characterized in that, The data writing sub-cycle includes a first reset phase and a data writing phase, and the driving method further includes: During the first reset phase, a first reset control signal is input to the reset module of the pixel unit; In the data writing phase following the first reset phase, data signals are written to the pulse width modulation module and pulse amplitude modulation module of the pixel unit.

12. The driving method according to claim 10, characterized in that, The light-emitting sub-cycle includes N-1 second reset phases and N-1 light-emitting phases, and the driving method further includes: During the second reset phase, a first reset control signal is input to the reset module of the pixel unit; In the light emission stage following the second reset stage, the ramp signal and the data signal are input to the pulse width modulation module and pulse amplitude modulation module of the pixel unit, so that the pixel unit controls the light emission device to emit light according to the ramp signal and the data signal.

13. The driving method according to claim 10, characterized in that, The driving method further includes: A first reset control signal and a light emission control signal are generated, wherein the first reset control signal is used to control the reset module in the pixel unit to reset, and the light emission control signal is used to control the pixel unit to emit light.

14. The driving method according to claim 13, characterized in that, During the first reset phase of the data writing sub-cycle, the first reset control signal is a low-level signal. During the data writing phase of the data writing sub-cycle, the first reset control signal is a high-level signal. During the data writing sub-cycle, the light emission control signal is a high-level signal; During the light-emitting sub-cycle, the light-emitting control signal is a low-level signal.

15. The driving method according to claim 14, characterized in that, During the second reset phase of the light-emitting sub-cycle, the first reset control signal is a low-level signal. During the light-emitting phase of the light-emitting sub-cycle, the first reset control signal is a high-level signal; During the light-emitting sub-cycle, the light-emitting control signal is a low-level signal.

16. The driving method according to claim 10, characterized in that, Each of the N regions comprises M rows of pixel units, where M is an integer greater than 1. The driving method further includes: During the data writing phase of the data writing sub-cycle, M scan signals are provided to the M rows of pixel units in each region.

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