Arbitrary Waveform Generation System and Method for Multi-Bit Fault-Tolerant Superconducting Quantum Computers

Abstract

The present invention relates to the field of quantum information technology, and particularly to an arbitrary waveform generation system and method for a multi-bit fault-tolerant superconducting quantum computer, including: a host computer for sending waveform data and control signals, reading the status information of the AWG board, and receiving the AWG return signal; several AWG boards for waveform output, the AWG boards being connected to the host computer through a high-speed communication link; the AWG board receives the waveform data sent by the host computer and stores it; receives an instruction sequence, and according to the instruction sequence, retrieves the stored waveform data; the waveform data is output as an analog waveform after passing through the DAC. The present invention has a flexible waveform mode generation mechanism, and supports the synchronous operation of multiple AWG boards, receives multi-bit feedback signals, selects the playback waveform according to the feedback signals, and can also add new waveform modes without modifying the hardware and without increasing the burden on the host computer.

Description

Technical Field

[0001] The present invention relates to the field of quantum information technology, and particularly to an arbitrary waveform generating system and method for a multi-bit fault-tolerant superconducting quantum computer. Background Art

[0002] Quantum algorithms generally require precise waveforms to ensure the correct operation of qubits. This includes precise control of parameters such as the frequency, amplitude, phase, and shape of the waveforms. In quantum gate operations, it is necessary to complete the switching from one waveform to another within an extremely short time. For example, in an ion trap quantum computer, the control waveform may need to change within a few nanoseconds to dozens of nanoseconds. Quantum systems often require real-time feedback to correct errors. This requires the waveform generator to dynamically adjust the waveforms of subsequent operations based on the results of the previous operation.

[0003] Quantum fault-tolerant computing requires a flexibly configurable AWG (Arbitrary Waveform Generator) to generate manipulation waveforms and be able to select the next waveform segment to play within a few nanoseconds according to the feedback result. However, existing commercial AWGs cannot achieve sufficient flexible configuration and cannot select and play the next waveform segment within a few nanoseconds according to an external input signal, which to a certain extent limits the development of quantum computing. Summary of the Invention

[0004] The technical solution provided by the present invention is: an arbitrary waveform generating system for a multi-bit fault-tolerant superconducting quantum computer, comprising:

[0005] A host computer, configured to send waveform data and control signals, read the status information of the AWG board, and receive the AWG return signal;

[0006] A plurality of AWG boards for waveform output, and the AWG boards are connected to the host computer through a high-speed communication link;

[0007] The AWG board is capable of receiving a synchronization signal sent by other AWG boards to achieve synchronous operation with other AWG boards;

[0008] The AWG board is capable of receiving feedback information to support error correction codes and sending pre-stored waveforms according to the feedback information;

[0009] The control signal consists of a plurality of instruction sequences, and the instruction sequences include truth tables, macro instructions, and firmware.

[0010] The present invention also provides an arbitrary waveform generating method for a multi-bit fault-tolerant superconducting quantum computer, and the method includes:

[0011] Receiving the waveform data sent by the host computer and storing it;

[0012] Receive an instruction sequence, and according to the instruction sequence, retrieve the stored waveform data;

[0013] The waveform data is output as an analog waveform after passing through the DAC.

[0014] Preferably, the receiving and storing the waveform data sent by the host computer includes the following steps:

[0015] Receive a control signal, firmware, and truth table;

[0016] Store the truth table and firmware in the internal memory of the AWG according to the control signal;

[0017] Store the waveform data in the storage area corresponding to the RAM address in the AWG;

[0018] The RAM address corresponds uniquely to a specific storage area of the AWG; the waveform data stored in a specific area within the AWG can be found through the RAM address.

[0019] Preferably, the storing the waveform data in the storage area corresponding to the RAM address in the AWG includes the following steps:

[0020] Receive a macro instruction and decode it through a decoder;

[0021] Divide the input macro instruction into multiple atomic instructions for output according to the instruction template preset in the firmware;

[0022] Generate a RAM address according to the start address and end address in the atomic instruction;

[0023] Store the waveform data in the storage area corresponding to the RAM address.

[0024] Preferably, the receiving an instruction sequence, and according to the instruction sequence, retrieving the stored waveform data includes the following steps:

[0025] Analyze the atomic instruction through a decoder to identify the intention of the atomic instruction;

[0026] Read the corresponding waveform data through the RAM address and play the waveform data;

[0027] Obtain the voltage value in the atomic instruction and output the voltage value.

[0028] Preferably, it further includes the step:

[0029] After analyzing the atomic instruction, decide whether to execute the atomic instruction according to the feedback signal; specifically including:

[0030] Obtain multiple truth tables;

[0031] Extract the group number in the atomic instruction;

[0032] Select the truth table corresponding to the number, and output the instruction selection signal to the decoder;

[0033] Based on the input instruction selection signal, the decoder decides whether to execute the corresponding atomic instruction;

[0034] After confirming that the synchronization signal is valid, start executing the first atomic instruction to synchronize multiple AWG boards.

[0035] Preferably, the atomic instruction includes a condition field and a play field. The play field includes a pre-waiting time, a pre-waiting voltage, RAM address information, loop, a post-waiting time, and a post-waiting voltage. The condition field includes a condition valid flag, a truth table selection, a matching value, and a group number.

[0036] Preferably, the analog waveform includes a pre-waiting voltage, a pre-waiting time, a waveform, a post-waiting voltage, and a post-waiting time.

[0037] The present invention also provides an electronic device, including a processor and a memory, for executing any waveform generation method of the multi-bit fault-tolerant superconducting quantum computer described above.

[0038] The present invention also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement any waveform generation method of the multi-bit fault-tolerant superconducting quantum computer.

[0039] Advantages of the present invention:

[0040] The present invention has a flexible waveform pattern generation mechanism. The so-called waveform pattern refers to scheduling instructions such as which segment to play first, which segment to play next, how many times each segment loops, and how much idle time in the middle. Through the synchronization signal, it can support the synchronous operation of multiple AWG boards and select the playback waveform according to the feedback signal; when the hardware cannot be modified, new waveform patterns can also be added without overloading the host computer too much. Description of the Drawings

[0041] Figure 1 It is a composition structure diagram of the system of the present invention;

[0042] Figure 2 It is a flowchart of the method of the present invention;

[0043] Figure 3 It is an atomic instruction format diagram of the present invention;

[0044] Figure 4 It is a schematic diagram of the composition structure of the play field of the present invention;

[0045] Figure 5 It is a schematic diagram of the composition structure of the condition field of the present invention. Detailed implementation manners

[0046] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments in the following description are only examples, and those skilled in the art can think of other obvious variations. The basic principles defined in the following description of the present invention can be applied to other implementation manners, variant schemes, improvement schemes, equivalent schemes, and other technical schemes without departing from the spirit and scope of the present invention.

[0047] It can be understood that the term "a" should be understood as "at least one" or "one or more". That is, in one embodiment, the number of an element can be one, while in other embodiments, the number of the element can be multiple. The term "a" cannot be understood as a limitation on the number.

[0048] Please refer to Figure 1 , the present invention provides an arbitrary waveform generation system for a multi-bit fault-tolerant superconducting quantum computer, including: a host computer and multiple AWG boards;

[0049] Wherein, the host computer and the AWG boards are connected through a high-speed communication link. The host computer sends waveform data and control signals through the high-speed communication link, and reads the status information of the AWG boards. In addition to receiving the control signals from the host computer, the AWG boards also receive the synchronization signals of other AWG boards for synchronous operation of multiple AWG boards. To support error correction codes, the AWG boards can also receive feedback signals from external devices and select to send pre-stored waveforms according to the feedback signals when necessary. The control signals are composed of multiple instruction sequences, and the instruction sequences include truth tables, macro instructions, and firmware.

[0050] The AWG board is composed of a high-speed communication link interface, an instruction processing unit, a waveform RAM, a selector, and a DAC.

[0051] The high-speed communication link interface sends the information sent by the host computer to different modules according to the category. The waveform data is written into the waveform RAM; the truth table is written into the instruction processing unit; the macro instruction is written into the instruction processing unit; the firmware is written into the instruction processing unit. The instruction processing unit generates RAM addresses according to the macro instructions, truth tables, synchronization signals, and feedback signals for reading the RAM data at specific addresses in the waveform RAM.

[0052] Please refer to Figure 2 , the present invention also provides an arbitrary waveform generation method for a multi-bit fault-tolerant superconducting quantum computer, including the following steps:

[0053] S1. Receive and store the waveform data sent by the host computer; specifically including the following steps:

[0054] S11. Receive control signals, firmware, and truth tables;

[0055] S12. Store the truth table and firmware in the internal memory of the AWG according to the control signal;

[0056] S13. Store the waveform data in the storage area corresponding to the RAM address in the AWG, specifically:

[0057] S131. Receive the macro instruction and decode it through the decoder;

[0058] S132. Divide the input macro instruction into multiple atomic instructions for output according to the instruction template preset in the firmware;

[0059] S133. Generate an incrementing RAM address according to the start address and end address in the atomic instruction;

[0060] S134. Store the waveform data in the storage area corresponding to the RAM address in the AWG board;

[0061] The RAM address corresponds uniquely to a specific storage area of the AWG board; the waveform data stored in a specific area of the AWG board can be found through the RAM address.

[0062] The firmware has a preset instruction template. Input a macro instruction and output several atomic instructions to form an atomic instruction queue. It should be noted that atomic instructions can also be mixed in the macro instruction sequence. After the hardware determines that it is an atomic instruction rather than a macro instruction, it is directly pushed into the atomic instruction queue instead of being decoded and disassembled by the MCU and the firmware memory. The number of atomic instructions corresponding to the macro instruction is completely determined by the firmware, so it can easily support very complex address jump styles. The firmware can also be changed after the hardware is finalized, and thus can support new macro instructions.

[0063] S2. Receive the instruction sequence and retrieve the stored waveform data according to the instruction sequence, specifically:

[0064] S21. Analyze the atomic instruction through the decoder to identify the intention of the atomic instruction;

[0065] S22. Read the corresponding waveform data through the RAM address and broadcast the waveform;

[0066] S23. Obtain the voltage value in the atomic instruction and output the voltage value.

[0067] Among them, analyzing the atomic instruction by the decoder and identifying the intention of the atomic instruction means that: if the atomic instruction requires sending a certain segment of waveform in the waveform RAM, then the decoder generates an increasing RAM address according to the start address and end address in the atomic instruction; if the atomic instruction requires sending the firmware voltage, then the decoder sends out the voltage value in the atomic instruction, which is a constant value in this embodiment. At the same time, the data source selection instruction sent by the instruction processing unit switches the selector to receive the voltage.

[0068] S3. The waveform data is output as an analog waveform after passing through the DAC.

[0069] In some cases, it is necessary to decide whether to execute the instruction according to the feedback signal, so it also includes the steps:

[0070] S210. After analyzing the atomic instruction, decide whether to execute the atomic instruction according to the feedback signal; specifically including:

[0071] S2101. Obtain multiple truth tables;

[0072] S2101. Extract the group number in the atomic instruction;

[0073] S2101. Select the truth table with the corresponding number and output the instruction selection signal to the decoder;

[0074] S2101. The decoder decides whether to execute the corresponding atomic instruction according to the input instruction selection signal;

[0075] S2101. After confirming that the synchronization signal is valid, start executing the first atomic instruction to synchronize multiple AWG boards.

[0076] Please combine Figure 3-4 The atomic instruction includes a condition field and a playback field. The playback field includes a pre-waiting time, a pre-waiting voltage, RAM address information, a loop, a post-waiting time, and a post-waiting voltage. The condition field includes a condition valid flag, a truth table selection, a matching value, and a group number. The analog waveform includes a pre-waiting voltage, a pre-waiting time, a waveform, a post-waiting voltage, and a post-waiting time.

[0077] The condition valid flag is used to indicate whether to consider the instruction selection to decide whether to play. If there is no need to consider, the contents of the truth table selection, the matching value, and the group number are ignored by the decoder.

[0078] If consideration is needed, the truth table sends out the selected value to select a certain truth table. By comparing the instruction selection with the matching value, it can be known whether playback is required. It should be noted that the matching value can be not only a single value, but also include simple rules. For example, only compare several of the bits, play if they are equal, or play if they are not equal. Since the truth table memory first performs a configurable transformation on the feedback signal and the matching value can also configure rules, this conditional execution function has great flexibility.

[0079] The group number is used to indicate which instructions need to be compared simultaneously to determine whether to play. When the first instruction in the atomic instruction queue exit needs to be compared (indicated by the condition valid flag), and several subsequent consecutive instructions also need to be compared, and the group numbers are all the same as the group number of the first instruction, then these instructions need to simultaneously receive the instruction selection (the value selected by the truth table can be determined by the first instruction), compare it with their own matching value, and decide whether to play. The instructions that are not played are deleted from the queue.

[0080] The present invention also provides an electronic device, including a processor and a memory, for executing any waveform generation method of the multi-bit fault-tolerant superconducting quantum computer described above.

[0081] The present invention also provides a computer-readable storage medium, and the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement any waveform generation method of the multi-bit fault-tolerant superconducting quantum computer described above.

[0082] Embodiments disclosed by the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. Embodiments disclosed by the present invention include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program codes for executing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), the above functions defined in the methods of the present application are executed. It should be noted that the computer-readable medium described above in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium can include, but are not limited to: an electrical connection having one or more wire segments, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or combined with an instruction execution system, apparatus, or device. In the present application, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, in which the computer-readable program code is carried. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, and the computer-readable medium can send, propagate, or transmit a program for use by or combined with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination of the above.

[0083] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur in a different order than that noted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0084] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The objectives of the present invention have been fully and effectively achieved. The functions and structural principles of the present invention have been demonstrated and illustrated in the embodiments. Without departing from the said principles, the embodiments of the present invention may have any variations or modifications.

Claims

1. An arbitrary waveform generation method for a multi-bit fault-tolerant superconducting quantum computer, the method being implemented based on an arbitrary waveform generation system, characterized in that: The system comprises: a host computer for sending waveform data and control signals, reading status information of the AWG board, and receiving AWG return signals; a plurality of AWG boards for waveform output, wherein the AWG boards are connected to the host computer via a high-speed communication link; The method comprises: receiving and storing waveform data sent by a host computer; receiving an instruction sequence, and calling out the stored waveform data according to the instruction sequence, including: analyzing the atomic instruction through a decoder, identifying the intention of the atomic instruction; reading the corresponding waveform data through a RAM address, and playing the waveform data; obtaining a voltage value in the atomic instruction, and outputting the voltage value; The receiving and storing of waveform data sent by the host computer includes the following steps: receiving a control signal, firmware, and a truth table; storing the truth table and firmware in an internal memory of the AWG according to the control signal; storing the waveform data in a storage area corresponding to a RAM address in the AWG; the RAM address uniquely corresponds to a specific storage area of ​​the AWG; and the waveform data stored in a specific area in the AWG can be found through the RAM address; After analyzing the atomic instruction, whether the atomic instruction is executed is determined according to the feedback signal; specifically, the method includes: obtaining multiple truth tables; extracting the group number in the atomic instruction; selecting the truth table with the corresponding number, and outputting the instruction selection signal to the decoder; the decoder determines whether to execute the corresponding atomic instruction according to the input instruction selection signal; after confirming that the synchronization signal is valid, the first atomic instruction is executed to synchronize multiple AWG boards.

2. The method for generating an arbitrary waveform of a multi-bit fault-tolerant superconducting quantum computer according to claim 1, characterized in that: The AWG board receives the synchronization signal sent by other AWG boards to achieve synchronous operation with other AWG boards; The AWG board receives a feedback signal to support the operation of the error correction code and sends a pre-stored waveform according to the feedback signal; the control signal is composed of a plurality of instruction sequences, and the instruction sequence includes a truth table, a macro instruction and a firmware.

3. The arbitrary waveform generation method of a multi-bit fault-tolerant superconducting quantum computer according to claim 2, characterized in that: The atomic instruction includes a conditional domain and a play domain, wherein the play domain includes a pre-wait time, a pre-wait voltage, RAM address information, a loop, a post-wait time and a post-wait voltage, and the conditional domain includes a conditional validity flag, a truth table selection, a matching value and a group number.

4. The method for generating an arbitrary waveform of a multi-bit fault-tolerant superconducting quantum computer according to claim 3, characterized in that: The step of storing the waveform data in a storage area corresponding to a RAM address in the AWG comprises the following steps: Receive macro instructions and decode them through a decoder; According to the instruction template preset in the firmware, the input macro instruction is divided into multiple atomic instructions for output; Generate RAM address according to the starting address and ending address in the atomic instruction; The waveform data is stored in the storage area corresponding to the RAM address.

5. The method for generating an arbitrary waveform of a multi-bit fault-tolerant superconducting quantum computer according to claim 4, characterized in that: The waveform data is output as an analog waveform after passing through the DAC.

6. The method for generating an arbitrary waveform of a multi-bit fault-tolerant superconducting quantum computer according to claim 5, characterized in that: The simulation waveform includes a front waiting voltage, a front waiting time, a waveform, a rear waiting voltage, and a rear waiting time.

7. An electronic device, comprising a processor and a memory, characterized in that: An arbitrary waveform generation method for executing a multi-bit fault-tolerant superconducting quantum computer as described in any one of claims 1-6.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the arbitrary waveform generation method of a multi-bit fault-tolerant superconducting quantum computer as described in any one of claims 1 to 6.

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