Ultra-high voltage silicon capacitor manufacturing method and system, silicon capacitor and electronic equipment

Abstract

The invention provides a manufacturing method and system of an ultrahigh-voltage silicon capacitor, the silicon capacitor and electronic equipment. The method comprises the following steps: etching a deep groove in a silicon substrate; depositing to generate a dielectric layer, and carrying out surface planarization treatment by adopting a CMP (Chemical Mechanical Polishing) process; depositing to generate a tungsten conductive layer, and carrying out surface planarization treatment by adopting a CMP (Chemical Mechanical Polishing) process; depositing to generate an IMD layer; forming holes in the IMD layer, depositing and generating a tungsten electrode contact layer, and performing surface planarization treatment by adopting a CMP process; an aluminum / copper conducting layer is deposited and generated, one section of the aluminum / copper conducting layer is connected with the dielectric layer through a first tungsten electrode contact layer, and the other section of the aluminum / copper conducting layer is connected with the silicon substrate through a second tungsten electrode contact layer; and thinning the back surface of the wafer to enable the thickness of the thinned wafer to be smaller than the depth of the deep groove. According to the invention, the bottom arc corners of the groove are ground away, the accumulation of an electric field at the bottom arc is eliminated, the purpose of ultra-high voltage is achieved, the weakness of a deep groove structure is eliminated, and the voltage resistance and reliability of the silicon capacitor are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method and system for manufacturing an ultra-high voltage silicon capacitor, a silicon capacitor, and an electronic device. Background Art

[0002] Silicon capacitors are capacitors made of silicon as the main body and thin film materials such as silicon dioxide / silicon nitride as dielectrics, using semiconductor chip manufacturing technology. With the advantages of ultra-small size, higher Q value, low insertion loss, stability, reliability, temperature resistance, aging resistance and lower leakage current, they have been widely used in data centers, aerospace, national defense, energy, communications, automobiles, automation and medical fields, and are expected to completely replace traditional ceramic capacitors in many fields.

[0003] To increase the capacitance density of silicon capacitors, semiconductor deep trench technology can be used to realize 3D silicon capacitors. The deep trenches can be used to increase the area (S) of the capacitor to increase the capacitance density. The withstand voltage of silicon capacitors is proportional to the thickness of the dielectric layer, V BR =E m *e, where V BR is the withstand voltage of silicon capacitor, E m is the avalanche threshold electric field, and e is the thickness of the dielectric layer.

[0004] Capacitance (C) and withstand voltage (V BR ) is inversely proportional. The thicker the dielectric layer, the higher the withstand voltage (V BR ) is higher, but the capacitance (C) is smaller. In order to improve the capacitance density of high-voltage silicon capacitor devices, 3D deep trench technology must be used. However, during the deep trench etching process, lateral drilling, residual bottom defects, rough sidewall surface and burrs are prone to occur at the bottom, which brings challenges to the subsequent dielectric filling. As a result, the bottom of the trench is the weakest position of the device's withstand voltage, which seriously affects the withstand voltage performance, product yield and reliability of high-voltage silicon capacitor devices. Summary of the invention

[0005] The technical problem to be solved by the present disclosure is to overcome the defect in the prior art that multiple problems are likely to occur at the bottom during deep trench etching, resulting in poor voltage resistance performance, and to provide a method, system, silicon capacitor and electronic device for manufacturing an ultra-high voltage silicon capacitor.

[0006] The present invention solves the above technical problems through the following technical solutions:

[0007] The present disclosure provides a method for manufacturing an ultra-high voltage silicon capacitor, the manufacturing method comprising:

[0008] etching deep trenches in a silicon substrate;

[0009] Depositing a dielectric layer, and performing a surface planarization process using a CMP (chemical mechanical polishing) process to remove the dielectric layer on the surface of the wafer;

[0010] Depositing a tungsten conductive layer, and performing a surface planarization process using a CMP process to remove the tungsten conductive layer on the surface of the wafer;

[0011] Deposition to generate an IMD (intermetal dielectric) layer;

[0012] A hole is opened in the IMD layer, a tungsten electrode contact layer is deposited and generated, and a surface planarization process is performed using a CMP process to remove the tungsten electrode contact layer on the surface of the wafer; wherein the tungsten electrode contact layer includes: a first tungsten electrode contact layer connected to the dielectric layer, and a second tungsten electrode contact layer connected to the silicon substrate;

[0013] Depositing and generating an aluminum / copper conductive layer, wherein a section of the aluminum / copper conductive layer is connected to the first tungsten electrode contact layer, and another section of the aluminum / copper conductive layer is connected to the second tungsten electrode contact layer;

[0014] The back side of the wafer is thinned so that the thickness of the thinned wafer is less than the depth of the deep trench.

[0015] Optionally, before the step of depositing a dielectric layer, the manufacturing method further comprises:

[0016] A TiN (titanium nitride) barrier layer is deposited on the silicon substrate.

[0017] Optionally, the dielectric layer is a NON dielectric layer;

[0018] The deposition generates a dielectric layer, comprising:

[0019] On the TiN barrier layer deposited on the silicon substrate, a SiN (silicon nitride) sublayer, a SiO2 (silicon dioxide) sublayer and a SiN sublayer are sequentially deposited to form the NON dielectric layer.

[0020] Optionally, after the step of depositing a dielectric layer and performing a surface planarization process using a CMP process, the manufacturing method further comprises:

[0021] A TiN barrier layer is deposited on the NON dielectric layer.

[0022] Optionally, the NON dielectric layer has a thickness of more than 2 μm (micrometer).

[0023] Optionally, the withstand voltage between the first tungsten electrode contact layer and the second tungsten electrode contact layer reaches above 2500V (volts).

[0024] Optionally, etching a deep trench on the silicon substrate includes:

[0025] A semiconductor deep trench process is adopted to etch a plurality of deep trenches on the silicon substrate.

[0026] The present disclosure also provides a manufacturing system for an ultra-high voltage silicon capacitor, the manufacturing system comprising: an etching module, a deposition and polishing module, an opening electrode contact module and a thinning module;

[0027] The etching module is used to etch deep grooves on a silicon substrate;

[0028] The deposition and polishing module is used to deposit and generate a dielectric layer, and to perform surface planarization processing using a CMP process to remove the dielectric layer on the surface of the wafer;

[0029] The deposition and polishing module is also used to deposit and generate a tungsten conductive layer, and use a CMP process to perform surface planarization to remove the tungsten conductive layer on the surface of the wafer;

[0030] The deposition and polishing module is also used for depositing and generating an IMD layer;

[0031] The opening electrode contact module is used to open a hole in the IMD layer, deposit and generate a tungsten electrode contact layer, and use a CMP process to perform surface planarization to remove the tungsten electrode contact layer on the surface of the wafer; wherein the tungsten electrode contact layer includes: a first tungsten electrode contact layer connected to the dielectric layer, and a second tungsten electrode contact layer connected to the silicon substrate;

[0032] The deposition and polishing module is also used to deposit and generate an aluminum / copper conductive layer, a section of the aluminum / copper conductive layer is connected to the first tungsten electrode contact layer, and another section of the aluminum / copper conductive layer is connected to the second tungsten electrode contact layer;

[0033] The thinning module is used to thin the back side of the wafer so that the thickness of the wafer after thinning is smaller than the depth of the deep groove.

[0034] Optionally, the deposition and polishing module is further used to deposit a TiN barrier layer on the silicon substrate.

[0035] Optionally, the dielectric layer is a NON dielectric layer;

[0036] The deposition and polishing module is also used to sequentially deposit a SiN sublayer, a SiO2 sublayer and a SiN sublayer on the TiN barrier layer deposited on the silicon substrate to form the NON dielectric layer.

[0037] Optionally, the deposition and polishing module is further used to deposit a TiN barrier layer on the NON dielectric layer.

[0038] Optionally, the NON dielectric layer has a thickness of more than 2 μm.

[0039] Optionally, the withstand voltage between the first tungsten electrode contact layer and the second tungsten electrode contact layer reaches above 2500V.

[0040] Optionally, the etching module is further used to etch a plurality of the deep trenches on the silicon substrate using a semiconductor deep trench process.

[0041] The present disclosure also provides a silicon capacitor, which is realized by utilizing the aforementioned method for manufacturing the ultra-high voltage silicon capacitor.

[0042] The present disclosure also provides an electronic device, which includes the aforementioned silicon capacitor.

[0043] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0044] The positive progress effect disclosed in the present invention is that: by thinning the back side of the wafer so that the thickness of the thinned wafer is less than the depth of the deep groove, that is, the dielectric layer at the bottom of the groove is completely ground off, the arc corners at the bottom of the groove are ground off, and the electric field is eliminated. The concentration of the arc at the bottom achieves the goal of ultra-high voltage, eliminates the weaknesses of the 3D deep trench structure, and improves the voltage resistance and reliability of silicon capacitor devices; compared with pure SiO2 dielectric, the NON dielectric layer has a higher avalanche threshold electric field and dielectric constant, which can further improve the voltage resistance and capacitance density of silicon capacitor devices. At the same time, the TiN barrier layer overcomes the device reliability problem that the SiN sublayer in the NON dielectric layer cannot be attached to the silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A flowchart of a method for manufacturing an ultra-high voltage silicon capacitor provided in Example 1 of the present disclosure;

[0046] Figure 2 A schematic diagram of a wafer cross section corresponding to the step S11 of the method for manufacturing an ultra-high voltage silicon capacitor provided in Embodiment 1 of the present disclosure;

[0047] Figure 3 A schematic diagram of a wafer cross section corresponding to the step S12 of the method for manufacturing an ultra-high voltage silicon capacitor provided in Embodiment 1 of the present disclosure;

[0048] Figure 4 A schematic diagram of a wafer cross section corresponding to the step S13 of the method for manufacturing an ultra-high voltage silicon capacitor provided in Embodiment 1 of the present disclosure;

[0049] Figure 5A schematic diagram of a wafer cross section corresponding to the step S14 of the method for manufacturing an ultra-high voltage silicon capacitor provided in Embodiment 1 of the present disclosure;

[0050] Figure 6 A schematic diagram of a wafer cross section corresponding to the step S15 of the method for manufacturing an ultra-high voltage silicon capacitor provided in Embodiment 1 of the present disclosure;

[0051] Figure 7 A schematic diagram of a wafer cross section corresponding to the step S16 of the method for manufacturing an ultra-high voltage silicon capacitor provided in Embodiment 1 of the present disclosure;

[0052] Figure 8 A schematic diagram of a wafer cross section corresponding to the step S17 of the method for manufacturing an ultra-high voltage silicon capacitor provided in Embodiment 1 of the present disclosure;

[0053] Fig. 9 A flowchart of a specific implementation of a method for manufacturing an ultra-high voltage silicon capacitor provided in Example 1 of the present disclosure;

[0054] Fig.10 A schematic diagram of a partial cross-section of a wafer of a method for manufacturing an ultra-high voltage silicon capacitor provided in Example 1 of the present disclosure;

[0055] Fig.11 A schematic diagram of a module of a system for manufacturing an ultra-high voltage silicon capacitor provided in Example 2 of the present disclosure. DETAILED DESCRIPTION

[0056] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0057] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0058] Example 1

[0059] Figure 1 A flowchart of a method for manufacturing an ultra-high voltage silicon capacitor provided by an exemplary embodiment of the present disclosure, the manufacturing method comprising:

[0060] S11. Etching deep trenches on the silicon substrate.

[0061] S12, depositing a dielectric layer, and performing surface planarization processing using a CMP process to remove the dielectric layer on the surface of the wafer.

[0062] S13, depositing a tungsten conductive layer, and performing surface planarization processing using a CMP process to remove the tungsten conductive layer on the surface of the wafer.

[0063] S14, depositing to generate an IMD layer.

[0064] S15, opening a hole in the IMD layer, depositing a tungsten electrode contact layer, and performing surface planarization by a CMP process to remove the tungsten electrode contact layer on the surface of the wafer. The tungsten electrode contact layer includes: a first tungsten electrode contact layer connected to the dielectric layer, and a second tungsten electrode contact layer connected to the silicon substrate.

[0065] S16, depositing and generating an aluminum / copper conductive layer, wherein a section of the aluminum / copper conductive layer is connected to the first tungsten electrode contact layer, and another section of the aluminum / copper conductive layer is connected to the second tungsten electrode contact layer.

[0066] S17, thinning the back side of the wafer so that the thickness of the thinned wafer is smaller than the depth of the deep trench.

[0067] Among them, the typical values ​​of the deep trench are: width of 6μm and depth greater than 100μm.

[0068] The corresponding schematic diagram of the wafer cross section after executing step S11 is as follows: Figure 2 As shown, the corresponding wafer cross-section diagram after executing step S12 is as shown in Figure 3 As shown, the corresponding schematic diagram of the wafer cross section after executing step S13 is as follows Figure 4 As shown, the corresponding schematic diagram of the wafer cross section after executing step S14 is as follows Figure 5 As shown, the corresponding schematic diagram of the wafer cross section after executing step S15 is as follows Figure 6 As shown, the corresponding schematic diagram of the wafer cross section after executing step S16 is as follows Figure 7 As shown, the corresponding schematic diagram of the wafer cross section after executing step S17 is as follows Figure 8 shown.

[0069] In this embodiment, the back side of the wafer is thinned so that the thickness of the thinned wafer is less than the depth of the deep groove, that is, the dielectric layer at the bottom of the groove is completely ground off, the arc corners at the bottom of the groove are ground off, and the electric field is eliminated. The concentration of the arc at the bottom is eliminated, and the goal of ultra-high voltage is achieved. The weaknesses of the 3D deep trench structure are eliminated, and the voltage resistance and reliability of the silicon capacitor device are improved; compared with the simple SiO2 dielectric, the NON dielectric layer has a higher avalanche threshold electric field and dielectric constant, which can further improve the voltage resistance and capacitance density of the silicon capacitor device. At the same time, the TiN barrier layer overcomes the device reliability problem that the SiN sublayer in the NON dielectric layer cannot be attached to the silicon substrate.

[0070] In one embodiment, referring to Fig. 9 Before step S12, the manufacturing method further includes:

[0071] S18. Depositing a TiN barrier layer on the silicon substrate.

[0072] Among them, the TiN barrier layer can solve the problem that the silicon substrate cannot be combined with the SiN dielectric layer.

[0073] in, Figure 4 The enlarged image of the dotted box is shown in Fig.10 As shown, there is a TiN barrier layer between the silicon substrate and the NON dielectric layer.

[0074] In one embodiment, the dielectric layer is a NON dielectric layer.

[0075] Reference Fig. 9 , step S12 comprises:

[0076] S121. On the TiN barrier layer deposited on the silicon substrate, a SiN sublayer, a SiO2 sublayer and a SiN sublayer are sequentially deposited to form a NON dielectric layer.

[0077] Among them, SiN cannot be combined with silicon (silicon substrate), but can be combined with TiN. First, the TiN barrier layer is deposited, and then the (NON) SiN sublayer / SiO2 sublayer / SiN sublayer are deposited in sequence to form a NON dielectric layer. The structure of the NON dielectric layer in the deep trench is as follows Fig.10 shown.

[0078] Compared with pure SiO2 dielectric, NON dielectric layer has higher avalanche threshold electric field and dielectric constant. Therefore, by introducing NON dielectric layer, ultra-high voltage can be achieved, which can further improve the voltage resistance and capacitance density of silicon capacitor devices.

[0079] In one embodiment, referring to Fig. 9 After step S12, the manufacturing method further includes:

[0080] S19, depositing a TiN barrier layer on the NON dielectric layer.

[0081] A TiN barrier layer is used to prevent the SiN sublayer in the NON dielectric layer from directly contacting the tungsten conductive layer. Figure 4 The enlarged image of the dotted box is shown in Fig.10 As shown, there is a TiN barrier layer between the NON dielectric layer and the tungsten conductive layer.

[0082] In one embodiment, the thickness of the NON dielectric layer is greater than 2 μm.

[0083] Among them, when the thickness of the NON dielectric layer reaches more than 2μm, the voltage resistance of the corresponding capacitor can reach more than 2500V.

[0084] In one embodiment, the withstand voltage between the first tungsten electrode contact layer and the second tungsten electrode contact layer reaches more than 2500V.

[0085] Among them, the first tungsten electrode contact layer and the second tungsten electrode contact layer correspond to the two poles of the silicon capacitor respectively, and the voltage resistance reaches more than 2500V, achieving ultra-high voltage.

[0086] In one embodiment, referring to Fig. 9 , step S11 comprises:

[0087] S111, etching a plurality of deep trenches on a silicon substrate using a semiconductor deep trench process.

[0088] Example 2

[0089] Corresponding to the aforementioned embodiment of the method for manufacturing an ultra-high voltage silicon capacitor, the present disclosure also provides an embodiment of a system for manufacturing an ultra-high voltage silicon capacitor.

[0090] Fig.11 A schematic diagram of a module of a system for manufacturing an ultra-high voltage silicon capacitor provided by an exemplary embodiment of the present disclosure, the system comprises: an etching module 21, a deposition and polishing module 22, an opening electrode contact module 23 and a thinning module 24.

[0091] The etching module 21 is used to etch deep trenches on the silicon substrate.

[0092] The deposition and polishing module 22 is used to deposit and generate a dielectric layer, and to perform surface planarization processing using a CMP process to remove the dielectric layer on the surface of the wafer.

[0093] The deposition and polishing module 22 is also used to deposit and generate a tungsten conductive layer, and to perform surface planarization processing using a CMP process to remove the tungsten conductive layer on the surface of the wafer.

[0094] The deposition and polishing module 22 is also used for depositing and generating an IMD layer.

[0095] The hole-opening electrode contact module 23 is used to open a hole in the IMD layer, deposit a tungsten electrode contact layer, and perform surface planarization using a CMP process to remove the tungsten electrode contact layer on the wafer surface. The tungsten electrode contact layer includes: a first tungsten electrode contact layer connected to the dielectric layer, and a second tungsten electrode contact layer connected to the silicon substrate.

[0096] The deposition and polishing module 22 is also used to deposit and generate an aluminum / copper conductive layer, wherein a section of the aluminum / copper conductive layer is connected to the first tungsten electrode contact layer, and another section of the aluminum / copper conductive layer is connected to the second tungsten electrode contact layer.

[0097] The thinning module 24 is used to thin the back side of the wafer so that the thickness of the wafer after thinning is smaller than the depth of the deep trench.

[0098] In this embodiment, the back side of the wafer is thinned so that the thickness of the thinned wafer is less than the depth of the deep groove, that is, the dielectric layer at the bottom of the groove is completely ground off, the arc corners at the bottom of the groove are ground off, and the electric field is eliminated. The concentration of the arc at the bottom is eliminated, and the goal of ultra-high voltage is achieved. The weaknesses of the 3D deep trench structure are eliminated, and the voltage resistance and reliability of the silicon capacitor device are improved; compared with the simple SiO2 dielectric, the NON dielectric layer has a higher avalanche threshold electric field and dielectric constant, which can further improve the voltage resistance and capacitance density of the silicon capacitor device. At the same time, the TiN barrier layer overcomes the device reliability problem that the SiN sublayer in the NON dielectric layer cannot be attached to the silicon substrate.

[0099] In one embodiment, the deposition and polishing module 22 is further used to deposit and generate a TiN barrier layer on the silicon substrate.

[0100] In one embodiment, the dielectric layer is a NON dielectric layer.

[0101] The deposition and polishing module 22 is also used to sequentially deposit a SiN sublayer, a SiO2 sublayer and a SiN sublayer on the TiN barrier layer deposited on the silicon substrate to form a NON dielectric layer.

[0102] In one embodiment, the deposition and polishing module 22 is further used to deposit a TiN barrier layer on the NON dielectric layer.

[0103] In one embodiment, the thickness of the NON dielectric layer is greater than 2 μm.

[0104] In one embodiment, the withstand voltage between the first tungsten electrode contact layer and the second tungsten electrode contact layer reaches more than 2500V.

[0105] In one embodiment, the etching module 21 is further used to etch a plurality of deep trenches on the silicon substrate using a semiconductor deep trench process.

[0106] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0107] Example 3

[0108] This embodiment provides a silicon capacitor, which is realized by using the manufacturing method of the ultra-high voltage silicon capacitor in Embodiment 1.

[0109] In this embodiment, the back side of the wafer is thinned so that the thickness of the thinned wafer is less than the depth of the deep groove, that is, the dielectric layer at the bottom of the groove is completely ground off, the arc corners at the bottom of the groove are ground off, and the electric field is eliminated. The concentration of the arc at the bottom is eliminated, and the goal of ultra-high voltage is achieved. The weaknesses of the 3D deep trench structure are eliminated, and the voltage resistance and reliability of the silicon capacitor device are improved; compared with the simple SiO2 dielectric, the NON dielectric layer has a higher avalanche threshold electric field and dielectric constant, which can further improve the voltage resistance and capacitance density of the silicon capacitor device. At the same time, the TiN barrier layer overcomes the device reliability problem that the SiN sublayer in the NON dielectric layer cannot be attached to the silicon substrate.

[0110] Example 4

[0111] This embodiment provides an electronic device, wherein the electronic device includes the silicon capacitor in the third embodiment.

[0112] In this embodiment, the back side of the wafer is thinned so that the thickness of the thinned wafer is less than the depth of the deep groove, that is, the dielectric layer at the bottom of the groove is completely ground off, the arc corners at the bottom of the groove are ground off, and the electric field is eliminated. The concentration of the arc at the bottom is eliminated, and the goal of ultra-high voltage is achieved. The weaknesses of the 3D deep trench structure are eliminated, and the voltage resistance and reliability of the silicon capacitor device are improved; compared with the simple SiO2 dielectric, the NON dielectric layer has a higher avalanche threshold electric field and dielectric constant, which can further improve the voltage resistance and capacitance density of the silicon capacitor device. At the same time, the TiN barrier layer overcomes the device reliability problem that the SiN sublayer in the NON dielectric layer cannot be attached to the silicon substrate.

[0113] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A method for manufacturing an ultra-high voltage silicon capacitor, characterized in that: The production method comprises: etching deep trenches in a silicon substrate; Depositing a dielectric layer, and performing surface planarization processing using a CMP process to remove the dielectric layer on the surface of the wafer; Depositing a tungsten conductive layer, and performing a surface planarization process using a CMP process to remove the tungsten conductive layer on the surface of the wafer; Deposition to generate an IMD layer; A hole is opened in the IMD layer, a tungsten electrode contact layer is deposited and generated, and a surface planarization process is performed using a CMP process to remove the tungsten electrode contact layer on the surface of the wafer; wherein the tungsten electrode contact layer includes: a first tungsten electrode contact layer connected to the dielectric layer, and a second tungsten electrode contact layer connected to the silicon substrate; Depositing and generating an aluminum / copper conductive layer, wherein a section of the aluminum / copper conductive layer is connected to the first tungsten electrode contact layer, and another section of the aluminum / copper conductive layer is connected to the second tungsten electrode contact layer; The back side of the wafer is thinned so that the thickness of the thinned wafer is less than the depth of the deep trench.

2. The method for manufacturing an ultra-high voltage silicon capacitor according to claim 1, characterized in that: Before the step of depositing a dielectric layer, the manufacturing method further comprises: A TiN barrier layer is deposited on the silicon substrate.

3. The method for manufacturing an ultra-high voltage silicon capacitor according to claim 2, characterized in that: The dielectric layer is a NON dielectric layer; The deposition generates a dielectric layer, comprising: On the TiN barrier layer deposited on the silicon substrate, a SiN sublayer, a SiO2 sublayer and a SiN sublayer are sequentially deposited to form the NON dielectric layer.

4. The method for manufacturing an ultra-high voltage silicon capacitor according to claim 3, characterized in that: After the step of depositing a dielectric layer and performing a surface planarization process using a CMP process, the manufacturing method further comprises: A TiN barrier layer is deposited on the NON dielectric layer.

5. The method for manufacturing an ultra-high voltage silicon capacitor according to claim 4, characterized in that: The thickness of the NON dielectric layer is greater than 2 μm.

6. The method for manufacturing an ultra-high voltage silicon capacitor according to claim 4, characterized in that: The withstand voltage between the first tungsten electrode contact layer and the second tungsten electrode contact layer reaches more than 2500V.

7. The method for manufacturing an ultra-high voltage silicon capacitor according to claim 1, characterized in that: The step of etching a deep trench on a silicon substrate comprises: A semiconductor deep trench process is adopted to etch a plurality of deep trenches on the silicon substrate.

8. A system for manufacturing ultra-high voltage silicon capacitors, characterized in that: The manufacturing system comprises: an etching module, a deposition and polishing module, an opening electrode contact module and a thinning module; The etching module is used to etch deep grooves on a silicon substrate; The deposition and polishing module is used to deposit and generate a dielectric layer, and to perform surface planarization processing using a CMP process to remove the dielectric layer on the surface of the wafer; The deposition and polishing module is also used to deposit and generate a tungsten conductive layer, and use a CMP process to perform surface planarization to remove the tungsten conductive layer on the surface of the wafer; The deposition and polishing module is also used for depositing and generating an IMD layer; The opening electrode contact module is used to open a hole in the IMD layer, deposit and generate a tungsten electrode contact layer, and use a CMP process to perform surface planarization to remove the tungsten electrode contact layer on the surface of the wafer; wherein the tungsten electrode contact layer includes: a first tungsten electrode contact layer connected to the dielectric layer, and a second tungsten electrode contact layer connected to the silicon substrate; The deposition and polishing module is also used to deposit and generate an aluminum / copper conductive layer, a section of the aluminum / copper conductive layer is connected to the first tungsten electrode contact layer, and another section of the aluminum / copper conductive layer is connected to the second tungsten electrode contact layer; The thinning module is used to thin the back side of the wafer so that the thickness of the wafer after thinning is smaller than the depth of the deep groove.

9. A silicon capacitor, characterized in that: The silicon capacitor is realized by using the manufacturing method of the ultra-high voltage silicon capacitor according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The electronic device comprises the silicon capacitor as claimed in claim 9.

Images