A display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes a display area and a non-display area surrounding the display area. The display area includes multiple first reference voltage lines, multiple second reference voltage lines, and data lines. The data lines extend along a first direction. The non-display area includes a first reference voltage bus and a second reference voltage bus. The first reference voltage lines are electrically connected to the first reference voltage bus. The second reference voltage lines are electrically connected to the second reference voltage bus. The first reference voltage bus includes a first bus segment and a second bus segment. The non-display area includes a fan-out area and a first non-display area located on both sides of the display area along the first direction. The non-display area includes a first bus segment and a second bus segment. At least a portion of the first bus segment is located in the fan-out area. At least a portion of the second bus segment is located in the first non-display area. The technical solution provided by this invention reduces the width of the side bezels of the display panel, further achieving a narrow bezel design.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are display panels that emit light through carrier injection and recombination driven by an electric field. Compared to liquid crystal display panels, OLED display panels are thinner and lighter, and have better viewing angles and contrast, thus attracting widespread attention.

[0003] To achieve narrow bezels in OLED displays, existing technologies employ fanout in AA (FIAA) technology. Specifically, metal traces are added in the row and column directions of the display area as FIAA traces, interconnected via transponder holes. This changes the fanout traces from the lower corner of the display panel to those extending from the display area, reducing space in the lower corner and bottom bezel, thus achieving a narrow bezel design. Summary of the Invention

[0004] This invention provides a display panel and display device to reduce the width of the side bezel of the display panel and further achieve a narrow bezel design.

[0005] In a first aspect, embodiments of the present invention provide a display panel, comprising: a display area and a non-display area surrounding the display area;

[0006] The display area includes multiple first reference voltage lines, multiple second reference voltage lines, and data lines; the data lines extend along a first direction.

[0007] The non-display area includes a first reference voltage bus and a second reference voltage bus; the first reference voltage line is electrically connected to the first reference voltage bus; the second reference voltage line is electrically connected to the second reference voltage bus.

[0008] The first reference voltage bus includes a first bus segment and a second bus segment;

[0009] The non-display area includes a fan-out area and a first non-display area located on both sides of the display area along the first direction; at least a portion of the first bus segment is located in the fan-out area; and at least a portion of the second bus segment is located in the first non-display area.

[0010] Secondly, embodiments of the present invention also provide a display device, including a display panel provided in any embodiment of the present invention.

[0011] In this invention, the display area of ​​the display panel is provided with a first reference voltage line, a second reference voltage line, and a data line extending along a first direction. The non-display area of ​​the display panel includes a first reference voltage bus and a second reference voltage bus. The first reference voltage bus is used to transmit a first reference voltage to the first reference voltage line, and the second reference voltage bus is used to transmit a second reference voltage to the second reference voltage line. The first reference voltage bus includes a first bus segment and a second bus segment. A fan-out area and a first non-display area are respectively provided on opposite sides of the display area along the first direction. At least a portion of the first bus segment is located in the fan-out area, and at least a portion of the second bus segment is located in the first non-display area. Because the buses for signals such as the first reference voltage and the second reference voltage are all located on the same layer, in this embodiment, the first reference voltage bus is located on the lower bezel where the fan-out area is located and the upper bezel where the first non-display area is located. This does not occupy the planar area of ​​the side bezel connecting the upper and lower bezels, leaving layout space for buses of other signals, reducing the resistance value of buses of other signals, and further enabling a narrow bezel design for the side bezels. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of a display panel in the prior art;

[0013] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0014] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0015] Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0016] Figure 5 for Figure 4 A magnified structural diagram of a local area B1 in the central display panel;

[0017] Figure 6 for Figure 4 A schematic diagram of another partial structure of local region B1 in the middle;

[0018] Figure 7 for Figure 4 A schematic diagram of another partial structure of local region B1 in the middle;

[0019] Figure 8 for Figure 4 A schematic diagram of another partial structure of local region B1 in the middle;

[0020] Figure 9 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0021] Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0022] Figure 11 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention;

[0023] Figure 12 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0024] Figure 13 for Figure 4 A schematic diagram of another partial structure of local region B1 in the middle;

[0025] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0026] Figure 15 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0027] Figure 16 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0028] Figure 17 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0029] Figure 18 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0030] Figure 19 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0031] Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0032] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0033] In existing technologies, to achieve a narrow bezel design for display panels, fanout-in-AA (FIAA) technology is used. This involves routing the fanout traces from the original bottom bezel of the display panel out of the display area, thereby reducing the bottom bezel width. However, during the development of this invention, the inventors discovered that the side bezels of the display panel are relatively wide, which is detrimental to the design of a narrow bezel. For example... Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a display panel in the prior art. The non-display area NA' of the display panel includes multiple buses arranged around the display area AA'. Each bus outputs a corresponding signal to the display area AA'. For example, buses BUS1' and BUS2' are used to output reference voltage, and BUS3' is used to output power signals. Along the Y' direction, side bezels are arranged on opposite sides of the display area AA', with the side having the bonding area 12' being the bottom bezel. Along the X' direction, left and right bezels are arranged on opposite sides of the display area AA'. The inventors further discovered that the bottom bezel of the prior art solution requires FIAA and fan-out routing design, so buses BUS1', BUS2', and BUS3' are all located on the side bezel. However, the side bezel of the display panel usually contains many driving circuits, and the above buses occupy a lot of space on the side bezel, which is not conducive to the narrow bezel design.

[0034] To reduce the width of the side bezel of the display panel and further achieve a narrow bezel design, embodiments of the present invention provide a display panel. Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present invention includes: a display area AA and a non-display area NA surrounding the display area AA;

[0035] The display area AA includes multiple first reference voltage lines 11, multiple second reference voltage lines 12, and data lines 23; the data lines 23 extend along the first direction Y.

[0036] The non-display area NA includes a first reference voltage bus 13 and a second reference voltage bus 14; the first reference voltage line 11 is electrically connected to the first reference voltage bus 13; and the second reference voltage line 12 is electrically connected to the second reference voltage bus 14.

[0037] The first reference voltage bus 13 includes a first bus segment 131 and a second bus segment 132;

[0038] The non-display area NA includes a fan-out area 15 located on both sides of the display area AA along the first direction Y and a first non-display area NA1; at least a portion of the first bus segment 131 is located in the fan-out area 15; at least a portion of the second bus segment 132 is located in the first non-display area NA1.

[0039] In this embodiment of the invention, the display area of ​​the display panel is provided with a first reference voltage line, a second reference voltage line, and a data line extending along a first direction. The non-display area of ​​the display panel includes a first reference voltage bus and a second reference voltage bus. The first reference voltage bus is used to transmit a first reference voltage to the first reference voltage line, and the second reference voltage bus is used to transmit a second reference voltage to the second reference voltage line. The first reference voltage bus includes a first bus segment and a second bus segment. A fan-out area and a first non-display area are respectively provided on opposite sides of the display area along the first direction. At least a portion of the first bus segment is located in the fan-out area, and at least a portion of the second bus segment is located in the first non-display area. In this embodiment, the first reference voltage bus is located on the lower bezel where the fan-out area is located and the upper bezel where the first non-display area is located, without occupying the planar area of ​​the side bezel connecting the upper and lower bezels. This leaves layout space for buses of other signals, reduces the resistance value of buses of other signals, and further enables a narrow bezel design for the side bezel.

[0040] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0041] The display panel includes a substrate and a driving circuit layer disposed on one side of the substrate. The display panel includes a display area AA and a non-display area NA, with the non-display area NA surrounding the display area AA. Data lines 23 extending along a first direction Y are disposed within the display area AA, wherein the first direction Y is parallel to the plane of the substrate of the display panel. The display area AA of the driving circuit layer also includes pixel driving circuits arranged in an array. Figure 2 (Not shown in the image), the driving circuit layer also includes a light-emitting element on the side away from the substrate. The pixel driving circuit outputs a driving current to the light-emitting element to make the light-emitting element emit light. Data line 23 is used to provide data signals to the pixel driving circuit.

[0042] The display area AA also includes a first reference voltage line 11 and a second reference voltage line 12. The first reference voltage line 11 is electrically connected to the first reference voltage bus 13 and receives the first reference voltage signal vref1. The first reference voltage line 11 is also used to transmit the first reference voltage signal vref1 to the pixel driving circuit. The second reference voltage line 12 is electrically connected to the second reference voltage bus 14 and receives the second reference voltage signal vref2. The second reference voltage line 12 is also used to transmit the second reference voltage signal vref2 to the pixel driving circuit.

[0043] Continue to refer to Figure 2Along the first direction Y, a fan-out area 15 and a first non-display area NA1 are respectively provided on opposite sides of the display area AA. The fan-out area 15 is located in the lower step area of ​​the display panel. Within the lower step area, a bonding area 151 is also provided on the side of the fan-out area 15 away from the display area AA. The bonding area 151 is used to bond the driver chip. The pad terminals of the driver chip are electrically connected to the data line 23 through the fan-out traces in the fan-out area 15, for outputting signals to the corresponding data line 23. The first reference voltage bus 13 includes at least a first bus segment 131 and a second bus segment 132. At least a portion of the first bus segment 131 is located in the fan-out area 15, and at least a portion of the second bus segment 132 is located in the first non-display area NA1. The fan-out area 15 and the first non-display area NA1 are connected via a side non-display area. Compared to the case where both the first reference voltage bus 13 and the second reference voltage bus 14 are located in the side non-display area, this embodiment places the first reference voltage bus 13 in both the first non-display area NA1 and the fan-out area 15. That is, this embodiment places the first reference voltage bus 13 in both the top and bottom bezels, effectively saving the width of the side non-display area and achieving a narrow bezel design for the display panel's side bezels. Furthermore, because this embodiment can also combine FIAA technology to reduce the width of the bottom bezel occupied by the fan-out traces and reduce the width of the fan-out area 15 along the first direction Y, it achieves a narrow bezel design for the bottom bezel of the display panel. This embodiment can simultaneously achieve narrowing of both the side and bottom bezels, increasing the screen-to-body ratio of the entire display panel and improving the image display effect.

[0044] Optionally, the first reference voltage vref1 is a reset signal provided to the pixel circuit, such as the reset signal of the control terminal of the driving transistor in the pixel driving circuit, or the reset signal of the light-emitting element. This embodiment does not impose any special limitations on this.

[0045] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Optionally, the non-display area NA may further include a second non-display area NA2 and a third non-display area NA3 located on both sides of the display area AA along the second direction X; the second direction X intersects with the first direction Y; the first non-display area NA1 is respectively arranged adjacent to the second non-display area NA2 and the third non-display area NA3; the second reference voltage bus 14 includes at least a third bus segment 141 and a fourth bus segment 142; at least a portion of the third bus segment 141 is located in the second non-display area NA2; at least a portion of the fourth bus segment 142 is located in the third non-display area NA3.

[0046] like Figure 3As shown, in this embodiment, along the first direction Y, the first non-display area NA1 and the fan-out area 15 are disposed on opposite sides of the display area AA; along the second direction X, the second non-display area NA2 and the third non-display area NA3 are disposed on opposite sides of the display area AA. The first non-display area NA1 is adjacent to both the second non-display area NA2 and the third non-display area NA3; the fan-out area 15 is adjacent to both the second non-display area NA2 and the third non-display area NA3. In this embodiment, the second direction X and the first direction Y intersect; optionally, the second direction X and the first direction Y can be perpendicular to each other.

[0047] The second reference voltage bus 14 may include a third bus segment 141 and a fourth bus segment 142. At least a portion of the third bus segment 141 is disposed in the second non-display area NA2, and at least a portion of the fourth bus segment 142 is disposed in the third non-display area NA3. In this embodiment, the first bus segment 131 of the first reference voltage bus 13 is located in the fan-out area 15, and the second bus segment 132 is located in the first non-display area NA1; the third bus segment 141 of the second reference voltage bus 14 is located in the second non-display area NA2, and the fourth bus segment 142 is located in the third non-display area NA3. That is, the first reference voltage bus 13 is located on both sides of the non-display area along the first direction Y of the display panel, and the second reference voltage bus 14 is located on both sides of the non-display area along the second direction X of the display panel. The first reference voltage bus 13 and the second reference voltage bus 14 are not arranged side by side in the same non-display area, so that the fan-out area 15, the first non-display area NA1, the second non-display area NA2, and the third non-display area NA3 are not occupied by multiple side-by-side buses, reducing the width of the non-display area and further realizing the narrow bezel design of the display panel. Compared to Figure 1 In the scheme shown, this embodiment places the first reference voltage bus 13 on the upper and lower borders, effectively reducing the space occupied by the side borders, facilitating the wiring and setting of the second reference voltage bus 14 on the side borders, reducing the transmission resistance of the second reference voltage bus 14, effectively reducing the overlap of signal lines on the side borders, and optimizing the transmission performance of each signal line.

[0048] Continue to refer to Figure 3 Optionally, adjacent non-display areas NA can be connected via a rounded corner area 16. To enhance the user and viewing experience of the display panel, the display panel in this embodiment can be a rounded corner screen, specifically, as shown below. Figure 3 As shown, two adjacent non-display areas NA can be connected by a rounded corner region 16. For example, the first non-display area NA1 and the second non-display area NA2 are connected by the rounded corner region 16. The rounded corner region 16 makes the display panel form a rounded rectangular plane. Display panels with curved edges are not only aesthetically pleasing but also less prone to damage, while display panels with right angles are easily damaged by force during use.

[0049] like Figure 3 As shown, optionally, the first non-display area NA1 and the second non-display area NA2 can be connected through the first rounded corner area 161; the first non-display area NA1 and the third non-display area NA3 can be connected through the second rounded corner area 162; the second bus segment 132 includes a first portion 1311 located in the first rounded corner area 161 and / or a second portion 1312 located in the second rounded corner area 162. Optionally, the second bus segment 132 can be partially or entirely disposed in the first non-display area NA1. Figure 3 The illustration takes the second bus segment 132 partially located in the first non-display area NA1 as an example. Since adjacent non-display areas NA1 are connected via a radius (R-corner) 16, in this embodiment, to further extend the length of the second bus segment 132 and optimize the resistance value of the first reference voltage bus 13, the second bus segment 132 can be extended to the radius (R-corner) 16 on both sides of the first non-display area NA1. Specifically, as shown... Figure 3 As shown, a first R-corner region 161 and a second R-corner region 162 are provided on both sides of the first non-display area NA1. The portion of the second bus segment 132 extending to the first R-corner region 161 can be the first portion 1311, and the portion of the second bus segment 132 extending to the second R-corner region 162 can be the second portion 1312. In this embodiment, the second bus segment 132 can include at least one of the first portion 1311 and the second portion 1312. On the one hand, in this embodiment, the first reference voltage bus 13 and the second reference voltage bus 14 are respectively set in different non-display areas, thereby reducing the bezel width, especially the width of the side bezel. On the other hand, in this embodiment, the second bus segment 132 located in the first non-display area NA1 is extended to the R-corner region 16, which can effectively increase the length of the first reference voltage bus 13. This facilitates the direct provision of the first reference voltage signal vref1 to more first reference voltage lines 11, rather than the mutual transmission of the first reference voltage signal vref1 through other first reference voltage lines 11. This helps to reduce the voltage drop of the first reference voltage signal vref1 on the first reference voltage line 11 and improves the power supply effect of the first reference voltage bus 13 to the pixel driving circuit. It is understandable that the display area of ​​the display panel, including the R-corner area, usually has a setting corresponding to the shape of the R-corner area. That is, the R-corner area also corresponds to a part of the pixel driving circuit. Extending the second bus segment 132 of the first non-display area NA1 to the R-corner area 16 can connect all the pixel driving circuits in the display area to the second bus segment 132, thereby improving the power supply effect of the first reference voltage line 11.

[0050] Continue to refer to Figure 3Optionally, the fan-out area 15 and the second non-display area NA2 can be connected via the third rounded corner area 163; the fan-out area 15 and the third non-display area NA3 can be connected via the fourth rounded corner area 164; the first bus segment 131 includes a third portion 1313 located in the third rounded corner area 163 and / or a fourth portion 1314 located in the fourth rounded corner area 164. Similarly, the first bus segment 131 can be partially or entirely located in the fan-out area 15. Figure 3 The illustration takes the first bus segment 131 partially located in the fan-out area 15 as an example. In this embodiment, to further extend the length of the first bus segment 131 and optimize the resistance value of the first reference voltage bus 13, the first bus segment 131 can be extended to the R-corner areas 16 on both sides of the first non-display area NA1. Specifically, as shown... Figure 3 As shown, a third R-corner region 163 and a fourth R-corner region 164 are provided on both sides of the fan-out region 15. The first bus segment 131 can be extended to the third R-corner region 163 to form a third part 1313, and the first bus segment 131 can also be extended to the fourth R-corner region 164 to form a fourth part 1314. Alternatively, the first bus segment 131 can be extended to both the third R-corner region 163 and the fourth R-corner region 164 to form the third part 1313 and the fourth part 1314, respectively. In this embodiment, extending the first bus segment 131 in the fan-out region 15 to the R-corner region 16 can effectively increase the length of the first reference voltage bus 13, making it easier to provide the first reference voltage signal vref1 to more first reference voltage lines 11, and improving the power supply effect of the first reference voltage bus 13 on the pixel driving circuit. It is understandable that the display area of ​​the display panel, including the R-corner area, usually has a corresponding setting corresponding to the shape of the R-corner area. That is, the R-corner area also corresponds to a part of the pixel driving circuit. Extending the first bus segment 131 of the fan-out area 15 to the R-corner area 16 can connect all the pixel driving circuits in the display area to the first bus segment 131 and its extension (the third part 1313 and / or the fourth part 1314), thereby improving the power supply effect of the first reference voltage line 11.

[0051] Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 5 for Figure 4 A partial structural schematic diagram of a local area B1. Optionally, the display area AA may include an array of pixel driving circuits 18; the display area AA includes a first irregular region 17; the first irregular region 17 is adjacent to the R-corner region 16, and the multiple pixel driving circuits 18 in the first irregular region 17 are distributed in a stepped manner; the first bus segment 131 and the second bus segment 132 extend along the edge of the first irregular region 17.

[0052] like Figure 4As shown, the display area AA includes an array of pixel driving circuits 18. The display area AA also includes a first reference voltage line 11 extending along a first direction Y and / or along a second direction X, and a second reference voltage line 12 extending along the first direction Y and / or along the second direction X. The first reference voltage line 11 and the second reference voltage line 12 intersect to define an area where the pixel driving circuit 18 can be disposed. For example, Figure 4 The display panel includes a first reference voltage line 11 extending along a first direction Y and a second direction X, and a second reference voltage line 12 extending along the first direction Y and the second direction X. To facilitate the distinction between the first reference voltage line 11 and the second reference voltage line 12, this embodiment uses a solid line to represent the first reference voltage line 11 and a dashed line to represent the second reference voltage line 12.

[0053] As can be seen from the above embodiments, adjacent non-display areas are connected by the R-corner region 16. Therefore, the portion of the display area AA in the display panel that is adjacent to the R-corner region 16 is also an irregular structure, such as... Figure 4 As shown, the display area AA includes a first irregularly shaped area 17, which is adjacent to the R-corner area 16. Figure 5 As shown, Figure 5 for Figure 4 This is an enlarged structural diagram of a portion of the display panel, specifically area B1. It's important to note that area B1 only captures a portion of the structure of the first irregularly shaped area 17 and a portion of the rounded corner area 16, thus clearly revealing the structure of the display panel at the boundary between these two areas. Figure 5 As shown, within the first irregular region 17, the pixel driving circuits 18 are distributed in a stepped manner along the extension direction of the first reference voltage line 11. Because the portion of the first reference voltage line 11 extending to the R-corner region 16 is curved, the pixel driving circuits 18 form a stepped arrangement. If the pixel driving circuits 18 are arranged in rows along the second direction Y, then along the first direction Y, the number of pixel driving circuits 18 in each row gradually decreases, resulting in a stepped arrangement at the edge of the first irregular region 17. Figure 5 As shown, Figure 5 The diagram only shows a portion of the metal film layer of the driving circuit layer, specifically two metal layers, one of which is the film layer for setting the first reference voltage line 11. In this embodiment, the portion of the second bus segment 132 extending to the R-corner region 16 can be set along the edge of the first irregular region 17, that is, the second bus segment 132 in the R-corner region 16 is also stepped. The stepped second bus segment 132 can be set close to the edge of the first irregular region 17, effectively saving the space occupied by the second bus segment 132 in the R-corner region 16, making it easier to leave layout space for other circuits and traces in the R-corner region 16, and reducing the width of the R-corner region 16, further realizing the narrow bezel design of the R-corner region 16. Figure 4 and Figure 5 As shown, the portion of the second bus segment 132 extending to the first R-corner region 161 is the first portion 1311, and the first portion 1311 is arranged along the stepped pixel driving circuit 18. Furthermore, as... Figure 4 As shown, the portion of the first bus segment 131 extending to the R-corner region 16 can also extend along the edge of the first irregular region 17. Thus, the first bus segment 131 is also arranged in a stepped manner in the R-corner region 16. This not only enables the first bus segment 131 to be electrically connected to the pixel circuits corresponding to the R-corner region 16, but also improves space utilization, reduces the space occupied by the R-corner region 16, and further realizes the narrow bezel design of the display panel.

[0054] Continue to refer to Figure 3 and Figure 4 Optionally, the third bus segment 141 and the fourth bus segment 142 may extend along the edge of the first irregular region 17. In this embodiment, the third bus segment 141 may be located only in the second non-display area NA2, or it may extend from the second non-display area NA2 to the R-corner region 16. Figure 3 As shown, the second non-display area NA2 is adjacent to the first R-corner area 161 and the third R-corner area 163, respectively. Therefore, the third bus segment 141 can extend to the first R-corner area 161 and / or the third R-corner area 163, increasing the length of the third bus segment 141. This allows the third bus segment 141 to connect more second reference voltage lines 12, thereby directly providing the second reference voltage signal vref2 to more second reference voltage lines 12, instead of transmitting the second reference voltage signal vref2 between other second reference voltage lines 12. This helps reduce the voltage drop of the second reference voltage signal vref2 on the second reference voltage lines 12, improving the power supply effect of the second reference voltage bus 14 to the pixel driving circuit. Similarly, the fourth bus segment 142 can be extended to the second R-corner region 162 and / or the fourth R-corner region 164, increasing the length of the fourth bus segment 142 so that the fourth bus segment 142 can connect more second reference voltage lines 12, reduce the voltage drop of the second reference voltage signal vref2 on the second reference voltage line 12, and improve the power supply effect of the second reference voltage bus 14 to the pixel driving circuit.

[0055] Figure 6 for Figure 4 Another partial structural diagram of local area B1. When the display area adjacent to the R-corner area 16 includes a first irregularly shaped area 17, and the edge of the first irregularly shaped area 17 includes pixel driving circuits 18 arranged in a stepped manner, then the portions of the third bus segment 141 and the fourth bus segment 142 extending to the R-corner area 16 can extend along the edge of the first irregularly shaped area 17, that is, along the steppedly arranged pixel driving circuits 18. For example, as shown... Figure 6As shown, the portion of the third bus segment 141 extending into the first R-corner region 161 forms a stepped shape, and the portion of the second bus segment 132 extending into the first R-corner region 161 is also stepped. In this embodiment, the stepped arrangement of the first reference voltage bus 13 and the second reference voltage line 12 in the R-corner region 16 further reduces the area occupied by the aforementioned buses in the R-corner region 16, reduces the border width of the R-corner region 16, and further realizes the narrow border design of the R-corner region 16.

[0056] Figure 7 for Figure 4 Another partial structural diagram of local region B1 in the middle. Figure 8 for Figure 4 Another partial structural diagram of local area B1. Optionally, the display panel may further include: a shielding bus 19; the shielding bus 19 extends along the edge of the first irregular region 17; in the first irregular region 17, the shielding bus 19 includes a linear first bus 191 and a stepped second bus 192; the first reference voltage bus 13 in the first irregular region 17 includes multiple segments of a first stage 133 extending along a first direction Y and a second stage 134 extending along a second direction X; the stepped second bus 192 in the first irregular region 17 includes multiple segments of a third stage 193 extending along the first direction Y and a fourth stage 194 extending along the second direction X; there is an overlapping area between the second stage 134 and the fourth stage 194.

[0057] In this embodiment, a shielding layer M0 may also be disposed between the substrate and the driving circuit layer. In a plane parallel to the substrate, the shielding layer M0 overlaps with the active layer 18a of the driving transistor in the pixel driving circuit, thereby preventing leakage current from the driving transistor. Furthermore, the shielding layer needs to be applied with a fixed potential to prevent it from floating, thus avoiding any impact on other metal layers. Figure 7 As shown, Figure 7 Only two film layers, the masking layer and the active layer 18a, are shown in this embodiment. In this embodiment, a masking bus 19 can also be formed in the masking layer. The masking bus 19 can be arranged around the display area. Within the first irregular region 17, the masking bus 19 includes a linear first bus 191 and a stepped second bus 192. The linear first bus 191 is arranged linearly along the edge of the first irregular region 17. The stepped second bus 192 includes a third stage 193 extending along the first direction Y and a fourth stage 194 extending along the second direction X. The third stage 193 and the fourth stage 194 are alternately connected to form a stepped shape. The first bus 191 and the stepped second bus 192 are electrically connected to form a bus assembly. In this embodiment, setting the masking bus 19 can simultaneously provide masking layers M0 corresponding to multiple rows of pixel driving circuits at multiple connection points, reducing the resistance value of the masking layer M0 and reducing the voltage drop (IR drop) of the masking layer M0.

[0058] Continue to refer to Figure 8 , Figure 8 The substrate contains only a shielding layer M0 and a metal layer M3 on which the first reference voltage bus 13 is disposed. In the first irregular region 17, the first reference voltage bus 13 includes multiple segments of a first stage 133 extending along a first direction Y and a second stage 134 extending along a second direction X. The first stage 133 and the second stage 134 are alternately connected to form a stepped shape. Because the first reference voltage bus 13 and the shielding bus 19 are located in different film layers, in a plane parallel to the substrate, the fourth stage 194 of the stepped second bus 192 extending along the second direction X overlaps with the second stage 134 of the first reference voltage bus 13 extending along the second direction X in a region B2. The design of the overlapping area B2 can improve the utilization of planar space, save space in the R-corner area in the plane parallel to the substrate, and the overlap of the first reference voltage bus 13 and the shielding bus 19 can improve the transmission effect and stability of the first reference voltage signal on the first reference voltage bus 13, so that the pixel driving circuit is completely reset in the reset phase without affecting the conduction of the pixel driving circuit in the next frame time, thereby enhancing the reliability of the pixel driving circuit and improving the display effect of the display panel.

[0059] Figure 9 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Optionally, the first reference voltage bus 13 may further include a fifth bus segment 135; the fifth bus segment 135 is located in the second non-display area NA2. In this embodiment, the first reference voltage bus 13 may also be provided on one side bezel, such as... Figure 9 As shown, a fifth bus segment 135 can be set within the second non-display area NA2. Optionally, the second bus segment 132, the fifth bus segment 135, and the first bus segment 131 are electrically connected sequentially to extend the total length of the first reference voltage bus 13. In this embodiment, the first reference voltage bus 13 is not set on the side bezel where the third non-display area NA3 is located. Therefore, while ensuring a reduction in the width of the side bezel, this embodiment extends the first reference voltage bus 13 to the second non-display area NA2 to connect the first reference voltage lines corresponding to more rows of pixel driving circuits, reducing the loss of the first reference voltage lines during transmission, improving the reliability of the pixel driving circuit, and thus improving the reliability of the entire display panel.

[0060] Figure 10This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Optionally, the first reference voltage bus 13 may further include a sixth bus segment 136; the sixth bus segment 136 is located in the third non-display area NA3. In this embodiment, a sixth bus segment 136 is also formed in the third non-display area NA3. Optionally, the second bus segment 132, the fifth bus segment 135, the first bus segment 131, and the sixth bus segment 136 can be electrically connected sequentially, effectively extending the first reference voltage bus 13. This allows for the connection of more rows of first reference voltage lines corresponding to pixel driving circuits through multiple connection terminals, reducing the loss of the first reference voltage lines during transmission, improving the reliability of the pixel driving circuits, and thus improving the reliability of the entire display panel. Optionally, along the second direction X, the width d1 of the fifth bus segment 135 may be smaller than the width d2 of the third bus segment 141; the width d3 of the sixth bus segment 136 may be smaller than the width d4 of the fourth bus segment 142. To further reduce the space occupied by the first reference voltage bus 13 in the side bezel, in this embodiment, the width d1 of the fifth bus segment 135 can be set to be smaller than the width d2 of the third bus segment 141, and the width d3 of the sixth bus segment 136 can be smaller than the width d4 of the fourth bus segment 142. Therefore, the widths of the first reference voltage bus 13 in both the second non-display area NA2 and the third non-display area NA3 are smaller than the widths of the second reference voltage bus 14 in both areas. Thus, although the side bezel in this embodiment simultaneously includes the first reference voltage bus 13 and the second reference voltage bus 14, the width of the first reference voltage bus 13 is smaller, occupying less side bezel width, which is beneficial for the narrow bezel design of the display panel.

[0061] Optionally, the first bus segment 131, the fifth bus segment 135, the second bus segment 132, and the sixth bus segment 136 can be connected sequentially to form a ring. In this embodiment, the first bus segment 131, the fifth bus segment 135, the second bus segment 132, and the sixth bus segment 136 can be set individually, and each of the first bus segment 131, the fifth bus segment 135, the second bus segment 132, and the sixth bus segment 136 can output a first reference voltage signal to the first reference voltage line, which can also increase the length of the first reference voltage bus and reduce the loss of the first reference voltage signal during transmission. In this embodiment, the first bus segment 131, the fifth bus segment 135, the second bus segment 132, and the sixth bus segment 136 can be connected to form a ring. When inputting the first reference voltage signal to the first reference voltage bus 13, only one input terminal needs to be set, and it is not necessary to set input terminals for the first bus segment 131, the fifth bus segment 135, the second bus segment 132, and the sixth bus segment 136 separately, simplifying the wiring design and further reducing the width of each bezel.

[0062] Figure 11This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention. Optionally, the first reference voltage bus 13 and the second reference voltage bus 14 may be located in different film layers; the fifth bus segment 135 and the third bus segment 141 at least partially overlap; and / or, the sixth bus segment 136 and the fourth bus segment 142 at least partially overlap. Figure 11 As shown, the display panel includes a substrate 100 and a driving circuit layer 101 disposed on one side of the substrate 100. In the display area AA, the driving circuit layer 101 includes an array of pixel driving circuits, each pixel driving circuit including multiple thin-film transistors T. In the non-display area NA, the first reference voltage bus 13 and the second reference voltage bus 14 can be located on different metal layers. When the first reference voltage bus 13 is provided with a fifth bus segment 135 and a sixth bus segment 136, the first reference voltage bus 13 and the second reference voltage bus 14 can be at least partially overlapped, reducing the occupancy of the side bezel's planar space, improving the planar space utilization of the display panel, and facilitating the narrow bezel design of the display panel's side bezels. For example, as... Figure 11 As shown, the driving circuit layer 101 may include a shielding layer M0, an active layer 18a, a gate layer 102, an intermediate metal layer 103, a source / drain layer 104, a third metal layer M3, and a fourth metal layer M4, sequentially located away from the substrate 100. The first reference voltage bus 13 may be disposed on the fourth metal layer M4, and the second reference voltage bus 14 may be disposed on the third metal layer M3. Therefore, in a plane parallel to the substrate 100, the fifth bus segment 135 and the third bus segment 141 may have an overlapping region, and the sixth bus segment 136 and the fourth bus segment 142 may also have an overlapping region. Furthermore, as... Figure 11 As shown, the display area AA also includes a data line 11 disposed on the same layer as the second reference voltage bus 14. The data line 11 is electrically connected to the source or drain of the thin film transistor T. The display area AA also includes an auxiliary trace 61 disposed on the same layer as the first reference voltage bus 13. The auxiliary trace 61 is the FIAA trace, which is used to transfer the fan-out line of the data line near the R-corner area to the display area AA.

[0063] Optionally, the first reference voltage bus 13 and the second reference voltage bus 14 can be arranged on the same layer. It is understood that the first reference voltage bus 13 and the second reference voltage bus 14 can be arranged on the same layer; for example, both the first reference voltage bus 13 and the second reference voltage bus 14 can be arranged on the third metal layer M3. In this embodiment, to reduce the planar space occupied by the first reference voltage bus 13 and the second reference voltage bus 14, the width of a portion of the first reference voltage bus 13 can be controlled to be smaller than the width of the second reference voltage bus 14, thereby achieving a narrow bezel design for the display panel and improving the user viewing experience.

[0064] Continue to refer to Figure 3Optionally, the first reference voltage line 11 may include a first connecting line 111 extending along a first direction Y and a second connecting line 112 extending along a second direction X; the first connecting line 111 and the second connecting line 112 are electrically connected; the second reference voltage line 12 includes a third connecting line 121 extending along the first direction Y and a fourth connecting line 122 extending along the second direction X; the third connecting line 121 and the fourth connecting line 122 are electrically connected; the first connecting line 111 is connected to the first bus segment 131 and the second bus segment 132 respectively; the fourth connecting line 122 is connected to the third bus segment 141 and the fourth bus segment 142 respectively.

[0065] In this embodiment, the first reference voltage line 11 can form a grid structure in the display area. Specifically, the first reference voltage line 11 includes a first connecting line 111 extending in the first direction Y and a second connecting line 112 extending in the second direction X, such as... Figure 3 As shown, at the intersection of the first connecting line 111 and the second connecting line 112, the first connecting line 111 and the second connecting line 112 can be electrically connected through vias. Similarly, the second reference voltage line 12 can also form a grid structure in the display area, specifically including a third connecting line 121 extending in the first direction Y and a fourth connecting line 122 extending in the second direction X, and the third connecting line 121 and the fourth connecting line 122 are electrically connected through vias.

[0066] In this embodiment, since the first reference voltage bus 13 is located in the fan-out area 15 and the first non-display area NA1, the first connecting line 111 extending along the first direction Y is connected to the first bus segment 131 and the second bus segment 132 respectively to obtain the first reference voltage signal vref1 and transmit it to the second connecting line 112. Similarly, the second reference voltage line 12 is located in the second non-display area NA2 and the third non-display area NA3, and the fourth connecting line 122 extending along the second direction X is connected to the third bus segment 141 and the fourth bus segment 142 respectively to obtain the second reference voltage signal vref2 and send it to the third connecting line 121. It should be noted that because the length of the top and bottom bezels is less than the width of the side bezels, that is, the lengths of the fan-out area 15 and the first non-display area NA1 are relatively small, this embodiment can set a bus branch 137 in the non-display area NA. In this embodiment, the first reference voltage signal vref1 is transmitted to the bus branch 137 through multiple input terminals. The bus branch 137 is connected to each of the first connection lines 111 nearby, thereby improving the power supply capability of the first reference voltage bus 13 to the driving pixel circuit. In addition, as Figure 2 As shown, the first reference voltage line 11 may only have a first connecting line 111 extending along the first direction Y, and the second reference voltage line 12 may only have a fourth connecting line 122 extending along the second direction X, so as to reduce the wiring density of the display area.

[0067] Figure 12This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 12 The structure of the first reference voltage line 11 and the second reference voltage line 12 is omitted, and only the power lines are shown separately. Optionally, the display area AA may further include: a first power line 21 and a second power line 22 extending along the second direction X; the non-display area NA further includes a first power bus 25 and a second power bus 24; the first power bus 25 is connected to the first power line 21; the second power bus 24 is connected to the second power line 22; the first power bus 25 includes a portion located in the second non-display area NA2 and the third non-display area NA3 and a portion extending to the R-corner area 16; and / or, the second power bus 24 includes a portion located in the second non-display area NA2 and the third non-display area NA3 and a portion extending to the R-corner area 16.

[0068] The buses within the non-display area NA, in addition to the first reference voltage bus 13 and the second reference voltage bus 14, also include a first power supply bus 25 and a second power supply bus 24, for example, as shown below. Figure 12 As shown, in the direction away from the display area AA, the buses in the non-display area NA are sequentially arranged as follows: a reference voltage bus 13, a second reference voltage bus 14, a first power bus 25, and a second power bus 24. The first power bus 25 may include portions located in the second non-display area NA2 and the third non-display area NA3, and a portion extending to the R-corner region 16. Similarly, the second power bus 24 may also include portions located in the second non-display area NA2 and the third non-display area NA3, and a portion extending to the R-corner region 16. The display area AA is provided with a first power line 21 and a second power line 22, both extending along the second direction X. The first power line 21 is used to obtain a first power signal PVDD from the first power bus 25 and transmit it to each pixel driving circuit. The second power line 22 obtains a second power signal PVEE from the second power bus 24 and transmits it to each pixel driving circuit. This embodiment illustrates a scenario with a large number of buses. These buses are typically located on the third metal layer M3. When there are many buses, the first reference voltage bus 13 is only located in the fan-out area 15 and the first non-display area NA1, occupying the area of ​​the top and bottom bezels. The remaining buses are located in the second non-display area NA2 and the third non-display area NA3, occupying the space of the side bezels. This embodiment effectively balances the bus settings of each bezel, resulting in a smaller overall bezel width for the display panel, thus meeting the user's requirement for narrow bezels.

[0069] Furthermore, the display panel may also include a first power line 21 and a second power line 22 extending along the second direction Y. Both the first power line 21 and the second power line 22 can then form a grid pattern. Figure 13 for Figure 4 A schematic diagram of another partial structure of local region B1. (See diagram below.) Figure 13As shown, the second power bus 24 can be designed in the first irregular region 17 to form a linear second power bus 241 and a stepped second power bus 242, in order to reduce the resistance value of the second power bus 24, thereby reducing the loss of the second power signal PVEE during transmission. Similarly, the first power bus 25 can also be a combination of the above-mentioned linear and stepped shapes to improve the signal transmission effect of the first power signal PVDD.

[0070] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Optionally, the display panel may include: a touch trace 106 connected to the touch electrode 105; a fan-out area 15 including multiple leads; the leads include at least: a first reference voltage lead 31, a first power lead 32, a second power lead 33, a second reference voltage lead 34, and a touch lead 35; the first reference voltage lead 31 is electrically connected to a first reference voltage bus; the second reference voltage lead 34 is electrically connected to a second reference voltage bus; the touch lead 35 is electrically connected to the touch trace; the first power lead 32 is connected to a first power bus 25; the second power lead 33 is connected to a second power bus 24; along the second direction X, the second reference voltage lead 34 is located between the first reference voltage lead 31 and the touch lead 35. Figure 14As shown, the fan-out area 15 is provided with a signal transmission route from the bonding area 151 to the corresponding fan-out line. Specifically, the fan-out area 15 includes a first reference voltage lead 31, a first power supply lead 32, a second power supply lead 33, and a second reference voltage lead 34. The first reference voltage lead 31 transmits the first reference voltage signal vref1 to the first reference voltage bus; the second reference voltage lead 34 transmits the second reference voltage signal vref2 to the second reference voltage bus; the first power supply lead 32 transmits the first power signal PVDD to the first power bus 25; and the second power supply lead 33 transmits the second power signal PVEE to the second power bus 24. For a display panel with touch functionality, multiple touch electrodes 105 and touch traces 106 connecting to the touch electrodes 105 are provided, and the corresponding fan-out area 15 is provided with touch leads 35. Along the second direction X, multiple touch leads 35 are disposed at the center, and other leads are disposed on both sides of the touch leads 35. There is a gap between the touch leads 35 and the other leads. In this embodiment, the second reference voltage lead 34 is located between the first reference voltage lead 31 and the touch leads 35. Thus, the second reference voltage lead 34 can be disposed at the above-mentioned gap, providing a large placement space. In this embodiment, the width of the second reference voltage lead 34 can also be set to be greater than that of the other leads, reducing the resistance of the second reference voltage lead 34 and reducing the loss of the second reference voltage signal vref2 during transmission. If the second reference voltage signal vref2 is used to reset the light-emitting element, this embodiment can provide a strong guarantee for the reset of the light-emitting element, improve the display effect of the display panel, and avoid afterimages during the display process.

[0071] Continue to refer to Figure 14 Optionally, the non-display area NA may further include: a bonding area 151; the bonding area 151 is located on the side of the fan-out area 15 away from the display area AA; the bonding area 151 includes a plurality of pads 411; the pads 411 are respectively connected to corresponding leads; along the second direction X, the pads 411 connected to the second reference voltage lead 34 are located between the pads 411 connected to the first power lead 32 and the pads 411 connected to the second power lead 33; the second reference voltage lead 34 crosses the first reference voltage lead 31 and connects to the corresponding pads 411 via jumpers. In this embodiment, the bonding area 151 is provided with pads 411 corresponding one-to-one with the fan-out leads. Although this embodiment sets the position of the second reference voltage lead 34 on the side of the first reference voltage lead 31 closer to the touch lead 35, the path order of existing driver chips is that the pads 411 of the second reference voltage lead 34 are located on the side of the first reference voltage lead 31 away from the touch lead 35. Specifically, as Figure 14As shown, the second reference voltage lead 34 crosses the first reference voltage lead 31 and the first power supply lead 32 via a jumper wire, connecting to its corresponding pad 411. Therefore, this embodiment does not require changes to the existing design of the driver chip, and while ensuring a large width for the second reference voltage lead 34, effectively reduces the manufacturing cost of the display panel by connecting the corresponding pad via a jumper wire.

[0072] Figure 15 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Optionally, the display area AA may further include an adjustment signal line 51; the non-display area NA may further include an adjustment signal bus 52; the adjustment signal bus 52 is electrically connected to the adjustment signal line 51; the adjustment signal bus 52 includes a seventh bus segment 53 and an eighth bus segment 54; the seventh bus segment 53 is located in the second non-display area NA2; the eighth bus segment 54 is located in the third non-display area NA3. The adjustment signal bus 52 can output an adjustment signal to the adjustment signal line 51 of the display area AA, so that the adjustment signal line 51 transmits the adjustment signal to the pixel driving circuit and is used to adjust the bias state of the driving transistor in the pixel driving circuit. The adjustment signal bus 52 includes a seventh bus segment 53 and an eighth bus segment 54. The seventh bus segment 53 is located in the second non-display area NA2, and the eighth bus segment 54 is located in the third non-display area NA3. Optionally, the seventh bus segment 53 extends to the rounded corner areas 16 on both sides of the second non-display area NA2, and the eighth bus segment 54 extends to the rounded corner areas 16 on both sides of the third non-display area NA3. This enhances the power supply effect of the adjustment signal bus 52 to the pixel driving circuit, effectively prevents bias problems of the driving transistors, and improves the accuracy of the display panel image. It should be noted that the specific film layers of the adjustment signal bus 52 are as follows... Figure 5 As shown, the adjustment signal bus 52 is located on the side of the second reference voltage bus 14 away from the display area.

[0073] Continue to refer to Figure 15Optionally, the adjustment signal line 51 may include a fifth connecting line 511 extending along the first direction Y and a sixth connecting line 512 extending along the second direction X; the fifth connecting line 511 and the sixth connecting line 512 are electrically connected; the sixth connecting line 512 is electrically connected to the seventh bus segment 53 and the eighth bus segment 54, respectively. In this embodiment, the fifth connecting line 511 extending along the first direction Y and the sixth connecting line 512 extending along the second direction X form a grid-like adjustment signal line 51, reducing the loss of the adjustment signal during transmission and improving the control performance of the adjustment signal on the pixel driving circuit. In addition, the display area AA may also be provided with a first reference voltage line 11, which may include a first connecting line 111 extending along the first direction Y and a second connecting line 112 extending along the second direction X, to reduce the loss of the first reference voltage signal vref1 during transmission. The second reference voltage line 12 includes a fourth connecting line 122 extending along the second direction X. Of course, in this embodiment, a third connecting line ( ) extending along the first direction Y of the second reference voltage line 12 may also be provided. Figure 15 (Not shown in the image). In this embodiment, a grid structure of adjustment signal line 51, first reference voltage line 11 and second reference voltage line 12 can be formed simultaneously in the display area to enhance the driving capability of adjustment signal bus 52, first reference voltage bus 13 and second reference voltage bus 14 for pixel driving circuit.

[0074] Continue to refer to Figure 15 Optionally, the first reference voltage bus 13, the second reference voltage bus 14, and the adjustment signal bus 52 can be configured on the same layer. For example... Figure 15 As shown, the first reference voltage bus 13, the second reference voltage bus 14, and the adjustment signal bus 52 are arranged side by side. The first reference voltage bus 13 is located in the fan-out area 15 and the first non-display area NA1 of the display panel, occupying the area of ​​the top and bottom bezels. The second reference voltage bus 14 and the adjustment signal bus 52 are located in the second non-display area NA2 and the third non-display area NA3, occupying the space of the side bezels. Thus, this embodiment effectively balances the bus settings of each bezel, making the overall bezel width of the display panel smaller, thus meeting the user's requirement for a narrow bezel.

[0075] Continue to refer to Figure 15 Optionally, the display area AA may also include an adjustment signal line 51; the non-display area NA may also include an adjustment signal bus 52; the adjustment signal bus 52 is electrically connected to the adjustment signal line 51; the lead may also include an adjustment signal lead 55; the adjusted signal lead 55 is electrically connected to the adjustment signal bus 52; along the second direction X, the second reference voltage lead 34 is located between the adjustment signal lead 55 and the touch lead 35; the adjustment signal lead 55 is located between the first reference voltage lead 31 and the second reference voltage lead 34.

[0076] Figure 15The touch traces 106 of the touch electrode 105 are omitted, and only the touch lead 35 is shown. In this embodiment, the fan-out area 15 includes an adjustment signal lead 55, which can transmit the adjustment signal to the adjustment signal bus 52, so that the adjustment signal bus 52 transmits the signal to the fifth connection line 511 and the sixth connection line 512. In the second direction X, multiple touch leads 35 are positioned at the center, with other leads positioned on either side of the touch leads 35. There are gaps between the touch leads 35 and the other leads. In this embodiment, the second reference voltage lead 34 is located between the first reference voltage lead 31 and the touch leads 35. Therefore, the second reference voltage lead 34 can be positioned at the aforementioned gaps, providing a larger setting space. In this embodiment, the width of the second reference voltage lead 34 can also be set to be greater than that of the other leads, reducing the resistance of the second reference voltage lead 34 and decreasing the loss of the second reference voltage signal vref2 during transmission. If the second reference voltage signal vref2 is used to reset the light-emitting element, this embodiment can provide strong protection for the reset of the light-emitting element, improving the display effect of the display panel and avoiding image retention during display. It should be noted that the adjustment signal lead 55 is located between the first reference voltage lead 31 and the second reference voltage lead 34. Therefore, the adjustment signal lead 55 is closer to the touch lead 35 and also has a wider setting space. The width of the adjustment signal lead 55 can be set to be greater than that of other leads to reduce the loss of the adjustment signal during transmission.

[0077] Optionally, the non-display area NA may further include: a bonding area 151; the bonding area 151 is located on the side of the fan-out area 15 away from the display area AA; the bonding area 151 includes multiple pads 411; the pads 411 are respectively connected to corresponding leads; along the second direction X, the pad 411 connected to the second reference voltage lead 34 is located between the pad 411 connected to the first power lead 32 and the pad 411 connected to the second power lead 33; the second reference voltage lead 34 is connected to the corresponding pad 411 via a jumper across the first reference voltage lead 31 and the adjustment signal lead 55. In existing driver chips, the path sequence is that the pad 411 of the second reference voltage lead 34 is located on the side of the pad 411 of the first reference voltage lead 31 away from the pad 411 of the touch lead 35. Specifically, as shown... Figure 15 As shown, the second reference voltage lead 34 crosses the first reference voltage lead 31, the adjustment signal lead 55, and the first power supply lead 32 via jumpers, connecting to its corresponding pad 411. Therefore, this embodiment does not require changes to the existing design of the driver chip. While ensuring a relatively large width for the second reference voltage lead 34 and the adjustment signal lead 55, the connection to the corresponding pads via jumpers effectively reduces the manufacturing cost of the display panel.

[0078] Optionally, the display area AA may include an array of pixel driving circuits; such as Figure 16 As shown, Figure 16This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention. The pixel driving circuit 18 includes a driving transistor 181, a first reset module 182, and a second reset module 183. The first terminal of the first reset module 182 is electrically connected to the control terminal of the driving transistor 181, and the second terminal of the first reset module 182 is electrically connected to the first reference voltage line 11. The first terminal of the driving transistor 181 is electrically connected to the first power supply line. The second terminal of the driving transistor 181 is electrically connected to the first terminal of the light-emitting element D1. The first terminal of the second reset module 183 is electrically connected to the first terminal of the light-emitting element D1, and the second terminal of the second reset module 183 is electrically connected to the second reference voltage line 12. The second terminal of the light-emitting element D1 is electrically connected to the second power supply line.

[0079] In this embodiment, the pixel driving circuit 18 includes a first reset module 182 and a second reset module 183. The first reset module 182 is used to transmit the first reference voltage signal vref1 output from the first reference voltage line 11 to the control terminal of the driving transistor 181 to reset the control terminal of the driving transistor 181 and prevent residual voltage from the previous frame from existing in the current frame. The second reset module 183 is used to transmit the second reference voltage signal vref2 output from the second reference voltage line 12 to the first terminal of the light-emitting element D1 to reset the first terminal of the light-emitting element D1 and prevent leakage current from existing in the light-emitting element D1. When the pixel driving circuit 18 needs to output driving current, the driving transistor 181 is turned on, and the first power line, the driving transistor 181, the light-emitting element D1, and the second power line are sequentially connected to form a circuit.

[0080] Figure 17 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. Optionally, the pixel driving circuit 18 may further include: a storage capacitor C1, a light-emitting control module 184, a data writing module 185, and a threshold grasping module 186; the first plate of the storage capacitor C1 is electrically connected to the first power line 21, and the second plate of the storage capacitor C1 is electrically connected to the control terminal of the driving transistor 181; the first terminal of the data writing module 185 is electrically connected to the first terminal of the driving transistor 181, and the second terminal of the data writing module 185 is electrically connected to the corresponding data line 23; the first terminal of the threshold grasping module 186 is electrically connected to the control terminal of the driving transistor 181, and the second terminal of the threshold grasping module 186 is electrically connected to the second terminal of the driving transistor 181; the first terminal of the first light-emitting control unit 187 of the light-emitting control module 184 is electrically connected to the first power line 21, and the second terminal of the first light-emitting control unit 187 is electrically connected to the first terminal of the driving transistor 181; the first terminal of the second light-emitting control unit 188 of the light-emitting control module 184 is electrically connected to the second terminal of the driving transistor 181, and the second terminal of the second light-emitting control unit 188 is electrically connected to the first terminal of the light-emitting element D1.

[0081] Figure 17 The pixel driving circuit of the 7T1C is shown. Specifically, the first reset module 182 includes a sixth transistor T6, the second reset module 183 includes a seventh transistor T7, the threshold capture module 186 includes a fifth transistor T5, the first light-emitting control unit 187 includes a second transistor T2, the second light-emitting control unit 188 includes a third transistor T3, and the data writing module 185 includes a fourth transistor T4. The driving transistor 181 can be referred to as the first transistor T1. This embodiment uses a low-temperature polycrystalline oxide (LTPO) display panel as an example. In the pixel driving circuit of the 7T1C, the fifth transistor T5 and the sixth transistor T6 are P-type transistors, and their active layers are formed using indium gallium zinc oxide. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are all N-type transistors, and their active layers are made of polycrystalline silicon. Specifically, the first reset module 182 operates in response to the first scan signal SCAN1 to connect the control terminal of the driving transistor T1 to the first reference voltage signal vref1; the storage capacitor C1 is used to connect the first power supply signal PVDD to the control terminal of the driving transistor T1; the data writing module 185 operates in response to the third scan signal SCAN3 to connect the first terminal of the driving transistor T1 to the corresponding data signal Vdata; the threshold grabbing module 186 operates in response to the second scan signal SCAN2 to connect the control terminal of the driving transistor to the second terminal; the light emission control module 184 operates in response to the light emission control signal EM to connect the first terminal of the driving transistor T1 to the first power supply signal PVDD, and simultaneously connect the second terminal of the driving transistor T1 to the first terminal of the light-emitting element D1; the second terminal of the light-emitting element D1 is connected to the second power supply signal PVEE; the second reset module 183 operates in response to the third scan signal SCAN3 to connect the first terminal of the light-emitting element D1 to the second reference voltage signal vref1. It should be noted that in this embodiment, a first scan signal SCAN1, a second scan signal SCAN2, a third scan signal SCAN3, and a fourth scan signal SCAN4 can be set. The effective levels of the first scan signal SCAN1 and the second scan signal SCAN2 are high, while the effective levels of the third scan signal SCAN3 and the fourth scan signal SCAN4 are low. Specifically, the effective levels of the second scan signal SCAN2 and the third scan signal SCAN3 have the same duration; and the effective levels of the first scan signal SCAN1 and the fourth scan signal SCAN4 have the same duration.

[0082] The pixel driving circuit operates through three phases: a reset phase, a data writing phase, and a light-emitting phase. During the reset phase, the sixth transistor T6 is turned on, while the driving transistors T1, T2, T3, T4, T5, and T7 are turned off. The first reference voltage signal vref1 is written to node N1 (the control terminal of the driving transistor), initializing the control terminal of driving transistor T1. During the data writing phase, driving transistors T1, T4, T5, and T7 are turned on, while the second transistor T2, T3, and T6 are turned off. The second reference voltage signal vref2 is written to node N4 (the light-emitting phase). The first terminal of the light-emitting element D1 is initialized; the data signal Vdata flows to node N2 (the first terminal of the light-emitting element D1) through the fourth transistor T4, then to node N3 (the first terminal of the driving transistor) through the driving transistor T1, and then to N1 through the fifth transistor; during the light-emitting stage, the driving transistor T1, the second transistor T2 and the third transistor T3 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, forming a current path from the first power supply signal PVDD to the second power supply signal PVEE, and the light-emitting element D1 is lit.

[0083] Figure 18 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. Optionally, the pixel driving circuit 18 may further include an adjustment signal module 189; the first end of the adjustment signal module 189 is connected to the adjustment signal line 51; the second end of the adjustment signal module 189 is connected to the first end of the driving transistor 181; the adjustment signal module 189 is used to transmit the adjustment signal DVH to the driving transistor 181.

[0084] Figure 18 The pixel driving circuit is 8T1C, compared to Figure 17 The pixel driving circuit shown in the diagram, the 8T1C pixel driving circuit adds an adjustment signal module 189. The adjustment signal module 189 includes an eighth transistor T8. The control terminal of the eighth transistor T8 is connected to the fourth scan signal SCAN4. The second terminal of the eighth transistor T8 is connected to the first terminal of the driving transistor T1 and the second terminal of the fourth transistor T4, respectively. The first terminal of the eighth transistor T8 is connected to the adjustment signal DVH. During the reset phase, the eighth transistor T8 is turned on, and the adjustment signal DVH is written to N2 to improve the bias state of the driving transistor T1. During the data writing phase and the light emission phase, the eighth transistor T8 is in the cutoff state. The remaining operation process is the same as described above. Figure 17 The operation of the pixel driving transistor T1 is the same, so I will not go into details again.

[0085] In this embodiment, the pixel driving circuit requires a first reference voltage bus 13, a second reference voltage bus 14, a first power supply bus 25, a second power supply bus 24, and an adjustment signal bus 52 to provide operating power. This embodiment illustrates a case with a large number of buses. These buses are typically located on the third metal layer M3. When there are many buses, the first reference voltage bus 13 is only located in the fan-out area 15 and the first non-display area NA1, occupying the area of ​​the top and bottom bezels. The remaining buses are located in the second non-display area NA2 and the third non-display area NA3, occupying the space of the side bezels. This embodiment effectively balances the bus configuration of each bezel, resulting in a smaller overall bezel width for the display panel, thus meeting the user's requirement for a narrow bezel.

[0086] Figure 19 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Optionally, the display area AA may further include auxiliary wiring 61; the data line 23 includes a first data line 23a and a second data line 23b; the fan-out area 15 includes a first data lead 15a and a second data lead 15b; the first data line 23a is electrically connected to the first data lead 15a; the second data line 23b is electrically connected to the second data lead 15b through the auxiliary wiring 61. Figure 19 As shown, the display area AA can be divided into a first display area AA1 and a second display area AA2; the data line 23 includes a first data line 23a and a second data line 23b. The first display area AA1 is provided with the first data line 23a, and the second display area AA2 is provided with the second data line 23b.

[0087] Optionally, a virtual trace 12a can be provided on the same layer as the auxiliary trace 61. The virtual trace 12a and the auxiliary trace 61 form a grid shape to maintain the display uniformity of the display panel. The virtual trace 12a can reduce the current attenuation caused by the trace resistance of different signals, thereby effectively improving the display effect of the display panel. The virtual trace 12a can be connected to any of the following signals: the first power signal PVDD, the second power signal PVEE, the first reference voltage signal vref1, and the second reference voltage signal vref2. Similarly, in order to reduce the current attenuation caused by the trace resistance of different signals, the shielding bus can be connected to the first power signal PVDD, the second power signal PVEE, the first reference voltage signal vref1, or the second reference voltage signal vref2 to further improve the display effect of the display panel.

[0088] This invention also provides a display device. Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 20 As shown, the display device provided in this embodiment of the invention includes the display panel 200 described in any embodiment of the invention. The display device can be as follows: Figure 20The display device of the mobile phone shown can also be the display device of electronic devices such as computers, televisions, and smart wearable devices. This embodiment does not make any special limitation on this.

[0089] The display device in this embodiment includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding features, which will not be described in detail here.

[0090] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: The display area and the non-display area surrounding the display area; The display area includes multiple first reference voltage lines, multiple second reference voltage lines, and data lines; the data lines extend along a first direction. The non-display area includes a first reference voltage bus and a second reference voltage bus; The first reference voltage line is electrically connected to the first reference voltage bus; The second reference voltage line is electrically connected to the second reference voltage bus; The first reference voltage bus includes a first bus segment and a second bus segment; The non-display area includes a fan-out area and a first non-display area located on both sides of the display area along the first direction; at least a portion of the first bus segment is located in the fan-out area; and at least a portion of the second bus segment is located in the first non-display area.

2. The display panel according to claim 1, characterized in that, The non-display area further includes a second non-display area and a third non-display area located on both sides of the display area along a second direction; the second direction intersects with the first direction; the first non-display area is respectively arranged adjacent to the second non-display area and the third non-display area; The second reference voltage bus includes at least a third bus segment and a fourth bus segment; At least a portion of the third bus segment is located in the second non-display area; at least a portion of the fourth bus segment is located in the third non-display area.

3. The display panel according to claim 2, characterized in that, Adjacent non-display areas are connected by a radius (R-corner area).

4. The display panel according to claim 2, characterized in that, The first non-display area and the second non-display area are connected by a first rounded corner area; the first non-display area and the third non-display area are connected by a second rounded corner area. The second bus segment includes a first portion located in the first R-corner region and / or a second portion located in the second R-corner region.

5. The display panel according to claim 2, characterized in that, The fan-out area and the second non-display area are connected by a third R-corner area; the fan-out area and the third non-display area are connected by a fourth R-corner area; The first bus segment includes a third portion located in the third R-angle region and / or a fourth portion located in the fourth R-angle region.

6. The display panel according to claim 3, characterized in that, The display area includes an array of pixel driving circuits; the display area includes a first irregularly shaped area; The first irregular region is adjacent to the R-corner region, and the multiple pixel driving circuits in the first irregular region are distributed in a stepped manner. The first bus segment and the second bus segment extend along the edge of the first irregular region.

7. The display panel according to claim 6, characterized in that, The third bus segment and the fourth bus segment extend along the edge of the first irregular region.

8. The display panel according to claim 6, characterized in that, It also includes: a shielding bus; the shielding bus extends along the edge of the first irregular region; in the first irregular region, the shielding bus includes a linear first bus and a stepped second bus; The first reference voltage bus in the first irregular region includes multiple first stages extending along a first direction and second stages extending along a second direction; The second bus in the first irregular region includes multiple third stages extending along the first direction and fourth stages extending along the second direction. There is an overlapping area between the second stage and the fourth stage.

9. The display panel according to claim 2, characterized in that, The first reference voltage bus further includes: a fifth bus segment; The fifth bus segment is located in the second non-display area.

10. The display panel according to claim 9, characterized in that, The first reference voltage bus further includes: a sixth bus segment; The sixth bus segment is located in the third non-display area.

11. The display panel according to claim 10, characterized in that, Along the second direction, the width of the fifth bus segment is smaller than the width of the third bus segment; the width of the sixth bus segment is smaller than the width of the fourth bus segment.

12. The display panel according to claim 10, characterized in that, The first bus segment, the fifth bus segment, the second bus segment, and the sixth bus segment are connected in sequence to form a ring.

13. The display panel according to claim 10, characterized in that, The first reference voltage bus and the second reference voltage bus are located in different film layers; The fifth bus segment at least partially overlaps with the third bus segment; and / or, The sixth bus segment overlaps at least partially with the fourth bus segment.

14. The display panel according to claim 1, characterized in that, The first reference voltage bus and the second reference voltage bus are configured on the same layer.

15. The display panel according to claim 2, characterized in that, The first reference voltage line includes a first connecting line extending along a first direction and a second connecting line extending along a second direction; the first connecting line and the second connecting line are electrically connected. The second reference voltage line includes a third connecting line extending along a first direction and a fourth connecting line extending along a second direction; the third connecting line is electrically connected to the fourth connecting line. The first connecting line is connected to the first bus segment and the second bus segment respectively; The fourth connection line is connected to both the third bus segment and the fourth bus segment.

16. The display panel according to claim 3, characterized in that, The display area further includes: a first power line and a second power line extending along the second direction; The non-display area further includes a first power bus and a second power bus; the first power bus is connected to the first power line; the second power bus is connected to the second power line. The first power bus includes portions located in the second and third non-display areas and a portion extending to the R-corner region; and / or, The second power bus includes portions located in the second and third non-display areas and a portion extending into the R-corner area.

17. The display panel according to claim 16, characterized in that, The display panel includes; Touch traces connected to touch electrodes; the fan-out area includes multiple leads; the leads include at least: a first reference voltage lead, a first power supply lead, a second power supply lead, a second reference voltage lead, and a touch lead; The first reference voltage lead is electrically connected to the first reference voltage bus; the second reference voltage lead is electrically connected to the second reference voltage bus; the touch lead is electrically connected to the touch trace; the first power lead is connected to the first power bus; the second power lead is connected to the second power bus. Along the second direction, the second reference voltage lead is located between the first reference voltage lead and the touch lead.

18. The display panel according to claim 16, characterized in that, The non-display area further includes: a binding area; the binding area is located on the side of the fan-out area away from the display area; The bonding area includes multiple pads; each pad is connected to a corresponding lead. Along the second direction, the pad connected to the second reference voltage lead is located between the pad connected to the first power lead and the pad connected to the second power lead; The second reference voltage lead is connected to the corresponding pad by a jumper wire that crosses the first reference voltage lead.

19. The display panel according to claim 2, characterized in that, The display area also includes adjustment signal lines; The non-display area also includes an adjustment signal bus; the adjustment signal bus is electrically connected to the adjustment signal line. The adjustment signal bus includes a seventh bus segment and an eighth bus segment; The seventh bus segment is located in the second non-display area; The eighth bus segment is located in the third non-display area.

20. The display panel according to claim 19, characterized in that, The adjustment signal line includes a fifth connecting line extending along a first direction and a sixth connecting line extending along a second direction; the fifth connecting line is electrically connected to the sixth connecting line. The sixth connecting line is electrically connected to the seventh bus segment and the eighth bus segment, respectively.

21. The display panel according to claim 19, characterized in that, The first reference voltage bus, the second reference voltage bus, and the adjustment signal bus are arranged on the same layer.

22. The display panel according to claim 17, characterized in that, The display area also includes adjustment signal lines; The non-display area also includes an adjustment signal bus; the adjustment signal bus is electrically connected to the adjustment signal line. The lead wire also includes an adjustment signal lead wire; the adjustment signal lead wire is electrically connected to the adjustment signal bus. Along the second direction, the second reference voltage lead is located between the adjustment signal lead and the touch lead; the adjustment signal lead is located between the first reference voltage lead and the second reference voltage lead.

23. The display panel according to claim 22, characterized in that, The non-display area further includes: a binding area; the binding area is located on the side of the fan-out area away from the display area; The bonding area includes multiple pads; each pad is connected to a corresponding lead. Along the second direction, the pad connected to the second reference voltage lead is located between the pad connected to the first power lead and the pad connected to the second power lead; The second reference voltage lead is connected to the corresponding pad by a jumper wire that crosses the first reference voltage lead and the adjustment signal lead.

24. The display panel according to claim 1, characterized in that, The display area includes an array of pixel driving circuits; The pixel driving circuit includes a driving transistor, a first reset module, and a second reset module. The first terminal of the first reset module is electrically connected to the control terminal of the driving transistor, and the second terminal of the first reset module is electrically connected to the first reference voltage line; the first terminal of the driving transistor is electrically connected to the first power supply line; the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element; the first terminal of the second reset module is electrically connected to the first terminal of the light-emitting element, and the second terminal of the second reset module is electrically connected to the second reference voltage line; the second terminal of the light-emitting element is electrically connected to the second power supply line.

25. The display panel according to claim 24, characterized in that, The pixel driving circuit also includes: a storage capacitor, a light emission control module, a data writing module, and a threshold capture module; The first plate of the storage capacitor is electrically connected to the first power line, and the second plate of the storage capacitor is electrically connected to the control terminal of the driving transistor; the first terminal of the data writing module is electrically connected to the first terminal of the driving transistor, and the second terminal of the data writing module is electrically connected to the corresponding data line; the first terminal of the threshold grasping module is electrically connected to the control terminal of the driving transistor, and the second terminal of the threshold grasping module is electrically connected to the second terminal of the driving transistor; the first terminal of the first light-emitting control unit of the light-emitting control module is electrically connected to the first power line, and the second terminal of the first light-emitting control unit is electrically connected to the first terminal of the driving transistor; the first terminal of the second light-emitting control unit of the light-emitting control module is electrically connected to the second terminal of the driving transistor, and the second terminal of the second light-emitting control unit is electrically connected to the first terminal of the light-emitting element.

26. The display panel according to claim 24, characterized in that, The pixel driving circuit also includes an adjustment signal module; The first end of the adjustment signal module is connected to the adjustment signal line; the second end of the adjustment signal module is connected to the first end of the driving transistor; the adjustment signal module is used to transmit the adjustment signal to the driving transistor.

27. The display panel according to claim 1, characterized in that, The display area also includes auxiliary wiring; the data lines include a first data line and a second data line; the fan-out area includes a first data lead and a second data lead; The first data line is electrically connected to the first data lead; the second data line is electrically connected to the second data lead through the auxiliary trace.

28. A display device, characterized in that, The display panel includes any one of claims 1-27.

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