Multi-rate multi-stage digital compensator for nonlinear system

Abstract

The invention relates to a multi-rate multi-stage digital compensator for a non-linear system. The invention discloses a multi-stage multi-rate digital pre-distortion system with strong adaptability. The system can improve the distortion precision of an input signal applied to a power amplifier. In addition, the digital pre-distortion system may be implemented using a reduced circuit area by reducing the number of coefficients used by applying to the model generating the distortion compensation signal. Further, the system may implement an improved digital pre-distortion adaptive engine that improves adjacent channel leakage rates of the digital pre-distortion system. Further, the system may compensate for non-linear impairments caused by analog / RF circuits and systems, and improve at least the following indicators: Error Vector Modulation (EVM), Adjacent Channel Leakage Rate (ACLR), Spectral Transmit Mask (SEM), and power consumption of the circuits and systems. One example of a circuit and system is a radio frequency power amplifier (RF PA).

Description

[0001] Introduced by merging

[0002] This application claims priority to U.S. Application No. 18 / 332,323, filed on June 9, 2023, which is incorporated herein by reference in its entirety for all purposes. Any and all applications for which a foreign or domestic priority claim is identified in the Application Data Sheet filed with the present application are incorporated herein by reference pursuant to 37 CFR 1.57. Technical Field

[0003] The present disclosure relates to a digital predistortion system for a power amplifier. Background Art

[0004] Wireless devices can use transceivers to send or receive radio frequency signals. The signal to be sent usually does not have a high enough power to reach its destination, such as a base station. Power amplifiers are often used to increase the signal strength of the signal to be transmitted, allowing it to travel a longer distance. Summary of the invention

[0005] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

[0006] In some aspects, the technology described herein relates to a digital predistortion system configured to distort a power amplifier input signal before being input to a power amplifier, the digital predistortion system comprising: a first compensator comprising a first plurality of processing circuit blocks, wherein each of the first plurality of processing circuit blocks is configured to implement a transfer function to modify the linearity of the first input signal input to the first compensator, and wherein each of the first plurality of processing circuit blocks is connected in parallel within the first compensator; a second compensator connected in series with the first compensator, the second compensator comprising a second plurality of processing circuit blocks, wherein each of the second plurality of processing circuit blocks is configured to implement a transfer function to modify the linearity of a second input signal input to the second compensator, wherein each of the second plurality of processing circuit blocks is connected in parallel within the second compensator, and wherein the second input signal is based at least in part on an output of the first compensator; and a first adder circuit configured to sum the output of each of the second plurality of processing circuit blocks to obtain a digital predistortion signal, wherein the first adder circuit is further configured to provide the digital predistortion signal as an input to the power amplifier.

[0007] In some aspects, the techniques described herein relate to a digital predistortion system wherein at least one of the first plurality of processing circuit blocks or the second plurality of processing circuit blocks implements a neural network.

[0008] In some aspects, the techniques described herein relate to a digital predistortion system wherein the second compensator further includes the first adder circuit.

[0009] In some aspects, the techniques described herein relate to a digital predistortion system wherein each processing circuit block in the first plurality of processing circuit blocks is configured to generate an output that is provided as an input to a corresponding processing circuit block in the second plurality of processing circuit blocks.

[0010] In some aspects, the techniques described herein relate to a digital predistortion system, further comprising a second adder circuit configured to sum an output of each of the first plurality of processing circuit blocks to obtain an intermediate signal, wherein the intermediate signal is provided as an input to the second compensator.

[0011] In some aspects, the techniques described herein relate to a digital predistortion system wherein at least one of the first compensator or the second compensator includes a memory that stores signal samples that enables the transfer function to operate over a larger sample range than a memoryless compensator.

[0012] In some aspects, the techniques described herein relate to a digital predistortion system further comprising a set of one or more compensators connected in series between the first compensator and the second compensator.

[0013] In some aspects, the techniques described herein relate to a digital predistortion system wherein a combination of at least the first compensator and the second compensator is configured to generate distortion of the power amplifier input signal such that an overall system response of a system including the power amplifier is linear.

[0014] In some aspects, the technology described herein relates to a digital predistortion system, wherein the first compensator also includes a plurality of downsampling circuits corresponding to the first plurality of processing circuit blocks, wherein each of the plurality of downsampling circuits is configured to downsample the first input signal to obtain a downsampled input signal, which is input to a corresponding processing circuit block in the first plurality of processing circuit blocks.

[0015] In some aspects, the techniques described herein relate to a digital predistortion system, wherein the first compensator further comprises a plurality of upsampling circuits corresponding to the first plurality of processing circuit blocks, wherein each of the plurality of upsampling circuits is configured to upsample an output of a corresponding processing circuit block in the first plurality of processing circuit blocks.

[0016] In some aspects, the techniques described herein relate to a digital predistortion system wherein at least one processing circuit block of the first plurality of processing circuit blocks implements a different transform function than at least another processing circuit block of the first plurality of processing circuit blocks.

[0017] In some aspects, the techniques described herein relate to a digital predistortion system wherein the transform function comprises one or more of a set of mathematical sequences or models configured to modify the linearity of an applied signal.

[0018] In some aspects, the techniques described herein relate to a digital predistortion system, wherein the transform function includes one or more weighting coefficients set based on a digital predistortion adaptive circuit, the digital predistortion adaptive circuit being configured to determine the one or more weighting coefficients using an adaptive algorithm applied to an output of the power amplifier.

[0019] In some aspects, the techniques described herein relate to a digital predistortion system wherein the transform function includes one or more weighting coefficients set based on a digital predistortion adaptive circuit configured to determine the one or more weighting coefficients using a back-propagation and least squares estimation algorithm applied to an output of the power amplifier.

[0020] In some aspects, the technology described herein relates to a transceiver radio comprising: a power amplifier; and a digital predistortion system connected in series with the power amplifier, the digital predistortion system comprising: a plurality of compensator circuits connected in series, wherein each of the plurality of compensator circuits comprises a plurality of nonlinear processing circuits connected in parallel, the nonlinear processing circuits being configured to implement a transform function to modify the linearity of an input signal received at a first compensator circuit in the plurality of compensator circuits; and an adder circuit configured to sum the output of each of the plurality of nonlinear processing circuits of a last compensator circuit in the plurality of compensator circuits to obtain a digital predistortion signal, wherein the adder circuit is further configured to provide the digital predistortion signal as an input to the power amplifier.

[0021] In some aspects, the technology described herein relates to a transceiver radio, further comprising a crest factor reduction circuit configured to receive a transmit signal and reduce a peak-to-peak average power ratio of the transmit signal to obtain a reduced peak-to-peak transmit signal, wherein the reduced peak-to-peak transmit signal is provided as an input signal to the digital predistortion system.

[0022] In some aspects, the techniques described herein relate to a transceiver radio, further comprising a digital predistortion adaptation circuit configured to receive an output of the power amplifier and configure one or more coefficients of a transfer function of at least one of the plurality of compensator circuits based at least in part on the power amplifier output.

[0023] In some aspects, the techniques described herein relate to a transceiver radio, wherein at least one compensator circuit further comprises a plurality of downsampling circuits corresponding to the plurality of nonlinear processing circuits, and wherein each of the plurality of downsampling circuits is configured to downsample the input signal to obtain a downsampled input signal, the downsampled input signal being input to a corresponding nonlinear processing circuit of the plurality of nonlinear processing circuits.

[0024] In some aspects, the techniques described herein relate to a transceiver radio, wherein at least one compensator circuit further comprises a plurality of upsampling circuits corresponding to the plurality of non-linear processing circuits, and wherein each of the plurality of upsampling circuits is configured to upsample an output of a corresponding non-linear processing circuit of the plurality of non-linear processing circuits.

[0025] In some aspects, the technology described herein relates to a wireless device, the wireless device comprising: an antenna, the antenna configured to transmit a signal received from a power amplifier; the power amplifier; a transceiver, including a digital predistortion system connected in series with the power amplifier, the digital predistortion system comprising: a plurality of compensator circuits connected in series, wherein each compensator circuit of the plurality of compensator circuits comprises a plurality of nonlinear processing circuits and linear processing circuits connected in parallel and is configured to implement a transfer function to modify the linearity of an input signal received at a first compensator circuit of the plurality of compensator circuits; and an adder circuit configured for summing the output of each of the plurality of nonlinear processing circuits of the last compensator circuit in the plurality of compensator circuits to obtain a digital predistortion signal, wherein the adder circuit is further configured to provide the digital predistortion signal as an input to the power amplifier; a digital predistortion adaptive circuit configured to receive the output of the power amplifier and configure one or more coefficients of a transfer function of at least one of the plurality of compensator circuits based at least in part on the power amplified output; and a coupler configured to provide the output of the power amplifier to the digital predistortion adaptive circuit.

[0026] Although certain embodiments and implementations are disclosed herein, the inventive subject matter extends beyond those specifically disclosed to other alternative embodiments and / or uses, as well as modifications and equivalents thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Various aspects and advantages of the embodiments provided herein are described with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, reference numerals may be reused to indicate the corresponding relationship between reference elements. The accompanying drawings are provided to illustrate the exemplary embodiments described herein and are not intended to limit the scope of the present disclosure. In addition, various features of different disclosed embodiments may be combined to form additional embodiments, which are part of the present disclosure. In addition, one or more features or structures may be removed or omitted.

[0028] Figure 1 An example digital linearization system is shown in accordance with certain embodiments.

[0029] Figure 2 A portion of a wireless system including a transceiver implementing digital predistortion is shown in accordance with some embodiments.

[0030] Figures 3A-3C Several example multi-stage implementations of digital predistortion systems according to certain embodiments are shown.

[0031] Figure 4Several examples of a multi-stage, multi-rate digital predistortion system processing a crest factor reduced signal at different sampling rates are shown in accordance with certain embodiments.

[0032] Figure 5 An example implementation of a multi-stage multi-rate digital predistortion system in accordance with certain embodiments is shown.

[0033] Figure 6 Another example implementation of a multi-stage multi-rate digital predistortion system in accordance with certain embodiments is shown.

[0034] Figure 7 An example implementation of a digital predistortion adaptation circuit implementing a least squares estimation adaptation algorithm in accordance with certain embodiments is shown.

[0035] Figure 8 An example implementation of a digital predistortion adaptation circuit implementing back-propagation and least squares estimation adaptation algorithms in accordance with certain embodiments is shown.

[0036] Fig. 9 Example system equations for an example multi-stage multi-rate digital predistortion system using a generalized memory polynomial model in accordance with certain embodiments are shown.

[0037] Fig.10 Simulation results of a multi-stage multi-rate digital predistortion system according to some embodiments are shown, the system being adapted by a digital predistortion adaptation circuit implementing back-propagation and least squares estimation adaptation algorithms.

[0038] Figures 11A-11D Measured results are shown for an implementation of a multi-stage multi-rate digital predistortion system adapted by a digital predistortion adaptation circuit implementing back-propagation and least squares estimation adaptation algorithms in accordance with certain embodiments.

[0039] Figures 12A-12C Measured results are shown for an implementation of a multi-stage multi-rate digital predistortion system adapted by a digital predistortion adaptation circuit implementing back-propagation and least squares estimation adaptation algorithms in accordance with certain embodiments. DETAILED DESCRIPTION

[0040] The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.For purposes of this disclosure, the terms mobile device and wireless device are used interchangeably.

[0041] introduction

[0042] In general, new wireless technologies require transmitters to operate more efficiently without compromising RF performance (e.g., bandwidth and emission) and implementation area. One area where efficiency improvements are desired is with respect to power amplifiers, and more specifically, power amplifier linearity.

[0043] like Figure 1 As shown, a nonlinear power amplifier can be configured to produce a linear output by distorting the input of the power amplifier so that the overall system response is linear. Digital predistortion can be used to distort the desired transmit signal so that the output of the power amplifier is linear. The nonlinear distortion compensation produced by the distortion compensation circuit combined with the nonlinear output of the power amplifier can result in a linear overall system response.

[0044] The distortion produced by a digital predistortion system can be based on the output of a power amplifier. The accuracy of digital predistortion can be improved by using a more complex model that can be used to determine the distortion applied to the nonlinear power amplifier. However, increasing the complexity of the model results in greater circuit area and power consumption.

[0045] The present disclosure relates to an adaptable multi-stage multi-rate digital predistortion system that can increase the accuracy of the distortion applied to a power amplifier input signal. In other words, the system disclosed herein can reduce the error between the generated distortion signal and the power amplifier output. In addition, the digital predistortion system can be implemented using a reduced circuit area by reducing the number of coefficients used by the model applied to generate the distortion compensation signal. In addition, the system can implement an improved digital predistortion adaptive engine that improves the adjacent channel leakage rate of the digital predistortion system. In addition, the system can compensate for nonlinear impairments caused by analog / RF circuits and systems, and at least improve the following indicators: error vector magnitude (EVM), adjacent channel leakage rate (ACLR), spectrum emission mask (SEM), and power consumption of circuits and systems. An example of a circuit and system is a radio frequency power amplifier (RF PA).

[0046] Digital Pre-Distortion System

[0047] Figure 2 A portion of a wireless system 200 is shown that includes an integrated transceiver or transceiver radio that implements digital predistortion according to certain embodiments. The wireless system 200 may include a transceiver radio 212 (or integrated transceiver), a power amplifier 202, and a coupler 210, among other circuit elements and systems. The transceiver radio 212 may include a digital predistortion system 204, a digital predistortion adaptation system 206 (DPD), a crest factor reduction circuit 208 (CFR), and a transmitter-observation-receiver 214, among other systems and circuits.

[0048] In some embodiments, the transceiver radio 212 may include a digital front end (DFE). The DFE may help the wireless system 200 convert between analog RF and digital baseband processing. The DFE may include at least a digital predistortion system 204, a digital predistortion adaptation system 206, and a crest factor reduction circuit 208.

[0049] In some embodiments, the transceiver radio 212 may include a power amplifier 202. In some embodiments, the transceiver radio 212 outputs a signal for transmission that is provided to the power amplifier 202 to increase the signal strength for the signal transmitted by the antenna 216. The coupler 210 may be used to provide a power signal or power measurement from the output of the power amplifier 202 to the transmitter-observation receiver 214, which may determine the signal output by the power amplifier 202 based on the measured power received from the coupler 210. The output signal may be provided by the transmitter-observation receiver 214 to the digital predistortion adaptive system 206. As described in more detail below, the digital predistortion adaptive system 206 may use the output signal of the power amplifier 202 to determine one or more coefficient values ​​for configuring one or more models used by the digital predistortion system 204 to determine the distortion or predistortion signal applied to the transmit signal before being provided to the power amplifier 202. Thus, the digital predistortion system 204 may be configured using a feedback mechanism to implement an improved compensation system for converting the output of the non-linear power amplifier 202 to a linear system response of the wireless system 200 or a transceiver radio 212 of the wireless system 200 .

[0050] The digital pre-distortion system 204 can be implemented as a series of compensators or compensation circuits. Each of these compensation circuits can implement different functions, algorithms, models or transformation functions, including models based on machine learning. In some embodiments, the digital pre-distortion system 204 can be a multi-stage system including multiple compensation circuits connected in series. Advantageously, by using a multi-stage system, the number of coefficients included in the implemented model can be reduced without increasing the amount of power leaking into adjacent channels. In addition, in some cases, the leakage rate of adjacent channels can be reduced. The reduction in the number of coefficients can not only improve efficiency while improving performance, but also reduce circuit area due to, for example, the reduction in the number of supporting coefficients necessary to implement the model performed by the compensation circuit.

[0051] The digital predistortion system 204 may apply distortion to an input signal corresponding to a signal to be transmitted. The input signal may be received from a crest factor reduction circuit 208. The crest factor reduction circuit 208 may reduce the peak-to-peak average power ratio of the signal to be transmitted to obtain a reduced peak-to-peak transmit signal. The reduced peak-to-peak transmit signal may be provided as an input to the digital predistortion system 204, which in turn may predistort the receive signal before it is provided to the power amplifier 202. Figure 2 As shown, the output of the digital predistortion system 204 can be provided to other subsequent circuits (e.g., a transmitter including an upsampler, a digital-to-analog converter, a mixer, a local oscillator, etc.) before being provided to the power amplifier 202, which can be a separate circuit or a part of the transmitter. In addition, the digital predistortion system 204 can apply predistortion based at least in part on feedback received from the power amplifier 202, which is used by the digital predistortion adaptation system 206 to configure the digital predistortion system 204.

[0052] Figures 3A-3C Several example multi-stage implementations of the digital predistortion system 204 according to certain embodiments are shown. Figure 3A As shown, the digital predistortion system 204 may include a compensator 302A and a compensator 302B. The compensators may be collectively or individually referred to as compensators 302. In addition, although only two compensators 302 are shown, the digital predistortion system 204 may include up to N compensators, where N may include any integer greater than 2.

[0053] Each compensator 302 may include a model 304. Model 304 may include a set of one or more models. In embodiments where compensator 302 includes multiple models 304, models 304 may be connected in parallel within compensator 302. Each model 304 may include any type of algorithm or model that may be used to determine the amount of pre-distortion to apply to a transmit signal prior to input to power amplifier 202. In addition, the algorithm or model may use the output from power amplifier 202 to help determine the pre-distortion to be applied to the transmit signal and / or configure an algorithm or model for determining the pre-distortion to be applied to the transmit signal. In some cases, the algorithm or model may include a machine learning based model. Some non-limiting examples of models, transformation functions, or mathematical series that may be implemented by the model 304 of the compensator 302 include: Taylor series, Volterra series, piecewise function, Saleh model, memory polynomial, orthogonal memory polynomial, exponential shape memory delay polynomial, envelope memory polynomial, generalized memory polynomial, dynamic deviation reduction, long term memory model, band-limited model, power dependent model, dynamic power model, spline interpolation lookup table or multi-band model, etc. Additionally, in some embodiments, the model 304 may include a neural network or other machine learning based model.

[0054] The output of the first stage of the digital predistortion system 204 (e.g., compensator 302A) may be provided as an input to the next stage of the digital predistortion system 204. The output of the last stage of the digital predistortion system 204 (e.g., compensator 302B) may be provided as an input to the power amplifier 202. In some embodiments, there may be circuitry between the digital predistortion system 204 and the power amplifier 202 that may further process the signal at the output of 302B before it is provided to the power amplifier 202, such as Figure 2 shown.

[0055] In some embodiments, each of the compensators 302 may be configured to implement a different model or perform different operations with respect to generating predistortion. Figure 3A As shown, compensator 302A can implement a nonlinear model that introduces nonlinearity into the received signal. And compensator 302B can include a memory that enables operation to consider a larger set or a larger range of samples of the processed signal. For example, while compensator 302A can process a smaller set of samples (e.g., 1, 5, 10, etc.) at a time, compensator 302B can process a larger set of samples (e.g., 10, 20, 50, etc.). It should be understood that other configurations are also possible.

[0056] For example, Figure 3BThe digital predistortion system 204 is shown to include at least two compensators 302C, each of which can implement a nonlinear and memory-based model. In other words, each of the compensators 302C can introduce a nonlinearity determined based on a set of current or previously received samples obtained from the input signal. The compensator 302C can include a memory and / or a sliding window that can access samples of the input signal, which enables the compensator 302C to apply the distortion window over more samples than the memoryless compensator 302.

[0057] Figure 3C Another example digital predistortion system 204 is shown, which includes a compensator 302D implementing a neural network. The compensator 302D can be connected to any other type of compensator 302 including the second compensator 302D. Figure 3C In the example shown, compensator 302D may be connected in series to compensator 302C.

[0058] Figure 4 Several examples of a multi-stage, multi-rate digital predistortion system processing a crest factor reduction signal at different sampling rates according to certain embodiments are shown. The crest factor reduction signal may be a reduced peak-to-peak transmit signal. The transmit signal may be provided as an input to a digital predistortion system 204, which in turn may be an input to a first compensator 302 of a plurality of compensators 302 connected in series as part of a digital precompensator system 204. The compensator 302 may output a crest factor signal distorted by the application of predistortion by the compensator 302 to the power amplifier 202.

[0059] exist Figure 4 In the example of , a first graph (e.g., graphs 402A, 404A, or 406A) is provided to illustrate the input of the digital predistortion system 204, a second graph (e.g., graphs 402B, 404B, or 404C) is provided to illustrate the output of the first compensator 302 within the digital predistortion system 204, a third graph (e.g., graphs 402C, 404C, 406C) is provided to illustrate the output of the final compensator 302 of the digital predistortion system 204, which can be provided to the power amplifier 202, and a fourth graph (e.g., graphs 402D, 404D, 406D) is provided to illustrate the output of the power amplifier 202.

[0060] Advantageously, in certain embodiments, the multi-stage, multi-rate digital predistortion system 204 of the present disclosure can reduce the power consumption of the crest factor reduction circuit 208, which in turn can reduce the overall power consumption of the wireless system 200. The power consumption of the crest factor reduction circuit 208 can be reduced by operating the crest factor reduction circuit 208 at a reduced sampling rate, which may be due to, for example, the multi-rate capability of the digital predistortion system 204 of the present disclosure. In a first example, shown by graph 402A, the output of the crest factor reduction circuit 208 is at a reduced sampling rate as shown by the area of ​​the dashed box, compared to the graphs 404A or 406A of the second and third examples, where the output of the crest factor reduction circuit 208 is at a fully supported sampling rate. Continuing with the first example, the first compensator 302 can maintain the same sampling rate as the output of the crest factor reduction circuit 208, as shown by the curve 402B representing the output of the first compensator 302. The final compensator 302 may then upsample the received signal, as shown by curve 402C, and the output of the power amplifier 202 may match the sampling rate of the output of the digital predistortion system 204, as shown by curve 402D.

[0061] In a second example, the output of the crest factor reduction circuit 208 may be at the full sampling rate as shown by curve 404A. The first compensator 302 may maintain the same sampling rate as shown by curve 404B illustrating the output of the first compensator 302, which may be provided as an input to the last (second in the illustrated example) compensator 302. The output of the last compensator 302 may be maintained at the full sampling rate (shown by curve 404C), and the output of the power amplifier 202 may also be maintained at the full sampling rate (shown by curve 404D).

[0062] In a third example, the output of the crest factor reduction circuit 208 may be at the full sampling rate as shown in graph 406A. However, unlike the second example, the first compensator 302 may reduce the sampling rate (e.g., downsample) of the processed signal, as shown in graph 406B, which shows the output of the first compensator 302, which may be provided as an input to the last (second in the illustrated example) compensator 302. The last compensator 302 may upsample the received signal to return the signal to the full sampling rate as shown in graph 404C. The output of the power amplifier 202 (shown by graph 404D) may remain at the full sampling rate.

[0063] Figure 5An example implementation of a multi-stage, multi-rate digital predistortion system 204 is shown in accordance with certain embodiments. As previously described, each compensator 302 may implement or execute a series of parallel models (e.g., models 502). Each of the models 502 may be a type of transformation function or machine learning model that may be used to modify the linearity of an input signal. The models 502 may be of the same type or different types of models (e.g., Volterra series, neural networks, generalized memory polynomials, etc.). In addition, each model 502 may be preceded by a downsampling circuit 504, and each model 502 may be followed by an upsampling circuit 506. As described with respect to Figure 4 As described in the example in, in some cases, the compensator 302 may downsample and / or upsample the signal provided to the model 502 or output by the model 502. In some cases, some compensators 302 (or models 502) do not perform downsampling or upsampling. In this case, the downsampling circuit 504 or the upsampling circuit 506 may be omitted. Alternatively, the downsampling circuit 504 and / or the upsampling circuit 506 may be retained but may not be used. Therefore, in some embodiments, the compensator 302 may be dynamically configured to modify the sampling rate of the signal processed by the compensator 302.

[0064] The output of each model 502 of the compensator 302 may be provided as an input to a corresponding model 502 in a subsequent compensator 302 within the same signal path. Thus, for example, the output of model 1,1 may be provided as an input to model 1,2 (not shown), and the output of model 1,2 may be provided as an input to the next model, and so on, until model 1,N is reached. The outputs of the models 502 of the last compensator 302 of the digital predistortion system 204 are all at the same sampling rate. If the output of one series of models 502 (e.g., model 1,N) is at a different sampling rate than the output of another series of models 502 [e.g., model 2,N], the upsampling circuit 506 of the model with the lower sampling rate may upsample the output of the model 502 so that all models generate outputs at the same sampling rate. The output of each model 502, which may be upsampled in some cases, may be provided to an adder or summing circuit 508 to generate a single signal, which may then be provided to the power amplifier 202 or an intermediate circuit (not shown) before the power amplifier 202.

[0065] Figure 6 Another example implementation of a multi-stage multi-rate digital predistortion system 204 according to some embodiments is shown. Figure 6In the example shown, the output of each set of models 502 for each compensator 302 may be provided to an adder or summing circuit 602. Thus, each compensator 302 may receive a single input signal, and each model 502 within a compensator 302 may receive the same input. Additionally, because the sampling rates should match in order to combine the outputs of each model 502, an upsampling circuit 506 may be used to ensure that each model 502 output for a given compensator 302 has the same sampling rate.

[0066] As previously described, the DPD adaptation system 206 may be used to configure the DPD system 204 based at least in part on the output of the power amplifier 202 and the output of the crest factor reduction circuit 208. Configuring the DPD system 204 may include setting coefficients or weights of variables within the model 502 of the compensator 302 of the DPD system 204.

[0067] Figure 7 An example implementation of a digital predistortion adaptive circuit 206 implementing a least squares estimation adaptive algorithm according to certain embodiments is shown. In certain embodiments, the digital predistortion adaptive system 206 may include a set of circuits or processors 702 configured to implement an adaptive algorithm to determine weighted values ​​for the model 502 implemented by the digital predistortion adaptive system 206. There may be up to N processors 702, each configured to implement an adaptive algorithm for an N-level model. Alternatively, there may be a single processor 702 configured to implement N instances of the adaptive algorithm for the N-level model. The adaptive algorithm or the processor 702 implementing the adaptive algorithm may be controlled by a controller 704, which may determine when the error difference between the output of the power amplifier 202 and the input of the digital predistortion adaptive system 206 meets a threshold (e.g., is less than a certain error value). The controller 704 may be included as part of the digital predistortion adaptive system 206. The digital predistortion adaptive system 206 may implement a least squares estimation (LSE) adaptive algorithm. The use of an adaptive algorithm by the digital predistortion adaptive system 206 to configure the coefficients of the digital predistortion system 204 may result in a reduction in adjacent channel leakage rate (ACLR).

[0068] Figure 8 An example implementation of a digital predistortion adaptation circuit 206 implementing back propagation and least squares estimation adaptation algorithms according to certain embodiments is shown. In certain embodiments, combining back propagation with LSE improves the ACLR of the digital predistortion system 204. Solving the least squares problem N times is both fast and computationally efficient. In addition, optimizing the first N-1 stages using the back propagation algorithm can provide a more optimized solution than using only LSE. Figure 8 The digital predistortion adaptive system 206 may include Figure 7The digital pre-distortion adaptive system 206 has the same elements. However, Figure 8 The digital predistortion adaptation system 206 may include an additional processor 802 that may perform LSE after the processor 702 performs the adaptation algorithm using back-propagation to compare the output of the power amplifier 202 with the input provided to the digital predistortion adaptation system 206 for each coefficient of the model 502 processed by the compensator 302.

[0069] Such a calibration strategy implemented by the digital predistortion adaptation system 206 for calibrating the coefficients of the model 502 may include feeding forward the input x through all stages of the adaptation algorithm (corresponding to the processor 702 or other computational circuitry) to solve for x (N) The output x can be solved as follows (1) -x (N) Each output in:

[0070]

[0071]

[0072] x (N) =B N (x N-1 )W (N)

[0073] The error function can be calculated as follows:

[0074]

[0075] The controller 704 may compare the calculated error with a threshold. If it is determined that the calculated error is small enough (e.g., less than the threshold), the processor 702 may output the calculated weight w as a coefficient value of the model 502 of the compensator 302. The weight may be calculated as follows:

[0076]

[0077] In addition, back propagation (BP) can be used to update W at the iteration (1) ...W (N-1) In addition, the additional processor 802 may use an LSE with the following objective function to determine W (N) :

[0078]

[0079] The calculation may be repeated until there is convergence as determined by the error calculated by the error function being less than a threshold value.

[0080] Fig. 92 shows example system equations for an example multi-stage multi-rate digital predistortion system 204 using a generalized memory polynomial model in accordance with some embodiments. Fig. 9 As shown in the table, although the use of a 2-stage digital predistortion system 204 can improve efficiency and reduce complexity, the number of coefficients remains the same. However, a 4-stage digital predistortion system 204 results in a reduction from 29 coefficients to 188 coefficients, thereby reducing the circuit size of the digital predistortion body system 204, reducing power requirements, and improving the overall performance of the digital predistortion body system 204, including improving the nonlinearity in the digital predistortion body system 204, which combined with the nonlinearity of the power amplifier 202 leads to an improvement in the linearity of the overall system (e.g., the wireless system 200).

[0081] Fig.10 1 shows simulation results of a multi-stage multi-rate digital predistortion system 204 according to some embodiments, which is adapted by a digital predistortion adaptation circuit 206 implementing a back-propagation and least squares estimation adaptation algorithm. In addition, Fig.10 The graph of Graph 1001 graphically illustrates the improvement in ACLR of the 4-level digital pre-distortion system 204 compared to the input, 1-level, and 2-level digital pre-distortion, with the bottom line 1002 representing the 4-level digital pre-distortion system 204.

[0082] Figures 11A-11D Measured results are shown for an implementation of a multi-stage multi-rate digital predistortion system adapted by a digital predistortion adaptation circuit implementing back-propagation and least squares estimation adaptation algorithms in accordance with certain embodiments. Fig.11A Measurement results of a 1-stage digital predistortion system 204 processing a signal having a center frequency of 2.6 GHz are shown. Fig. 11B Shows the processing and Fig.11A Measurement results of a 2-stage digital predistortion system 204 for the same signal. Fig. 11C Shows the processing and Fig.11A Measurement results of the 4-level DPD system 204 for the same signal. Figures 11A-11C From the 1-stage, 2-stage, and 4-stage graphs shown in FIG, it can be seen that as more stages are added to the digital predistortion system 204, both the low-band ACLR and the high-band ACLR improve.

[0083] Fig.11D Shown is a table showing the improvements between the 1-level, 2-level, and 4-level digital predistortion systems 204. As shown in the table, the number of coefficients remains the same between the 1-level and 2-level digital predistortion systems 204. However, the 4-level digital predistortion system 204 reduces the number of coefficients, reducing the power and area to implement the digital predistortion system 204 while improving the ACLR as shown in the table. Fig.11DAs shown in the table in FIG. 1 , the ACLR improvement between stage 1 and stage 2 of the digital predistortion system 204 is at least 3 dB. In addition, when going from stage 2 to stage 4, there is at least a 2 dB improvement while the number of coefficients is reduced. In addition, for operating band unwanted emissions (OBUE), a total improvement of almost 10 dB / MHz is obtained between stage 1 and stage 4.

[0084] also, Fig.11D The table in illustrates the measurement results of a multi-stage multi-rate digital predistortion system 204 adapted by a digital predistortion adaptation circuit 206 implementing a least squares estimation adaptation algorithm and a digital predistortion adaptation circuit implementing a back propagation and least squares estimation adaptation algorithm according to some embodiments. Fig.11D As shown in the table in FIG. 1 , when only LSE is used to calibrate the DPD system 204 for the DPD adaptive system 206, the improvement may be limited. However, when both back propagation and LSE are used to calibrate the DPD system 204 for the DPD adaptive system 206, the measurement results show that the offline ACLR improvement between the level 1 and level 4 DPD bulk systems 204 is more than 10 dB for the worst case ACLR and more than 5 dB for the worst case alternating ACLR.

[0085] Figures 12A-12C Measured results are shown for an implementation of a multi-stage multi-rate digital predistortion system adapted by a digital predistortion adaptation circuit implementing back-propagation and least squares estimation adaptation algorithms in accordance with certain embodiments. Fig. 12A Measurement results of a 1-stage digital predistortion system 204 processing a signal having a center frequency of 3.5 GHz are shown. Fig. 12B Shows the processing and Fig. 12A The measurement results of the 6-level digital predistortion system 204 for the same signal. Figures 12A-12B From the 1 and 6 level graphs shown in , it can be seen that as more levels are added to the digital predistortion system 204, the ACLR improves.

[0086] Fig. 12C Shown is a table showing the improvement between the 1-level and 6-level digital predistortion systems 204. As shown in the table, when the number of levels is increased, the number of coefficients is reduced by more than 100. At the same time, ACLR can be improved by at least 5 dB and OBUE can be improved by 3.5 dB / MHz.

[0087] the term

[0088] Unless otherwise specifically stated or understood otherwise in the context of use, conditional language used herein, such as "may," "might," "could," "might," "for example," etc., can generally be used to convey that some embodiments include, while other embodiments do not include, certain features, elements, and / or states. Therefore, such conditional language generally does not mean that features, elements, and / or states can be required by one or more embodiments in any way, or that one or more embodiments must include these features, elements, or states.

[0089] Unless specifically stated otherwise, transitional language such as the phrase "at least one of X, Y, and Z" can be understood with context generally used to convey that an item, term, etc. may be X, Y, or Z. Thus, such transitional language generally does not mean that certain embodiments require the presence of at least one of X, Y, and Z.

[0090] Although the above detailed description may have shown, described and pointed out novel features applicable to various embodiments, it is understood that various omissions, substitutions and / or changes in the form and details of any particular embodiment may be made without departing from the spirit of the present disclosure. It is recognized that certain embodiments may be embodied in a form that does not provide all of the features and benefits set forth herein, as some features may be used or practiced separately from other features.

[0091] All processes described herein can be embodied in a software code module executed by a computing system including one or more computers or processors and fully automated by the software code module. The code module can be stored in any type of non-transient computer readable medium or other computer storage device. Some or all methods can be embodied in specialized computer hardware.

[0092] Many other variations other than those described herein will be apparent from this disclosure. For example, depending on the embodiment, certain actions, events, or functions of any algorithm described herein may be performed in a different order, may be added, merged, or omitted entirely (e.g., not all described actions or events are necessary for the practice of the algorithm). In addition, in some embodiments, actions or events may be performed simultaneously, e.g., by multithreading, interrupt handling, or multiple processors or processor cores, or on other parallel architectures, rather than sequentially. In addition, different tasks or processes may be performed by different machines and / or computing systems that may work together.

[0093] The various illustrative logic blocks and modules described in conjunction with the embodiments disclosed herein may be implemented or executed by a machine, such as a processing unit or processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be a controller, a microcontroller or a state machine, a combination thereof, and the like. The processor may include a circuit configured to process computer executable instructions. In another embodiment, the processor includes an FPGA or other programmable device that performs logic operations without processing computer executable instructions. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Although this article is primarily described with respect to digital technology, the processor may also primarily include analog components. The computing environment may include any type of computer system, including but not limited to a microprocessor-based computer system, a mainframe computer, a digital signal processor, a portable computing device, a computing engine within a device controller or a device, and the like.

[0094] In addition, features described in conjunction with one embodiment may be incorporated into another of the disclosed embodiments even if not explicitly discussed herein, and embodiments may have combinations of features that still fall within the scope of the present disclosure. For example, features described above in conjunction with one embodiment may be used with a different embodiment described herein, and the combination still falls within the scope of the present disclosure.

[0095] It should be understood that the various features and aspects of the disclosed embodiments can be combined with or replaced with each other to form a variation of the embodiments of the present disclosure. Therefore, the scope of the disclosure herein should not be limited by the specific embodiments described above. Therefore, unless otherwise specified, or unless clearly incompatible, each embodiment of the present disclosure, in addition to its basic features described herein, may also include one or more features from each other embodiment disclosed herein as described herein.

[0096] Features, materials, characteristics or groups described in conjunction with a particular aspect, embodiment or example may be understood to be applicable to any other aspect, embodiment or example described in this section or elsewhere in this specification unless incompatible therewith. All features disclosed in this specification (including any accompanying claims, abstract and drawings) and / or all steps of any method or process so disclosed may be combined in any combination, except combinations where at least some of such features and / or steps may be mutually exclusive. Protection may not be limited to the details of any preceding embodiments. The protection extends to any novel one or any novel combination of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one or any novel combination of the steps of any method or process so disclosed.

[0097] In addition, the features and attributes of the specific embodiments disclosed above can be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the components and systems described can generally be integrated into a single product or packaged into multiple products.

[0098] In addition, although operations may be described in the drawings or described in a particular order in the specification, such operations need not be performed in the particular order or sequence shown, or all operations need not be performed to achieve the desired results. Other operations that may not be depicted or described may be incorporated into the example methods and processes. For example, one or more additional operations may be performed before, after, simultaneously, or between any operations described. In addition, in other implementations, operations may be rearranged or reordered, including at least partially performed in parallel. Those skilled in the art will appreciate that in some embodiments, the actual steps taken in the process shown and / or disclosed may be different from the steps shown in the figures. Depending on the embodiment, some of the above steps may be removed, and other steps may be added.

[0099] For purposes of the present disclosure, certain aspects, advantages, and novel features may be described herein. Not all of these advantages may be achieved according to any particular embodiment. Thus, for example, those skilled in the art will recognize that the present disclosure may be embodied or implemented in a manner that achieves one advantage or a group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

[0100] As used herein, language of degree, such as the terms "approximately," "about," "generally," and "substantially," as used herein, refers to a value, amount, or characteristic that is close to a stated value, amount, or characteristic that still performs a desired function or achieves a desired result. For example, the terms "approximately," "about," "generally," and "substantially" may refer to an amount that may be within 10%, within 5%, within 1%, within 0.1%, and within 0.01% of the stated amount. As another example, in certain embodiments, the terms "substantially parallel" and "substantially parallel" refer to a value, amount, or characteristic that deviates from exact parallelism by less than or equal to 15 degrees, 10 degrees, 5 degrees, 3 degrees, 1 degree, 0.1 degrees, or other.

[0101] The scope of the present disclosure may not be intended to be limited by the specific disclosure of preferred embodiments in this section or elsewhere in this specification, and may be defined by the claims presented in this section or elsewhere in the specification or by future claims presented. The language of the claims may be interpreted broadly based on the language used in the claims, and not limited to the examples described in this specification or examples described during the prosecution of the application, which examples may be interpreted as non-exclusive.

[0102] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprises," "comprising," and the like are to be construed in an inclusive sense rather than an exclusive or exhaustive sense, that is, in the sense of "including but not limited to."

Claims

1. A digital predistortion system configured to distort a power amplifier input signal before being input to a power amplifier, the digital predistortion system comprising: a first compensator comprising a first plurality of processing circuit blocks, wherein each of the first plurality of processing circuit blocks is configured to implement a transfer function to modify the linearity of a first input signal input to the first compensator, and wherein each of the first plurality of processing circuit blocks is connected in parallel within the first compensator; a second compensator connected in series with the first compensator, the second compensator comprising a second plurality of processing circuit blocks, wherein each of the second plurality of processing circuit blocks is configured to implement a transfer function to modify the linearity of a second input signal input to the second compensator, wherein each of the second plurality of processing circuit blocks is connected in parallel within the second compensator, and wherein the second input signal is based at least in part on an output of the first compensator; and A first adder circuit is configured to sum the output of each processing circuit block in the second plurality of processing circuit blocks to obtain a digital predistortion signal, wherein the first adder circuit is further configured to provide the digital predistortion signal as an input to the power amplifier.

2. The digital predistortion system according to claim 1, wherein: At least one of the first plurality of processing circuit blocks or the second plurality of processing circuit blocks implements a neural network.

3. The digital predistortion system according to claim 1, wherein: The second compensator also includes the first adder circuit.

4. The digital predistortion system according to claim 1, wherein: Each processing circuit block in the first plurality of processing circuit blocks is configured to generate an output that is provided as an input to a corresponding processing circuit block in the second plurality of processing circuit blocks.

5. The digital predistortion system of claim 1 , further comprising a second adder circuit configured to sum the output of each of the first plurality of processing circuit blocks to obtain an intermediate signal, wherein the intermediate signal is provided as an input to the second compensator.

6. The digital predistortion system according to claim 1, wherein: At least one of the first compensator or the second compensator includes a memory that stores signal samples that enables the transfer function to operate over a larger sample range than a memoryless compensator.

7. The digital predistortion system of claim 1, further comprising a set of one or more compensators connected in series between the first compensator and the second compensator.

8. The digital predistortion system according to claim 1, wherein: A combination of at least the first compensator and the second compensator is configured to generate a distortion of the power amplifier input signal such that an overall system response of a system including the power amplifier is linear.

9. The digital predistortion system according to claim 1, wherein: The first compensator further includes a plurality of down-sampling circuits corresponding to the first plurality of processing circuit blocks, wherein each of the plurality of down-sampling circuits is configured to down-sample the first input signal to obtain a down-sampled input signal, which is input to a corresponding processing circuit block among the first plurality of processing circuit blocks.

10. The digital predistortion system according to claim 1, wherein: The first compensator further includes a plurality of up-sampling circuits corresponding to the first plurality of processing circuit blocks, wherein each of the plurality of up-sampling circuits is configured to up-sample an output of a corresponding processing circuit block of the first plurality of processing circuit blocks.

11. The digital predistortion system according to claim 1, wherein: At least one processing circuit block of the first plurality of processing circuit blocks implements a different transform function than at least another processing circuit block of the first plurality of processing circuit blocks.

12. The digital predistortion system according to claim 1, wherein: The transform function includes one or more of a set of mathematical sequences or models configured to modify the linearity of the applied signal.

13. The digital predistortion system according to claim 1, wherein: The transfer function includes one or more weighting coefficients set based on a digital predistortion adaptation circuit configured to determine the one or more weighting coefficients using an adaptive algorithm applied to an output of the power amplifier.

14. The digital predistortion system according to claim 1, wherein: The transfer function includes one or more weighting coefficients set based on a digital predistortion adaptation circuit configured to determine the one or more weighting coefficients using a back-propagation and least squares estimation algorithm applied to an output of the power amplifier.

15. A transceiver radio comprising: Power amplifier; and A digital predistortion system connected in series with the power amplifier, the digital predistortion system comprising: a plurality of compensator circuits connected in series, wherein each compensator circuit of the plurality of compensator circuits comprises a plurality of non-linear processing circuits connected in parallel, the non-linear processing circuits being configured to implement a transfer function to modify the linearity of an input signal received at a first compensator circuit of the plurality of compensator circuits; and an adder circuit configured to sum the output of each of the plurality of nonlinear processing circuits of the last compensator circuit in the plurality of compensator circuits to obtain a digital predistortion signal, wherein the adder circuit is further configured to provide the digital predistortion signal as an input to the power amplifier.

16. The transceiver radio of claim 15, further comprising a crest factor reduction circuit configured to receive a transmit signal and reduce a peak-to-peak average power ratio of the transmit signal to obtain a reduced peak-to-peak transmit signal, wherein the reduced peak-to-peak transmit signal is provided as an input signal to the digital predistortion system.

17. The transceiver radio of claim 15, further comprising a digital predistortion adaptation circuit configured to receive an output of the power amplifier and configure one or more coefficients of a transfer function of at least one of the plurality of compensator circuits based at least in part on the power amplifier output.

18. The transceiver radio of claim 15, wherein: At least one compensator circuit further comprises a plurality of down-sampling circuits corresponding to the plurality of non-linear processing circuits, and wherein each of the plurality of down-sampling circuits is configured to down-sample the input signal to obtain a down-sampled input signal, which is input to a corresponding non-linear processing circuit of the plurality of non-linear processing circuits.

19. The transceiver radio of claim 15, wherein: At least one compensator circuit further includes a plurality of up-sampling circuits corresponding to the plurality of non-linear processing circuits, and wherein each of the plurality of up-sampling circuits is configured to up-sample an output of a corresponding non-linear processing circuit of the plurality of non-linear processing circuits.

20. A wireless device comprising: an antenna configured to transmit a signal received from the power amplifier; the power amplifier; A transceiver, comprising a digital pre-distortion system connected in series with the power amplifier, the digital pre-distortion system comprising: a plurality of compensator circuits connected in series, wherein each compensator circuit of the plurality of compensator circuits comprises a plurality of nonlinear processing circuits and linear processing circuits connected in parallel and is configured to implement a transfer function to modify the linearity of an input signal received at a first compensator circuit of the plurality of compensator circuits; and an adder circuit configured to sum the output of each of the plurality of nonlinear processing circuits of a last compensator circuit of the plurality of compensator circuits to obtain a digital predistortion signal, wherein the adder circuit is further configured to provide the digital predistortion signal as an input to the power amplifier; a digital predistortion adaptation circuit configured to receive an output of the power amplifier and configure one or more coefficients of a transfer function of at least one compensator circuit of the plurality of compensator circuits based at least in part on the power amplifier output; and A coupler is configured to provide the output of the power amplifier to the digital predistortion adaptive circuit.

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